* [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero
@ 2017-04-26 10:04 Vladimir Murzin
2017-05-02 8:31 ` Vladimir Murzin
0 siblings, 1 reply; 7+ messages in thread
From: Vladimir Murzin @ 2017-04-26 10:04 UTC (permalink / raw)
To: linux-arm-kernel
Cache support is optional feature in M-class cores, thus DminLine or
IminLine of Cache Type Register is zero if caches are not implemented,
but we check the whole CTR which has other features encoded there.
Let's be more precise and check for DminLine and IminLine of CTR
before we set cacheid.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm/kernel/setup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index f4e5450..231a1d83 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -315,7 +315,7 @@ static void __init cacheid_init(void)
if (arch >= CPU_ARCH_ARMv6) {
unsigned int cachetype = read_cpuid_cachetype();
- if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
+ if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
cacheid = 0;
} else if ((cachetype & (7 << 29)) == 4 << 29) {
/* ARMv7 register format */
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero
2017-04-26 10:04 [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero Vladimir Murzin
@ 2017-05-02 8:31 ` Vladimir Murzin
2017-05-03 19:14 ` Russell King - ARM Linux
0 siblings, 1 reply; 7+ messages in thread
From: Vladimir Murzin @ 2017-05-02 8:31 UTC (permalink / raw)
To: linux-arm-kernel
On 26/04/17 11:04, Vladimir Murzin wrote:
> Cache support is optional feature in M-class cores, thus DminLine or
> IminLine of Cache Type Register is zero if caches are not implemented,
> but we check the whole CTR which has other features encoded there.
> Let's be more precise and check for DminLine and IminLine of CTR
> before we set cacheid.
>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm/kernel/setup.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index f4e5450..231a1d83 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -315,7 +315,7 @@ static void __init cacheid_init(void)
> if (arch >= CPU_ARCH_ARMv6) {
> unsigned int cachetype = read_cpuid_cachetype();
>
> - if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
> + if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
> cacheid = 0;
> } else if ((cachetype & (7 << 29)) == 4 << 29) {
> /* ARMv7 register format */
>
Ok for patch tracker?
Vladimir
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero
2017-05-02 8:31 ` Vladimir Murzin
@ 2017-05-03 19:14 ` Russell King - ARM Linux
2017-05-04 8:13 ` Vladimir Murzin
0 siblings, 1 reply; 7+ messages in thread
From: Russell King - ARM Linux @ 2017-05-03 19:14 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 02, 2017 at 09:31:24AM +0100, Vladimir Murzin wrote:
> On 26/04/17 11:04, Vladimir Murzin wrote:
> > Cache support is optional feature in M-class cores, thus DminLine or
> > IminLine of Cache Type Register is zero if caches are not implemented,
> > but we check the whole CTR which has other features encoded there.
> > Let's be more precise and check for DminLine and IminLine of CTR
> > before we set cacheid.
> >
> > Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> > ---
> > arch/arm/kernel/setup.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> > index f4e5450..231a1d83 100644
> > --- a/arch/arm/kernel/setup.c
> > +++ b/arch/arm/kernel/setup.c
> > @@ -315,7 +315,7 @@ static void __init cacheid_init(void)
> > if (arch >= CPU_ARCH_ARMv6) {
> > unsigned int cachetype = read_cpuid_cachetype();
> >
> > - if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
> > + if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
> > cacheid = 0;
> > } else if ((cachetype & (7 << 29)) == 4 << 29) {
> > /* ARMv7 register format */
> >
>
> Ok for patch tracker?
Not yet, I've been away and I've no time right now to evaluate this
change. I'm hopefully going to catch up with some email in the coming
days.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero
2017-05-03 19:14 ` Russell King - ARM Linux
@ 2017-05-04 8:13 ` Vladimir Murzin
2017-05-26 9:52 ` Vladimir Murzin
0 siblings, 1 reply; 7+ messages in thread
From: Vladimir Murzin @ 2017-05-04 8:13 UTC (permalink / raw)
To: linux-arm-kernel
On 03/05/17 20:14, Russell King - ARM Linux wrote:
> On Tue, May 02, 2017 at 09:31:24AM +0100, Vladimir Murzin wrote:
>> On 26/04/17 11:04, Vladimir Murzin wrote:
>>> Cache support is optional feature in M-class cores, thus DminLine or
>>> IminLine of Cache Type Register is zero if caches are not implemented,
>>> but we check the whole CTR which has other features encoded there.
>>> Let's be more precise and check for DminLine and IminLine of CTR
>>> before we set cacheid.
>>>
>>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>>> ---
>>> arch/arm/kernel/setup.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>>> index f4e5450..231a1d83 100644
>>> --- a/arch/arm/kernel/setup.c
>>> +++ b/arch/arm/kernel/setup.c
>>> @@ -315,7 +315,7 @@ static void __init cacheid_init(void)
>>> if (arch >= CPU_ARCH_ARMv6) {
>>> unsigned int cachetype = read_cpuid_cachetype();
>>>
>>> - if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
>>> + if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
>>> cacheid = 0;
>>> } else if ((cachetype & (7 << 29)) == 4 << 29) {
>>> /* ARMv7 register format */
>>>
>>
>> Ok for patch tracker?
>
> Not yet, I've been away and I've no time right now to evaluate this
> change. I'm hopefully going to catch up with some email in the coming
> days.
>
Noted.
Cheers
Vladimir
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero
2017-05-04 8:13 ` Vladimir Murzin
@ 2017-05-26 9:52 ` Vladimir Murzin
2017-06-08 8:29 ` Vladimir Murzin
0 siblings, 1 reply; 7+ messages in thread
From: Vladimir Murzin @ 2017-05-26 9:52 UTC (permalink / raw)
To: linux-arm-kernel
Gentle ping...
On 04/05/17 09:13, Vladimir Murzin wrote:
> On 03/05/17 20:14, Russell King - ARM Linux wrote:
>> On Tue, May 02, 2017 at 09:31:24AM +0100, Vladimir Murzin wrote:
>>> On 26/04/17 11:04, Vladimir Murzin wrote:
>>>> Cache support is optional feature in M-class cores, thus DminLine or
>>>> IminLine of Cache Type Register is zero if caches are not implemented,
>>>> but we check the whole CTR which has other features encoded there.
>>>> Let's be more precise and check for DminLine and IminLine of CTR
>>>> before we set cacheid.
>>>>
>>>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>>>> ---
>>>> arch/arm/kernel/setup.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>>>> index f4e5450..231a1d83 100644
>>>> --- a/arch/arm/kernel/setup.c
>>>> +++ b/arch/arm/kernel/setup.c
>>>> @@ -315,7 +315,7 @@ static void __init cacheid_init(void)
>>>> if (arch >= CPU_ARCH_ARMv6) {
>>>> unsigned int cachetype = read_cpuid_cachetype();
>>>>
>>>> - if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
>>>> + if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
>>>> cacheid = 0;
>>>> } else if ((cachetype & (7 << 29)) == 4 << 29) {
>>>> /* ARMv7 register format */
>>>>
>>>
>>> Ok for patch tracker?
>>
>> Not yet, I've been away and I've no time right now to evaluate this
>> change. I'm hopefully going to catch up with some email in the coming
>> days.
>>
>
> Noted.
>
> Cheers
> Vladimir
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero
2017-05-26 9:52 ` Vladimir Murzin
@ 2017-06-08 8:29 ` Vladimir Murzin
2017-06-08 16:22 ` Russell King - ARM Linux
0 siblings, 1 reply; 7+ messages in thread
From: Vladimir Murzin @ 2017-06-08 8:29 UTC (permalink / raw)
To: linux-arm-kernel
Ping!
On 26/05/17 10:52, Vladimir Murzin wrote:
> Gentle ping...
>
> On 04/05/17 09:13, Vladimir Murzin wrote:
>> On 03/05/17 20:14, Russell King - ARM Linux wrote:
>>> On Tue, May 02, 2017 at 09:31:24AM +0100, Vladimir Murzin wrote:
>>>> On 26/04/17 11:04, Vladimir Murzin wrote:
>>>>> Cache support is optional feature in M-class cores, thus DminLine or
>>>>> IminLine of Cache Type Register is zero if caches are not implemented,
>>>>> but we check the whole CTR which has other features encoded there.
>>>>> Let's be more precise and check for DminLine and IminLine of CTR
>>>>> before we set cacheid.
>>>>>
>>>>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>>>>> ---
>>>>> arch/arm/kernel/setup.c | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>>>>> index f4e5450..231a1d83 100644
>>>>> --- a/arch/arm/kernel/setup.c
>>>>> +++ b/arch/arm/kernel/setup.c
>>>>> @@ -315,7 +315,7 @@ static void __init cacheid_init(void)
>>>>> if (arch >= CPU_ARCH_ARMv6) {
>>>>> unsigned int cachetype = read_cpuid_cachetype();
>>>>>
>>>>> - if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
>>>>> + if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
>>>>> cacheid = 0;
>>>>> } else if ((cachetype & (7 << 29)) == 4 << 29) {
>>>>> /* ARMv7 register format */
>>>>>
>>>>
>>>> Ok for patch tracker?
>>>
>>> Not yet, I've been away and I've no time right now to evaluate this
>>> change. I'm hopefully going to catch up with some email in the coming
>>> days.
>>>
>>
>> Noted.
>>
>> Cheers
>> Vladimir
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero
2017-06-08 8:29 ` Vladimir Murzin
@ 2017-06-08 16:22 ` Russell King - ARM Linux
0 siblings, 0 replies; 7+ messages in thread
From: Russell King - ARM Linux @ 2017-06-08 16:22 UTC (permalink / raw)
To: linux-arm-kernel
Yea, found a copy of the ARMv7M ARM, and this seems to be sane, as the
minimum cache line size (according to CCSIDR) is 4 words, so the minimum
value in CTR for these fields should be 2 when caches are implemented.
On Thu, Jun 08, 2017 at 09:29:24AM +0100, Vladimir Murzin wrote:
> Ping!
>
> On 26/05/17 10:52, Vladimir Murzin wrote:
> > Gentle ping...
> >
> > On 04/05/17 09:13, Vladimir Murzin wrote:
> >> On 03/05/17 20:14, Russell King - ARM Linux wrote:
> >>> On Tue, May 02, 2017 at 09:31:24AM +0100, Vladimir Murzin wrote:
> >>>> On 26/04/17 11:04, Vladimir Murzin wrote:
> >>>>> Cache support is optional feature in M-class cores, thus DminLine or
> >>>>> IminLine of Cache Type Register is zero if caches are not implemented,
> >>>>> but we check the whole CTR which has other features encoded there.
> >>>>> Let's be more precise and check for DminLine and IminLine of CTR
> >>>>> before we set cacheid.
> >>>>>
> >>>>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> >>>>> ---
> >>>>> arch/arm/kernel/setup.c | 2 +-
> >>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> >>>>> index f4e5450..231a1d83 100644
> >>>>> --- a/arch/arm/kernel/setup.c
> >>>>> +++ b/arch/arm/kernel/setup.c
> >>>>> @@ -315,7 +315,7 @@ static void __init cacheid_init(void)
> >>>>> if (arch >= CPU_ARCH_ARMv6) {
> >>>>> unsigned int cachetype = read_cpuid_cachetype();
> >>>>>
> >>>>> - if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
> >>>>> + if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
> >>>>> cacheid = 0;
> >>>>> } else if ((cachetype & (7 << 29)) == 4 << 29) {
> >>>>> /* ARMv7 register format */
> >>>>>
> >>>>
> >>>> Ok for patch tracker?
> >>>
> >>> Not yet, I've been away and I've no time right now to evaluate this
> >>> change. I'm hopefully going to catch up with some email in the coming
> >>> days.
> >>>
> >>
> >> Noted.
> >>
> >> Cheers
> >> Vladimir
> >>
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> linux-arm-kernel at lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >>
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
>
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-06-08 16:22 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-26 10:04 [PATCH] ARM: V7M: Set cacheid iff DminLine or IminLine is nonzero Vladimir Murzin
2017-05-02 8:31 ` Vladimir Murzin
2017-05-03 19:14 ` Russell King - ARM Linux
2017-05-04 8:13 ` Vladimir Murzin
2017-05-26 9:52 ` Vladimir Murzin
2017-06-08 8:29 ` Vladimir Murzin
2017-06-08 16:22 ` Russell King - ARM Linux
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