* [PATCH 0/2] sunxi: fix SUNIV D$ support
@ 2022-10-13 13:26 Icenowy Zheng
2022-10-13 13:26 ` [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache Icenowy Zheng
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Icenowy Zheng @ 2022-10-13 13:26 UTC (permalink / raw)
To: Jagan Teki, Andre Przywara; +Cc: u-boot, linux-sunxi, Icenowy Zheng
Currently D$ support of SUNIV is broken because of duplicated definition
of the D$ enabling function.
Mask the one in mach-sunxi to fix the build error when D$ is enabled,
and enable the D$ on Lichee Pi Nano.
Icenowy Zheng (2):
sunxi: fix SUNIV build when enabling D-Cache
configs: sunxi: licheepi_nano: enable D-Cache
arch/arm/mach-sunxi/board.c | 2 +-
configs/licheepi_nano_defconfig | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
--
2.37.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache
2022-10-13 13:26 [PATCH 0/2] sunxi: fix SUNIV D$ support Icenowy Zheng
@ 2022-10-13 13:26 ` Icenowy Zheng
2022-10-17 9:26 ` Andre Przywara
2022-10-13 13:26 ` [PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache Icenowy Zheng
2022-10-17 6:47 ` [PATCH 0/2] sunxi: fix SUNIV D$ support Andre Przywara
2 siblings, 1 reply; 6+ messages in thread
From: Icenowy Zheng @ 2022-10-13 13:26 UTC (permalink / raw)
To: Jagan Teki, Andre Przywara; +Cc: u-boot, linux-sunxi, Icenowy Zheng
The enable_caches function in architecture-specific board code is only
necessary for V7A CPUs, code for both V8A and ARM926 have already
declared this function.
Only provide our implementation of enable_caches() for V7A CPUs.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
arch/arm/mach-sunxi/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 62bb40b8c8..60ccf909db 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -488,7 +488,7 @@ void reset_cpu(void)
}
#endif
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
--
2.37.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache
2022-10-13 13:26 [PATCH 0/2] sunxi: fix SUNIV D$ support Icenowy Zheng
2022-10-13 13:26 ` [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache Icenowy Zheng
@ 2022-10-13 13:26 ` Icenowy Zheng
2022-10-17 9:27 ` Andre Przywara
2022-10-17 6:47 ` [PATCH 0/2] sunxi: fix SUNIV D$ support Andre Przywara
2 siblings, 1 reply; 6+ messages in thread
From: Icenowy Zheng @ 2022-10-13 13:26 UTC (permalink / raw)
To: Jagan Teki, Andre Przywara; +Cc: u-boot, linux-sunxi, Icenowy Zheng
As the compile error when D-Cache is enabled is gone, we can have
D-Cache enabled now.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
configs/licheepi_nano_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
index a9776bbcac..b80d32c502 100644
--- a/configs/licheepi_nano_defconfig
+++ b/configs/licheepi_nano_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
-CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
CONFIG_SPL=y
--
2.37.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] sunxi: fix SUNIV D$ support
2022-10-13 13:26 [PATCH 0/2] sunxi: fix SUNIV D$ support Icenowy Zheng
2022-10-13 13:26 ` [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache Icenowy Zheng
2022-10-13 13:26 ` [PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache Icenowy Zheng
@ 2022-10-17 6:47 ` Andre Przywara
2 siblings, 0 replies; 6+ messages in thread
From: Andre Przywara @ 2022-10-17 6:47 UTC (permalink / raw)
To: Icenowy Zheng, Jagan Teki; +Cc: u-boot, linux-sunxi
On 13/10/2022 14:26, Icenowy Zheng wrote:
Hi Icenowy,
> Currently D$ support of SUNIV is broken because of duplicated definition
> of the D$ enabling function.
>
> Mask the one in mach-sunxi to fix the build error when D$ is enabled,
> and enable the D$ on Lichee Pi Nano.
Ah, very nice. I was always wondering why we would need to disable the
data cache, but it wasn't high enough on my list to investigate.
So indeed that both builds and works nicely: md5sum-ing 48MB goes from
21 seconds down to 3 seconds now!
Will merge it as part of the first pull request.
Many thanks!
Andre
>
> Icenowy Zheng (2):
> sunxi: fix SUNIV build when enabling D-Cache
> configs: sunxi: licheepi_nano: enable D-Cache
>
> arch/arm/mach-sunxi/board.c | 2 +-
> configs/licheepi_nano_defconfig | 1 -
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache
2022-10-13 13:26 ` [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache Icenowy Zheng
@ 2022-10-17 9:26 ` Andre Przywara
0 siblings, 0 replies; 6+ messages in thread
From: Andre Przywara @ 2022-10-17 9:26 UTC (permalink / raw)
To: Icenowy Zheng, Jagan Teki; +Cc: u-boot, linux-sunxi
On 13/10/2022 14:26, Icenowy Zheng wrote:
> The enable_caches function in architecture-specific board code is only
> necessary for V7A CPUs, code for both V8A and ARM926 have already
> declared this function.
>
> Only provide our implementation of enable_caches() for V7A CPUs.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Merging into sunxi/master.
Cheers,
Andre
> ---
> arch/arm/mach-sunxi/board.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 62bb40b8c8..60ccf909db 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -488,7 +488,7 @@ void reset_cpu(void)
> }
> #endif
>
> -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
> +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
> void enable_caches(void)
> {
> /* Enable D-cache. I-cache is already enabled in start.S */
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache
2022-10-13 13:26 ` [PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache Icenowy Zheng
@ 2022-10-17 9:27 ` Andre Przywara
0 siblings, 0 replies; 6+ messages in thread
From: Andre Przywara @ 2022-10-17 9:27 UTC (permalink / raw)
To: Icenowy Zheng, Jagan Teki; +Cc: u-boot, linux-sunxi
On 13/10/2022 14:26, Icenowy Zheng wrote:
> As the compile error when D-Cache is enabled is gone, we can have
> D-Cache enabled now.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks,
Andre
> ---
> configs/licheepi_nano_defconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
> index a9776bbcac..b80d32c502 100644
> --- a/configs/licheepi_nano_defconfig
> +++ b/configs/licheepi_nano_defconfig
> @@ -1,7 +1,6 @@
> CONFIG_ARM=y
> CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
> CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
> -CONFIG_SYS_DCACHE_OFF=y
> CONFIG_ARCH_SUNXI=y
> CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
> CONFIG_SPL=y
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-10-17 9:28 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-13 13:26 [PATCH 0/2] sunxi: fix SUNIV D$ support Icenowy Zheng
2022-10-13 13:26 ` [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache Icenowy Zheng
2022-10-17 9:26 ` Andre Przywara
2022-10-13 13:26 ` [PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache Icenowy Zheng
2022-10-17 9:27 ` Andre Przywara
2022-10-17 6:47 ` [PATCH 0/2] sunxi: fix SUNIV D$ support Andre Przywara
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