* [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board
@ 2016-11-17 4:36 Alastair D'Silva
2016-11-17 4:36 ` [Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses Alastair D'Silva
` (4 more replies)
0 siblings, 5 replies; 22+ messages in thread
From: Alastair D'Silva @ 2016-11-17 4:36 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, Peter Maydell, Cédric Le Goater, Andrew Jeffery,
Joel Stanley, Alastair D'Silva
From: Alastair D'Silva <alastair@d-silva.org>
This patch series adds support for the Epson RX8900 RTC to the
Aspeed board.
The tests use the existing imx25 infrastructure, and some minor
changes have been made to uniquely identify the I2C buses.
Support for named interrupts has been implemented in qtest to
facilitate testing.
Alastair D'Silva (4):
arm: Uniquely name imx25 I2C buses.
qtest: Support named interrupts
hw/timer: Add Epson RX8900 RTC support
arm: Add an RX8900 RTC to the ASpeed board
default-configs/arm-softmmu.mak | 1 +
hw/arm/aspeed.c | 8 +
hw/arm/imx25_pdk.c | 2 +-
hw/i2c/imx_i2c.c | 6 +-
hw/timer/Makefile.objs | 2 +
hw/timer/rx8900.c | 891 ++++++++++++++++++++++++++++++++++++++++
hw/timer/rx8900_regs.h | 125 ++++++
qtest.c | 98 +++--
tests/Makefile.include | 2 +
tests/libqtest.c | 87 +++-
tests/libqtest.h | 59 +++
tests/rx8900-test.c | 800 ++++++++++++++++++++++++++++++++++++
12 files changed, 2051 insertions(+), 30 deletions(-)
create mode 100644 hw/timer/rx8900.c
create mode 100644 hw/timer/rx8900_regs.h
create mode 100644 tests/rx8900-test.c
--
2.7.4
^ permalink raw reply [flat|nested] 22+ messages in thread* [Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses. 2016-11-17 4:36 [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva @ 2016-11-17 4:36 ` Alastair D'Silva 2016-11-17 7:50 ` Cédric Le Goater 2016-11-17 4:36 ` [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts Alastair D'Silva ` (3 subsequent siblings) 4 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-17 4:36 UTC (permalink / raw) To: qemu-arm Cc: qemu-devel, Peter Maydell, Cédric Le Goater, Andrew Jeffery, Joel Stanley, Alastair D'Silva From: Alastair D'Silva <alastair@d-silva.org> The imx25 chip provides 3 i2c buses, but they have all been named "i2c", which makes it difficult to predict which bus a device will be connected to when specified on the command line. This patch addresses the issue by naming the buses uniquely: i2c.0 i2c.1 i2c.2 Signed-off-by: Alastair D'Silva <alastair@d-silva.org> --- hw/arm/imx25_pdk.c | 2 +- hw/i2c/imx_i2c.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 025b608..1f7512c 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -139,7 +139,7 @@ static void imx25_pdk_init(MachineState *machine) * of simple qtest. See "make check" for details. */ i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(&s->soc.i2c[0]), - "i2c"), + "i2c.0"), "ds1338", 0x68); } } diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c index 37e5a62..7be10fb 100644 --- a/hw/i2c/imx_i2c.c +++ b/hw/i2c/imx_i2c.c @@ -305,12 +305,16 @@ static const VMStateDescription imx_i2c_vmstate = { static void imx_i2c_realize(DeviceState *dev, Error **errp) { IMXI2CState *s = IMX_I2C(dev); + static int bus_count; + char name[16]; + + snprintf(name, sizeof(name), "i2c.%d", bus_count++); memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C, IMX_I2C_MEM_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - s->bus = i2c_init_bus(DEVICE(dev), "i2c"); + s->bus = i2c_init_bus(DEVICE(dev), name); } static void imx_i2c_class_init(ObjectClass *klass, void *data) -- 2.7.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses. 2016-11-17 4:36 ` [Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses Alastair D'Silva @ 2016-11-17 7:50 ` Cédric Le Goater 0 siblings, 0 replies; 22+ messages in thread From: Cédric Le Goater @ 2016-11-17 7:50 UTC (permalink / raw) To: Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley, Alastair D'Silva Hello, On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > From: Alastair D'Silva <alastair@d-silva.org> > > The imx25 chip provides 3 i2c buses, but they have all been named > "i2c", which makes it difficult to predict which bus a device will > be connected to when specified on the command line. > > This patch addresses the issue by naming the buses uniquely: > i2c.0 i2c.1 i2c.2 > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > --- > hw/arm/imx25_pdk.c | 2 +- > hw/i2c/imx_i2c.c | 6 +++++- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c > index 025b608..1f7512c 100644 > --- a/hw/arm/imx25_pdk.c > +++ b/hw/arm/imx25_pdk.c > @@ -139,7 +139,7 @@ static void imx25_pdk_init(MachineState *machine) > * of simple qtest. See "make check" for details. > */ > i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(&s->soc.i2c[0]), > - "i2c"), > + "i2c.0"), > "ds1338", 0x68); or just : i2c_create_slave(s->soc.i2c[0].bus, "ds1338", 0x68); ? C. > } > } > diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c > index 37e5a62..7be10fb 100644 > --- a/hw/i2c/imx_i2c.c > +++ b/hw/i2c/imx_i2c.c > @@ -305,12 +305,16 @@ static const VMStateDescription imx_i2c_vmstate = { > static void imx_i2c_realize(DeviceState *dev, Error **errp) > { > IMXI2CState *s = IMX_I2C(dev); > + static int bus_count; > + char name[16]; > + > + snprintf(name, sizeof(name), "i2c.%d", bus_count++); > > memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C, > IMX_I2C_MEM_SIZE); > sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); > sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); > - s->bus = i2c_init_bus(DEVICE(dev), "i2c"); > + s->bus = i2c_init_bus(DEVICE(dev), name); > } > > static void imx_i2c_class_init(ObjectClass *klass, void *data) > ^ permalink raw reply [flat|nested] 22+ messages in thread
* [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts 2016-11-17 4:36 [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva 2016-11-17 4:36 ` [Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses Alastair D'Silva @ 2016-11-17 4:36 ` Alastair D'Silva 2016-11-22 17:22 ` Cédric Le Goater 2016-11-17 4:36 ` [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva ` (2 subsequent siblings) 4 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-17 4:36 UTC (permalink / raw) To: qemu-arm Cc: qemu-devel, Peter Maydell, Cédric Le Goater, Andrew Jeffery, Joel Stanley, Alastair D'Silva From: Alastair D'Silva <alastair@d-silva.org> The QTest framework cannot work with named interrupts. This patch adds support for them, as well as the ability to manipulate them from within a test. Read actions are via callbacks, which allows for pulsed interrupts to be read (the polled method used for the unnamed interrupts cannot read pulsed interrupts as the value is reverted before the test sees the changes). Signed-off-by: Alastair D'Silva <alastair@d-silva.org> --- qtest.c | 98 ++++++++++++++++++++++++++++++++++++++++++-------------- tests/libqtest.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++--- tests/libqtest.h | 59 ++++++++++++++++++++++++++++++++++ 3 files changed, 216 insertions(+), 28 deletions(-) diff --git a/qtest.c b/qtest.c index 46b99ae..a56503b 100644 --- a/qtest.c +++ b/qtest.c @@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev; static FILE *qtest_log_fp; static CharBackend qtest_chr; static GString *inbuf; -static int irq_levels[MAX_IRQ]; static qemu_timeval start_time; static bool qtest_opened; @@ -160,10 +159,16 @@ static bool qtest_opened; * * IRQ raise NUM * IRQ lower NUM + * IRQ_NAMED NAME NUM LEVEL * * where NUM is an IRQ number. For the PC, interrupts can be intercepted * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with * NUM=0 even though it is remapped to GSI 2). + * + * > irq_set NAME NUM LEVEL + * < OK + * + * Set the named input IRQ to the level (0/1) */ static int hex2nib(char ch) @@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr, va_end(ap); } +typedef struct qtest_irq { + qemu_irq old_irq; + char *name; + bool last_level; +} qtest_irq; + static void qtest_irq_handler(void *opaque, int n, int level) { - qemu_irq old_irq = *(qemu_irq *)opaque; - qemu_set_irq(old_irq, level); + qtest_irq *data = (qtest_irq *)opaque; + level = !!level; + + qemu_set_irq(data->old_irq, level); - if (irq_levels[n] != level) { + if (level != data->last_level) { CharBackend *chr = &qtest_chr; - irq_levels[n] = level; qtest_send_prefix(chr); - qtest_sendf(chr, "IRQ %s %d\n", - level ? "raise" : "lower", n); + + if (data->name) { + qtest_sendf(chr, "IRQ_NAMED %s %d %d\n", + data->name, n, level); + } else { + qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n); + } + + data->last_level = level; } } @@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (!dev) { qtest_send_prefix(chr); qtest_send(chr, "FAIL Unknown device\n"); - return; + return; } if (irq_intercept_dev) { @@ -299,33 +318,69 @@ static void qtest_process_command(CharBackend *chr, gchar **words) } else { qtest_send(chr, "OK\n"); } - return; + return; } QLIST_FOREACH(ngl, &dev->gpios, node) { - /* We don't support intercept of named GPIOs yet */ - if (ngl->name) { - continue; - } if (words[0][14] == 'o') { int i; for (i = 0; i < ngl->num_out; ++i) { - qemu_irq *disconnected = g_new0(qemu_irq, 1); - qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, - disconnected, i); + qtest_irq *data = g_new0(qtest_irq, 1); + data->name = ngl->name; + qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, data, + i); - *disconnected = qdev_intercept_gpio_out(dev, icpt, + data->old_irq = qdev_intercept_gpio_out(dev, icpt, ngl->name, i); } } else { - qemu_irq_intercept_in(ngl->in, qtest_irq_handler, - ngl->num_in); + qtest_irq *data = g_new0(qtest_irq, 1); + data->old_irq = *ngl->in; + data->name = ngl->name; + qemu_irq_intercept_in(ngl->in, qtest_irq_handler, ngl->num_in); } } irq_intercept_dev = dev; qtest_send_prefix(chr); qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "irq_set") == 0) { + DeviceState *dev; + NamedGPIOList *ngl; + int level; + qemu_irq irq = NULL; + int irq_num; + + g_assert(words[1]); /* device */ + g_assert(words[2]); /* gpio list */ + g_assert(words[3]); /* gpio line in list */ + g_assert(words[4]); /* level */ + dev = DEVICE(object_resolve_path(words[1], NULL)); + if (!dev) { + qtest_send_prefix(chr); + qtest_send(chr, "FAIL Unknown device\n"); + return; + } + + irq_num = atoi(words[3]); + level = atoi(words[4]); + + QLIST_FOREACH(ngl, &dev->gpios, node) { + if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > irq_num) { + irq = ngl->in[irq_num]; + } + } + + if (irq == NULL) { + qtest_send_prefix(chr); + qtest_send(chr, "FAIL Unknown IRQ\n"); + return; + } + + qemu_set_irq(irq, level); + + qtest_send_prefix(chr); + qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "outb") == 0 || strcmp(words[0], "outw") == 0 || strcmp(words[0], "outl") == 0) { @@ -622,8 +677,6 @@ static int qtest_can_read(void *opaque) static void qtest_event(void *opaque, int event) { - int i; - switch (event) { case CHR_EVENT_OPENED: /* @@ -632,9 +685,6 @@ static void qtest_event(void *opaque, int event) * used. Injects an extra reset even when it's not used, and * that can mess up tests, e.g. -boot once. */ - for (i = 0; i < ARRAY_SIZE(irq_levels); i++) { - irq_levels[i] = 0; - } qemu_gettimeofday(&start_time); qtest_opened = true; if (qtest_log_fp) { diff --git a/tests/libqtest.c b/tests/libqtest.c index 6f69752..43da151 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -21,12 +21,16 @@ #include <sys/wait.h> #include <sys/un.h> +#include <glib.h> + #include "qapi/qmp/json-parser.h" #include "qapi/qmp/json-streamer.h" #include "qapi/qmp/qjson.h" + #define MAX_IRQ 256 #define SOCKET_TIMEOUT 50 +#define IRQ_KEY_LENGTH 64 QTestState *global_qtest; @@ -34,12 +38,22 @@ struct QTestState { int fd; int qmp_fd; + GHashTable *irq_handlers; bool irq_level[MAX_IRQ]; GString *rx; pid_t qemu_pid; /* our child QEMU process */ bool big_endian; }; +typedef struct irq_action { + void (*cb)(void *opaque, const char *name, int irq, bool level); + void *opaque; + const char *name; + int n; + bool level; +} irq_action; + + static GHookList abrt_hooks; static GList *qtest_instances; static struct sigaction sigact_old; @@ -216,6 +230,8 @@ QTestState *qtest_init(const char *extra_args) s->big_endian = qtest_query_target_endianness(s); + s->irq_handlers = g_hash_table_new_full(g_str_hash, g_str_equal, g_free, g_free); + return s; } @@ -224,6 +240,8 @@ void qtest_quit(QTestState *s) qtest_instances = g_list_remove(qtest_instances, s); g_hook_destroy_link(&abrt_hooks, g_hook_find_data(&abrt_hooks, TRUE, s)); + g_hash_table_destroy(s->irq_handlers); + /* Uninstall SIGABRT handler on last instance */ if (!qtest_instances) { cleanup_sigabrt_handler(); @@ -304,11 +322,35 @@ static GString *qtest_recv_line(QTestState *s) return line; } +void qtest_irq_attach(QTestState *s, const char *name, int irq, + void (*irq_cb)(void *opaque, const char *name, int irq, bool level), + void *opaque) +{ + char key[IRQ_KEY_LENGTH]; + irq_action *action = g_new0(irq_action, 1); + + action->cb = irq_cb; + action->name = name; + action->n = irq; + action->opaque = opaque; + action->level = false; + + g_assert_cmpint(snprintf(key, sizeof(key), "%s.%d", + name, irq), <, sizeof(key)); + + g_hash_table_insert(s->irq_handlers, g_strdup(key), action); +} + +#define MAX_ACTIONS 256 static gchar **qtest_rsp(QTestState *s, int expected_args) { GString *line; gchar **words; int i; + int action_index; + int action_count = 0; + bool action_raise[MAX_ACTIONS]; + irq_action *actions[MAX_ACTIONS]; redo: line = qtest_recv_line(s); @@ -325,10 +367,29 @@ redo: g_assert_cmpint(irq, >=, 0); g_assert_cmpint(irq, <, MAX_IRQ); - if (strcmp(words[1], "raise") == 0) { - s->irq_level[irq] = true; - } else { - s->irq_level[irq] = false; + s->irq_level[irq] = (strcmp(words[1], "raise") == 0); + + g_strfreev(words); + goto redo; + } else if (strcmp(words[0], "IRQ_NAMED") == 0) { + bool level; + char key[IRQ_KEY_LENGTH]; + irq_action *action; + + g_assert(words[1] != NULL); + g_assert(words[2] != NULL); + g_assert(words[3] != NULL); + + level = (words[3][0] == '1'); + + g_assert_cmpint(snprintf(key, sizeof(key), "%s.%s", + words[1], words[2]), <, sizeof(key)); + + action = g_hash_table_lookup(s->irq_handlers, key); + + if (action) { + action_raise[action_count] = level; + actions[action_count++] = action; } g_strfreev(words); @@ -346,6 +407,17 @@ redo: g_strfreev(words); } +/* Defer processing of IRQ actions until all communications have been handled, + * otherwise, interrupt handler that cause further communication can disrupt + * the communication stream + */ + for (action_index = 0; action_index < action_count; action_index++) { + irq_action *action = actions[action_index]; + action->cb(action->opaque, action->name, action->n, + action_raise[action_index]); + action->level = action_raise[action_index]; + } + return words; } @@ -918,3 +990,10 @@ bool qtest_big_endian(QTestState *s) { return s->big_endian; } + +void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n, + bool level) +{ + qtest_sendf(s, "irq_set %s %s %d %d\n", id, gpiolist, n, level); + qtest_rsp(s, 0); +} diff --git a/tests/libqtest.h b/tests/libqtest.h index 90f182e..c74373c 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -176,6 +176,34 @@ void qtest_irq_intercept_in(QTestState *s, const char *string); void qtest_irq_intercept_out(QTestState *s, const char *string); /** + * irq_attach: + * @s: #QTestState instance to operate on. + * @name: the name of the GPIO list containing the IRQ + * @irq: The IRQ number within the GPIO list to attach to + * @irq_cb: The callback to execute when the interrupt changes + * @opaque: opaque info to pass to the callback + * + * Attach a callback to an intercepted interrupt + */ +void qtest_irq_attach(QTestState *s, const char *name, int irq, + void (*irq_cb)(void *opaque, const char *name, int irq, bool level), + void *opaque); + +/** + * qtest_irq_set + * Set an interrupt level + * @s: #QTestState instance to operate on. + * @id: the device to inject interrupts for + * @gpiolist: the GPIO list containing the IRQ + * @n: the GPIO within the list + * @level: the IRQ level + * + * Set an interrupt to a nominated level + */ +void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n, + bool level); + +/** * qtest_outb: * @s: #QTestState instance to operate on. * @addr: I/O port to write to. @@ -626,6 +654,37 @@ static inline void irq_intercept_out(const char *string) } /** + * irq_attach: + * @name: the name of the gpio list containing the IRQ + * @irq: The IRQ to attach to + * @irq_cb: The callback to execute when the interrupt changes + * @opaque: opaque info to pass to the callback + * + * Attach a callback to an intecepted interrupt + */ +static inline void irq_attach(const char *name, int irq, + void (*irq_cb)(void *opaque, const char *name, int irq, bool level), + void *opaque) +{ + qtest_irq_attach(global_qtest, name, irq, irq_cb, opaque); +} + +/** + * qtest_irq_set + * Set an interrupt level + * @id: the device to inject interrupts for + * @gpiolist: the GPIO list containing the line to seh + * @n: the line to set within the list + * @level: the IRQ level + */ +static inline void irq_set(const char *id, const char *gpiolist, int n, + bool level) +{ + qtest_irq_set(global_qtest, id, gpiolist, n, level); +} + + +/** * outb: * @addr: I/O port to write to. * @value: Value being written. -- 2.7.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts 2016-11-17 4:36 ` [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts Alastair D'Silva @ 2016-11-22 17:22 ` Cédric Le Goater 2016-11-22 17:24 ` Paolo Bonzini 0 siblings, 1 reply; 22+ messages in thread From: Cédric Le Goater @ 2016-11-22 17:22 UTC (permalink / raw) To: Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley, Alastair D'Silva, Paolo Bonzini On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > From: Alastair D'Silva <alastair@d-silva.org> > > The QTest framework cannot work with named interrupts. This patch > adds support for them, as well as the ability to manipulate them > from within a test. > > Read actions are via callbacks, which allows for pulsed interrupts > to be read (the polled method used for the unnamed interrupts > cannot read pulsed interrupts as the value is reverted before the > test sees the changes). > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> This looks OK to me but I am clearly not an expert in this area. Maybe Paolo has some comments to add. Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > qtest.c | 98 ++++++++++++++++++++++++++++++++++++++++++-------------- > tests/libqtest.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++--- > tests/libqtest.h | 59 ++++++++++++++++++++++++++++++++++ > 3 files changed, 216 insertions(+), 28 deletions(-) > > diff --git a/qtest.c b/qtest.c > index 46b99ae..a56503b 100644 > --- a/qtest.c > +++ b/qtest.c > @@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev; > static FILE *qtest_log_fp; > static CharBackend qtest_chr; > static GString *inbuf; > -static int irq_levels[MAX_IRQ]; > static qemu_timeval start_time; > static bool qtest_opened; > > @@ -160,10 +159,16 @@ static bool qtest_opened; > * > * IRQ raise NUM > * IRQ lower NUM > + * IRQ_NAMED NAME NUM LEVEL > * > * where NUM is an IRQ number. For the PC, interrupts can be intercepted > * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with > * NUM=0 even though it is remapped to GSI 2). > + * > + * > irq_set NAME NUM LEVEL > + * < OK > + * > + * Set the named input IRQ to the level (0/1) > */ > > static int hex2nib(char ch) > @@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr, > va_end(ap); > } > > +typedef struct qtest_irq { > + qemu_irq old_irq; > + char *name; > + bool last_level; > +} qtest_irq; > + > static void qtest_irq_handler(void *opaque, int n, int level) > { > - qemu_irq old_irq = *(qemu_irq *)opaque; > - qemu_set_irq(old_irq, level); > + qtest_irq *data = (qtest_irq *)opaque; > + level = !!level; > + > + qemu_set_irq(data->old_irq, level); > > - if (irq_levels[n] != level) { > + if (level != data->last_level) { > CharBackend *chr = &qtest_chr; > - irq_levels[n] = level; > qtest_send_prefix(chr); > - qtest_sendf(chr, "IRQ %s %d\n", > - level ? "raise" : "lower", n); > + > + if (data->name) { > + qtest_sendf(chr, "IRQ_NAMED %s %d %d\n", > + data->name, n, level); > + } else { > + qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n); > + } > + > + data->last_level = level; > } > } > > @@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) > if (!dev) { > qtest_send_prefix(chr); > qtest_send(chr, "FAIL Unknown device\n"); > - return; > + return; > } > > if (irq_intercept_dev) { > @@ -299,33 +318,69 @@ static void qtest_process_command(CharBackend *chr, gchar **words) > } else { > qtest_send(chr, "OK\n"); > } > - return; > + return; > } > > QLIST_FOREACH(ngl, &dev->gpios, node) { > - /* We don't support intercept of named GPIOs yet */ > - if (ngl->name) { > - continue; > - } > if (words[0][14] == 'o') { > int i; > for (i = 0; i < ngl->num_out; ++i) { > - qemu_irq *disconnected = g_new0(qemu_irq, 1); > - qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, > - disconnected, i); > + qtest_irq *data = g_new0(qtest_irq, 1); > + data->name = ngl->name; > + qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, data, > + i); > > - *disconnected = qdev_intercept_gpio_out(dev, icpt, > + data->old_irq = qdev_intercept_gpio_out(dev, icpt, > ngl->name, i); > } > } else { > - qemu_irq_intercept_in(ngl->in, qtest_irq_handler, > - ngl->num_in); > + qtest_irq *data = g_new0(qtest_irq, 1); > + data->old_irq = *ngl->in; > + data->name = ngl->name; > + qemu_irq_intercept_in(ngl->in, qtest_irq_handler, ngl->num_in); > } > } > irq_intercept_dev = dev; > qtest_send_prefix(chr); > qtest_send(chr, "OK\n"); > > + } else if (strcmp(words[0], "irq_set") == 0) { > + DeviceState *dev; > + NamedGPIOList *ngl; > + int level; > + qemu_irq irq = NULL; > + int irq_num; > + > + g_assert(words[1]); /* device */ > + g_assert(words[2]); /* gpio list */ > + g_assert(words[3]); /* gpio line in list */ > + g_assert(words[4]); /* level */ > + dev = DEVICE(object_resolve_path(words[1], NULL)); > + if (!dev) { > + qtest_send_prefix(chr); > + qtest_send(chr, "FAIL Unknown device\n"); > + return; > + } > + > + irq_num = atoi(words[3]); > + level = atoi(words[4]); > + > + QLIST_FOREACH(ngl, &dev->gpios, node) { > + if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > irq_num) { > + irq = ngl->in[irq_num]; > + } > + } > + > + if (irq == NULL) { > + qtest_send_prefix(chr); > + qtest_send(chr, "FAIL Unknown IRQ\n"); > + return; > + } > + > + qemu_set_irq(irq, level); > + > + qtest_send_prefix(chr); > + qtest_send(chr, "OK\n"); > } else if (strcmp(words[0], "outb") == 0 || > strcmp(words[0], "outw") == 0 || > strcmp(words[0], "outl") == 0) { > @@ -622,8 +677,6 @@ static int qtest_can_read(void *opaque) > > static void qtest_event(void *opaque, int event) > { > - int i; > - > switch (event) { > case CHR_EVENT_OPENED: > /* > @@ -632,9 +685,6 @@ static void qtest_event(void *opaque, int event) > * used. Injects an extra reset even when it's not used, and > * that can mess up tests, e.g. -boot once. > */ > - for (i = 0; i < ARRAY_SIZE(irq_levels); i++) { > - irq_levels[i] = 0; > - } > qemu_gettimeofday(&start_time); > qtest_opened = true; > if (qtest_log_fp) { > diff --git a/tests/libqtest.c b/tests/libqtest.c > index 6f69752..43da151 100644 > --- a/tests/libqtest.c > +++ b/tests/libqtest.c > @@ -21,12 +21,16 @@ > #include <sys/wait.h> > #include <sys/un.h> > > +#include <glib.h> > + > #include "qapi/qmp/json-parser.h" > #include "qapi/qmp/json-streamer.h" > #include "qapi/qmp/qjson.h" > > + > #define MAX_IRQ 256 > #define SOCKET_TIMEOUT 50 > +#define IRQ_KEY_LENGTH 64 > > QTestState *global_qtest; > > @@ -34,12 +38,22 @@ struct QTestState > { > int fd; > int qmp_fd; > + GHashTable *irq_handlers; > bool irq_level[MAX_IRQ]; > GString *rx; > pid_t qemu_pid; /* our child QEMU process */ > bool big_endian; > }; > > +typedef struct irq_action { > + void (*cb)(void *opaque, const char *name, int irq, bool level); > + void *opaque; > + const char *name; > + int n; > + bool level; > +} irq_action; > + > + > static GHookList abrt_hooks; > static GList *qtest_instances; > static struct sigaction sigact_old; > @@ -216,6 +230,8 @@ QTestState *qtest_init(const char *extra_args) > > s->big_endian = qtest_query_target_endianness(s); > > + s->irq_handlers = g_hash_table_new_full(g_str_hash, g_str_equal, g_free, g_free); > + > return s; > } > > @@ -224,6 +240,8 @@ void qtest_quit(QTestState *s) > qtest_instances = g_list_remove(qtest_instances, s); > g_hook_destroy_link(&abrt_hooks, g_hook_find_data(&abrt_hooks, TRUE, s)); > > + g_hash_table_destroy(s->irq_handlers); > + > /* Uninstall SIGABRT handler on last instance */ > if (!qtest_instances) { > cleanup_sigabrt_handler(); > @@ -304,11 +322,35 @@ static GString *qtest_recv_line(QTestState *s) > return line; > } > > +void qtest_irq_attach(QTestState *s, const char *name, int irq, > + void (*irq_cb)(void *opaque, const char *name, int irq, bool level), > + void *opaque) > +{ > + char key[IRQ_KEY_LENGTH]; > + irq_action *action = g_new0(irq_action, 1); > + > + action->cb = irq_cb; > + action->name = name; > + action->n = irq; > + action->opaque = opaque; > + action->level = false; > + > + g_assert_cmpint(snprintf(key, sizeof(key), "%s.%d", > + name, irq), <, sizeof(key)); > + > + g_hash_table_insert(s->irq_handlers, g_strdup(key), action); > +} > + > +#define MAX_ACTIONS 256 > static gchar **qtest_rsp(QTestState *s, int expected_args) > { > GString *line; > gchar **words; > int i; > + int action_index; > + int action_count = 0; > + bool action_raise[MAX_ACTIONS]; > + irq_action *actions[MAX_ACTIONS]; > > redo: > line = qtest_recv_line(s); > @@ -325,10 +367,29 @@ redo: > g_assert_cmpint(irq, >=, 0); > g_assert_cmpint(irq, <, MAX_IRQ); > > - if (strcmp(words[1], "raise") == 0) { > - s->irq_level[irq] = true; > - } else { > - s->irq_level[irq] = false; > + s->irq_level[irq] = (strcmp(words[1], "raise") == 0); > + > + g_strfreev(words); > + goto redo; > + } else if (strcmp(words[0], "IRQ_NAMED") == 0) { > + bool level; > + char key[IRQ_KEY_LENGTH]; > + irq_action *action; > + > + g_assert(words[1] != NULL); > + g_assert(words[2] != NULL); > + g_assert(words[3] != NULL); > + > + level = (words[3][0] == '1'); > + > + g_assert_cmpint(snprintf(key, sizeof(key), "%s.%s", > + words[1], words[2]), <, sizeof(key)); > + > + action = g_hash_table_lookup(s->irq_handlers, key); > + > + if (action) { > + action_raise[action_count] = level; > + actions[action_count++] = action; > } > > g_strfreev(words); > @@ -346,6 +407,17 @@ redo: > g_strfreev(words); > } > > +/* Defer processing of IRQ actions until all communications have been handled, > + * otherwise, interrupt handler that cause further communication can disrupt > + * the communication stream > + */ > + for (action_index = 0; action_index < action_count; action_index++) { > + irq_action *action = actions[action_index]; > + action->cb(action->opaque, action->name, action->n, > + action_raise[action_index]); > + action->level = action_raise[action_index]; > + } > + > return words; > } > > @@ -918,3 +990,10 @@ bool qtest_big_endian(QTestState *s) > { > return s->big_endian; > } > + > +void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n, > + bool level) > +{ > + qtest_sendf(s, "irq_set %s %s %d %d\n", id, gpiolist, n, level); > + qtest_rsp(s, 0); > +} > diff --git a/tests/libqtest.h b/tests/libqtest.h > index 90f182e..c74373c 100644 > --- a/tests/libqtest.h > +++ b/tests/libqtest.h > @@ -176,6 +176,34 @@ void qtest_irq_intercept_in(QTestState *s, const char *string); > void qtest_irq_intercept_out(QTestState *s, const char *string); > > /** > + * irq_attach: > + * @s: #QTestState instance to operate on. > + * @name: the name of the GPIO list containing the IRQ > + * @irq: The IRQ number within the GPIO list to attach to > + * @irq_cb: The callback to execute when the interrupt changes > + * @opaque: opaque info to pass to the callback > + * > + * Attach a callback to an intercepted interrupt > + */ > +void qtest_irq_attach(QTestState *s, const char *name, int irq, > + void (*irq_cb)(void *opaque, const char *name, int irq, bool level), > + void *opaque); > + > +/** > + * qtest_irq_set > + * Set an interrupt level > + * @s: #QTestState instance to operate on. > + * @id: the device to inject interrupts for > + * @gpiolist: the GPIO list containing the IRQ > + * @n: the GPIO within the list > + * @level: the IRQ level > + * > + * Set an interrupt to a nominated level > + */ > +void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n, > + bool level); > + > +/** > * qtest_outb: > * @s: #QTestState instance to operate on. > * @addr: I/O port to write to. > @@ -626,6 +654,37 @@ static inline void irq_intercept_out(const char *string) > } > > /** > + * irq_attach: > + * @name: the name of the gpio list containing the IRQ > + * @irq: The IRQ to attach to > + * @irq_cb: The callback to execute when the interrupt changes > + * @opaque: opaque info to pass to the callback > + * > + * Attach a callback to an intecepted interrupt > + */ > +static inline void irq_attach(const char *name, int irq, > + void (*irq_cb)(void *opaque, const char *name, int irq, bool level), > + void *opaque) > +{ > + qtest_irq_attach(global_qtest, name, irq, irq_cb, opaque); > +} > + > +/** > + * qtest_irq_set > + * Set an interrupt level > + * @id: the device to inject interrupts for > + * @gpiolist: the GPIO list containing the line to seh > + * @n: the line to set within the list > + * @level: the IRQ level > + */ > +static inline void irq_set(const char *id, const char *gpiolist, int n, > + bool level) > +{ > + qtest_irq_set(global_qtest, id, gpiolist, n, level); > +} > + > + > +/** > * outb: > * @addr: I/O port to write to. > * @value: Value being written. > ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts 2016-11-22 17:22 ` Cédric Le Goater @ 2016-11-22 17:24 ` Paolo Bonzini 2016-11-22 22:31 ` Alastair D'Silva 0 siblings, 1 reply; 22+ messages in thread From: Paolo Bonzini @ 2016-11-22 17:24 UTC (permalink / raw) To: Cédric Le Goater, Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley, Alastair D'Silva On 22/11/2016 18:22, Cédric Le Goater wrote: >> + >> + g_assert(words[1]); /* device */ >> + g_assert(words[2]); /* gpio list */ >> + g_assert(words[3]); /* gpio line in list */ >> + g_assert(words[4]); /* level */ >> + dev = DEVICE(object_resolve_path(words[1], NULL)); >> + if (!dev) { >> + qtest_send_prefix(chr); >> + qtest_send(chr, "FAIL Unknown device\n"); >> + return; >> + } >> + >> + irq_num = atoi(words[3]); >> + level = atoi(words[4]); >> + >> + QLIST_FOREACH(ngl, &dev->gpios, node) { >> + if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > irq_num) { >> + irq = ngl->in[irq_num]; >> + } >> + } >> + >> + if (irq == NULL) { >> + qtest_send_prefix(chr); >> + qtest_send(chr, "FAIL Unknown IRQ\n"); >> + return; >> + } >> + >> + qemu_set_irq(irq, level); This seems wrong. The IRQ should not be modifiable by the test. Paolo >> + >> + qtest_send_prefix(chr); >> + qtest_send(chr, "OK\n"); ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts 2016-11-22 17:24 ` Paolo Bonzini @ 2016-11-22 22:31 ` Alastair D'Silva 2016-11-22 22:39 ` Paolo Bonzini 0 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-22 22:31 UTC (permalink / raw) To: Paolo Bonzini, Cédric Le Goater, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley On Tue, 2016-11-22 at 18:24 +0100, Paolo Bonzini wrote: > > On 22/11/2016 18:22, Cédric Le Goater wrote: > > > > > > > > + > > > + g_assert(words[1]); /* device */ > > > + g_assert(words[2]); /* gpio list */ > > > + g_assert(words[3]); /* gpio line in list */ > > > + g_assert(words[4]); /* level */ > > > + dev = DEVICE(object_resolve_path(words[1], NULL)); > > > + if (!dev) { > > > + qtest_send_prefix(chr); > > > + qtest_send(chr, "FAIL Unknown device\n"); > > > + return; > > > + } > > > + > > > + irq_num = atoi(words[3]); > > > + level = atoi(words[4]); > > > + > > > + QLIST_FOREACH(ngl, &dev->gpios, node) { > > > + if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > > > > irq_num) { > > > + irq = ngl->in[irq_num]; > > > + } > > > + } > > > + > > > + if (irq == NULL) { > > > + qtest_send_prefix(chr); > > > + qtest_send(chr, "FAIL Unknown IRQ\n"); > > > + return; > > > + } > > > + > > > + qemu_set_irq(irq, level); > > This seems wrong. The IRQ should not be modifiable by the test. > > Paolo > Thanks Paolo, could you please advise as to why that is? The situation I am addressing is that I device under test that changes behaviour when a GPIO line is raised. Is there another way I should be raising that line from within qtest? -- Alastair D'Silva Open Source Developer Linux Technology Centre, IBM Australia mob: 0423 762 819 ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts 2016-11-22 22:31 ` Alastair D'Silva @ 2016-11-22 22:39 ` Paolo Bonzini 2016-11-22 23:19 ` Alastair D'Silva 0 siblings, 1 reply; 22+ messages in thread From: Paolo Bonzini @ 2016-11-22 22:39 UTC (permalink / raw) To: Alastair D'Silva, Cédric Le Goater, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley On 22/11/2016 23:31, Alastair D'Silva wrote: >>>> > > > + if (irq == NULL) { >>>> > > > + qtest_send_prefix(chr); >>>> > > > + qtest_send(chr, "FAIL Unknown IRQ\n"); >>>> > > > + return; >>>> > > > + } >>>> > > > + >>>> > > > + qemu_set_irq(irq, level); >> > >> > This seems wrong. The IRQ should not be modifiable by the test. >> > >> > Paolo >> > > Thanks Paolo, could you please advise as to why that is? > > The situation I am addressing is that I device under test that changes > behaviour when a GPIO line is raised. Is there another way I should be > raising that line from within qtest? What causes the GPIO line to be raised in the normal emulated case? Paolo ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts 2016-11-22 22:39 ` Paolo Bonzini @ 2016-11-22 23:19 ` Alastair D'Silva 2016-11-23 9:43 ` Paolo Bonzini 0 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-22 23:19 UTC (permalink / raw) To: Paolo Bonzini, Cédric Le Goater, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley On Tue, 2016-11-22 at 23:39 +0100, Paolo Bonzini wrote: > On 22/11/2016 23:31, Alastair D'Silva wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > + if (irq == NULL) { > > > > > > > > + qtest_send_prefix(chr); > > > > > > > > + qtest_send(chr, "FAIL Unknown IRQ\n"); > > > > > > > > + return; > > > > > > > > + } > > > > > > > > + > > > > > > > > + qemu_set_irq(irq, level); > > > > > > > > This seems wrong. The IRQ should not be modifiable by the > > > > test. > > > > > > > > Paolo > > > > > > Thanks Paolo, could you please advise as to why that is? Could you answer this please? I would like to understand why. > > The situation I am addressing is that I device under test that > > changes > > behaviour when a GPIO line is raised. Is there another way I should > > be > > raising that line from within qtest? > > What causes the GPIO line to be raised in the normal emulated case? > > It would be wired to a GPIO line from the host microcontroller, under software control. In this test case, the device is connected to a "borrowed" board via the command line: snprintf(args, sizeof(args), "-display none -machine imx25-pdk " "-device rx8900,bus=i2c.0,address=0x%x,id=%s", RX8900_ADDR, RX8900_TEST_ID); I couldn't see a way to wire in the the GPIO to the host via the command line, but even if there was, manipulating it would require manipulating the host CPU, which would broaden the scope of the test. At the moment, the test has no dependency on/interaction with the host CPU, it's just using it to provide an I2C bus. -- Alastair D'Silva Open Source Developer Linux Technology Centre, IBM Australia mob: 0423 762 819 ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts 2016-11-22 23:19 ` Alastair D'Silva @ 2016-11-23 9:43 ` Paolo Bonzini 2016-11-23 10:05 ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias 0 siblings, 1 reply; 22+ messages in thread From: Paolo Bonzini @ 2016-11-23 9:43 UTC (permalink / raw) To: Alastair D'Silva Cc: Cédric Le Goater, qemu-arm, qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley ----- Original Message ----- > From: "Alastair D'Silva" <alastair@au1.ibm.com> > To: "Paolo Bonzini" <pbonzini@redhat.com>, "Cédric Le Goater" <clg@kaod.org>, qemu-arm@nongnu.org > Cc: qemu-devel@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>, "Andrew Jeffery" <andrew@aj.id.au>, "Joel > Stanley" <joel@jms.id.au> > Sent: Wednesday, November 23, 2016 12:19:50 AM > Subject: Re: [PATCH 2/4] qtest: Support named interrupts > > On Tue, 2016-11-22 at 23:39 +0100, Paolo Bonzini wrote: > > On 22/11/2016 23:31, Alastair D'Silva wrote: > > > > > > > > This seems wrong. The IRQ should not be modifiable by the > > > > test. > > > > > > Thanks Paolo, could you please advise as to why that is? > > Could you answer this please? I would like to understand why. Well, I didn't know yet until I knew what the GPIO line was for. :) But in general, the idea is that the qtest acts as the CPU. The test cases can control the passing of time precisely, and they can _observe_ additional events (such as interrupts or GPIO lines) but they don't inject anything that the CPU cannot inject. The reason is to make the tests more like small programs. It does mean that you are limited by the connections of the board. > > > The situation I am addressing is that I device under test that > > > changes > > > behaviour when a GPIO line is raised. Is there another way I should > > > be > > > raising that line from within qtest? > > > > What causes the GPIO line to be raised in the normal emulated case? > > It would be wired to a GPIO line from the host microcontroller, under > software control. Note I said the normal emulated case, not the real hardware case. Is there a GPIO controller that is not yet part of the ASpeed models? If the emulated ASpeed board cannot yet work with FOut, I would just leave it out of the testcases. Paolo > In this test case, the device is connected to a "borrowed" board via > the command line: > snprintf(args, sizeof(args), "-display none -machine imx25-pdk " > "-device rx8900,bus=i2c.0,address=0x%x,id=%s", > RX8900_ADDR, RX8900_TEST_ID); > > I couldn't see a way to wire in the the GPIO to the host via the > command line, but even if there was, manipulating it would require > manipulating the host CPU, which would broaden the scope of the test. > At the moment, the test has no dependency on/interaction with the host > CPU, it's just using it to provide an I2C bus. ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 2/4] qtest: Support named interrupts 2016-11-23 9:43 ` Paolo Bonzini @ 2016-11-23 10:05 ` Edgar E. Iglesias 2016-11-23 10:34 ` Paolo Bonzini 0 siblings, 1 reply; 22+ messages in thread From: Edgar E. Iglesias @ 2016-11-23 10:05 UTC (permalink / raw) To: Paolo Bonzini Cc: Alastair D'Silva, Peter Maydell, Andrew Jeffery, qemu-devel, qemu-arm, Joel Stanley, Cédric Le Goater On Wed, Nov 23, 2016 at 04:43:01AM -0500, Paolo Bonzini wrote: > > > ----- Original Message ----- > > From: "Alastair D'Silva" <alastair@au1.ibm.com> > > To: "Paolo Bonzini" <pbonzini@redhat.com>, "Cédric Le Goater" <clg@kaod.org>, qemu-arm@nongnu.org > > Cc: qemu-devel@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>, "Andrew Jeffery" <andrew@aj.id.au>, "Joel > > Stanley" <joel@jms.id.au> > > Sent: Wednesday, November 23, 2016 12:19:50 AM > > Subject: Re: [PATCH 2/4] qtest: Support named interrupts > > > > On Tue, 2016-11-22 at 23:39 +0100, Paolo Bonzini wrote: > > > On 22/11/2016 23:31, Alastair D'Silva wrote: > > > > > > > > > > This seems wrong. The IRQ should not be modifiable by the > > > > > test. > > > > > > > > Thanks Paolo, could you please advise as to why that is? > > > > Could you answer this please? I would like to understand why. > > Well, I didn't know yet until I knew what the GPIO line was for. :) > > But in general, the idea is that the qtest acts as the CPU. The test > cases can control the passing of time precisely, and they can _observe_ > additional events (such as interrupts or GPIO lines) but they don't inject > anything that the CPU cannot inject. The reason is to make the tests > more like small programs. It does mean that you are limited by the > connections of the board. Hi Paolo, At some point we added support for using Qtest together with emulated CPUs. In those cases, Qtest acts more like a test access port that can access stuff within the VM. It can be used to test devices in combination with guest SW. IMO, raising and lowering signals is useful and extending it to support named interrupts seems like a useful feature to me... Best regards, Edgar > > > > > The situation I am addressing is that I device under test that > > > > changes > > > > behaviour when a GPIO line is raised. Is there another way I should > > > > be > > > > raising that line from within qtest? > > > > > > What causes the GPIO line to be raised in the normal emulated case? > > > > It would be wired to a GPIO line from the host microcontroller, under > > software control. > > Note I said the normal emulated case, not the real hardware case. > Is there a GPIO controller that is not yet part of the ASpeed models? > > If the emulated ASpeed board cannot yet work with FOut, I would just > leave it out of the testcases. > > Paolo > > > In this test case, the device is connected to a "borrowed" board via > > the command line: > > snprintf(args, sizeof(args), "-display none -machine imx25-pdk " > > "-device rx8900,bus=i2c.0,address=0x%x,id=%s", > > RX8900_ADDR, RX8900_TEST_ID); > > > > I couldn't see a way to wire in the the GPIO to the host via the > > command line, but even if there was, manipulating it would require > > manipulating the host CPU, which would broaden the scope of the test. > > > At the moment, the test has no dependency on/interaction with the host > > CPU, it's just using it to provide an I2C bus. > ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 2/4] qtest: Support named interrupts 2016-11-23 10:05 ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias @ 2016-11-23 10:34 ` Paolo Bonzini 0 siblings, 0 replies; 22+ messages in thread From: Paolo Bonzini @ 2016-11-23 10:34 UTC (permalink / raw) To: Edgar E. Iglesias Cc: Peter Maydell, Alastair D'Silva, Andrew Jeffery, qemu-devel, qemu-arm, Joel Stanley, Cédric Le Goater On 23/11/2016 11:05, Edgar E. Iglesias wrote: >> > >> > But in general, the idea is that the qtest acts as the CPU. The test >> > cases can control the passing of time precisely, and they can _observe_ >> > additional events (such as interrupts or GPIO lines) but they don't inject >> > anything that the CPU cannot inject. The reason is to make the tests >> > more like small programs. It does mean that you are limited by the >> > connections of the board. > Hi Paolo, > > At some point we added support for using Qtest together with emulated > CPUs. In those cases, Qtest acts more like a test access port that can > access stuff within the VM. It can be used to test devices in combination > with guest SW. > > IMO, raising and lowering signals is useful and extending it to support > named interrupts seems like a useful feature to me... Fair enough! Paolo ^ permalink raw reply [flat|nested] 22+ messages in thread
* [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support 2016-11-17 4:36 [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva 2016-11-17 4:36 ` [Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses Alastair D'Silva 2016-11-17 4:36 ` [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts Alastair D'Silva @ 2016-11-17 4:36 ` Alastair D'Silva 2016-11-17 8:29 ` Cédric Le Goater 2016-11-17 4:36 ` [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board Alastair D'Silva 2016-11-17 15:33 ` [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board no-reply 4 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-17 4:36 UTC (permalink / raw) To: qemu-arm Cc: qemu-devel, Peter Maydell, Cédric Le Goater, Andrew Jeffery, Joel Stanley, Alastair D'Silva From: Alastair D'Silva <alastair@d-silva.org> This patch adds support for the Epson RX8900 RTC chip. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> --- default-configs/arm-softmmu.mak | 1 + hw/timer/Makefile.objs | 2 + hw/timer/rx8900.c | 891 ++++++++++++++++++++++++++++++++++++++++ hw/timer/rx8900_regs.h | 125 ++++++ tests/Makefile.include | 2 + tests/rx8900-test.c | 800 ++++++++++++++++++++++++++++++++++++ 6 files changed, 1821 insertions(+) create mode 100644 hw/timer/rx8900.c create mode 100644 hw/timer/rx8900_regs.h create mode 100644 tests/rx8900-test.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 6de3e16..adb600e 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y CONFIG_ALLWINNER_EMAC=y CONFIG_IMX_FEC=y CONFIG_DS1338=y +CONFIG_RX8900=y CONFIG_PFLASH_CFI01=y CONFIG_PFLASH_CFI02=y CONFIG_MICRODRIVE=y diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 7ba8c23..fa028ac 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o common-obj-$(CONFIG_CADENCE) += cadence_ttc.o common-obj-$(CONFIG_DS1338) += ds1338.o +common-obj-$(CONFIG_RX8900) += rx8900.o common-obj-$(CONFIG_HPET) += hpet.o common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o common-obj-$(CONFIG_M48T59) += m48t59.o @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o common-obj-$(CONFIG_IMX) += imx_gpt.o common-obj-$(CONFIG_LM32) += lm32_timer.o common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o +common-obj-$(CONFIG_RX8900) += rx8900.o obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c new file mode 100644 index 0000000..208a31b --- /dev/null +++ b/hw/timer/rx8900.c @@ -0,0 +1,891 @@ +/* + * Epson RX8900SA/CE Realtime Clock Module + * + * Copyright (c) 2016 IBM Corporation + * Authors: + * Alastair D'Silva <alastair@d-silva.org> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + * Datasheet available at: + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE&lang=en + * + * Not implemented: + * Implement Timer Counters + * Implement i2c timeout + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/i2c/i2c.h" +#include "hw/timer/rx8900_regs.h" +#include "hw/ptimer.h" +#include "qemu/main-loop.h" +#include "qemu/bcd.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "qapi/visitor.h" + + #include <sys/time.h> + + #include <execinfo.h> + +#define TYPE_RX8900 "rx8900" +#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900) + +static bool log; + +typedef struct RX8900State { + I2CSlave parent_obj; + + ptimer_state *sec_timer; /* triggered once per second */ + ptimer_state *fout_timer; + ptimer_state *countdown_timer; + bool fout; + int64_t offset; + uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */ + uint8_t wday_offset; + uint8_t nvram[RX8900_NVRAM_SIZE]; + int32_t ptr; /* Wrapped to stay within RX8900_NVRAM_SIZE */ + bool addr_byte; + uint8_t last_interrupt_seconds; + uint8_t last_update_interrupt_minutes; + qemu_irq interrupt_pin; + qemu_irq fout_pin; +} RX8900State; + +static const VMStateDescription vmstate_rx8900 = { + .name = "rx8900", + .version_id = 2, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_I2C_SLAVE(parent_obj, RX8900State), + VMSTATE_PTIMER(sec_timer, RX8900State), + VMSTATE_PTIMER(fout_timer, RX8900State), + VMSTATE_PTIMER(countdown_timer, RX8900State), + VMSTATE_BOOL(fout, RX8900State), + VMSTATE_INT64(offset, RX8900State), + VMSTATE_UINT8_V(weekday, RX8900State, 2), + VMSTATE_UINT8_V(wday_offset, RX8900State, 2), + VMSTATE_UINT8_ARRAY(nvram, RX8900State, RX8900_NVRAM_SIZE), + VMSTATE_INT32(ptr, RX8900State), + VMSTATE_BOOL(addr_byte, RX8900State), + VMSTATE_UINT8_V(last_interrupt_seconds, RX8900State, 2), + VMSTATE_UINT8_V(last_update_interrupt_minutes, RX8900State, 2), + VMSTATE_END_OF_LIST() + } +}; + +static void rx8900_reset(DeviceState *dev); +static void disable_countdown_timer(RX8900State *s); +static void enable_countdown_timer(RX8900State *s); +static void disable_timer(RX8900State *s); +static void enable_timer(RX8900State *s); + +#ifdef RX8900_TRACE +#define RX8900_TRACE_BUF_SIZE 256 +/** + * Emit a trace message + * @param file the source filename + * @param line the line number the message was emitted from + * @param dev the RX8900 device + * @param fmt a printf style format + */ +static void trace(const char *file, int line, const char *func, + I2CSlave *dev, const char *fmt, ...) +{ + va_list ap; + char buf[RX8900_TRACE_BUF_SIZE]; + char timestamp[32]; + int len; + struct timeval now; + struct tm *now2; + + gettimeofday(&now, NULL); + now2 = localtime(&now.tv_sec); + + strftime(timestamp, sizeof(timestamp), "%F %T", now2); + + len = snprintf(buf, sizeof(buf), "\n\t%s.%03ld %s:%s:%d: RX8900 %s %s@0x%x: %s", + timestamp, now.tv_usec / 1000, + file, func, line, dev->qdev.id, dev->qdev.parent_bus->name, + dev->address, fmt); + if (len >= RX8900_TRACE_BUF_SIZE) { + error_report("%s:%d: Trace buffer overflow", file, line); + } + + va_start(ap, fmt); + error_vreport(buf, ap); + va_end(ap); +} + +/** + * Emit a trace message + * @param dev the RX8900 device + * @param fmt a printf format + */ +#define TRACE(dev, fmt, ...) \ + do { \ + if (log) { \ + trace(__FILE__, __LINE__, __func__, &dev, fmt, ## __VA_ARGS__); \ + } \ + } while (0) +#else +#define TRACE(dev, fmt, ...) +#endif + +static void capture_current_time(RX8900State *s) +{ + /* Capture the current time into the secondary registers + * which will be actually read by the data transfer operation. + */ + struct tm now; + qemu_get_timedate(&now, s->offset); + s->nvram[SECONDS] = to_bcd(now.tm_sec); + s->nvram[MINUTES] = to_bcd(now.tm_min); + s->nvram[HOURS] = to_bcd(now.tm_hour); + + s->nvram[WEEKDAY] = 0x01 << ((now.tm_wday + s->wday_offset) % 7); + s->nvram[DAY] = to_bcd(now.tm_mday); + s->nvram[MONTH] = to_bcd(now.tm_mon + 1); + s->nvram[YEAR] = to_bcd(now.tm_year % 100); + + s->nvram[EXT_SECONDS] = s->nvram[SECONDS]; + s->nvram[EXT_MINUTES] = s->nvram[MINUTES]; + s->nvram[EXT_HOURS] = s->nvram[HOURS]; + s->nvram[EXT_WEEKDAY] = s->nvram[WEEKDAY]; + s->nvram[EXT_DAY] = s->nvram[DAY]; + s->nvram[EXT_MONTH] = s->nvram[MONTH]; + s->nvram[EXT_YEAR] = s->nvram[YEAR]; + + TRACE(s->parent_obj, "Update current time to %02d:%02d:%02d %d %d/%d/%d " + "(0x%02x%02x%02x%02x%02x%02x%02x)", + now.tm_hour, now.tm_min, now.tm_sec, + (now.tm_wday + s->wday_offset) % 7, + now.tm_mday, now.tm_mon, now.tm_year + 1900, + s->nvram[HOURS], s->nvram[MINUTES], s->nvram[SECONDS], + s->nvram[WEEKDAY], + s->nvram[DAY], s->nvram[MONTH], s->nvram[YEAR]); +} + +/** + * Increment the internal register pointer, dealing with wrapping + * @param s the RTC to operate on + */ +static void inc_regptr(RX8900State *s) +{ + /* The register pointer wraps around after 0x1F + */ + s->ptr = (s->ptr + 1) & (RX8900_NVRAM_SIZE - 1); + TRACE(s->parent_obj, "Operating on register 0x%02x", s->ptr); + + if (s->ptr == 0x00) { + TRACE(s->parent_obj, "Register pointer has overflowed, wrapping to 0"); + capture_current_time(s); + } +} + +/** + * Receive an I2C Event + * @param i2c the i2c device instance + * @param event the event to handle + */ +static void rx8900_event(I2CSlave *i2c, enum i2c_event event) +{ + RX8900State *s = RX8900(i2c); + + switch (event) { + case I2C_START_RECV: + /* In h/w, time capture happens on any START condition, not just a + * START_RECV. For the emulation, it doesn't actually matter, + * since a START_RECV has to occur before the data can be read. + */ + capture_current_time(s); + break; + case I2C_START_SEND: + s->addr_byte = true; + break; + case I2C_FINISH: + if (s->weekday < 7) { + /* We defer the weekday calculation as it is handed to us before + * the date has been updated. If we calculate the weekday offset + * when it is passed to us, we will incorrectly determine it + * based on the current emulated date, rather than the date that + * has been written. + */ + struct tm now; + qemu_get_timedate(&now, s->offset); + + s->wday_offset = (s->weekday - now.tm_wday + 7) % 7; + + TRACE(s->parent_obj, "Set weekday to %d (0x%02x), wday_offset=%d", + s->weekday, BIT(s->weekday), s->wday_offset); + + s->weekday = 7; + } + break; + + default: + break; + } +} + +/** + * Perform an i2c receive action + * @param i2c the i2c device instance + * @return the value of the current register + * @post the internal register pointer is incremented + */ +static int rx8900_recv(I2CSlave *i2c) +{ + RX8900State *s = RX8900(i2c); + uint8_t res = s->nvram[s->ptr]; + TRACE(s->parent_obj, "Read register 0x%x = 0x%x", s->ptr, res); + inc_regptr(s); + return res; +} + +/** + * Validate the extension register and perform actions based on the bits + * @param s the RTC to operate on + * @param data the new data for the extension register + */ +static void update_extension_register(RX8900State *s, uint8_t data) +{ + if (data & EXT_MASK_TEST) { + error_report("WARNING: RX8900 - " + "Test bit is enabled but is forbidden by the manufacturer"); + } + + if ((data ^ s->nvram[EXTENSION_REGISTER]) & + (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) { + uint8_t fsel = (data & (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) + >> EXT_REG_FSEL0; + /* FSELx has changed */ + switch (fsel) { + case 0x01: + TRACE(s->parent_obj, "Setting fout to 1024Hz"); + ptimer_set_limit(s->fout_timer, 32, 1); + break; + case 0x02: + TRACE(s->parent_obj, "Setting fout to 1Hz"); + ptimer_set_limit(s->fout_timer, 32768, 1); + break; + default: + TRACE(s->parent_obj, "Setting fout to 32768Hz"); + ptimer_set_limit(s->fout_timer, 1, 1); + break; + } + } + + if ((data ^ s->nvram[EXTENSION_REGISTER]) & + (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) { + uint8_t tsel = (data & (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) + >> EXT_REG_TSEL0; + /* TSELx has changed */ + switch (tsel) { + case 0x00: + TRACE(s->parent_obj, "Setting countdown timer to 64 Hz"); + ptimer_set_limit(s->countdown_timer, 4096 / 64, 1); + break; + case 0x01: + TRACE(s->parent_obj, "Setting countdown timer to 1 Hz"); + ptimer_set_limit(s->countdown_timer, 4096, 1); + break; + case 0x02: + TRACE(s->parent_obj, + "Setting countdown timer to per minute updates"); + ptimer_set_limit(s->countdown_timer, 4069 * 60, 1); + break; + case 0x03: + TRACE(s->parent_obj, "Setting countdown timer to 4096Hz"); + ptimer_set_limit(s->countdown_timer, 1, 1); + break; + } + } + + if (data & EXT_MASK_TE) { + enable_countdown_timer(s); + } + + s->nvram[EXTENSION_REGISTER] = data; + s->nvram[EXT_EXTENSION_REGISTER] = data; + +} +/** + * Validate the control register and perform actions based on the bits + * @param s the RTC to operate on + * @param data the new value for the control register + */ + +static void update_control_register(RX8900State *s, uint8_t data) +{ + uint8_t diffmask = ~s->nvram[CONTROL_REGISTER] & data; + + if (diffmask & CTRL_MASK_WP0) { + data &= ~CTRL_MASK_WP0; + error_report("WARNING: RX8900 - " + "Attempt to write to write protected bit %d in control register", + CTRL_REG_WP0); + } + + if (diffmask & CTRL_MASK_WP1) { + data &= ~CTRL_MASK_WP1; + error_report("WARNING: RX8900 - " + "Attempt to write to write protected bit %d in control register", + CTRL_REG_WP1); + } + + if (data & CTRL_MASK_RESET) { + data &= ~CTRL_MASK_RESET; + rx8900_reset(DEVICE(s)); + } + + if (diffmask & CTRL_MASK_UIE) { + /* Update interrupts were off and are now on */ + struct tm now; + + TRACE(s->parent_obj, "Enabling update timer"); + + qemu_get_timedate(&now, s->offset); + + s->last_update_interrupt_minutes = now.tm_min; + s->last_interrupt_seconds = now.tm_sec; + enable_timer(s); + } + + if (diffmask & CTRL_MASK_AIE) { + /* Alarm interrupts were off and are now on */ + struct tm now; + + TRACE(s->parent_obj, "Enabling alarm"); + + qemu_get_timedate(&now, s->offset); + + s->last_interrupt_seconds = now.tm_sec; + enable_timer(s); + } + + if (!(data & (CTRL_MASK_UIE | CTRL_MASK_AIE))) { + disable_timer(s); + } + + if (data & CTRL_MASK_TIE) { + enable_countdown_timer(s); + } + + s->nvram[CONTROL_REGISTER] = data; + s->nvram[EXT_CONTROL_REGISTER] = data; +} + +/** + * Validate the flag register + * @param s the RTC to operate on + * @param data the new value for the flag register + */ +static void validate_flag_register(RX8900State *s, uint8_t *data) +{ + uint8_t diffmask = ~s->nvram[FLAG_REGISTER] & *data; + + if (diffmask & FLAG_MASK_VDET) { + *data &= ~FLAG_MASK_VDET; + error_report("WARNING: RX8900 - " + "Only 0 can be written to VDET bit %d in the flag register", + FLAG_REG_VDET); + } + + if (diffmask & FLAG_MASK_VLF) { + *data &= ~FLAG_MASK_VLF; + error_report("WARNING: RX8900 - " + "Only 0 can be written to VLF bit %d in the flag register", + FLAG_REG_VLF); + } + + if (diffmask & FLAG_MASK_UNUSED_2) { + *data &= ~FLAG_MASK_UNUSED_2; + error_report("WARNING: RX8900 - " + "Only 0 can be written to unused bit %d in the flag register", + FLAG_REG_UNUSED_2); + } + + if (diffmask & FLAG_MASK_UNUSED_6) { + *data &= ~FLAG_MASK_UNUSED_6; + error_report("WARNING: RX8900 - " + "Only 0 can be written to unused bit %d in the flag register", + FLAG_REG_UNUSED_6); + } + + if (diffmask & FLAG_MASK_UNUSED_7) { + *data &= ~FLAG_MASK_UNUSED_7; + error_report("WARNING: RX8900 - " + "Only 0 can be written to unused bit %d in the flag register", + FLAG_REG_UNUSED_7); + } +} + +/** + * Tick the per second timer (can be called more frequently as it early exits + * if the wall clock has not progressed) + * @param opaque the RTC to tick + */ +static void rx8900_timer_tick(void *opaque) +{ + RX8900State *s = (RX8900State *)opaque; + struct tm now; + bool fire_interrupt = false; + + qemu_get_timedate(&now, s->offset); + + if (now.tm_sec == s->last_interrupt_seconds) { + return; + } + + s->last_interrupt_seconds = now.tm_sec; + + TRACE(s->parent_obj, "Tick"); + + /* Update timer interrupt */ + if (s->nvram[CONTROL_REGISTER] & CTRL_MASK_UIE) { + if ((s->nvram[EXTENSION_REGISTER] & EXT_MASK_USEL) && + now.tm_min != s->last_update_interrupt_minutes) { + s->last_update_interrupt_minutes = now.tm_min; + s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF; + fire_interrupt = true; + } else if (!(s->nvram[EXTENSION_REGISTER] & EXT_MASK_USEL)) { + /* per second update interrupt */ + s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF; + fire_interrupt = true; + } + } + + /* Alarm interrupt */ + if ((s->nvram[CONTROL_REGISTER] & CTRL_MASK_AIE) && now.tm_sec == 0) { + if (s->nvram[ALARM_MINUTE] == to_bcd(now.tm_min) && + s->nvram[ALARM_HOUR] == to_bcd(now.tm_hour) && + s->nvram[ALARM_WEEK_DAY] == + ((s->nvram[EXTENSION_REGISTER] & EXT_MASK_WADA) ? + to_bcd(now.tm_mday) : + 0x01 << ((now.tm_wday + s->wday_offset) % 7))) { + TRACE(s->parent_obj, "Triggering alarm"); + s->nvram[FLAG_REGISTER] |= FLAG_MASK_AF; + fire_interrupt = true; + } + } + + if (fire_interrupt) { + TRACE(s->parent_obj, "Pulsing interrupt"); + qemu_irq_pulse(s->interrupt_pin); + } +} + +/** + * Disable the per second timer + * @param s the RTC to operate on + */ +static void disable_timer(RX8900State *s) +{ + TRACE(s->parent_obj, "Disabling timer"); + ptimer_stop(s->sec_timer); +} + +/** + * Enable the per second timer + * @param s the RTC to operate on + */ +static void enable_timer(RX8900State *s) +{ + TRACE(s->parent_obj, "Enabling timer"); + ptimer_run(s->sec_timer, 0); +} + +/** + * Handle FOUT_ENABLE (FOE) line + * Enables/disables the FOUT line + * @param opaque the device instance + * @param n the IRQ number + * @param level true if the line has been raised + */ +static void rx8900_fout_enable_handler(void *opaque, int n, int level) +{ + RX8900State *s = RX8900(opaque); + + if (level) { + TRACE(s->parent_obj, "Enabling fout"); + ptimer_run(s->fout_timer, 0); + } else { + /* disable fout */ + TRACE(s->parent_obj, "Disabling fout"); + ptimer_stop(s->fout_timer); + } +} + +/** + * Tick the FOUT timer + * @param opaque the device instance + */ +static void rx8900_fout_tick(void *opaque) +{ + RX8900State *s = (RX8900State *)opaque; + + TRACE(s->parent_obj, "fout toggle"); + s->fout = !s->fout; + + if (s->fout) { + qemu_irq_raise(s->fout_pin); + } else { + qemu_irq_lower(s->fout_pin); + } +} + + +/** + * Disable the countdown timer + * @param s the RTC to operate on + */ +static void disable_countdown_timer(RX8900State *s) +{ + TRACE(s->parent_obj, "Disabling countdown timer"); + ptimer_stop(s->countdown_timer); +} + +/** + * Enable the per second timer + * @param s the RTC to operate on + */ +static void enable_countdown_timer(RX8900State *s) +{ + TRACE(s->parent_obj, "Enabling countdown timer"); + ptimer_run(s->countdown_timer, 0); +} + +/** + * Tick the countdown timer + * @param opaque the device instance + */ +static void rx8900_countdown_tick(void *opaque) +{ + RX8900State *s = (RX8900State *)opaque; + + uint16_t count = s->nvram[TIMER_COUNTER_0] + + ((s->nvram[TIMER_COUNTER_1] & 0x0F) << 8); + TRACE(s->parent_obj, "countdown tick, count=%d", count); + count--; + + s->nvram[TIMER_COUNTER_0] = (uint8_t)(count & 0x00ff); + s->nvram[TIMER_COUNTER_1] = (uint8_t)((count & 0x0f00) >> 8); + + if (count == 0) { + TRACE(s->parent_obj, "Countdown has elapsed, pulsing interrupt"); + + disable_countdown_timer(s); + + s->nvram[FLAG_REGISTER] |= FLAG_MASK_TF; + qemu_irq_pulse(s->interrupt_pin); + } +} + + +/** + * Receive a byte of data from i2c + * @param i2c the i2c device that is receiving data + * @param data the data that was received + */ +static int rx8900_send(I2CSlave *i2c, uint8_t data) +{ + RX8900State *s = RX8900(i2c); + struct tm now; + + TRACE(s->parent_obj, "Received I2C data 0x%02x", data); + + if (s->addr_byte) { + s->ptr = data & (RX8900_NVRAM_SIZE - 1); + TRACE(s->parent_obj, "Operating on register 0x%02x", s->ptr); + s->addr_byte = false; + return 0; + } + + TRACE(s->parent_obj, "Set data 0x%02x=0x%02x", s->ptr, data); + + qemu_get_timedate(&now, s->offset); + switch (s->ptr) { + case SECONDS: + case EXT_SECONDS: + now.tm_sec = from_bcd(data & 0x7f); + s->offset = qemu_timedate_diff(&now); + break; + + case MINUTES: + case EXT_MINUTES: + now.tm_min = from_bcd(data & 0x7f); + s->offset = qemu_timedate_diff(&now); + break; + + case HOURS: + case EXT_HOURS: + now.tm_hour = from_bcd(data & 0x3f); + s->offset = qemu_timedate_diff(&now); + break; + + case WEEKDAY: + case EXT_WEEKDAY: { + int user_wday = ctz32(data); + /* The day field is supposed to contain a value in + * the range 0-6. Otherwise behavior is undefined. + */ + switch (data) { + case 0x01: + case 0x02: + case 0x04: + case 0x08: + case 0x10: + case 0x20: + case 0x40: + break; + default: + error_report("WARNING: RX8900 - weekday data '%x' is out of range," + " undefined behavior will result", data); + break; + } + s->weekday = user_wday; + break; + } + + case DAY: + case EXT_DAY: + now.tm_mday = from_bcd(data & 0x3f); + s->offset = qemu_timedate_diff(&now); + break; + + case MONTH: + case EXT_MONTH: + now.tm_mon = from_bcd(data & 0x1f) - 1; + s->offset = qemu_timedate_diff(&now); + break; + + case YEAR: + case EXT_YEAR: + now.tm_year = from_bcd(data) + 100; + s->offset = qemu_timedate_diff(&now); + break; + + case EXTENSION_REGISTER: + case EXT_EXTENSION_REGISTER: + update_extension_register(s, data); + break; + + case FLAG_REGISTER: + case EXT_FLAG_REGISTER: + validate_flag_register(s, &data); + + s->nvram[FLAG_REGISTER] = data; + s->nvram[EXT_FLAG_REGISTER] = data; + break; + + case CONTROL_REGISTER: + case EXT_CONTROL_REGISTER: + update_control_register(s, data); + break; + + default: + s->nvram[s->ptr] = data; + } + + inc_regptr(s); + return 0; +} + +/** + * Get the device temperature in Celcius as a property + * @param obj the device + * @param v + * @param name the property name + * @param opaque + * @param errp an error object to populate on failure + */ +static void rx8900_get_temperature(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RX8900State *s = RX8900(obj); + double value = (s->nvram[TEMPERATURE] * 2.0f - 187.1f) / 3.218f; + + TRACE(s->parent_obj, "Read temperature property, 0x%x = %f°C", + s->nvram[TEMPERATURE], value); + + visit_type_number(v, name, &value, errp); +} + +/** + * Set the device temperature in Celcius as a property + * @param obj the device + * @param v + * @param name the property name + * @param opaque + * @param errp an error object to populate on failure + */ +static void rx8900_set_temperature(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RX8900State *s = RX8900(obj); + Error *local_err = NULL; + double temp; /* degrees Celcius */ + visit_type_number(v, name, &temp, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + if (temp >= 100 || temp < -58) { + error_setg(errp, "value %f°C is out of range", temp); + return; + } + + s->nvram[TEMPERATURE] = (uint8_t) ((temp * 3.218f + 187.19f) / 2); + + TRACE(s->parent_obj, "Set temperature property, 0x%x = %f°C", + s->nvram[TEMPERATURE], temp); +} + + +/** + * Initialize the device + * @param i2c the i2c device instance + */ +static int rx8900_init(I2CSlave *i2c) +{ + TRACE(*i2c, "Initialized"); + + return 0; +} + +/** + * Configure device properties + * @param obj the device + */ +static void rx8900_initfn(Object *obj) +{ + object_property_add(obj, "temperature", "number", + rx8900_get_temperature, + rx8900_set_temperature, NULL, NULL, NULL); +} + +/** + * Reset the device + * @param dev the RX8900 device to reset + */ +static void rx8900_reset(DeviceState *dev) +{ + RX8900State *s = RX8900(dev); + + TRACE(s->parent_obj, "Reset"); + + /* The clock is running and synchronized with the host */ + s->offset = 0; + s->weekday = 7; /* Set to an invalid value */ + + /* Temperature formulation from the datasheet + * ( TEMP[ 7:0 ] * 2 - 187.19) / 3.218 + * + * Set the initial state to 25 degrees Celcius + */ + s->nvram[TEMPERATURE] = 135; /* (25 * 3.218 + 187.19) / 2 */ + + s->nvram[EXTENSION_REGISTER] = EXT_MASK_TSEL1; + s->nvram[CONTROL_REGISTER] = CTRL_MASK_CSEL0; + s->nvram[FLAG_REGISTER] = FLAG_MASK_VLF | FLAG_MASK_VDET; + + s->ptr = 0; + TRACE(s->parent_obj, "Operating on register 0x%02x", s->ptr); + + s->addr_byte = false; +} + +/** + * Realize an RX8900 device instance + * Set up timers + * Configure GPIO lines + * @param dev the device instance to realize + * @param errp an error object to populate on error + */ +static void rx8900_realize(DeviceState *dev, Error **errp) +{ + RX8900State *s = RX8900(dev); + I2CSlave *i2c = I2C_SLAVE(dev); + QEMUBH *bh; + char name[64]; + + s->fout = false; + + memset(s->nvram, 0, RX8900_NVRAM_SIZE); + + bh = qemu_bh_new(rx8900_timer_tick, s); + s->sec_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); + /* we trigger the timer at 10Hz and check for rollover, as the qemu + * clock does not advance in realtime in the test environment, + * leading to unstable test results + */ + ptimer_set_freq(s->sec_timer, 10); + ptimer_set_limit(s->sec_timer, 1, 1); + + bh = qemu_bh_new(rx8900_fout_tick, s); + s->fout_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); + /* frequency doubled to generate 50% duty cycle square wave */ + ptimer_set_freq(s->fout_timer, 32768 * 2); + ptimer_set_limit(s->fout_timer, 1, 1); + + bh = qemu_bh_new(rx8900_countdown_tick, s); + s->countdown_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); + ptimer_set_freq(s->countdown_timer, 4096); + ptimer_set_limit(s->countdown_timer, 4096, 1); + + + snprintf(name, sizeof(name), "rx8900-interrupt-out"); + qdev_init_gpio_out_named(&i2c->qdev, &s->interrupt_pin, name, 1); + TRACE(s->parent_obj, "Interrupt pin is '%s'", name); + + snprintf(name, sizeof(name), "rx8900-fout-enable"); + qdev_init_gpio_in_named(&i2c->qdev, rx8900_fout_enable_handler, name, 1); + TRACE(s->parent_obj, "Fout-enable pin is '%s'", name); + + snprintf(name, sizeof(name), "rx8900-fout"); + qdev_init_gpio_out_named(&i2c->qdev, &s->fout_pin, name, 1); + TRACE(s->parent_obj, "Fout pin is '%s'", name); +} + +/** + * Set up the device callbacks + * @param klass the device class + * @param data + */ +static void rx8900_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + + k->init = rx8900_init; + k->event = rx8900_event; + k->recv = rx8900_recv; + k->send = rx8900_send; + dc->realize = rx8900_realize; + dc->reset = rx8900_reset; + dc->vmsd = &vmstate_rx8900; +} + +static const TypeInfo rx8900_info = { + .name = TYPE_RX8900, + .parent = TYPE_I2C_SLAVE, + .instance_size = sizeof(RX8900State), + .instance_init = rx8900_initfn, + .class_init = rx8900_class_init, +}; + +/** + * Register the device with QEMU + */ +static void rx8900_register_types(void) +{ + log = getenv("RX8900_TRACE") != NULL; + type_register_static(&rx8900_info); +} + +type_init(rx8900_register_types) diff --git a/hw/timer/rx8900_regs.h b/hw/timer/rx8900_regs.h new file mode 100644 index 0000000..5261c76 --- /dev/null +++ b/hw/timer/rx8900_regs.h @@ -0,0 +1,125 @@ +/* + * Epson RX8900SA/CE Realtime Clock Module + * + * Copyright (c) 2016 IBM Corporation + * Authors: + * Alastair D'Silva <alastair@d-silva.org> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + * Datasheet available at: + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE&lang=en + * + */ + +#ifndef RX8900_REGS_H +#define RX8900_REGS_H + +#include "qemu/bitops.h" + +#define RX8900_NVRAM_SIZE 0x20 + +typedef enum RX8900Addresses { + SECONDS = 0x00, + MINUTES = 0x01, + HOURS = 0x02, + WEEKDAY = 0x03, + DAY = 0x04, + MONTH = 0x05, + YEAR = 0x06, + RAM = 0x07, + ALARM_MINUTE = 0x08, + ALARM_HOUR = 0x09, + ALARM_WEEK_DAY = 0x0A, + TIMER_COUNTER_0 = 0x0B, + TIMER_COUNTER_1 = 0x0C, + EXTENSION_REGISTER = 0x0D, + FLAG_REGISTER = 0X0E, + CONTROL_REGISTER = 0X0F, + EXT_SECONDS = 0x010, /* Alias of SECONDS */ + EXT_MINUTES = 0x11, /* Alias of MINUTES */ + EXT_HOURS = 0x12, /* Alias of HOURS */ + EXT_WEEKDAY = 0x13, /* Alias of WEEKDAY */ + EXT_DAY = 0x14, /* Alias of DAY */ + EXT_MONTH = 0x15, /* Alias of MONTH */ + EXT_YEAR = 0x16, /* Alias of YEAR */ + TEMPERATURE = 0x17, + BACKUP_FUNCTION = 0x18, + NO_USE_1 = 0x19, + NO_USE_2 = 0x1A, + EXT_TIMER_COUNTER_0 = 0x1B, /* Alias of TIMER_COUNTER_0 */ + EXT_TIMER_COUNTER_1 = 0x1C, /* Alias of TIMER_COUNTER_1 */ + EXT_EXTENSION_REGISTER = 0x1D, /* Alias of EXTENSION_REGISTER */ + EXT_FLAG_REGISTER = 0X1E, /* Alias of FLAG_REGISTER */ + EXT_CONTROL_REGISTER = 0X1F /* Alias of CONTROL_REGISTER */ +} RX8900Addresses; + +typedef enum ExtRegBits { + EXT_REG_TSEL0 = 0, + EXT_REG_TSEL1 = 1, + EXT_REG_FSEL0 = 2, + EXT_REG_FSEL1 = 3, + EXT_REG_TE = 4, + EXT_REG_USEL = 5, + EXT_REG_WADA = 6, + EXT_REG_TEST = 7 +} ExtRegBits; + +typedef enum ExtRegMasks { + EXT_MASK_TSEL0 = BIT(0), + EXT_MASK_TSEL1 = BIT(1), + EXT_MASK_FSEL0 = BIT(2), + EXT_MASK_FSEL1 = BIT(3), + EXT_MASK_TE = BIT(4), + EXT_MASK_USEL = BIT(5), + EXT_MASK_WADA = BIT(6), + EXT_MASK_TEST = BIT(7) +} ExtRegMasks; + +typedef enum CtrlRegBits { + CTRL_REG_RESET = 0, + CTRL_REG_WP0 = 1, + CTRL_REG_WP1 = 2, + CTRL_REG_AIE = 3, + CTRL_REG_TIE = 4, + CTRL_REG_UIE = 5, + CTRL_REG_CSEL0 = 6, + CTRL_REG_CSEL1 = 7 +} CtrlRegBits; + +typedef enum CtrlRegMask { + CTRL_MASK_RESET = BIT(0), + CTRL_MASK_WP0 = BIT(1), + CTRL_MASK_WP1 = BIT(2), + CTRL_MASK_AIE = BIT(3), + CTRL_MASK_TIE = BIT(4), + CTRL_MASK_UIE = BIT(5), + CTRL_MASK_CSEL0 = BIT(6), + CTRL_MASK_CSEL1 = BIT(7) +} CtrlRegMask; + +typedef enum FlagRegBits { + FLAG_REG_VDET = 0, + FLAG_REG_VLF = 1, + FLAG_REG_UNUSED_2 = 2, + FLAG_REG_AF = 3, + FLAG_REG_TF = 4, + FLAG_REG_UF = 5, + FLAG_REG_UNUSED_6 = 6, + FLAG_REG_UNUSED_7 = 7 +} FlagRegBits; + +#define RX8900_INTERRUPT_SOURCES 6 +typedef enum FlagRegMask { + FLAG_MASK_VDET = BIT(0), + FLAG_MASK_VLF = BIT(1), + FLAG_MASK_UNUSED_2 = BIT(2), + FLAG_MASK_AF = BIT(3), + FLAG_MASK_TF = BIT(4), + FLAG_MASK_UF = BIT(5), + FLAG_MASK_UNUSED_6 = BIT(6), + FLAG_MASK_UNUSED_7 = BIT(7) +} FlagRegMask; + +#endif diff --git a/tests/Makefile.include b/tests/Makefile.include index e98d3b6..e52e355 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -300,6 +300,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF) check-qtest-arm-y = tests/tmp105-test$(EXESUF) check-qtest-arm-y += tests/ds1338-test$(EXESUF) +check-qtest-arm-y += tests/rx8900-test$(EXESUF) check-qtest-arm-y += tests/m25p80-test$(EXESUF) gcov-files-arm-y += hw/misc/tmp105.c check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) @@ -637,6 +638,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \ tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-y) tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c new file mode 100644 index 0000000..a56426b --- /dev/null +++ b/tests/rx8900-test.c @@ -0,0 +1,800 @@ +/* + * QTest testcase for the Enpes RX8900SA/CE RTC + * + * Copyright (c) 2016 IBM Corporation + * Authors: + * Alastair D'Silva <alastair@d-silva.org> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/timer/rx8900_regs.h" +#include "libqtest.h" +#include "libqos/i2c.h" +#include "qemu/timer.h" + +#define IMX25_I2C_0_BASE 0x43F80000 +#define RX8900_TEST_ID "rx8900-test" +#define RX8900_ADDR 0x32 +#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out" +#define RX8900_FOUT_ENABLE "rx8900-fout-enable" +#define RX8900_FOUT "rx8900-fout" + +static I2CAdapter *i2c; +static uint8_t addr; + +static inline uint8_t bcd2bin(uint8_t x) +{ + return (x & 0x0f) + (x >> 4) * 10; +} + +static inline uint8_t bin2bcd(uint8_t x) +{ + return (x / 10 << 4) | (x % 10); +} + +static void qmp_rx8900_set_temperature(const char *id, double value) +{ + QDict *response; + + response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, " + "'property': 'temperature', 'value': %f } }", id, value); + g_assert(qdict_haskey(response, "return")); + QDECREF(response); +} + +/** + * Read an RX8900 register + * @param reg the address of the register + * @return the value of the register + */ +static uint8_t read_register(RX8900Addresses reg) +{ + uint8_t val; + uint8_t reg_address = (uint8_t)reg; + + i2c_send(i2c, addr, ®_address, 1); + i2c_recv(i2c, addr, &val, 1); + + return val; +} + +/** + * Write to an RX8900 register + * @param reg the address of the register + * @param val the value to write + */ +static uint8_t write_register(RX8900Addresses reg, uint8_t val) +{ + uint8_t buf[2]; + + buf[0] = reg; + buf[1] = val; + + i2c_send(i2c, addr, buf, 2); + + return val; +} + +/** + * Set bits in a register + * @param reg the address of the register + * @param mask a mask of the bits to set + */ +static void set_bits_in_register(RX8900Addresses reg, uint8_t mask) +{ + uint8_t value = read_register(reg); + value |= mask; + write_register(reg, value); +} + +/** + * Clear bits in a register + * @param reg the address of the register + * @param mask a mask of the bits to set + */ +static void clear_bits_in_register(RX8900Addresses reg, uint8_t mask) +{ + uint8_t value = read_register(reg); + value &= ~mask; + write_register(reg, value); +} + +/** + * Read a number of sequential RX8900 registers + * @param reg the address of the first register + * @param buf (out) an output buffer to stash the register values + * @param count the number of registers to read + */ +static void read_registers(RX8900Addresses reg, uint8_t *buf, uint8_t count) +{ + uint8_t reg_address = (uint8_t)reg; + + i2c_send(i2c, addr, ®_address, 1); + i2c_recv(i2c, addr, buf, count); +} + +/** + * Write to a sequential number of RX8900 registers + * @param reg the address of the first register + * @param buffer a buffer of values to write + * @param count the sumber of registers to write + */ +static void write_registers(RX8900Addresses reg, uint8_t *buffer, uint8_t count) +{ + uint8_t buf[RX8900_NVRAM_SIZE + 1]; + + buf[0] = (uint8_t)reg; + memcpy(buf + 1, buffer, count); + + i2c_send(i2c, addr, buf, count + 1); +} + +/** + * Set the time on the RX8900 + * @param secs the seconds to set + * @param mins the minutes to set + * @param hours the hours to set + * @param weekday the day of the week to set (0 = Sunday) + * @param day the day of the month to set + * @param month the month to set + * @param year the year to set + */ +static void set_time(uint8_t secs, uint8_t mins, uint8_t hours, + uint8_t weekday, uint8_t day, uint8_t month, uint8_t year) +{ + uint8_t buf[7]; + + buf[0] = bin2bcd(secs); + buf[1] = bin2bcd(mins); + buf[2] = bin2bcd(hours); + buf[3] = BIT(weekday); + buf[4] = bin2bcd(day); + buf[5] = bin2bcd(month); + buf[6] = bin2bcd(year); + + write_registers(SECONDS, buf, 7); +} + + +/** + * Check basic communication + */ +static void send_and_receive(void) +{ + uint8_t buf[7]; + time_t now = time(NULL); + struct tm *tm_ptr; + + /* retrieve the date */ + read_registers(SECONDS, buf, 7); + + tm_ptr = gmtime(&now); + + /* check retrieved time against local time */ + g_assert_cmpuint(bcd2bin(buf[0]), == , tm_ptr->tm_sec); + g_assert_cmpuint(bcd2bin(buf[1]), == , tm_ptr->tm_min); + g_assert_cmpuint(bcd2bin(buf[2]), == , tm_ptr->tm_hour); + g_assert_cmpuint(bcd2bin(buf[4]), == , tm_ptr->tm_mday); + g_assert_cmpuint(bcd2bin(buf[5]), == , 1 + tm_ptr->tm_mon); + g_assert_cmpuint(2000 + bcd2bin(buf[6]), == , 1900 + tm_ptr->tm_year); +} + +/** + * Check that the temperature can be altered via properties + */ +static void check_temperature(void) +{ + /* Check the initial temperature is 25C */ + uint8_t temperature; + + temperature = read_register(TEMPERATURE); + g_assert_cmpuint(temperature, == , 135); + + /* Set the temperature to 40C and check the temperature again */ + qmp_rx8900_set_temperature(RX8900_TEST_ID, 40.0f); + temperature = read_register(TEMPERATURE); + g_assert_cmpuint(temperature, == , 157); +} + +/** + * Check that the time rolls over correctly + */ +static void check_rollover(void) +{ + uint8_t buf[7]; + + + set_time(59, 59, 23, 1, 29, 2, 16); + + /* Wait for the clock to rollover */ + sleep(2); + + memset(buf, 0, sizeof(buf)); + + /* Check that the clock rolled over */ + /* Read from registers starting at 0x00 */ + buf[0] = 0x00; + + read_registers(SECONDS, buf, 7); + + /* Ignore seconds as there may be some noise, + * we expect 00:00:xx Tuesday 1/3/2016 + */ + g_assert_cmpuint(bcd2bin(buf[1]), == , 0); + g_assert_cmpuint(bcd2bin(buf[2]), == , 0); + g_assert_cmpuint(bcd2bin(buf[3]), == , 0x04); + g_assert_cmpuint(bcd2bin(buf[4]), == , 1); + g_assert_cmpuint(bcd2bin(buf[5]), == , 3); + g_assert_cmpuint(bcd2bin(buf[6]), == , 16); +} + +uint32_t interrupt_counts[RX8900_INTERRUPT_SOURCES]; + +/** + * Reset the interrupt counts + */ +static void count_reset(void) +{ + for (int source = 0; source < RX8900_INTERRUPT_SOURCES; source++) { + interrupt_counts[source] = 0; + } +} + +/** + * Handle an RX8900 interrupt (update the counts for that interrupt type) + */ +static void handle_interrupt(void *opaque, const char *name, int irq, + bool level) +{ + if (!level) { + return; + } + + uint8_t flags = read_register(FLAG_REGISTER); + + for (int flag = 0; flag < 8; flag++) { + if (flags & BIT(flag)) { + interrupt_counts[flag]++; + } + } + + write_register(FLAG_REGISTER, 0x00); +} + +uint32_t fout_counts; + +/** + * Handle an Fout state change + */ +static void handle_fout(void *opaque, const char *name, int irq, bool level) +{ + if (!level) { + return; + } + + fout_counts++; +} + +/** + * Reset the fout count + */ +static void fout_count_reset(void) +{ + fout_counts = 0; +} + + +/** + * Sleep for some real time while counting interrupts + * @param delay the delay in microseconds + * @param loop the loop time in microseconds + */ +static void wait_for(uint64_t delay, uint64_t loop) +{ + struct timeval end, now; + + gettimeofday(&end, NULL); + delay += end.tv_usec; + end.tv_sec += delay / 1000000; + end.tv_usec = delay % 1000000; + + while (gettimeofday(&now, NULL), + now.tv_sec < end.tv_sec || now.tv_usec < end.tv_usec) { + clock_step(loop * 1000); + usleep(loop); + } +} + +/** + * Sleep for some emulated time while counting interrupts + * @param delay the delay in nanoseconds + * @param loop the loop time in nanoseconds + */ +static void wait_cycles(uint64_t delay, uint64_t loop) +{ + uint64_t counter; + + for (counter = 0; counter < delay; counter += loop) { + clock_step(loop); + } +} + + +/** + * Check that when the update timer interrupt is disabled, that no interrupts + * occur + */ +static void check_update_interrupt_disabled(void) +{ + /* Disable the update interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); + + /* Wait for the clock to rollover, this will cover both seconds & minutes + */ + set_time(59, 59, 23, 1, 29, 2, 16); + + count_reset(); + wait_for(2 * 1000000, 1000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); +} + + +/** + * Check that when the update timer interrupt is enabled and configured for + * per second updates, that we get the appropriate number of interrupts + */ +static void check_update_interrupt_seconds(void) +{ + set_time(59, 59, 23, 1, 29, 2, 16); + + /* Enable the update interrupt for per second updates */ + clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_USEL); + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); + + count_reset(); + wait_for(5.1f * 1000000ULL, 1000); + + /* Disable the update interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 5); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); +} + +/** + * Check that when the update timer interrupt is enabled and configured for + * per minute updates, that we get the appropriate number of interrupts + */ +static void check_update_interrupt_minutes(void) +{ + set_time(59, 59, 23, 1, 29, 2, 16); + + /* Enable the update interrupt for per minute updates */ + set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_USEL); + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); + + count_reset(); + wait_for(5 * 1000000ULL, 1000); + + /* Disable the update interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 1); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); +} + + +/** + * Check that when the alarm timer interrupt is disabled, that no interrupts + * occur + */ +static void check_alarm_interrupt_disabled(void) +{ + /* Disable the alarm interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + /* Set an alarm for midnight */ + uint8_t buf[3]; + + buf[0] = bin2bcd(0); /* minutes */ + buf[1] = bin2bcd(0); /* hours */ + buf[2] = bin2bcd(1); /* day */ + + write_registers(ALARM_MINUTE, buf, 3); + + /* Wait for the clock to rollover */ + set_time(59, 59, 23, 1, 29, 2, 16); + + count_reset(); + wait_for(2 * 1000000, 1000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); +} + +/** + * Check that when the alarm timer interrupt is enabled, that an interrupt + * occurs + */ +static void check_alarm_interrupt_day_of_month(void) +{ + + /* Set an alarm for midnight */ + uint8_t buf[3]; + + buf[0] = bin2bcd(0); /* minutes */ + buf[1] = bin2bcd(0); /* hours */ + buf[2] = bin2bcd(1); /* day */ + + write_registers(ALARM_MINUTE, buf, 3); + + /* Set alarm to day of month mode */ + set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); + + /* Enable the alarm interrupt */ + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + /* Wait for the clock to rollover */ + set_time(59, 59, 23, 1, 29, 2, 16); + + count_reset(); + wait_for(2 * 1000000, 1000); + + /* Disable the alarm interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 1); +} + +/** + * Check that when the alarm timer interrupt is enabled, that an interrupt + * does not occur + */ +static void check_alarm_interrupt_day_of_month_negative(void) +{ + + /* Set an alarm for midnight */ + uint8_t buf[3]; + + buf[0] = bin2bcd(0); /* minutes */ + buf[1] = bin2bcd(0); /* hours */ + buf[2] = bin2bcd(2); /* day */ + + write_registers(ALARM_MINUTE, buf, 3); + + /* Set alarm to day of month mode */ + set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); + + /* Enable the alarm interrupt */ + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + /* Wait for the clock to rollover */ + set_time(59, 59, 23, 1, 29, 2, 16); + + count_reset(); + wait_for(2 * 1000000, 1000); + + /* Disable the alarm interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); +} + +/** + * Check that when the alarm timer interrupt is enabled, that an interrupt + * occurs + */ +static void check_alarm_interrupt_day_of_week(void) +{ + + /* Set an alarm for midnight */ + uint8_t buf[3]; + + buf[0] = bin2bcd(0); /* minutes */ + buf[1] = bin2bcd(0); /* hours */ + buf[2] = 0x01 << 2; /* day */ + + write_registers(ALARM_MINUTE, buf, 3); + + /* Set alarm to day of week mode */ + clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); + + /* Enable the alarm interrupt */ + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + /* Wait for the clock to rollover */ + set_time(59, 59, 23, 1, 29, 2, 16); + + count_reset(); + wait_for(2 * 1000000, 1000); + + /* Disable the alarm interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 1); +} + +/** + * Check that when the alarm timer interrupt is enabled, that an interrupt + * does not occur + */ +static void check_alarm_interrupt_day_of_week_negative(void) +{ + + /* Set an alarm for midnight */ + uint8_t buf[3]; + + buf[0] = bin2bcd(0); /* minutes */ + buf[1] = bin2bcd(0); /* hours */ + buf[2] = 0x01 << 2; /* day */ + + write_registers(ALARM_MINUTE, buf, 3); + + /* Set alarm to day of week mode */ + clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); + + /* Enable the alarm interrupt */ + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + /* Wait for the clock to rollover */ + set_time(59, 59, 23, 3, 29, 2, 16); + + count_reset(); + wait_for(2 * 1000000, 1000); + + /* Disable the alarm interrupt */ + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); +} + +/** + * Check that the reset function + */ +static void check_reset(void) +{ + set_bits_in_register(FLAG_REGISTER, FLAG_MASK_UF); + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_RESET); + + g_assert_cmpuint(read_register(FLAG_REGISTER), ==, + FLAG_MASK_VLF | FLAG_MASK_VDET); +} + +/** + * Check that Fout operates at 1Hz + */ +static void check_fout_1hz(void) +{ + uint8_t ext_reg = read_register(EXTENSION_REGISTER); + ext_reg |= EXT_MASK_FSEL1; + ext_reg &= ~EXT_MASK_FSEL0; + write_register(EXTENSION_REGISTER, ext_reg); + + /* Enable Fout */ + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true); + + fout_count_reset(); + wait_cycles(2 * 1000000000ULL, 1000000); + + /* disable Fout */ + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false); + + g_assert_cmpuint(fout_counts, ==, 2); +} + +/** + * Check that Fout operates at 1024Hz + */ +static void check_fout_1024hz(void) +{ + uint8_t ext_reg = read_register(EXTENSION_REGISTER); + ext_reg |= EXT_MASK_FSEL0; + ext_reg &= ~EXT_MASK_FSEL1; + write_register(EXTENSION_REGISTER, ext_reg); + + /* Enable Fout */ + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true); + + fout_count_reset(); + wait_cycles(2 * 1000000000ULL, 100000); + + /* disable Fout */ + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false); + + g_assert_cmpuint(fout_counts, ==, 1024 * 2); +} + +/** + * Check that Fout operates at 32768Hz + */ +static void check_fout_32768hz(void) +{ + uint8_t ext_reg = read_register(EXTENSION_REGISTER); + ext_reg &= ~EXT_MASK_FSEL0; + ext_reg &= ~EXT_MASK_FSEL1; + write_register(EXTENSION_REGISTER, ext_reg); + + /* Enable Fout */ + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true); + + fout_count_reset(); + wait_cycles(2 * 1000000000ULL, 15000); + + /* disable Fout */ + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false); + + /* There appears to be some rounding errors in the timer, + * we'll tolerate it for now + */ + g_assert_cmpuint(fout_counts, >=, 32768 * 2); + g_assert_cmpuint(fout_counts, <=, 65540); +} + +/** + * Check the countdown timer operates at 1 Hz + */ +static void check_countdown_1hz(void) +{ + uint8_t ext_reg; + + write_register(TIMER_COUNTER_0, 5); + write_register(TIMER_COUNTER_1, 0); + + ext_reg = read_register(EXTENSION_REGISTER); + ext_reg &= ~EXT_MASK_TSEL1; + ext_reg |= EXT_MASK_TSEL0; + ext_reg |= EXT_MASK_TE; + write_register(EXTENSION_REGISTER, ext_reg); + + count_reset(); + wait_cycles(5 * 1000000000ULL, 1000000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); + + wait_cycles(1 * 1000000000ULL, 1000000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); +} + +/** + * Check the countdown timer operates at 64 Hz + */ +static void check_countdown_64hz(void) +{ + uint8_t ext_reg; + + write_register(TIMER_COUNTER_0, 0x40); + write_register(TIMER_COUNTER_1, 0x01); /* 5 * 64 */ + + ext_reg = read_register(EXTENSION_REGISTER); + ext_reg &= ~EXT_MASK_TSEL0; + ext_reg &= ~EXT_MASK_TSEL1; + ext_reg |= EXT_MASK_TE; + write_register(EXTENSION_REGISTER, ext_reg); + + count_reset(); + wait_cycles(5 * 1000000000ULL, 1000000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); + + wait_cycles(1 * 1000000000ULL, 1000000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); +} + +/** + * Check the countdown timer operates at 4096 Hz + */ +static void check_countdown_4096hz(void) +{ + uint8_t ext_reg; + + write_register(TIMER_COUNTER_0, 0xFF); + write_register(TIMER_COUNTER_1, 0x0F); /* 4095 */ + ext_reg = read_register(EXTENSION_REGISTER); + ext_reg |= EXT_MASK_TSEL0; + ext_reg |= EXT_MASK_TSEL1; + ext_reg |= EXT_MASK_TE; + write_register(EXTENSION_REGISTER, ext_reg); + + count_reset(); + wait_cycles(999755859ULL, 10000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); + + wait_cycles(244141ULL, 10000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); +} + +/** + * Check the countdown timer operates at 1 minute + */ +static void check_countdown_1m(void) +{ + uint8_t ext_reg; + + write_register(TIMER_COUNTER_0, 0x01); + write_register(TIMER_COUNTER_1, 0x00); + ext_reg = read_register(EXTENSION_REGISTER); + ext_reg &= ~EXT_MASK_TSEL0; + ext_reg |= EXT_MASK_TSEL1; + ext_reg |= EXT_MASK_TE; + write_register(EXTENSION_REGISTER, ext_reg); + + count_reset(); + wait_cycles(59 * 1000000000ULL, 100000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); + + wait_cycles(1000000000LL, 100000); + + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); +} + + +int main(int argc, char **argv) +{ + QTestState *s = NULL; + int ret; + char args[255]; + snprintf(args, sizeof(args), "-display none -machine imx25-pdk " + "-device rx8900,bus=i2c.0,address=0x%x,id=%s", + RX8900_ADDR, RX8900_TEST_ID); + + g_test_init(&argc, &argv, NULL); + + s = qtest_start(args); + i2c = imx_i2c_create(IMX25_I2C_0_BASE); + addr = RX8900_ADDR; + + irq_intercept_out(RX8900_TEST_ID); + irq_attach(RX8900_INTERRUPT_OUT, 0, handle_interrupt, NULL); + irq_attach(RX8900_FOUT, 0, handle_fout, NULL); + + qtest_add_func("/rx8900/reset", check_reset); + qtest_add_func("/rx8900/tx-rx", send_and_receive); + qtest_add_func("/rx8900/temperature", check_temperature); + qtest_add_func("/rx8900/rollover", check_rollover); + qtest_add_func("/rx8900/update-interrupt-disabled", + check_update_interrupt_disabled); + qtest_add_func("/rx8900/update-interrupt-seconds", + check_update_interrupt_seconds); + qtest_add_func("/rx8900/update-interrupt-minutes", + check_update_interrupt_minutes); + qtest_add_func("/rx8900/alarm-interrupt-disabled", + check_alarm_interrupt_disabled); + qtest_add_func("/rx8900/alarm-interrupt-month", + check_alarm_interrupt_day_of_month); + qtest_add_func("/rx8900/alarm-interrupt-month-negative", + check_alarm_interrupt_day_of_month_negative); + qtest_add_func("/rx8900/alarm-interrupt-week", + check_alarm_interrupt_day_of_week); + qtest_add_func("/rx8900/alarm-interrupt-week-negative", + check_alarm_interrupt_day_of_week_negative); + qtest_add_func("/rx8900/fout_1hz", check_fout_1hz); + qtest_add_func("/rx8900/fout_1024hz", check_fout_1024hz); + qtest_add_func("/rx8900/fout_32768hz", check_fout_32768hz); + qtest_add_func("/rx8900/countdown_1hz", check_countdown_1hz); + qtest_add_func("/rx8900/countdown_64hz", check_countdown_64hz); + qtest_add_func("/rx8900/countdown_4096hz", check_countdown_4096hz); + qtest_add_func("/rx8900/countdown_1m", check_countdown_1m); + + ret = g_test_run(); + + if (s) { + qtest_quit(s); + } + g_free(i2c); + + return ret; +} -- 2.7.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support 2016-11-17 4:36 ` [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva @ 2016-11-17 8:29 ` Cédric Le Goater 2016-11-18 0:19 ` Alastair D'Silva 0 siblings, 1 reply; 22+ messages in thread From: Cédric Le Goater @ 2016-11-17 8:29 UTC (permalink / raw) To: Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley, Alastair D'Silva On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > From: Alastair D'Silva <alastair@d-silva.org> > > This patch adds support for the Epson RX8900 RTC chip. It would be nice to have a short list of the features this chip has and also the main point of the design. I see you are using a BH. > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > --- > default-configs/arm-softmmu.mak | 1 + > hw/timer/Makefile.objs | 2 + > hw/timer/rx8900.c | 891 ++++++++++++++++++++++++++++++++++++++++ > hw/timer/rx8900_regs.h | 125 ++++++ > tests/Makefile.include | 2 + > tests/rx8900-test.c | 800 ++++++++++++++++++++++++++++++++++++ Nice test ! But Why aren't you using the aspeed machine in qtest ? The reason I am asking is because the I2C controller model is a little too simplistic in the way it handles the irq status and we would need a test for it. Also I would put the test case in another patch, after the model and after patch 2 also which introduces named interrupts for qtest. > 6 files changed, 1821 insertions(+) > create mode 100644 hw/timer/rx8900.c > create mode 100644 hw/timer/rx8900_regs.h > create mode 100644 tests/rx8900-test.c > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > index 6de3e16..adb600e 100644 > --- a/default-configs/arm-softmmu.mak > +++ b/default-configs/arm-softmmu.mak > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y > CONFIG_ALLWINNER_EMAC=y > CONFIG_IMX_FEC=y > CONFIG_DS1338=y > +CONFIG_RX8900=y > CONFIG_PFLASH_CFI01=y > CONFIG_PFLASH_CFI02=y > CONFIG_MICRODRIVE=y > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs > index 7ba8c23..fa028ac 100644 > --- a/hw/timer/Makefile.objs > +++ b/hw/timer/Makefile.objs > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o > common-obj-$(CONFIG_DS1338) += ds1338.o > +common-obj-$(CONFIG_RX8900) += rx8900.o > common-obj-$(CONFIG_HPET) += hpet.o > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o > common-obj-$(CONFIG_M48T59) += m48t59.o > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o > common-obj-$(CONFIG_IMX) += imx_gpt.o > common-obj-$(CONFIG_LM32) += lm32_timer.o > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o > +common-obj-$(CONFIG_RX8900) += rx8900.o > > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o > diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c > new file mode 100644 > index 0000000..208a31b > --- /dev/null > +++ b/hw/timer/rx8900.c > @@ -0,0 +1,891 @@ > +/* > + * Epson RX8900SA/CE Realtime Clock Module > + * > + * Copyright (c) 2016 IBM Corporation > + * Authors: > + * Alastair D'Silva <alastair@d-silva.org> > + * > + * This code is licensed under the GPL version 2 or later. See > + * the COPYING file in the top-level directory. > + * > + * Datasheet available at: > + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE&lang=en > + * > + * Not implemented: > + * Implement Timer Counters > + * Implement i2c timeout > + */ > + > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "hw/i2c/i2c.h" > +#include "hw/timer/rx8900_regs.h" > +#include "hw/ptimer.h" > +#include "qemu/main-loop.h" > +#include "qemu/bcd.h" > +#include "qemu/error-report.h" > +#include "qemu/log.h" > +#include "qapi/error.h" > +#include "qapi/visitor.h" > + > + #include <sys/time.h> > + > + #include <execinfo.h> > + > +#define TYPE_RX8900 "rx8900" > +#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900) > + > +static bool log; > + > +typedef struct RX8900State { > + I2CSlave parent_obj; > + > + ptimer_state *sec_timer; /* triggered once per second */ > + ptimer_state *fout_timer; > + ptimer_state *countdown_timer; > + bool fout; > + int64_t offset; > + uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */ > + uint8_t wday_offset; > + uint8_t nvram[RX8900_NVRAM_SIZE]; > + int32_t ptr; /* Wrapped to stay within RX8900_NVRAM_SIZE */ > + bool addr_byte; > + uint8_t last_interrupt_seconds; > + uint8_t last_update_interrupt_minutes; > + qemu_irq interrupt_pin; > + qemu_irq fout_pin; > +} RX8900State; > + > +static const VMStateDescription vmstate_rx8900 = { > + .name = "rx8900", > + .version_id = 2, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_I2C_SLAVE(parent_obj, RX8900State), > + VMSTATE_PTIMER(sec_timer, RX8900State), > + VMSTATE_PTIMER(fout_timer, RX8900State), > + VMSTATE_PTIMER(countdown_timer, RX8900State), > + VMSTATE_BOOL(fout, RX8900State), > + VMSTATE_INT64(offset, RX8900State), > + VMSTATE_UINT8_V(weekday, RX8900State, 2), > + VMSTATE_UINT8_V(wday_offset, RX8900State, 2), > + VMSTATE_UINT8_ARRAY(nvram, RX8900State, RX8900_NVRAM_SIZE), > + VMSTATE_INT32(ptr, RX8900State), > + VMSTATE_BOOL(addr_byte, RX8900State), > + VMSTATE_UINT8_V(last_interrupt_seconds, RX8900State, 2), > + VMSTATE_UINT8_V(last_update_interrupt_minutes, RX8900State, 2), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void rx8900_reset(DeviceState *dev); > +static void disable_countdown_timer(RX8900State *s); > +static void enable_countdown_timer(RX8900State *s); > +static void disable_timer(RX8900State *s); > +static void enable_timer(RX8900State *s); > + > +#ifdef RX8900_TRACE > +#define RX8900_TRACE_BUF_SIZE 256 > +/** > + * Emit a trace message > + * @param file the source filename > + * @param line the line number the message was emitted from > + * @param dev the RX8900 device > + * @param fmt a printf style format > + */ > +static void trace(const char *file, int line, const char *func, > + I2CSlave *dev, const char *fmt, ...) > +{ > + va_list ap; > + char buf[RX8900_TRACE_BUF_SIZE]; > + char timestamp[32]; > + int len; > + struct timeval now; > + struct tm *now2; > + > + gettimeofday(&now, NULL); > + now2 = localtime(&now.tv_sec); > + > + strftime(timestamp, sizeof(timestamp), "%F %T", now2); > + > + len = snprintf(buf, sizeof(buf), "\n\t%s.%03ld %s:%s:%d: RX8900 %s %s@0x%x: %s", > + timestamp, now.tv_usec / 1000, > + file, func, line, dev->qdev.id, dev->qdev.parent_bus->name, > + dev->address, fmt); > + if (len >= RX8900_TRACE_BUF_SIZE) { > + error_report("%s:%d: Trace buffer overflow", file, line); > + } > + > + va_start(ap, fmt); > + error_vreport(buf, ap); > + va_end(ap); > +} > + > +/** > + * Emit a trace message > + * @param dev the RX8900 device > + * @param fmt a printf format > + */ > +#define TRACE(dev, fmt, ...) \ > + do { \ > + if (log) { \ > + trace(__FILE__, __LINE__, __func__, &dev, fmt, ## __VA_ARGS__); \ > + } \ > + } while (0) > +#else > +#define TRACE(dev, fmt, ...) > +#endif Although this is very pratical and nicely written, I don't think you can keep these TRACE calls in the code. You should use the qemu trace subsystem for it. > +static void capture_current_time(RX8900State *s) > +{ > + /* Capture the current time into the secondary registers > + * which will be actually read by the data transfer operation. > + */ > + struct tm now; > + qemu_get_timedate(&now, s->offset); > + s->nvram[SECONDS] = to_bcd(now.tm_sec); > + s->nvram[MINUTES] = to_bcd(now.tm_min); > + s->nvram[HOURS] = to_bcd(now.tm_hour); > + > + s->nvram[WEEKDAY] = 0x01 << ((now.tm_wday + s->wday_offset) % 7); > + s->nvram[DAY] = to_bcd(now.tm_mday); > + s->nvram[MONTH] = to_bcd(now.tm_mon + 1); > + s->nvram[YEAR] = to_bcd(now.tm_year % 100); > + > + s->nvram[EXT_SECONDS] = s->nvram[SECONDS]; > + s->nvram[EXT_MINUTES] = s->nvram[MINUTES]; > + s->nvram[EXT_HOURS] = s->nvram[HOURS]; > + s->nvram[EXT_WEEKDAY] = s->nvram[WEEKDAY]; > + s->nvram[EXT_DAY] = s->nvram[DAY]; > + s->nvram[EXT_MONTH] = s->nvram[MONTH]; > + s->nvram[EXT_YEAR] = s->nvram[YEAR]; > + > + TRACE(s->parent_obj, "Update current time to %02d:%02d:%02d %d %d/%d/%d " > + "(0x%02x%02x%02x%02x%02x%02x%02x)", > + now.tm_hour, now.tm_min, now.tm_sec, > + (now.tm_wday + s->wday_offset) % 7, > + now.tm_mday, now.tm_mon, now.tm_year + 1900, > + s->nvram[HOURS], s->nvram[MINUTES], s->nvram[SECONDS], > + s->nvram[WEEKDAY], > + s->nvram[DAY], s->nvram[MONTH], s->nvram[YEAR]); > +} > + > +/** > + * Increment the internal register pointer, dealing with wrapping > + * @param s the RTC to operate on > + */ > +static void inc_regptr(RX8900State *s) > +{ > + /* The register pointer wraps around after 0x1F > + */ > + s->ptr = (s->ptr + 1) & (RX8900_NVRAM_SIZE - 1); > + TRACE(s->parent_obj, "Operating on register 0x%02x", s->ptr); > + > + if (s->ptr == 0x00) { > + TRACE(s->parent_obj, "Register pointer has overflowed, wrapping to 0"); > + capture_current_time(s); > + } > +} > + > +/** > + * Receive an I2C Event > + * @param i2c the i2c device instance > + * @param event the event to handle > + */ > +static void rx8900_event(I2CSlave *i2c, enum i2c_event event) > +{ > + RX8900State *s = RX8900(i2c); > + > + switch (event) { > + case I2C_START_RECV: > + /* In h/w, time capture happens on any START condition, not just a > + * START_RECV. For the emulation, it doesn't actually matter, > + * since a START_RECV has to occur before the data can be read. > + */ > + capture_current_time(s); > + break; > + case I2C_START_SEND: > + s->addr_byte = true; > + break; > + case I2C_FINISH: > + if (s->weekday < 7) { > + /* We defer the weekday calculation as it is handed to us before > + * the date has been updated. If we calculate the weekday offset > + * when it is passed to us, we will incorrectly determine it > + * based on the current emulated date, rather than the date that > + * has been written. > + */ > + struct tm now; > + qemu_get_timedate(&now, s->offset); > + > + s->wday_offset = (s->weekday - now.tm_wday + 7) % 7; > + > + TRACE(s->parent_obj, "Set weekday to %d (0x%02x), wday_offset=%d", > + s->weekday, BIT(s->weekday), s->wday_offset); > + > + s->weekday = 7; > + } > + break; > + > + default: > + break; > + } > +} > + > +/** > + * Perform an i2c receive action > + * @param i2c the i2c device instance > + * @return the value of the current register > + * @post the internal register pointer is incremented > + */ > +static int rx8900_recv(I2CSlave *i2c) > +{ > + RX8900State *s = RX8900(i2c); > + uint8_t res = s->nvram[s->ptr]; > + TRACE(s->parent_obj, "Read register 0x%x = 0x%x", s->ptr, res); > + inc_regptr(s); > + return res; > +} > + > +/** > + * Validate the extension register and perform actions based on the bits > + * @param s the RTC to operate on > + * @param data the new data for the extension register > + */ > +static void update_extension_register(RX8900State *s, uint8_t data) > +{ > + if (data & EXT_MASK_TEST) { > + error_report("WARNING: RX8900 - " > + "Test bit is enabled but is forbidden by the manufacturer"); may be use instead : qemu_log_mask(LOG_GUEST_ERROR, > + } > + > + if ((data ^ s->nvram[EXTENSION_REGISTER]) & > + (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) { > + uint8_t fsel = (data & (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) > + >> EXT_REG_FSEL0; > + /* FSELx has changed */ > + switch (fsel) { > + case 0x01: > + TRACE(s->parent_obj, "Setting fout to 1024Hz"); > + ptimer_set_limit(s->fout_timer, 32, 1); > + break; > + case 0x02: > + TRACE(s->parent_obj, "Setting fout to 1Hz"); > + ptimer_set_limit(s->fout_timer, 32768, 1); > + break; > + default: > + TRACE(s->parent_obj, "Setting fout to 32768Hz"); > + ptimer_set_limit(s->fout_timer, 1, 1); > + break; > + } > + } > + > + if ((data ^ s->nvram[EXTENSION_REGISTER]) & > + (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) { > + uint8_t tsel = (data & (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) > + >> EXT_REG_TSEL0; > + /* TSELx has changed */ > + switch (tsel) { > + case 0x00: > + TRACE(s->parent_obj, "Setting countdown timer to 64 Hz"); > + ptimer_set_limit(s->countdown_timer, 4096 / 64, 1); > + break; > + case 0x01: > + TRACE(s->parent_obj, "Setting countdown timer to 1 Hz"); > + ptimer_set_limit(s->countdown_timer, 4096, 1); > + break; > + case 0x02: > + TRACE(s->parent_obj, > + "Setting countdown timer to per minute updates"); > + ptimer_set_limit(s->countdown_timer, 4069 * 60, 1); > + break; > + case 0x03: > + TRACE(s->parent_obj, "Setting countdown timer to 4096Hz"); > + ptimer_set_limit(s->countdown_timer, 1, 1); > + break; > + } > + } > + > + if (data & EXT_MASK_TE) { > + enable_countdown_timer(s); > + } > + > + s->nvram[EXTENSION_REGISTER] = data; > + s->nvram[EXT_EXTENSION_REGISTER] = data; > + > +} > +/** > + * Validate the control register and perform actions based on the bits > + * @param s the RTC to operate on > + * @param data the new value for the control register > + */ > + > +static void update_control_register(RX8900State *s, uint8_t data) > +{ > + uint8_t diffmask = ~s->nvram[CONTROL_REGISTER] & data; > + > + if (diffmask & CTRL_MASK_WP0) { > + data &= ~CTRL_MASK_WP0; > + error_report("WARNING: RX8900 - " > + "Attempt to write to write protected bit %d in control register", > + CTRL_REG_WP0); may be use instead : qemu_log_mask(LOG_GUEST_ERROR, > + } > + > + if (diffmask & CTRL_MASK_WP1) { > + data &= ~CTRL_MASK_WP1; > + error_report("WARNING: RX8900 - " > + "Attempt to write to write protected bit %d in control register", > + CTRL_REG_WP1); ditto for all in fact. > + } > + > + if (data & CTRL_MASK_RESET) { > + data &= ~CTRL_MASK_RESET; > + rx8900_reset(DEVICE(s)); > + } > + > + if (diffmask & CTRL_MASK_UIE) { > + /* Update interrupts were off and are now on */ > + struct tm now; > + > + TRACE(s->parent_obj, "Enabling update timer"); > + > + qemu_get_timedate(&now, s->offset); > + > + s->last_update_interrupt_minutes = now.tm_min; > + s->last_interrupt_seconds = now.tm_sec; > + enable_timer(s); > + } > + > + if (diffmask & CTRL_MASK_AIE) { > + /* Alarm interrupts were off and are now on */ > + struct tm now; > + > + TRACE(s->parent_obj, "Enabling alarm"); > + > + qemu_get_timedate(&now, s->offset); > + > + s->last_interrupt_seconds = now.tm_sec; > + enable_timer(s); > + } > + > + if (!(data & (CTRL_MASK_UIE | CTRL_MASK_AIE))) { > + disable_timer(s); > + } > + > + if (data & CTRL_MASK_TIE) { > + enable_countdown_timer(s); > + } > + > + s->nvram[CONTROL_REGISTER] = data; > + s->nvram[EXT_CONTROL_REGISTER] = data; > +} > + > +/** > + * Validate the flag register > + * @param s the RTC to operate on > + * @param data the new value for the flag register > + */ > +static void validate_flag_register(RX8900State *s, uint8_t *data) > +{ > + uint8_t diffmask = ~s->nvram[FLAG_REGISTER] & *data; > + > + if (diffmask & FLAG_MASK_VDET) { > + *data &= ~FLAG_MASK_VDET; > + error_report("WARNING: RX8900 - " > + "Only 0 can be written to VDET bit %d in the flag register", > + FLAG_REG_VDET); > + } > + > + if (diffmask & FLAG_MASK_VLF) { > + *data &= ~FLAG_MASK_VLF; > + error_report("WARNING: RX8900 - " > + "Only 0 can be written to VLF bit %d in the flag register", > + FLAG_REG_VLF); > + } > + > + if (diffmask & FLAG_MASK_UNUSED_2) { > + *data &= ~FLAG_MASK_UNUSED_2; > + error_report("WARNING: RX8900 - " > + "Only 0 can be written to unused bit %d in the flag register", > + FLAG_REG_UNUSED_2); > + } > + > + if (diffmask & FLAG_MASK_UNUSED_6) { > + *data &= ~FLAG_MASK_UNUSED_6; > + error_report("WARNING: RX8900 - " > + "Only 0 can be written to unused bit %d in the flag register", > + FLAG_REG_UNUSED_6); > + } > + > + if (diffmask & FLAG_MASK_UNUSED_7) { > + *data &= ~FLAG_MASK_UNUSED_7; > + error_report("WARNING: RX8900 - " > + "Only 0 can be written to unused bit %d in the flag register", > + FLAG_REG_UNUSED_7); > + } > +} > + > +/** > + * Tick the per second timer (can be called more frequently as it early exits > + * if the wall clock has not progressed) > + * @param opaque the RTC to tick > + */ > +static void rx8900_timer_tick(void *opaque) > +{ > + RX8900State *s = (RX8900State *)opaque; > + struct tm now; > + bool fire_interrupt = false; > + > + qemu_get_timedate(&now, s->offset); > + > + if (now.tm_sec == s->last_interrupt_seconds) { > + return; > + } > + > + s->last_interrupt_seconds = now.tm_sec; > + > + TRACE(s->parent_obj, "Tick"); > + > + /* Update timer interrupt */ > + if (s->nvram[CONTROL_REGISTER] & CTRL_MASK_UIE) { > + if ((s->nvram[EXTENSION_REGISTER] & EXT_MASK_USEL) && > + now.tm_min != s->last_update_interrupt_minutes) { > + s->last_update_interrupt_minutes = now.tm_min; > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF; > + fire_interrupt = true; > + } else if (!(s->nvram[EXTENSION_REGISTER] & EXT_MASK_USEL)) { > + /* per second update interrupt */ > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF; > + fire_interrupt = true; > + } > + } > + > + /* Alarm interrupt */ > + if ((s->nvram[CONTROL_REGISTER] & CTRL_MASK_AIE) && now.tm_sec == 0) { > + if (s->nvram[ALARM_MINUTE] == to_bcd(now.tm_min) && > + s->nvram[ALARM_HOUR] == to_bcd(now.tm_hour) && > + s->nvram[ALARM_WEEK_DAY] == > + ((s->nvram[EXTENSION_REGISTER] & EXT_MASK_WADA) ? > + to_bcd(now.tm_mday) : > + 0x01 << ((now.tm_wday + s->wday_offset) % 7))) { that's a nice if condition :) May be we could use a temp variable for the last one. > + TRACE(s->parent_obj, "Triggering alarm"); > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_AF; > + fire_interrupt = true; > + } > + } > + > + if (fire_interrupt) { > + TRACE(s->parent_obj, "Pulsing interrupt"); > + qemu_irq_pulse(s->interrupt_pin); > + } > +} > + > +/** > + * Disable the per second timer > + * @param s the RTC to operate on > + */ > +static void disable_timer(RX8900State *s) > +{ > + TRACE(s->parent_obj, "Disabling timer"); > + ptimer_stop(s->sec_timer); > +} > + > +/** > + * Enable the per second timer > + * @param s the RTC to operate on > + */ > +static void enable_timer(RX8900State *s) > +{ > + TRACE(s->parent_obj, "Enabling timer"); > + ptimer_run(s->sec_timer, 0); > +} > + > +/** > + * Handle FOUT_ENABLE (FOE) line > + * Enables/disables the FOUT line > + * @param opaque the device instance > + * @param n the IRQ number > + * @param level true if the line has been raised > + */ > +static void rx8900_fout_enable_handler(void *opaque, int n, int level) > +{ > + RX8900State *s = RX8900(opaque); > + > + if (level) { > + TRACE(s->parent_obj, "Enabling fout"); > + ptimer_run(s->fout_timer, 0); > + } else { > + /* disable fout */ > + TRACE(s->parent_obj, "Disabling fout"); > + ptimer_stop(s->fout_timer); > + } > +} > + > +/** > + * Tick the FOUT timer > + * @param opaque the device instance > + */ > +static void rx8900_fout_tick(void *opaque) > +{ > + RX8900State *s = (RX8900State *)opaque; > + > + TRACE(s->parent_obj, "fout toggle"); > + s->fout = !s->fout; > + > + if (s->fout) { > + qemu_irq_raise(s->fout_pin); > + } else { > + qemu_irq_lower(s->fout_pin); > + } > +} > + > + > +/** > + * Disable the countdown timer > + * @param s the RTC to operate on > + */ > +static void disable_countdown_timer(RX8900State *s) > +{ > + TRACE(s->parent_obj, "Disabling countdown timer"); > + ptimer_stop(s->countdown_timer); > +} > + > +/** > + * Enable the per second timer > + * @param s the RTC to operate on > + */ > +static void enable_countdown_timer(RX8900State *s) > +{ > + TRACE(s->parent_obj, "Enabling countdown timer"); > + ptimer_run(s->countdown_timer, 0); > +} These helpers don't add much I think. > +/** > + * Tick the countdown timer > + * @param opaque the device instance > + */ > +static void rx8900_countdown_tick(void *opaque) > +{ > + RX8900State *s = (RX8900State *)opaque; > + > + uint16_t count = s->nvram[TIMER_COUNTER_0] + > + ((s->nvram[TIMER_COUNTER_1] & 0x0F) << 8); > + TRACE(s->parent_obj, "countdown tick, count=%d", count); > + count--; > + > + s->nvram[TIMER_COUNTER_0] = (uint8_t)(count & 0x00ff); > + s->nvram[TIMER_COUNTER_1] = (uint8_t)((count & 0x0f00) >> 8); > + > + if (count == 0) { > + TRACE(s->parent_obj, "Countdown has elapsed, pulsing interrupt"); > + > + disable_countdown_timer(s); > + > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_TF; > + qemu_irq_pulse(s->interrupt_pin); > + } > +} > + > + > +/** > + * Receive a byte of data from i2c > + * @param i2c the i2c device that is receiving data > + * @param data the data that was received > + */ > +static int rx8900_send(I2CSlave *i2c, uint8_t data) > +{ > + RX8900State *s = RX8900(i2c); > + struct tm now; > + > + TRACE(s->parent_obj, "Received I2C data 0x%02x", data); > + > + if (s->addr_byte) { > + s->ptr = data & (RX8900_NVRAM_SIZE - 1); > + TRACE(s->parent_obj, "Operating on register 0x%02x", s->ptr); > + s->addr_byte = false; > + return 0; > + } > + > + TRACE(s->parent_obj, "Set data 0x%02x=0x%02x", s->ptr, data); > + > + qemu_get_timedate(&now, s->offset); > + switch (s->ptr) { > + case SECONDS: > + case EXT_SECONDS: > + now.tm_sec = from_bcd(data & 0x7f); > + s->offset = qemu_timedate_diff(&now); > + break; > + > + case MINUTES: > + case EXT_MINUTES: > + now.tm_min = from_bcd(data & 0x7f); > + s->offset = qemu_timedate_diff(&now); > + break; > + > + case HOURS: > + case EXT_HOURS: > + now.tm_hour = from_bcd(data & 0x3f); > + s->offset = qemu_timedate_diff(&now); > + break; > + > + case WEEKDAY: > + case EXT_WEEKDAY: { > + int user_wday = ctz32(data); > + /* The day field is supposed to contain a value in > + * the range 0-6. Otherwise behavior is undefined. > + */ > + switch (data) { > + case 0x01: > + case 0x02: > + case 0x04: > + case 0x08: > + case 0x10: > + case 0x20: > + case 0x40: > + break; > + default: > + error_report("WARNING: RX8900 - weekday data '%x' is out of range," > + " undefined behavior will result", data); > + break; > + } > + s->weekday = user_wday; > + break; > + } > + > + case DAY: > + case EXT_DAY: > + now.tm_mday = from_bcd(data & 0x3f); > + s->offset = qemu_timedate_diff(&now); > + break; > + > + case MONTH: > + case EXT_MONTH: > + now.tm_mon = from_bcd(data & 0x1f) - 1; > + s->offset = qemu_timedate_diff(&now); > + break; > + > + case YEAR: > + case EXT_YEAR: > + now.tm_year = from_bcd(data) + 100; > + s->offset = qemu_timedate_diff(&now); > + break; > + > + case EXTENSION_REGISTER: > + case EXT_EXTENSION_REGISTER: > + update_extension_register(s, data); > + break; > + > + case FLAG_REGISTER: > + case EXT_FLAG_REGISTER: > + validate_flag_register(s, &data); > + > + s->nvram[FLAG_REGISTER] = data; > + s->nvram[EXT_FLAG_REGISTER] = data; > + break; > + > + case CONTROL_REGISTER: > + case EXT_CONTROL_REGISTER: > + update_control_register(s, data); > + break; > + > + default: > + s->nvram[s->ptr] = data; > + } > + > + inc_regptr(s); > + return 0; > +} > + > +/** > + * Get the device temperature in Celcius as a property > + * @param obj the device > + * @param v > + * @param name the property name > + * @param opaque > + * @param errp an error object to populate on failure > + */ > +static void rx8900_get_temperature(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RX8900State *s = RX8900(obj); > + double value = (s->nvram[TEMPERATURE] * 2.0f - 187.1f) / 3.218f; > + > + TRACE(s->parent_obj, "Read temperature property, 0x%x = %f°C", > + s->nvram[TEMPERATURE], value); > + > + visit_type_number(v, name, &value, errp); > +} > + > +/** > + * Set the device temperature in Celcius as a property > + * @param obj the device > + * @param v > + * @param name the property name > + * @param opaque > + * @param errp an error object to populate on failure > + */ > +static void rx8900_set_temperature(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RX8900State *s = RX8900(obj); > + Error *local_err = NULL; > + double temp; /* degrees Celcius */ > + visit_type_number(v, name, &temp, &local_err); > + if (local_err) { > + error_propagate(errp, local_err); > + return; > + } > + if (temp >= 100 || temp < -58) { > + error_setg(errp, "value %f°C is out of range", temp); > + return; > + } > + > + s->nvram[TEMPERATURE] = (uint8_t) ((temp * 3.218f + 187.19f) / 2); > + > + TRACE(s->parent_obj, "Set temperature property, 0x%x = %f°C", > + s->nvram[TEMPERATURE], temp); > +} > + > + > +/** > + * Initialize the device > + * @param i2c the i2c device instance > + */ > +static int rx8900_init(I2CSlave *i2c) > +{ > + TRACE(*i2c, "Initialized"); > + > + return 0; > +} you can remove this routine. > +/** > + * Configure device properties > + * @param obj the device > + */ > +static void rx8900_initfn(Object *obj) > +{ > + object_property_add(obj, "temperature", "number", > + rx8900_get_temperature, > + rx8900_set_temperature, NULL, NULL, NULL); > +} > + > +/** > + * Reset the device > + * @param dev the RX8900 device to reset > + */ > +static void rx8900_reset(DeviceState *dev) > +{ > + RX8900State *s = RX8900(dev); > + > + TRACE(s->parent_obj, "Reset"); > + > + /* The clock is running and synchronized with the host */ > + s->offset = 0; > + s->weekday = 7; /* Set to an invalid value */ > + > + /* Temperature formulation from the datasheet > + * ( TEMP[ 7:0 ] * 2 - 187.19) / 3.218 > + * > + * Set the initial state to 25 degrees Celcius > + */ > + s->nvram[TEMPERATURE] = 135; /* (25 * 3.218 + 187.19) / 2 */ > + > + s->nvram[EXTENSION_REGISTER] = EXT_MASK_TSEL1; > + s->nvram[CONTROL_REGISTER] = CTRL_MASK_CSEL0; > + s->nvram[FLAG_REGISTER] = FLAG_MASK_VLF | FLAG_MASK_VDET; Just asking : why not fully memset(0) the nvram and then set the values ? Thanks, C. > + s->ptr = 0; > + TRACE(s->parent_obj, "Operating on register 0x%02x", s->ptr); > + > + s->addr_byte = false; > +} > + > +/** > + * Realize an RX8900 device instance > + * Set up timers > + * Configure GPIO lines > + * @param dev the device instance to realize > + * @param errp an error object to populate on error > + */ > +static void rx8900_realize(DeviceState *dev, Error **errp) > +{ > + RX8900State *s = RX8900(dev); > + I2CSlave *i2c = I2C_SLAVE(dev); > + QEMUBH *bh; > + char name[64]; > + > + s->fout = false; > + > + memset(s->nvram, 0, RX8900_NVRAM_SIZE); > + > + bh = qemu_bh_new(rx8900_timer_tick, s); > + s->sec_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); > + /* we trigger the timer at 10Hz and check for rollover, as the qemu > + * clock does not advance in realtime in the test environment, > + * leading to unstable test results > + */ > + ptimer_set_freq(s->sec_timer, 10); > + ptimer_set_limit(s->sec_timer, 1, 1); > + > + bh = qemu_bh_new(rx8900_fout_tick, s); > + s->fout_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); > + /* frequency doubled to generate 50% duty cycle square wave */ > + ptimer_set_freq(s->fout_timer, 32768 * 2); > + ptimer_set_limit(s->fout_timer, 1, 1); > + > + bh = qemu_bh_new(rx8900_countdown_tick, s); > + s->countdown_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); > + ptimer_set_freq(s->countdown_timer, 4096); > + ptimer_set_limit(s->countdown_timer, 4096, 1); > + > + > + snprintf(name, sizeof(name), "rx8900-interrupt-out"); > + qdev_init_gpio_out_named(&i2c->qdev, &s->interrupt_pin, name, 1); > + TRACE(s->parent_obj, "Interrupt pin is '%s'", name); > + > + snprintf(name, sizeof(name), "rx8900-fout-enable"); > + qdev_init_gpio_in_named(&i2c->qdev, rx8900_fout_enable_handler, name, 1); > + TRACE(s->parent_obj, "Fout-enable pin is '%s'", name); > + > + snprintf(name, sizeof(name), "rx8900-fout"); > + qdev_init_gpio_out_named(&i2c->qdev, &s->fout_pin, name, 1); > + TRACE(s->parent_obj, "Fout pin is '%s'", name); > +} > + > +/** > + * Set up the device callbacks > + * @param klass the device class > + * @param data > + */ > +static void rx8900_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); > + > + k->init = rx8900_init; > + k->event = rx8900_event; > + k->recv = rx8900_recv; > + k->send = rx8900_send; > + dc->realize = rx8900_realize; > + dc->reset = rx8900_reset; > + dc->vmsd = &vmstate_rx8900; > +} > + > +static const TypeInfo rx8900_info = { > + .name = TYPE_RX8900, > + .parent = TYPE_I2C_SLAVE, > + .instance_size = sizeof(RX8900State), > + .instance_init = rx8900_initfn, > + .class_init = rx8900_class_init, > +}; > + > +/** > + * Register the device with QEMU > + */ > +static void rx8900_register_types(void) > +{ > + log = getenv("RX8900_TRACE") != NULL; > + type_register_static(&rx8900_info); > +} > + > +type_init(rx8900_register_types) > diff --git a/hw/timer/rx8900_regs.h b/hw/timer/rx8900_regs.h > new file mode 100644 > index 0000000..5261c76 > --- /dev/null > +++ b/hw/timer/rx8900_regs.h > @@ -0,0 +1,125 @@ > +/* > + * Epson RX8900SA/CE Realtime Clock Module > + * > + * Copyright (c) 2016 IBM Corporation > + * Authors: > + * Alastair D'Silva <alastair@d-silva.org> > + * > + * This code is licensed under the GPL version 2 or later. See > + * the COPYING file in the top-level directory. > + * > + * Datasheet available at: > + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE&lang=en > + * > + */ > + > +#ifndef RX8900_REGS_H > +#define RX8900_REGS_H > + > +#include "qemu/bitops.h" > + > +#define RX8900_NVRAM_SIZE 0x20 > + > +typedef enum RX8900Addresses { > + SECONDS = 0x00, > + MINUTES = 0x01, > + HOURS = 0x02, > + WEEKDAY = 0x03, > + DAY = 0x04, > + MONTH = 0x05, > + YEAR = 0x06, > + RAM = 0x07, > + ALARM_MINUTE = 0x08, > + ALARM_HOUR = 0x09, > + ALARM_WEEK_DAY = 0x0A, > + TIMER_COUNTER_0 = 0x0B, > + TIMER_COUNTER_1 = 0x0C, > + EXTENSION_REGISTER = 0x0D, > + FLAG_REGISTER = 0X0E, > + CONTROL_REGISTER = 0X0F, > + EXT_SECONDS = 0x010, /* Alias of SECONDS */ > + EXT_MINUTES = 0x11, /* Alias of MINUTES */ > + EXT_HOURS = 0x12, /* Alias of HOURS */ > + EXT_WEEKDAY = 0x13, /* Alias of WEEKDAY */ > + EXT_DAY = 0x14, /* Alias of DAY */ > + EXT_MONTH = 0x15, /* Alias of MONTH */ > + EXT_YEAR = 0x16, /* Alias of YEAR */ > + TEMPERATURE = 0x17, > + BACKUP_FUNCTION = 0x18, > + NO_USE_1 = 0x19, > + NO_USE_2 = 0x1A, > + EXT_TIMER_COUNTER_0 = 0x1B, /* Alias of TIMER_COUNTER_0 */ > + EXT_TIMER_COUNTER_1 = 0x1C, /* Alias of TIMER_COUNTER_1 */ > + EXT_EXTENSION_REGISTER = 0x1D, /* Alias of EXTENSION_REGISTER */ > + EXT_FLAG_REGISTER = 0X1E, /* Alias of FLAG_REGISTER */ > + EXT_CONTROL_REGISTER = 0X1F /* Alias of CONTROL_REGISTER */ > +} RX8900Addresses; > + > +typedef enum ExtRegBits { > + EXT_REG_TSEL0 = 0, > + EXT_REG_TSEL1 = 1, > + EXT_REG_FSEL0 = 2, > + EXT_REG_FSEL1 = 3, > + EXT_REG_TE = 4, > + EXT_REG_USEL = 5, > + EXT_REG_WADA = 6, > + EXT_REG_TEST = 7 > +} ExtRegBits; > + > +typedef enum ExtRegMasks { > + EXT_MASK_TSEL0 = BIT(0), > + EXT_MASK_TSEL1 = BIT(1), > + EXT_MASK_FSEL0 = BIT(2), > + EXT_MASK_FSEL1 = BIT(3), > + EXT_MASK_TE = BIT(4), > + EXT_MASK_USEL = BIT(5), > + EXT_MASK_WADA = BIT(6), > + EXT_MASK_TEST = BIT(7) > +} ExtRegMasks; > + > +typedef enum CtrlRegBits { > + CTRL_REG_RESET = 0, > + CTRL_REG_WP0 = 1, > + CTRL_REG_WP1 = 2, > + CTRL_REG_AIE = 3, > + CTRL_REG_TIE = 4, > + CTRL_REG_UIE = 5, > + CTRL_REG_CSEL0 = 6, > + CTRL_REG_CSEL1 = 7 > +} CtrlRegBits; > + > +typedef enum CtrlRegMask { > + CTRL_MASK_RESET = BIT(0), > + CTRL_MASK_WP0 = BIT(1), > + CTRL_MASK_WP1 = BIT(2), > + CTRL_MASK_AIE = BIT(3), > + CTRL_MASK_TIE = BIT(4), > + CTRL_MASK_UIE = BIT(5), > + CTRL_MASK_CSEL0 = BIT(6), > + CTRL_MASK_CSEL1 = BIT(7) > +} CtrlRegMask; > + > +typedef enum FlagRegBits { > + FLAG_REG_VDET = 0, > + FLAG_REG_VLF = 1, > + FLAG_REG_UNUSED_2 = 2, > + FLAG_REG_AF = 3, > + FLAG_REG_TF = 4, > + FLAG_REG_UF = 5, > + FLAG_REG_UNUSED_6 = 6, > + FLAG_REG_UNUSED_7 = 7 > +} FlagRegBits; > + > +#define RX8900_INTERRUPT_SOURCES 6 > +typedef enum FlagRegMask { > + FLAG_MASK_VDET = BIT(0), > + FLAG_MASK_VLF = BIT(1), > + FLAG_MASK_UNUSED_2 = BIT(2), > + FLAG_MASK_AF = BIT(3), > + FLAG_MASK_TF = BIT(4), > + FLAG_MASK_UF = BIT(5), > + FLAG_MASK_UNUSED_6 = BIT(6), > + FLAG_MASK_UNUSED_7 = BIT(7) > +} FlagRegMask; > + > +#endif > diff --git a/tests/Makefile.include b/tests/Makefile.include > index e98d3b6..e52e355 100644 > --- a/tests/Makefile.include > +++ b/tests/Makefile.include > @@ -300,6 +300,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF) > > check-qtest-arm-y = tests/tmp105-test$(EXESUF) > check-qtest-arm-y += tests/ds1338-test$(EXESUF) > +check-qtest-arm-y += tests/rx8900-test$(EXESUF) > check-qtest-arm-y += tests/m25p80-test$(EXESUF) > gcov-files-arm-y += hw/misc/tmp105.c > check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) > @@ -637,6 +638,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \ > tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) > tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) > tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) > +tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-y) > tests/m25p80-test$(EXESUF): tests/m25p80-test.o > tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) > tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) > diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c > new file mode 100644 > index 0000000..a56426b > --- /dev/null > +++ b/tests/rx8900-test.c > @@ -0,0 +1,800 @@ > +/* > + * QTest testcase for the Enpes RX8900SA/CE RTC > + * > + * Copyright (c) 2016 IBM Corporation > + * Authors: > + * Alastair D'Silva <alastair@d-silva.org> > + * > + * This code is licensed under the GPL version 2 or later. See > + * the COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/timer/rx8900_regs.h" > +#include "libqtest.h" > +#include "libqos/i2c.h" > +#include "qemu/timer.h" > + > +#define IMX25_I2C_0_BASE 0x43F80000 > +#define RX8900_TEST_ID "rx8900-test" > +#define RX8900_ADDR 0x32 > +#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out" > +#define RX8900_FOUT_ENABLE "rx8900-fout-enable" > +#define RX8900_FOUT "rx8900-fout" > > +static I2CAdapter *i2c; > +static uint8_t addr; > + > +static inline uint8_t bcd2bin(uint8_t x) > +{ > + return (x & 0x0f) + (x >> 4) * 10; > +} > + > +static inline uint8_t bin2bcd(uint8_t x) > +{ > + return (x / 10 << 4) | (x % 10); > +} > + > +static void qmp_rx8900_set_temperature(const char *id, double value) > +{ > + QDict *response; > + > + response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, " > + "'property': 'temperature', 'value': %f } }", id, value); > + g_assert(qdict_haskey(response, "return")); > + QDECREF(response); > +} > + > +/** > + * Read an RX8900 register > + * @param reg the address of the register > + * @return the value of the register > + */ > +static uint8_t read_register(RX8900Addresses reg) > +{ > + uint8_t val; > + uint8_t reg_address = (uint8_t)reg; > + > + i2c_send(i2c, addr, ®_address, 1); > + i2c_recv(i2c, addr, &val, 1); > + > + return val; > +} > + > +/** > + * Write to an RX8900 register > + * @param reg the address of the register > + * @param val the value to write > + */ > +static uint8_t write_register(RX8900Addresses reg, uint8_t val) > +{ > + uint8_t buf[2]; > + > + buf[0] = reg; > + buf[1] = val; > + > + i2c_send(i2c, addr, buf, 2); > + > + return val; > +} > + > +/** > + * Set bits in a register > + * @param reg the address of the register > + * @param mask a mask of the bits to set > + */ > +static void set_bits_in_register(RX8900Addresses reg, uint8_t mask) > +{ > + uint8_t value = read_register(reg); > + value |= mask; > + write_register(reg, value); > +} > + > +/** > + * Clear bits in a register > + * @param reg the address of the register > + * @param mask a mask of the bits to set > + */ > +static void clear_bits_in_register(RX8900Addresses reg, uint8_t mask) > +{ > + uint8_t value = read_register(reg); > + value &= ~mask; > + write_register(reg, value); > +} > + > +/** > + * Read a number of sequential RX8900 registers > + * @param reg the address of the first register > + * @param buf (out) an output buffer to stash the register values > + * @param count the number of registers to read > + */ > +static void read_registers(RX8900Addresses reg, uint8_t *buf, uint8_t count) > +{ > + uint8_t reg_address = (uint8_t)reg; > + > + i2c_send(i2c, addr, ®_address, 1); > + i2c_recv(i2c, addr, buf, count); > +} > + > +/** > + * Write to a sequential number of RX8900 registers > + * @param reg the address of the first register > + * @param buffer a buffer of values to write > + * @param count the sumber of registers to write > + */ > +static void write_registers(RX8900Addresses reg, uint8_t *buffer, uint8_t count) > +{ > + uint8_t buf[RX8900_NVRAM_SIZE + 1]; > + > + buf[0] = (uint8_t)reg; > + memcpy(buf + 1, buffer, count); > + > + i2c_send(i2c, addr, buf, count + 1); > +} > + > +/** > + * Set the time on the RX8900 > + * @param secs the seconds to set > + * @param mins the minutes to set > + * @param hours the hours to set > + * @param weekday the day of the week to set (0 = Sunday) > + * @param day the day of the month to set > + * @param month the month to set > + * @param year the year to set > + */ > +static void set_time(uint8_t secs, uint8_t mins, uint8_t hours, > + uint8_t weekday, uint8_t day, uint8_t month, uint8_t year) > +{ > + uint8_t buf[7]; > + > + buf[0] = bin2bcd(secs); > + buf[1] = bin2bcd(mins); > + buf[2] = bin2bcd(hours); > + buf[3] = BIT(weekday); > + buf[4] = bin2bcd(day); > + buf[5] = bin2bcd(month); > + buf[6] = bin2bcd(year); > + > + write_registers(SECONDS, buf, 7); > +} > + > + > +/** > + * Check basic communication > + */ > +static void send_and_receive(void) > +{ > + uint8_t buf[7]; > + time_t now = time(NULL); > + struct tm *tm_ptr; > + > + /* retrieve the date */ > + read_registers(SECONDS, buf, 7); > + > + tm_ptr = gmtime(&now); > + > + /* check retrieved time against local time */ > + g_assert_cmpuint(bcd2bin(buf[0]), == , tm_ptr->tm_sec); > + g_assert_cmpuint(bcd2bin(buf[1]), == , tm_ptr->tm_min); > + g_assert_cmpuint(bcd2bin(buf[2]), == , tm_ptr->tm_hour); > + g_assert_cmpuint(bcd2bin(buf[4]), == , tm_ptr->tm_mday); > + g_assert_cmpuint(bcd2bin(buf[5]), == , 1 + tm_ptr->tm_mon); > + g_assert_cmpuint(2000 + bcd2bin(buf[6]), == , 1900 + tm_ptr->tm_year); > +} > + > +/** > + * Check that the temperature can be altered via properties > + */ > +static void check_temperature(void) > +{ > + /* Check the initial temperature is 25C */ > + uint8_t temperature; > + > + temperature = read_register(TEMPERATURE); > + g_assert_cmpuint(temperature, == , 135); > + > + /* Set the temperature to 40C and check the temperature again */ > + qmp_rx8900_set_temperature(RX8900_TEST_ID, 40.0f); > + temperature = read_register(TEMPERATURE); > + g_assert_cmpuint(temperature, == , 157); > +} > + > +/** > + * Check that the time rolls over correctly > + */ > +static void check_rollover(void) > +{ > + uint8_t buf[7]; > + > + > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + /* Wait for the clock to rollover */ > + sleep(2); > + > + memset(buf, 0, sizeof(buf)); > + > + /* Check that the clock rolled over */ > + /* Read from registers starting at 0x00 */ > + buf[0] = 0x00; > + > + read_registers(SECONDS, buf, 7); > + > + /* Ignore seconds as there may be some noise, > + * we expect 00:00:xx Tuesday 1/3/2016 > + */ > + g_assert_cmpuint(bcd2bin(buf[1]), == , 0); > + g_assert_cmpuint(bcd2bin(buf[2]), == , 0); > + g_assert_cmpuint(bcd2bin(buf[3]), == , 0x04); > + g_assert_cmpuint(bcd2bin(buf[4]), == , 1); > + g_assert_cmpuint(bcd2bin(buf[5]), == , 3); > + g_assert_cmpuint(bcd2bin(buf[6]), == , 16); > +} > + > +uint32_t interrupt_counts[RX8900_INTERRUPT_SOURCES]; > + > +/** > + * Reset the interrupt counts > + */ > +static void count_reset(void) > +{ > + for (int source = 0; source < RX8900_INTERRUPT_SOURCES; source++) { > + interrupt_counts[source] = 0; > + } > +} > + > +/** > + * Handle an RX8900 interrupt (update the counts for that interrupt type) > + */ > +static void handle_interrupt(void *opaque, const char *name, int irq, > + bool level) > +{ > + if (!level) { > + return; > + } > + > + uint8_t flags = read_register(FLAG_REGISTER); > + > + for (int flag = 0; flag < 8; flag++) { > + if (flags & BIT(flag)) { > + interrupt_counts[flag]++; > + } > + } > + > + write_register(FLAG_REGISTER, 0x00); > +} > + > +uint32_t fout_counts; > + > +/** > + * Handle an Fout state change > + */ > +static void handle_fout(void *opaque, const char *name, int irq, bool level) > +{ > + if (!level) { > + return; > + } > + > + fout_counts++; > +} > + > +/** > + * Reset the fout count > + */ > +static void fout_count_reset(void) > +{ > + fout_counts = 0; > +} > + > + > +/** > + * Sleep for some real time while counting interrupts > + * @param delay the delay in microseconds > + * @param loop the loop time in microseconds > + */ > +static void wait_for(uint64_t delay, uint64_t loop) > +{ > + struct timeval end, now; > + > + gettimeofday(&end, NULL); > + delay += end.tv_usec; > + end.tv_sec += delay / 1000000; > + end.tv_usec = delay % 1000000; > + > + while (gettimeofday(&now, NULL), > + now.tv_sec < end.tv_sec || now.tv_usec < end.tv_usec) { > + clock_step(loop * 1000); > + usleep(loop); > + } > +} > + > +/** > + * Sleep for some emulated time while counting interrupts > + * @param delay the delay in nanoseconds > + * @param loop the loop time in nanoseconds > + */ > +static void wait_cycles(uint64_t delay, uint64_t loop) > +{ > + uint64_t counter; > + > + for (counter = 0; counter < delay; counter += loop) { > + clock_step(loop); > + } > +} > + > + > +/** > + * Check that when the update timer interrupt is disabled, that no interrupts > + * occur > + */ > +static void check_update_interrupt_disabled(void) > +{ > + /* Disable the update interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); > + > + /* Wait for the clock to rollover, this will cover both seconds & minutes > + */ > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + count_reset(); > + wait_for(2 * 1000000, 1000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); > +} > + > + > +/** > + * Check that when the update timer interrupt is enabled and configured for > + * per second updates, that we get the appropriate number of interrupts > + */ > +static void check_update_interrupt_seconds(void) > +{ > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + /* Enable the update interrupt for per second updates */ > + clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_USEL); > + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); > + > + count_reset(); > + wait_for(5.1f * 1000000ULL, 1000); > + > + /* Disable the update interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 5); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); > +} > + > +/** > + * Check that when the update timer interrupt is enabled and configured for > + * per minute updates, that we get the appropriate number of interrupts > + */ > +static void check_update_interrupt_minutes(void) > +{ > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + /* Enable the update interrupt for per minute updates */ > + set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_USEL); > + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); > + > + count_reset(); > + wait_for(5 * 1000000ULL, 1000); > + > + /* Disable the update interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 1); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); > +} > + > + > +/** > + * Check that when the alarm timer interrupt is disabled, that no interrupts > + * occur > + */ > +static void check_alarm_interrupt_disabled(void) > +{ > + /* Disable the alarm interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + /* Set an alarm for midnight */ > + uint8_t buf[3]; > + > + buf[0] = bin2bcd(0); /* minutes */ > + buf[1] = bin2bcd(0); /* hours */ > + buf[2] = bin2bcd(1); /* day */ > + > + write_registers(ALARM_MINUTE, buf, 3); > + > + /* Wait for the clock to rollover */ > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + count_reset(); > + wait_for(2 * 1000000, 1000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); > +} > + > +/** > + * Check that when the alarm timer interrupt is enabled, that an interrupt > + * occurs > + */ > +static void check_alarm_interrupt_day_of_month(void) > +{ > + > + /* Set an alarm for midnight */ > + uint8_t buf[3]; > + > + buf[0] = bin2bcd(0); /* minutes */ > + buf[1] = bin2bcd(0); /* hours */ > + buf[2] = bin2bcd(1); /* day */ > + > + write_registers(ALARM_MINUTE, buf, 3); > + > + /* Set alarm to day of month mode */ > + set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); > + > + /* Enable the alarm interrupt */ > + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + /* Wait for the clock to rollover */ > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + count_reset(); > + wait_for(2 * 1000000, 1000); > + > + /* Disable the alarm interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 1); > +} > + > +/** > + * Check that when the alarm timer interrupt is enabled, that an interrupt > + * does not occur > + */ > +static void check_alarm_interrupt_day_of_month_negative(void) > +{ > + > + /* Set an alarm for midnight */ > + uint8_t buf[3]; > + > + buf[0] = bin2bcd(0); /* minutes */ > + buf[1] = bin2bcd(0); /* hours */ > + buf[2] = bin2bcd(2); /* day */ > + > + write_registers(ALARM_MINUTE, buf, 3); > + > + /* Set alarm to day of month mode */ > + set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); > + > + /* Enable the alarm interrupt */ > + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + /* Wait for the clock to rollover */ > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + count_reset(); > + wait_for(2 * 1000000, 1000); > + > + /* Disable the alarm interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); > +} > + > +/** > + * Check that when the alarm timer interrupt is enabled, that an interrupt > + * occurs > + */ > +static void check_alarm_interrupt_day_of_week(void) > +{ > + > + /* Set an alarm for midnight */ > + uint8_t buf[3]; > + > + buf[0] = bin2bcd(0); /* minutes */ > + buf[1] = bin2bcd(0); /* hours */ > + buf[2] = 0x01 << 2; /* day */ > + > + write_registers(ALARM_MINUTE, buf, 3); > + > + /* Set alarm to day of week mode */ > + clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); > + > + /* Enable the alarm interrupt */ > + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + /* Wait for the clock to rollover */ > + set_time(59, 59, 23, 1, 29, 2, 16); > + > + count_reset(); > + wait_for(2 * 1000000, 1000); > + > + /* Disable the alarm interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 1); > +} > + > +/** > + * Check that when the alarm timer interrupt is enabled, that an interrupt > + * does not occur > + */ > +static void check_alarm_interrupt_day_of_week_negative(void) > +{ > + > + /* Set an alarm for midnight */ > + uint8_t buf[3]; > + > + buf[0] = bin2bcd(0); /* minutes */ > + buf[1] = bin2bcd(0); /* hours */ > + buf[2] = 0x01 << 2; /* day */ > + > + write_registers(ALARM_MINUTE, buf, 3); > + > + /* Set alarm to day of week mode */ > + clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA); > + > + /* Enable the alarm interrupt */ > + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + /* Wait for the clock to rollover */ > + set_time(59, 59, 23, 3, 29, 2, 16); > + > + count_reset(); > + wait_for(2 * 1000000, 1000); > + > + /* Disable the alarm interrupt */ > + clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0); > + g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0); > +} > + > +/** > + * Check that the reset function > + */ > +static void check_reset(void) > +{ > + set_bits_in_register(FLAG_REGISTER, FLAG_MASK_UF); > + set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_RESET); > + > + g_assert_cmpuint(read_register(FLAG_REGISTER), ==, > + FLAG_MASK_VLF | FLAG_MASK_VDET); > +} > + > +/** > + * Check that Fout operates at 1Hz > + */ > +static void check_fout_1hz(void) > +{ > + uint8_t ext_reg = read_register(EXTENSION_REGISTER); > + ext_reg |= EXT_MASK_FSEL1; > + ext_reg &= ~EXT_MASK_FSEL0; > + write_register(EXTENSION_REGISTER, ext_reg); > + > + /* Enable Fout */ > + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true); > + > + fout_count_reset(); > + wait_cycles(2 * 1000000000ULL, 1000000); > + > + /* disable Fout */ > + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false); > + > + g_assert_cmpuint(fout_counts, ==, 2); > +} > + > +/** > + * Check that Fout operates at 1024Hz > + */ > +static void check_fout_1024hz(void) > +{ > + uint8_t ext_reg = read_register(EXTENSION_REGISTER); > + ext_reg |= EXT_MASK_FSEL0; > + ext_reg &= ~EXT_MASK_FSEL1; > + write_register(EXTENSION_REGISTER, ext_reg); > + > + /* Enable Fout */ > + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true); > + > + fout_count_reset(); > + wait_cycles(2 * 1000000000ULL, 100000); > + > + /* disable Fout */ > + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false); > + > + g_assert_cmpuint(fout_counts, ==, 1024 * 2); > +} > + > +/** > + * Check that Fout operates at 32768Hz > + */ > +static void check_fout_32768hz(void) > +{ > + uint8_t ext_reg = read_register(EXTENSION_REGISTER); > + ext_reg &= ~EXT_MASK_FSEL0; > + ext_reg &= ~EXT_MASK_FSEL1; > + write_register(EXTENSION_REGISTER, ext_reg); > + > + /* Enable Fout */ > + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true); > + > + fout_count_reset(); > + wait_cycles(2 * 1000000000ULL, 15000); > + > + /* disable Fout */ > + irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false); > + > + /* There appears to be some rounding errors in the timer, > + * we'll tolerate it for now > + */ > + g_assert_cmpuint(fout_counts, >=, 32768 * 2); > + g_assert_cmpuint(fout_counts, <=, 65540); > +} > + > +/** > + * Check the countdown timer operates at 1 Hz > + */ > +static void check_countdown_1hz(void) > +{ > + uint8_t ext_reg; > + > + write_register(TIMER_COUNTER_0, 5); > + write_register(TIMER_COUNTER_1, 0); > + > + ext_reg = read_register(EXTENSION_REGISTER); > + ext_reg &= ~EXT_MASK_TSEL1; > + ext_reg |= EXT_MASK_TSEL0; > + ext_reg |= EXT_MASK_TE; > + write_register(EXTENSION_REGISTER, ext_reg); > + > + count_reset(); > + wait_cycles(5 * 1000000000ULL, 1000000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); > + > + wait_cycles(1 * 1000000000ULL, 1000000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); > +} > + > +/** > + * Check the countdown timer operates at 64 Hz > + */ > +static void check_countdown_64hz(void) > +{ > + uint8_t ext_reg; > + > + write_register(TIMER_COUNTER_0, 0x40); > + write_register(TIMER_COUNTER_1, 0x01); /* 5 * 64 */ > + > + ext_reg = read_register(EXTENSION_REGISTER); > + ext_reg &= ~EXT_MASK_TSEL0; > + ext_reg &= ~EXT_MASK_TSEL1; > + ext_reg |= EXT_MASK_TE; > + write_register(EXTENSION_REGISTER, ext_reg); > + > + count_reset(); > + wait_cycles(5 * 1000000000ULL, 1000000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); > + > + wait_cycles(1 * 1000000000ULL, 1000000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); > +} > + > +/** > + * Check the countdown timer operates at 4096 Hz > + */ > +static void check_countdown_4096hz(void) > +{ > + uint8_t ext_reg; > + > + write_register(TIMER_COUNTER_0, 0xFF); > + write_register(TIMER_COUNTER_1, 0x0F); /* 4095 */ > + ext_reg = read_register(EXTENSION_REGISTER); > + ext_reg |= EXT_MASK_TSEL0; > + ext_reg |= EXT_MASK_TSEL1; > + ext_reg |= EXT_MASK_TE; > + write_register(EXTENSION_REGISTER, ext_reg); > + > + count_reset(); > + wait_cycles(999755859ULL, 10000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); > + > + wait_cycles(244141ULL, 10000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); > +} > + > +/** > + * Check the countdown timer operates at 1 minute > + */ > +static void check_countdown_1m(void) > +{ > + uint8_t ext_reg; > + > + write_register(TIMER_COUNTER_0, 0x01); > + write_register(TIMER_COUNTER_1, 0x00); > + ext_reg = read_register(EXTENSION_REGISTER); > + ext_reg &= ~EXT_MASK_TSEL0; > + ext_reg |= EXT_MASK_TSEL1; > + ext_reg |= EXT_MASK_TE; > + write_register(EXTENSION_REGISTER, ext_reg); > + > + count_reset(); > + wait_cycles(59 * 1000000000ULL, 100000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0); > + > + wait_cycles(1000000000LL, 100000); > + > + g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1); > +} > + > + > +int main(int argc, char **argv) > +{ > + QTestState *s = NULL; > + int ret; > + char args[255]; > + snprintf(args, sizeof(args), "-display none -machine imx25-pdk " > + "-device rx8900,bus=i2c.0,address=0x%x,id=%s", > + RX8900_ADDR, RX8900_TEST_ID); > + > + g_test_init(&argc, &argv, NULL); > + > + s = qtest_start(args); > + i2c = imx_i2c_create(IMX25_I2C_0_BASE); > + addr = RX8900_ADDR; > + > + irq_intercept_out(RX8900_TEST_ID); > + irq_attach(RX8900_INTERRUPT_OUT, 0, handle_interrupt, NULL); > + irq_attach(RX8900_FOUT, 0, handle_fout, NULL); > + > + qtest_add_func("/rx8900/reset", check_reset); > + qtest_add_func("/rx8900/tx-rx", send_and_receive); > + qtest_add_func("/rx8900/temperature", check_temperature); > + qtest_add_func("/rx8900/rollover", check_rollover); > + qtest_add_func("/rx8900/update-interrupt-disabled", > + check_update_interrupt_disabled); > + qtest_add_func("/rx8900/update-interrupt-seconds", > + check_update_interrupt_seconds); > + qtest_add_func("/rx8900/update-interrupt-minutes", > + check_update_interrupt_minutes); > + qtest_add_func("/rx8900/alarm-interrupt-disabled", > + check_alarm_interrupt_disabled); > + qtest_add_func("/rx8900/alarm-interrupt-month", > + check_alarm_interrupt_day_of_month); > + qtest_add_func("/rx8900/alarm-interrupt-month-negative", > + check_alarm_interrupt_day_of_month_negative); > + qtest_add_func("/rx8900/alarm-interrupt-week", > + check_alarm_interrupt_day_of_week); > + qtest_add_func("/rx8900/alarm-interrupt-week-negative", > + check_alarm_interrupt_day_of_week_negative); > + qtest_add_func("/rx8900/fout_1hz", check_fout_1hz); > + qtest_add_func("/rx8900/fout_1024hz", check_fout_1024hz); > + qtest_add_func("/rx8900/fout_32768hz", check_fout_32768hz); > + qtest_add_func("/rx8900/countdown_1hz", check_countdown_1hz); > + qtest_add_func("/rx8900/countdown_64hz", check_countdown_64hz); > + qtest_add_func("/rx8900/countdown_4096hz", check_countdown_4096hz); > + qtest_add_func("/rx8900/countdown_1m", check_countdown_1m); > + > + ret = g_test_run(); > + > + if (s) { > + qtest_quit(s); > + } > + g_free(i2c); > + > + return ret; > +} > ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support 2016-11-17 8:29 ` Cédric Le Goater @ 2016-11-18 0:19 ` Alastair D'Silva 2016-11-18 8:52 ` Cédric Le Goater 0 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-18 0:19 UTC (permalink / raw) To: Cédric Le Goater, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley On Thu, 2016-11-17 at 09:29 +0100, Cédric Le Goater wrote: On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > > > > From: Alastair D'Silva <alastair@d-silva.org> > > > > This patch adds support for the Epson RX8900 RTC chip. > > It would be nice to have a short list of the features this > chip has and also the main point of the design. I see you > are using a BH. > Ok > > > > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > > --- > > default-configs/arm-softmmu.mak | 1 + > > hw/timer/Makefile.objs | 2 + > > hw/timer/rx8900.c | 891 > > ++++++++++++++++++++++++++++++++++++++++ > > hw/timer/rx8900_regs.h | 125 ++++++ > > tests/Makefile.include | 2 + > > tests/rx8900-test.c | 800 > > ++++++++++++++++++++++++++++++++++++ > > Nice test ! But Why aren't you using the aspeed machine in > qtest ? > > The reason I am asking is because the I2C controller model > is a little too simplistic in the way it handles the irq > status and we would need a test for it. > The aspeed machine is missing a bunch of I2C infrastructure (imx_i2c_create & friends) required to access it from the test harness, and I don't have the knowledge required to implement it. I am working on the premise that the RX8900 is an independent device, and so can be tested independently of the aspeed model. > > Also I would put the test case in another patch, after the > model and after patch 2 also which introduces named > interrupts for qtest. > Ok > > > > > 6 files changed, 1821 insertions(+) > > create mode 100644 hw/timer/rx8900.c > > create mode 100644 hw/timer/rx8900_regs.h > > create mode 100644 tests/rx8900-test.c > > > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm- > > softmmu.mak > > index 6de3e16..adb600e 100644 > > --- a/default-configs/arm-softmmu.mak > > +++ b/default-configs/arm-softmmu.mak > > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y > > CONFIG_ALLWINNER_EMAC=y > > CONFIG_IMX_FEC=y > > CONFIG_DS1338=y > > +CONFIG_RX8900=y > > CONFIG_PFLASH_CFI01=y > > CONFIG_PFLASH_CFI02=y > > CONFIG_MICRODRIVE=y > > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs > > index 7ba8c23..fa028ac 100644 > > --- a/hw/timer/Makefile.objs > > +++ b/hw/timer/Makefile.objs > > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o > > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o > > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o > > common-obj-$(CONFIG_DS1338) += ds1338.o > > +common-obj-$(CONFIG_RX8900) += rx8900.o > > common-obj-$(CONFIG_HPET) += hpet.o > > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o > > common-obj-$(CONFIG_M48T59) += m48t59.o > > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o > > common-obj-$(CONFIG_IMX) += imx_gpt.o > > common-obj-$(CONFIG_LM32) += lm32_timer.o > > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o > > +common-obj-$(CONFIG_RX8900) += rx8900.o > > > > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o > > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o > > diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c > > new file mode 100644 > > index 0000000..208a31b > > --- /dev/null > > +++ b/hw/timer/rx8900.c > > @@ -0,0 +1,891 @@ > > +/* > > + * Epson RX8900SA/CE Realtime Clock Module > > + * > > + * Copyright (c) 2016 IBM Corporation > > + * Authors: > > + * Alastair D'Silva <alastair@d-silva.org> > > + * > > + * This code is licensed under the GPL version 2 or later. See > > + * the COPYING file in the top-level directory. > > + * > > + * Datasheet available at: > > + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE > > &lang=en > > + * > > + * Not implemented: > > + * Implement Timer Counters > > + * Implement i2c timeout > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu-common.h" > > +#include "hw/i2c/i2c.h" > > +#include "hw/timer/rx8900_regs.h" > > +#include "hw/ptimer.h" > > +#include "qemu/main-loop.h" > > +#include "qemu/bcd.h" > > +#include "qemu/error-report.h" > > +#include "qemu/log.h" > > +#include "qapi/error.h" > > +#include "qapi/visitor.h" > > + > > + #include <sys/time.h> > > + > > + #include <execinfo.h> > > + > > +#define TYPE_RX8900 "rx8900" > > +#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900) > > + > > +static bool log; > > + > > +typedef struct RX8900State { > > + I2CSlave parent_obj; > > + > > + ptimer_state *sec_timer; /* triggered once per second */ > > + ptimer_state *fout_timer; > > + ptimer_state *countdown_timer; > > + bool fout; > > + int64_t offset; > > + uint8_t weekday; /* Saved for deferred offset calculation, 0-6 > > */ > > + uint8_t wday_offset; > > + uint8_t nvram[RX8900_NVRAM_SIZE]; > > + int32_t ptr; /* Wrapped to stay within RX8900_NVRAM_SIZE */ > > + bool addr_byte; > > + uint8_t last_interrupt_seconds; > > + uint8_t last_update_interrupt_minutes; > > + qemu_irq interrupt_pin; > > + qemu_irq fout_pin; > > +} RX8900State; > > + > > +static const VMStateDescription vmstate_rx8900 = { > > + .name = "rx8900", > > + .version_id = 2, > > + .minimum_version_id = 1, > > + .fields = (VMStateField[]) { > > + VMSTATE_I2C_SLAVE(parent_obj, RX8900State), > > + VMSTATE_PTIMER(sec_timer, RX8900State), > > + VMSTATE_PTIMER(fout_timer, RX8900State), > > + VMSTATE_PTIMER(countdown_timer, RX8900State), > > + VMSTATE_BOOL(fout, RX8900State), > > + VMSTATE_INT64(offset, RX8900State), > > + VMSTATE_UINT8_V(weekday, RX8900State, 2), > > + VMSTATE_UINT8_V(wday_offset, RX8900State, 2), > > + VMSTATE_UINT8_ARRAY(nvram, RX8900State, > > RX8900_NVRAM_SIZE), > > + VMSTATE_INT32(ptr, RX8900State), > > + VMSTATE_BOOL(addr_byte, RX8900State), > > + VMSTATE_UINT8_V(last_interrupt_seconds, RX8900State, 2), > > + VMSTATE_UINT8_V(last_update_interrupt_minutes, > > RX8900State, 2), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void rx8900_reset(DeviceState *dev); > > +static void disable_countdown_timer(RX8900State *s); > > +static void enable_countdown_timer(RX8900State *s); > > +static void disable_timer(RX8900State *s); > > +static void enable_timer(RX8900State *s); > > + > > +#ifdef RX8900_TRACE > > +#define RX8900_TRACE_BUF_SIZE 256 > > +/** > > + * Emit a trace message > > + * @param file the source filename > > + * @param line the line number the message was emitted from > > + * @param dev the RX8900 device > > + * @param fmt a printf style format > > + */ > > +static void trace(const char *file, int line, const char *func, > > + I2CSlave *dev, const char *fmt, ...) > > +{ > > + va_list ap; > > + char buf[RX8900_TRACE_BUF_SIZE]; > > + char timestamp[32]; > > + int len; > > + struct timeval now; > > + struct tm *now2; > > + > > + gettimeofday(&now, NULL); > > + now2 = localtime(&now.tv_sec); > > + > > + strftime(timestamp, sizeof(timestamp), "%F %T", now2); > > + > > + len = snprintf(buf, sizeof(buf), "\n\t%s.%03ld %s:%s:%d: > > RX8900 %s %s@0x%x: %s", > > + timestamp, now.tv_usec / 1000, > > + file, func, line, dev->qdev.id, dev->qdev.parent_bus- > > >name, > > + dev->address, fmt); > > + if (len >= RX8900_TRACE_BUF_SIZE) { > > + error_report("%s:%d: Trace buffer overflow", file, line); > > + } > > + > > + va_start(ap, fmt); > > + error_vreport(buf, ap); > > + va_end(ap); > > +} > > + > > +/** > > + * Emit a trace message > > + * @param dev the RX8900 device > > + * @param fmt a printf format > > + */ > > +#define TRACE(dev, fmt, ...) \ > > + do { \ > > + if (log) { \ > > + trace(__FILE__, __LINE__, __func__, &dev, fmt, ## > > __VA_ARGS__); \ > > + } \ > > + } while (0) > > +#else > > +#define TRACE(dev, fmt, ...) > > +#endif > > > Although this is very pratical and nicely written, I don't > think you can keep these TRACE calls in the code. You should > use the qemu trace subsystem for it. > Ok. Would it be worth expanding this to include the file & line, or do you expect resistance? > > > > > +static void capture_current_time(RX8900State *s) > > +{ > > + /* Capture the current time into the secondary registers > > + * which will be actually read by the data transfer operation. > > + */ > > + struct tm now; > > + qemu_get_timedate(&now, s->offset); > > + s->nvram[SECONDS] = to_bcd(now.tm_sec); > > + s->nvram[MINUTES] = to_bcd(now.tm_min); > > + s->nvram[HOURS] = to_bcd(now.tm_hour); > > + > > + s->nvram[WEEKDAY] = 0x01 << ((now.tm_wday + s->wday_offset) % > > 7); > > + s->nvram[DAY] = to_bcd(now.tm_mday); > > + s->nvram[MONTH] = to_bcd(now.tm_mon + 1); > > + s->nvram[YEAR] = to_bcd(now.tm_year % 100); > > + > > + s->nvram[EXT_SECONDS] = s->nvram[SECONDS]; > > + s->nvram[EXT_MINUTES] = s->nvram[MINUTES]; > > + s->nvram[EXT_HOURS] = s->nvram[HOURS]; > > + s->nvram[EXT_WEEKDAY] = s->nvram[WEEKDAY]; > > + s->nvram[EXT_DAY] = s->nvram[DAY]; > > + s->nvram[EXT_MONTH] = s->nvram[MONTH]; > > + s->nvram[EXT_YEAR] = s->nvram[YEAR]; > > + > > + TRACE(s->parent_obj, "Update current time to %02d:%02d:%02d %d > > %d/%d/%d " > > + "(0x%02x%02x%02x%02x%02x%02x%02x)", > > + now.tm_hour, now.tm_min, now.tm_sec, > > + (now.tm_wday + s->wday_offset) % 7, > > + now.tm_mday, now.tm_mon, now.tm_year + 1900, > > + s->nvram[HOURS], s->nvram[MINUTES], s->nvram[SECONDS], > > + s->nvram[WEEKDAY], > > + s->nvram[DAY], s->nvram[MONTH], s->nvram[YEAR]); > > +} > > + > > +/** > > + * Increment the internal register pointer, dealing with wrapping > > + * @param s the RTC to operate on > > + */ > > +static void inc_regptr(RX8900State *s) > > +{ > > + /* The register pointer wraps around after 0x1F > > + */ > > + s->ptr = (s->ptr + 1) & (RX8900_NVRAM_SIZE - 1); > > + TRACE(s->parent_obj, "Operating on register 0x%02x", s->ptr); > > + > > + if (s->ptr == 0x00) { > > + TRACE(s->parent_obj, "Register pointer has overflowed, > > wrapping to 0"); > > + capture_current_time(s); > > + } > > +} > > + > > +/** > > + * Receive an I2C Event > > + * @param i2c the i2c device instance > > + * @param event the event to handle > > + */ > > +static void rx8900_event(I2CSlave *i2c, enum i2c_event event) > > +{ > > + RX8900State *s = RX8900(i2c); > > + > > + switch (event) { > > + case I2C_START_RECV: > > + /* In h/w, time capture happens on any START condition, > > not just a > > + * START_RECV. For the emulation, it doesn't actually > > matter, > > + * since a START_RECV has to occur before the data can be > > read. > > + */ > > + capture_current_time(s); > > + break; > > + case I2C_START_SEND: > > + s->addr_byte = true; > > + break; > > + case I2C_FINISH: > > + if (s->weekday < 7) { > > + /* We defer the weekday calculation as it is handed to > > us before > > + * the date has been updated. If we calculate the > > weekday offset > > + * when it is passed to us, we will incorrectly > > determine it > > + * based on the current emulated date, rather than the > > date that > > + * has been written. > > + */ > > + struct tm now; > > + qemu_get_timedate(&now, s->offset); > > + > > + s->wday_offset = (s->weekday - now.tm_wday + 7) % 7; > > + > > + TRACE(s->parent_obj, "Set weekday to %d (0x%02x), > > wday_offset=%d", > > + s->weekday, BIT(s->weekday), s->wday_offset); > > + > > + s->weekday = 7; > > + } > > + break; > > + > > + default: > > + break; > > + } > > +} > > + > > +/** > > + * Perform an i2c receive action > > + * @param i2c the i2c device instance > > + * @return the value of the current register > > + * @post the internal register pointer is incremented > > + */ > > +static int rx8900_recv(I2CSlave *i2c) > > +{ > > + RX8900State *s = RX8900(i2c); > > + uint8_t res = s->nvram[s->ptr]; > > + TRACE(s->parent_obj, "Read register 0x%x = 0x%x", s->ptr, > > res); > > + inc_regptr(s); > > + return res; > > +} > > + > > +/** > > + * Validate the extension register and perform actions based on > > the bits > > + * @param s the RTC to operate on > > + * @param data the new data for the extension register > > + */ > > +static void update_extension_register(RX8900State *s, uint8_t > > data) > > +{ > > + if (data & EXT_MASK_TEST) { > > + error_report("WARNING: RX8900 - " > > + "Test bit is enabled but is forbidden by the > > manufacturer"); > > may be use instead : > > qemu_log_mask(LOG_GUEST_ERROR, > OK > > > > + } > > + > > + if ((data ^ s->nvram[EXTENSION_REGISTER]) & > > + (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) { > > + uint8_t fsel = (data & (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) > > + >> EXT_REG_FSEL0; > > + /* FSELx has changed */ > > + switch (fsel) { > > + case 0x01: > > + TRACE(s->parent_obj, "Setting fout to 1024Hz"); > > + ptimer_set_limit(s->fout_timer, 32, 1); > > + break; > > + case 0x02: > > + TRACE(s->parent_obj, "Setting fout to 1Hz"); > > + ptimer_set_limit(s->fout_timer, 32768, 1); > > + break; > > + default: > > + TRACE(s->parent_obj, "Setting fout to 32768Hz"); > > + ptimer_set_limit(s->fout_timer, 1, 1); > > + break; > > + } > > + } > > + > > + if ((data ^ s->nvram[EXTENSION_REGISTER]) & > > + (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) { > > + uint8_t tsel = (data & (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) > > + >> EXT_REG_TSEL0; > > + /* TSELx has changed */ > > + switch (tsel) { > > + case 0x00: > > + TRACE(s->parent_obj, "Setting countdown timer to 64 > > Hz"); > > + ptimer_set_limit(s->countdown_timer, 4096 / 64, 1); > > + break; > > + case 0x01: > > + TRACE(s->parent_obj, "Setting countdown timer to 1 > > Hz"); > > + ptimer_set_limit(s->countdown_timer, 4096, 1); > > + break; > > + case 0x02: > > + TRACE(s->parent_obj, > > + "Setting countdown timer to per minute > > updates"); > > + ptimer_set_limit(s->countdown_timer, 4069 * 60, 1); > > + break; > > + case 0x03: > > + TRACE(s->parent_obj, "Setting countdown timer to > > 4096Hz"); > > + ptimer_set_limit(s->countdown_timer, 1, 1); > > + break; > > + } > > + } > > + > > + if (data & EXT_MASK_TE) { > > + enable_countdown_timer(s); > > + } > > + > > + s->nvram[EXTENSION_REGISTER] = data; > > + s->nvram[EXT_EXTENSION_REGISTER] = data; > > + > > +} > > +/** > > + * Validate the control register and perform actions based on the > > bits > > + * @param s the RTC to operate on > > + * @param data the new value for the control register > > + */ > > + > > +static void update_control_register(RX8900State *s, uint8_t data) > > +{ > > + uint8_t diffmask = ~s->nvram[CONTROL_REGISTER] & data; > > + > > + if (diffmask & CTRL_MASK_WP0) { > > + data &= ~CTRL_MASK_WP0; > > + error_report("WARNING: RX8900 - " > > + "Attempt to write to write protected bit %d in control > > register", > > + CTRL_REG_WP0); > > > may be use instead : > > qemu_log_mask(LOG_GUEST_ERROR, > > > > > + } > > + > > + if (diffmask & CTRL_MASK_WP1) { > > + data &= ~CTRL_MASK_WP1; > > + error_report("WARNING: RX8900 - " > > + "Attempt to write to write protected bit %d in control > > register", > > + CTRL_REG_WP1); > > ditto for all in fact. > > > > > + } > > + > > + if (data & CTRL_MASK_RESET) { > > + data &= ~CTRL_MASK_RESET; > > + rx8900_reset(DEVICE(s)); > > + } > > + > > + if (diffmask & CTRL_MASK_UIE) { > > + /* Update interrupts were off and are now on */ > > + struct tm now; > > + > > + TRACE(s->parent_obj, "Enabling update timer"); > > + > > + qemu_get_timedate(&now, s->offset); > > + > > + s->last_update_interrupt_minutes = now.tm_min; > > + s->last_interrupt_seconds = now.tm_sec; > > + enable_timer(s); > > + } > > + > > + if (diffmask & CTRL_MASK_AIE) { > > + /* Alarm interrupts were off and are now on */ > > + struct tm now; > > + > > + TRACE(s->parent_obj, "Enabling alarm"); > > + > > + qemu_get_timedate(&now, s->offset); > > + > > + s->last_interrupt_seconds = now.tm_sec; > > + enable_timer(s); > > + } > > + > > + if (!(data & (CTRL_MASK_UIE | CTRL_MASK_AIE))) { > > + disable_timer(s); > > + } > > + > > + if (data & CTRL_MASK_TIE) { > > + enable_countdown_timer(s); > > + } > > + > > + s->nvram[CONTROL_REGISTER] = data; > > + s->nvram[EXT_CONTROL_REGISTER] = data; > > +} > > + > > +/** > > + * Validate the flag register > > + * @param s the RTC to operate on > > + * @param data the new value for the flag register > > + */ > > +static void validate_flag_register(RX8900State *s, uint8_t *data) > > +{ > > + uint8_t diffmask = ~s->nvram[FLAG_REGISTER] & *data; > > + > > + if (diffmask & FLAG_MASK_VDET) { > > + *data &= ~FLAG_MASK_VDET; > > + error_report("WARNING: RX8900 - " > > + "Only 0 can be written to VDET bit %d in the flag > > register", > > + FLAG_REG_VDET); > > + } > > + > > + if (diffmask & FLAG_MASK_VLF) { > > + *data &= ~FLAG_MASK_VLF; > > + error_report("WARNING: RX8900 - " > > + "Only 0 can be written to VLF bit %d in the flag > > register", > > + FLAG_REG_VLF); > > + } > > + > > + if (diffmask & FLAG_MASK_UNUSED_2) { > > + *data &= ~FLAG_MASK_UNUSED_2; > > + error_report("WARNING: RX8900 - " > > + "Only 0 can be written to unused bit %d in the flag > > register", > > + FLAG_REG_UNUSED_2); > > + } > > + > > + if (diffmask & FLAG_MASK_UNUSED_6) { > > + *data &= ~FLAG_MASK_UNUSED_6; > > + error_report("WARNING: RX8900 - " > > + "Only 0 can be written to unused bit %d in the flag > > register", > > + FLAG_REG_UNUSED_6); > > + } > > + > > + if (diffmask & FLAG_MASK_UNUSED_7) { > > + *data &= ~FLAG_MASK_UNUSED_7; > > + error_report("WARNING: RX8900 - " > > + "Only 0 can be written to unused bit %d in the flag > > register", > > + FLAG_REG_UNUSED_7); > > + } > > +} > > + > > +/** > > + * Tick the per second timer (can be called more frequently as it > > early exits > > + * if the wall clock has not progressed) > > + * @param opaque the RTC to tick > > + */ > > +static void rx8900_timer_tick(void *opaque) > > +{ > > + RX8900State *s = (RX8900State *)opaque; > > + struct tm now; > > + bool fire_interrupt = false; > > + > > + qemu_get_timedate(&now, s->offset); > > + > > + if (now.tm_sec == s->last_interrupt_seconds) { > > + return; > > + } > > + > > + s->last_interrupt_seconds = now.tm_sec; > > + > > + TRACE(s->parent_obj, "Tick"); > > + > > + /* Update timer interrupt */ > > + if (s->nvram[CONTROL_REGISTER] & CTRL_MASK_UIE) { > > + if ((s->nvram[EXTENSION_REGISTER] & EXT_MASK_USEL) && > > + now.tm_min != s->last_update_interrupt_minutes) { > > + s->last_update_interrupt_minutes = now.tm_min; > > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF; > > + fire_interrupt = true; > > + } else if (!(s->nvram[EXTENSION_REGISTER] & > > EXT_MASK_USEL)) { > > + /* per second update interrupt */ > > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF; > > + fire_interrupt = true; > > + } > > + } > > + > > + /* Alarm interrupt */ > > + if ((s->nvram[CONTROL_REGISTER] & CTRL_MASK_AIE) && now.tm_sec > > == 0) { > > + if (s->nvram[ALARM_MINUTE] == to_bcd(now.tm_min) && > > + s->nvram[ALARM_HOUR] == to_bcd(now.tm_hour) && > > + s->nvram[ALARM_WEEK_DAY] == > > + ((s->nvram[EXTENSION_REGISTER] & > > EXT_MASK_WADA) ? > > + to_bcd(now.tm_mday) : > > + 0x01 << ((now.tm_wday + s- > > >wday_offset) % 7))) { > > > that's a nice if condition :) May be we could use a temp variable for > the last one. Ok, it was more readable with longer lines :) > > > > > + TRACE(s->parent_obj, "Triggering alarm"); > > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_AF; > > + fire_interrupt = true; > > + } > > + } > > + > > + if (fire_interrupt) { > > + TRACE(s->parent_obj, "Pulsing interrupt"); > > + qemu_irq_pulse(s->interrupt_pin); > > + } > > +} > > + > > +/** > > + * Disable the per second timer > > + * @param s the RTC to operate on > > + */ > > +static void disable_timer(RX8900State *s) > > +{ > > + TRACE(s->parent_obj, "Disabling timer"); > > + ptimer_stop(s->sec_timer); > > +} > > + > > +/** > > + * Enable the per second timer > > + * @param s the RTC to operate on > > + */ > > +static void enable_timer(RX8900State *s) > > +{ > > + TRACE(s->parent_obj, "Enabling timer"); > > + ptimer_run(s->sec_timer, 0); > > +} > > + > > +/** > > + * Handle FOUT_ENABLE (FOE) line > > + * Enables/disables the FOUT line > > + * @param opaque the device instance > > + * @param n the IRQ number > > + * @param level true if the line has been raised > > + */ > > +static void rx8900_fout_enable_handler(void *opaque, int n, int > > level) > > +{ > > + RX8900State *s = RX8900(opaque); > > + > > + if (level) { > > + TRACE(s->parent_obj, "Enabling fout"); > > + ptimer_run(s->fout_timer, 0); > > + } else { > > + /* disable fout */ > > + TRACE(s->parent_obj, "Disabling fout"); > > + ptimer_stop(s->fout_timer); > > + } > > +} > > + > > +/** > > + * Tick the FOUT timer > > + * @param opaque the device instance > > + */ > > +static void rx8900_fout_tick(void *opaque) > > +{ > > + RX8900State *s = (RX8900State *)opaque; > > + > > + TRACE(s->parent_obj, "fout toggle"); > > + s->fout = !s->fout; > > + > > + if (s->fout) { > > + qemu_irq_raise(s->fout_pin); > > + } else { > > + qemu_irq_lower(s->fout_pin); > > + } > > +} > > + > > + > > +/** > > + * Disable the countdown timer > > + * @param s the RTC to operate on > > + */ > > +static void disable_countdown_timer(RX8900State *s) > > +{ > > + TRACE(s->parent_obj, "Disabling countdown timer"); > > + ptimer_stop(s->countdown_timer); > > +} > > + > > +/** > > + * Enable the per second timer > > + * @param s the RTC to operate on > > + */ > > +static void enable_countdown_timer(RX8900State *s) > > +{ > > + TRACE(s->parent_obj, "Enabling countdown timer"); > > + ptimer_run(s->countdown_timer, 0); > > +} > > These helpers don't add much I think. They are called in multiple places and add tracing. > > > > +/** > > + * Tick the countdown timer > > + * @param opaque the device instance > > + */ > > +static void rx8900_countdown_tick(void *opaque) > > +{ > > + RX8900State *s = (RX8900State *)opaque; > > + > > + uint16_t count = s->nvram[TIMER_COUNTER_0] + > > + ((s->nvram[TIMER_COUNTER_1] & 0x0F) << 8); > > + TRACE(s->parent_obj, "countdown tick, count=%d", count); > > + count--; > > + > > + s->nvram[TIMER_COUNTER_0] = (uint8_t)(count & 0x00ff); > > + s->nvram[TIMER_COUNTER_1] = (uint8_t)((count & 0x0f00) >> 8); > > + > > + if (count == 0) { > > + TRACE(s->parent_obj, "Countdown has elapsed, pulsing > > interrupt"); > > + > > + disable_countdown_timer(s); > > + > > + s->nvram[FLAG_REGISTER] |= FLAG_MASK_TF; > > + qemu_irq_pulse(s->interrupt_pin); > > + } > > +} > > + > > + > > +/** > > + * Receive a byte of data from i2c > > + * @param i2c the i2c device that is receiving data > > + * @param data the data that was received > > + */ > > +static int rx8900_send(I2CSlave *i2c, uint8_t data) > > +{ > > + RX8900State *s = RX8900(i2c); > > + struct tm now; > > + > > + TRACE(s->parent_obj, "Received I2C data 0x%02x", data); > > + > > + if (s->addr_byte) { > > + s->ptr = data & (RX8900_NVRAM_SIZE - 1); > > + TRACE(s->parent_obj, "Operating on register 0x%02x", s- > > >ptr); > > + s->addr_byte = false; > > + return 0; > > + } > > + > > + TRACE(s->parent_obj, "Set data 0x%02x=0x%02x", s->ptr, data); > > + > > + qemu_get_timedate(&now, s->offset); > > + switch (s->ptr) { > > + case SECONDS: > > + case EXT_SECONDS: > > + now.tm_sec = from_bcd(data & 0x7f); > > + s->offset = qemu_timedate_diff(&now); > > + break; > > + > > + case MINUTES: > > + case EXT_MINUTES: > > + now.tm_min = from_bcd(data & 0x7f); > > + s->offset = qemu_timedate_diff(&now); > > + break; > > + > > + case HOURS: > > + case EXT_HOURS: > > + now.tm_hour = from_bcd(data & 0x3f); > > + s->offset = qemu_timedate_diff(&now); > > + break; > > + > > + case WEEKDAY: > > + case EXT_WEEKDAY: { > > + int user_wday = ctz32(data); > > + /* The day field is supposed to contain a value in > > + * the range 0-6. Otherwise behavior is undefined. > > + */ > > + switch (data) { > > + case 0x01: > > + case 0x02: > > + case 0x04: > > + case 0x08: > > + case 0x10: > > + case 0x20: > > + case 0x40: > > + break; > > + default: > > + error_report("WARNING: RX8900 - weekday data '%x' is > > out of range," > > + " undefined behavior will result", data); > > + break; > > + } > > + s->weekday = user_wday; > > + break; > > + } > > + > > + case DAY: > > + case EXT_DAY: > > + now.tm_mday = from_bcd(data & 0x3f); > > + s->offset = qemu_timedate_diff(&now); > > + break; > > + > > + case MONTH: > > + case EXT_MONTH: > > + now.tm_mon = from_bcd(data & 0x1f) - 1; > > + s->offset = qemu_timedate_diff(&now); > > + break; > > + > > + case YEAR: > > + case EXT_YEAR: > > + now.tm_year = from_bcd(data) + 100; > > + s->offset = qemu_timedate_diff(&now); > > + break; > > + > > + case EXTENSION_REGISTER: > > + case EXT_EXTENSION_REGISTER: > > + update_extension_register(s, data); > > + break; > > + > > + case FLAG_REGISTER: > > + case EXT_FLAG_REGISTER: > > + validate_flag_register(s, &data); > > + > > + s->nvram[FLAG_REGISTER] = data; > > + s->nvram[EXT_FLAG_REGISTER] = data; > > + break; > > + > > + case CONTROL_REGISTER: > > + case EXT_CONTROL_REGISTER: > > + update_control_register(s, data); > > + break; > > + > > + default: > > + s->nvram[s->ptr] = data; > > + } > > + > > + inc_regptr(s); > > + return 0; > > +} > > + > > +/** > > + * Get the device temperature in Celcius as a property > > + * @param obj the device > > + * @param v > > + * @param name the property name > > + * @param opaque > > + * @param errp an error object to populate on failure > > + */ > > +static void rx8900_get_temperature(Object *obj, Visitor *v, const > > char *name, > > + void *opaque, Error **errp) > > +{ > > + RX8900State *s = RX8900(obj); > > + double value = (s->nvram[TEMPERATURE] * 2.0f - 187.1f) / > > 3.218f; > > + > > + TRACE(s->parent_obj, "Read temperature property, 0x%x = %f°C", > > + s->nvram[TEMPERATURE], value); > > + > > + visit_type_number(v, name, &value, errp); > > +} > > + > > +/** > > + * Set the device temperature in Celcius as a property > > + * @param obj the device > > + * @param v > > + * @param name the property name > > + * @param opaque > > + * @param errp an error object to populate on failure > > + */ > > +static void rx8900_set_temperature(Object *obj, Visitor *v, const > > char *name, > > + void *opaque, Error **errp) > > +{ > > + RX8900State *s = RX8900(obj); > > + Error *local_err = NULL; > > + double temp; /* degrees Celcius */ > > + visit_type_number(v, name, &temp, &local_err); > > + if (local_err) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + if (temp >= 100 || temp < -58) { > > + error_setg(errp, "value %f°C is out of range", temp); > > + return; > > + } > > + > > + s->nvram[TEMPERATURE] = (uint8_t) ((temp * 3.218f + 187.19f) / > > 2); > > + > > + TRACE(s->parent_obj, "Set temperature property, 0x%x = %f°C", > > + s->nvram[TEMPERATURE], temp); > > +} > > + > > + > > +/** > > + * Initialize the device > > + * @param i2c the i2c device instance > > + */ > > +static int rx8900_init(I2CSlave *i2c) > > +{ > > + TRACE(*i2c, "Initialized"); > > + > > + return 0; > > +} > > you can remove this routine. > I don't think I can, core.c:i2c_slave_qdev_init() calls it without a guard. > > > > +/** > > + * Configure device properties > > + * @param obj the device > > + */ > > +static void rx8900_initfn(Object *obj) > > +{ > > + object_property_add(obj, "temperature", "number", > > + rx8900_get_temperature, > > + rx8900_set_temperature, NULL, NULL, NULL); > > +} > > + > > +/** > > + * Reset the device > > + * @param dev the RX8900 device to reset > > + */ > > +static void rx8900_reset(DeviceState *dev) > > +{ > > + RX8900State *s = RX8900(dev); > > + > > + TRACE(s->parent_obj, "Reset"); > > + > > + /* The clock is running and synchronized with the host */ > > + s->offset = 0; > > + s->weekday = 7; /* Set to an invalid value */ > > + > > + /* Temperature formulation from the datasheet > > + * ( TEMP[ 7:0 ] * 2 - 187.19) / 3.218 > > + * > > + * Set the initial state to 25 degrees Celcius > > + */ > > + s->nvram[TEMPERATURE] = 135; /* (25 * 3.218 + 187.19) / 2 */ > > + > > + s->nvram[EXTENSION_REGISTER] = EXT_MASK_TSEL1; > > + s->nvram[CONTROL_REGISTER] = CTRL_MASK_CSEL0; > > + s->nvram[FLAG_REGISTER] = FLAG_MASK_VLF | FLAG_MASK_VDET; > > Just asking : why not fully memset(0) the nvram and then set > the values ? I also use this function for a soft-reset, which does not clear the nvram. Actually, I should move the temperature out of there... Cheers, -- Alastair D'Silva Open Source Developer Linux Technology Centre, IBM Australia mob: 0423 762 819 ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support 2016-11-18 0:19 ` Alastair D'Silva @ 2016-11-18 8:52 ` Cédric Le Goater 0 siblings, 0 replies; 22+ messages in thread From: Cédric Le Goater @ 2016-11-18 8:52 UTC (permalink / raw) To: Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley >>> +/** >>> + * Initialize the device >>> + * @param i2c the i2c device instance >>> + */ >>> +static int rx8900_init(I2CSlave *i2c) >>> +{ >>> + TRACE(*i2c, "Initialized"); >>> + >>> + return 0; >>> +} >> >> you can remove this routine. >> > > I don't think I can, core.c:i2c_slave_qdev_init() calls it without a > guard. ah yes. So may be, we should add a test in i2c_slave_qdev_init() and kill these : ds1338_init pxa2xx_i2c_slave_init aer915_init tosa_dac_init it looks like a good cleanup. Thanks, C. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board 2016-11-17 4:36 [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva ` (2 preceding siblings ...) 2016-11-17 4:36 ` [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva @ 2016-11-17 4:36 ` Alastair D'Silva 2016-11-22 16:56 ` Cédric Le Goater 2016-11-17 15:33 ` [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board no-reply 4 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-17 4:36 UTC (permalink / raw) To: qemu-arm Cc: qemu-devel, Peter Maydell, Cédric Le Goater, Andrew Jeffery, Joel Stanley, Alastair D'Silva From: Alastair D'Silva <alastair@d-silva.org> Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32 Signed-off-by: Alastair D'Silva <alastair@d-silva.org> --- hw/arm/aspeed.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c7206fd..554ae20 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -100,6 +100,8 @@ static void aspeed_board_init(MachineState *machine, { AspeedBoardState *bmc; AspeedSoCClass *sc; + I2CBus *i2c12; + DeviceState *rx8900; bmc = g_new0(AspeedBoardState, 1); object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name); @@ -137,6 +139,12 @@ static void aspeed_board_init(MachineState *machine, aspeed_board_binfo.ram_size = ram_size; aspeed_board_binfo.loader_start = sc->info->sdram_base; + i2c12 = aspeed_i2c_get_bus((DeviceState *)&bmc->soc.i2c, 11); + rx8900 = i2c_create_slave(i2c12, "rx8900", 0x32); + + qdev_connect_gpio_out_named(rx8900, "rx8900-interrupt-out", 0, + qdev_get_gpio_in(DEVICE(&bmc->soc.vic), 22)); + arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo); } -- 2.7.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board 2016-11-17 4:36 ` [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board Alastair D'Silva @ 2016-11-22 16:56 ` Cédric Le Goater 2016-11-23 0:46 ` Alastair D'Silva 0 siblings, 1 reply; 22+ messages in thread From: Cédric Le Goater @ 2016-11-22 16:56 UTC (permalink / raw) To: Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley, Alastair D'Silva On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > From: Alastair D'Silva <alastair@d-silva.org> > > Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32 If this is a board device, we should include it under a machine routine. Is that for the palmetto ? The ast2500 does not have a RTC. Thanks, C. > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > --- > hw/arm/aspeed.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index c7206fd..554ae20 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -100,6 +100,8 @@ static void aspeed_board_init(MachineState *machine, > { > > AspeedBoardState *bmc; > AspeedSoCClass *sc; > + I2CBus *i2c12; > + DeviceState *rx8900; > > bmc = g_new0(AspeedBoardState, 1); > object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name); > @@ -137,6 +139,12 @@ static void aspeed_board_init(MachineState *machine, > aspeed_board_binfo.ram_size = ram_size; > aspeed_board_binfo.loader_start = sc->info->sdram_base; > > + i2c12 = aspeed_i2c_get_bus((DeviceState *)&bmc->soc.i2c, 11); > + rx8900 = i2c_create_slave(i2c12, "rx8900", 0x32); > + > + qdev_connect_gpio_out_named(rx8900, "rx8900-interrupt-out", 0, > + qdev_get_gpio_in(DEVICE(&bmc->soc.vic), 22)); > + > arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo); > } > > ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board 2016-11-22 16:56 ` Cédric Le Goater @ 2016-11-23 0:46 ` Alastair D'Silva 2016-11-23 8:48 ` Cédric Le Goater 0 siblings, 1 reply; 22+ messages in thread From: Alastair D'Silva @ 2016-11-23 0:46 UTC (permalink / raw) To: Cédric Le Goater, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley On Tue, 2016-11-22 at 17:56 +0100, Cédric Le Goater wrote: > On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > > > > From: Alastair D'Silva <alastair@d-silva.org> > > > > Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32 > > If this is a board device, we should include it under a machine > routine. > > Is that for the palmetto ? The ast2500 does not have a RTC. > > Thanks, > > C. Ok -- Alastair D'Silva Open Source Developer Linux Technology Centre, IBM Australia mob: 0423 762 819 ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board 2016-11-23 0:46 ` Alastair D'Silva @ 2016-11-23 8:48 ` Cédric Le Goater 2016-11-24 0:15 ` Andrew Jeffery 0 siblings, 1 reply; 22+ messages in thread From: Cédric Le Goater @ 2016-11-23 8:48 UTC (permalink / raw) To: Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Andrew Jeffery, Joel Stanley On 11/23/2016 01:46 AM, Alastair D'Silva wrote: > On Tue, 2016-11-22 at 17:56 +0100, Cédric Le Goater wrote: >> On 11/17/2016 05:36 AM, Alastair D'Silva wrote: >>> >>> From: Alastair D'Silva <alastair@d-silva.org> >>> >>> Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32 >> >> If this is a board device, we should include it under a machine >> routine. >> >> Is that for the palmetto ? The ast2500 does not have a RTC. >> >> Thanks, >> >> C. > > Ok I suppose we could change aspeed_board_init() to return a AspeedSoCState* and use the soc object in the specific <machine>_init routines to add devices. Andrew, what is your opinion on that ? Thanks, C. ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board 2016-11-23 8:48 ` Cédric Le Goater @ 2016-11-24 0:15 ` Andrew Jeffery 0 siblings, 0 replies; 22+ messages in thread From: Andrew Jeffery @ 2016-11-24 0:15 UTC (permalink / raw) To: Cédric Le Goater, Alastair D'Silva, qemu-arm Cc: qemu-devel, Peter Maydell, Joel Stanley [-- Attachment #1: Type: text/plain, Size: 1366 bytes --] On Wed, 2016-11-23 at 09:48 +0100, Cédric Le Goater wrote: > On 11/23/2016 01:46 AM, Alastair D'Silva wrote: > > On Tue, 2016-11-22 at 17:56 +0100, Cédric Le Goater wrote: > > > On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > > > > > > > > > > > > From: Alastair D'Silva <alastair@d-silva.org> > > > > > > > > Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32 > > > > > > If this is a board device, we should include it under a machine > > > routine. > > > > > > Is that for the palmetto ? The ast2500 does not have a RTC. > > > > > > Thanks, > > > > > > C. > > > > Ok > > > I suppose we could change aspeed_board_init() to return > a AspeedSoCState* and use the soc object in the specific > <machine>_init routines to add devices. > > Andrew, what is your opinion on that ? I see the I2C bus configuration as a declarative problem. In a similar vein we already have AspeedBoardConfig, so I think we should try to describe the buses and attached devices there. That way we can have a generic aspeed_i2c_bus_init() routine that we call inside aspeed_board_init(). This would avoid encoding the buses and their slaves in the board- specific init code. Is that a reasonable alternative? I agree that we need to use a different approach to that which the current patch is using. Andrew [-- Attachment #2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board 2016-11-17 4:36 [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva ` (3 preceding siblings ...) 2016-11-17 4:36 ` [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board Alastair D'Silva @ 2016-11-17 15:33 ` no-reply 4 siblings, 0 replies; 22+ messages in thread From: no-reply @ 2016-11-17 15:33 UTC (permalink / raw) To: alastair Cc: famz, qemu-arm, peter.maydell, andrew, qemu-devel, joel, alastair, clg Hi, Your series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Subject: [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board Type: series Message-id: 1479357400-17441-1-git-send-email-alastair@au1.ibm.com === TEST SCRIPT BEGIN === #!/bin/bash set -e git submodule update --init dtc # Let docker tests dump environment info export SHOW_ENV=1 export J=16 make docker-test-quick@centos6 make docker-test-mingw@fedora === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 477fb82 arm: Add an RX8900 RTC to the ASpeed board 6e0c516 hw/timer: Add Epson RX8900 RTC support 320decf qtest: Support named interrupts cd85764 arm: Uniquely name imx25 I2C buses. === OUTPUT BEGIN === Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into 'dtc'... Submodule path 'dtc': checked out '65cc4d2748a2c2e6f27f1cf39e07a5dbabd80ebf' BUILD centos6 make[1]: Entering directory `/var/tmp/patchew-tester-tmp-ie51qv7a/src' ARCHIVE qemu.tgz ARCHIVE dtc.tgz COPY RUNNER RUN test-quick in qemu:centos6 Packages installed: SDL-devel-1.2.14-7.el6_7.1.x86_64 ccache-3.1.6-2.el6.x86_64 epel-release-6-8.noarch gcc-4.4.7-17.el6.x86_64 git-1.7.1-4.el6_7.1.x86_64 glib2-devel-2.28.8-5.el6.x86_64 libfdt-devel-1.4.0-1.el6.x86_64 make-3.81-23.el6.x86_64 package g++ is not installed pixman-devel-0.32.8-1.el6.x86_64 tar-1.23-15.el6_8.x86_64 zlib-devel-1.2.3-29.el6.x86_64 Environment variables: PACKAGES=libfdt-devel ccache tar git make gcc g++ zlib-devel glib2-devel SDL-devel pixman-devel epel-release HOSTNAME=1e95015cd9c9 TERM=xterm MAKEFLAGS= -j16 HISTSIZE=1000 J=16 USER=root CCACHE_DIR=/var/tmp/ccache EXTRA_CONFIGURE_OPTS= V= SHOW_ENV=1 MAIL=/var/spool/mail/root PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin PWD=/ LANG=en_US.UTF-8 TARGET_LIST= HISTCONTROL=ignoredups SHLVL=1 HOME=/root TEST_DIR=/tmp/qemu-test LOGNAME=root LESSOPEN=||/usr/bin/lesspipe.sh %s FEATURES= dtc DEBUG= G_BROKEN_FILENAMES=1 CCACHE_HASHDIR= _=/usr/bin/env Configure options: --enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install No C++ compiler available; disabling C++ specific optional code Install prefix /var/tmp/qemu-build/install BIOS directory /var/tmp/qemu-build/install/share/qemu binary directory /var/tmp/qemu-build/install/bin library directory /var/tmp/qemu-build/install/lib module directory /var/tmp/qemu-build/install/lib/qemu libexec directory /var/tmp/qemu-build/install/libexec include directory /var/tmp/qemu-build/install/include config directory /var/tmp/qemu-build/install/etc local state directory /var/tmp/qemu-build/install/var Manual directory /var/tmp/qemu-build/install/share/man ELF interp prefix /usr/gnemul/qemu-%M Source path /tmp/qemu-test/src C compiler cc Host C compiler cc C++ compiler Objective-C compiler cc ARFLAGS rv CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g QEMU_CFLAGS -I/usr/include/pixman-1 -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wmissing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g make make install install python python -B smbd /usr/sbin/smbd module support no host CPU x86_64 host big endian no target list x86_64-softmmu aarch64-softmmu tcg debug enabled no gprof enabled no sparse enabled no strip binaries yes profiler no static build no pixman system SDL support yes (1.2.14) GTK support no GTK GL support no VTE support no TLS priority NORMAL GNUTLS support no GNUTLS rnd no libgcrypt no libgcrypt kdf no nettle no nettle kdf no libtasn1 no curses support no virgl support no curl support no mingw32 support no Audio drivers oss Block whitelist (rw) Block whitelist (ro) VirtFS support no VNC support yes VNC SASL support no VNC JPEG support no VNC PNG support no xen support no brlapi support no bluez support no Documentation no PIE yes vde support no netmap support no Linux AIO support no ATTR/XATTR support yes Install blobs yes KVM support yes COLO support yes RDMA support no TCG interpreter no fdt support yes preadv support yes fdatasync yes madvise yes posix_madvise yes libcap-ng support no vhost-net support yes vhost-scsi support yes vhost-vsock support yes Trace backends log spice support no rbd support no xfsctl support no smartcard support no libusb no usb net redir no OpenGL support no OpenGL dmabufs no libiscsi support no libnfs support no build guest agent yes QGA VSS support no QGA w32 disk info no QGA MSI support no seccomp support no coroutine backend ucontext coroutine pool yes debug stack usage no GlusterFS support no Archipelago support no gcov gcov gcov enabled no TPM support yes libssh2 support no TPM passthrough yes QOM debugging yes lzo support no snappy support no bzip2 support no NUMA host support no tcmalloc support no jemalloc support no avx2 optimization no replication support yes GEN x86_64-softmmu/config-devices.mak.tmp GEN aarch64-softmmu/config-devices.mak.tmp GEN config-host.h GEN qemu-options.def GEN qapi-types.h GEN qmp-commands.h GEN qapi-event.h GEN qapi-visit.h GEN qmp-introspect.h GEN x86_64-softmmu/config-devices.mak GEN aarch64-softmmu/config-devices.mak GEN module_block.h GEN tests/test-qapi-types.h GEN tests/test-qapi-visit.h GEN tests/test-qmp-commands.h GEN tests/test-qapi-event.h GEN tests/test-qmp-introspect.h GEN config-all-devices.mak GEN trace/generated-tracers.h GEN trace/generated-tcg-tracers.h GEN trace/generated-helpers-wrappers.h GEN trace/generated-helpers.h CC tests/qemu-iotests/socket_scm_helper.o GEN qga/qapi-generated/qga-qapi-types.h GEN qga/qapi-generated/qga-qapi-visit.h GEN qga/qapi-generated/qga-qmp-commands.h GEN qga/qapi-generated/qga-qapi-types.c GEN qga/qapi-generated/qga-qapi-visit.c GEN qga/qapi-generated/qga-qmp-marshal.c GEN qmp-introspect.c GEN qapi-types.c GEN qapi-visit.c GEN qapi-event.c CC qapi/qapi-visit-core.o CC qapi/qapi-dealloc-visitor.o CC qapi/qobject-input-visitor.o CC qapi/qobject-output-visitor.o CC qapi/qmp-registry.o CC qapi/qmp-dispatch.o CC qapi/string-input-visitor.o CC qapi/string-output-visitor.o CC qapi/opts-visitor.o CC qapi/qapi-clone-visitor.o CC qapi/qmp-event.o CC qapi/qapi-util.o CC qobject/qnull.o CC qobject/qint.o CC qobject/qstring.o CC qobject/qdict.o CC qobject/qlist.o CC qobject/qfloat.o CC qobject/qbool.o CC qobject/qjson.o CC qobject/qobject.o CC qobject/json-lexer.o CC qobject/json-streamer.o CC qobject/json-parser.o GEN trace/generated-tracers.c CC trace/control.o CC trace/qmp.o CC util/osdep.o CC util/cutils.o CC util/unicode.o CC util/qemu-timer-common.o CC util/bufferiszero.o CC util/compatfd.o CC util/event_notifier-posix.o CC util/mmap-alloc.o CC util/oslib-posix.o CC util/qemu-openpty.o CC util/qemu-thread-posix.o CC util/memfd.o CC util/envlist.o CC util/path.o CC util/module.o CC util/bitmap.o CC util/bitops.o CC util/hbitmap.o CC util/fifo8.o CC util/acl.o CC util/error.o CC util/qemu-error.o CC util/id.o CC util/iov.o CC util/qemu-config.o CC util/qemu-sockets.o CC util/uri.o CC util/notify.o CC util/qemu-option.o CC util/qemu-progress.o CC util/hexdump.o CC util/crc32c.o CC util/uuid.o CC util/throttle.o CC util/getauxval.o CC util/readline.o CC util/rcu.o CC util/qemu-coroutine.o CC util/qemu-coroutine-lock.o CC util/qemu-coroutine-io.o CC util/qemu-coroutine-sleep.o CC util/coroutine-ucontext.o CC util/buffer.o CC util/timed-average.o CC util/base64.o CC util/log.o CC util/qdist.o CC util/qht.o CC util/range.o CC crypto/pbkdf-stub.o CC stubs/arch-query-cpu-def.o CC stubs/arch-query-cpu-model-expansion.o CC stubs/arch-query-cpu-model-comparison.o CC stubs/arch-query-cpu-model-baseline.o CC stubs/bdrv-next-monitor-owned.o CC stubs/blk-commit-all.o CC stubs/blockdev-close-all-bdrv-states.o CC stubs/cpu-get-clock.o CC stubs/clock-warp.o CC stubs/cpu-get-icount.o CC stubs/dump.o CC stubs/error-printf.o CC stubs/fdset-add-fd.o CC stubs/fdset-find-fd.o CC stubs/fdset-get-fd.o CC stubs/fdset-remove-fd.o CC stubs/gdbstub.o CC stubs/get-fd.o CC stubs/get-next-serial.o CC stubs/get-vm-name.o CC stubs/iothread.o CC stubs/iothread-lock.o CC stubs/is-daemonized.o CC stubs/machine-init-done.o CC stubs/migr-blocker.o CC stubs/mon-is-qmp.o CC stubs/monitor-init.o CC stubs/notify-event.o CC stubs/qtest.o CC stubs/replay.o CC stubs/replay-user.o CC stubs/reset.o CC stubs/runstate-check.o CC stubs/set-fd-handler.o CC stubs/slirp.o CC stubs/sysbus.o CC stubs/trace-control.o CC stubs/uuid.o CC stubs/vm-stop.o CC stubs/vmstate.o CC stubs/cpus.o CC stubs/kvm.o CC stubs/qmp_pc_dimm_device_list.o CC stubs/target-monitor-defs.o CC stubs/iohandler.o CC stubs/target-get-monitor-def.o CC stubs/vhost.o CC stubs/smbios_type_38.o CC stubs/ipmi.o CC contrib/ivshmem-client/ivshmem-client.o CC stubs/pc_madt_cpu_entry.o CC stubs/migration-colo.o CC contrib/ivshmem-client/main.o CC contrib/ivshmem-server/ivshmem-server.o CC contrib/ivshmem-server/main.o CC async.o CC qemu-nbd.o CC thread-pool.o CC block.o CC blockjob.o CC main-loop.o CC iohandler.o CC qemu-timer.o CC aio-posix.o CC qemu-io-cmds.o CC replication.o CC block/raw_bsd.o CC block/vmdk.o CC block/qcow.o CC block/vdi.o CC block/cloop.o CC block/bochs.o CC block/vpc.o CC block/vvfat.o CC block/dmg.o CC block/qcow2.o CC block/qcow2-refcount.o CC block/qcow2-cache.o CC block/qcow2-cluster.o CC block/qcow2-snapshot.o CC block/qed.o CC block/qed-gencb.o CC block/qed-l2-cache.o CC block/qed-table.o CC block/qed-cluster.o CC block/qed-check.o CC block/vhdx.o CC block/vhdx-endian.o CC block/vhdx-log.o CC block/quorum.o CC block/parallels.o CC block/blkdebug.o CC block/blkverify.o CC block/blkreplay.o CC block/block-backend.o CC block/snapshot.o CC block/qapi.o CC block/null.o CC block/raw-posix.o CC block/commit.o CC block/mirror.o CC block/io.o CC block/throttle-groups.o CC block/nbd.o CC block/nbd-client.o CC block/sheepdog.o CC block/accounting.o CC block/dirty-bitmap.o CC block/write-threshold.o CC block/backup.o CC block/replication.o CC block/crypto.o CC nbd/server.o CC nbd/client.o CC nbd/common.o CC crypto/init.o CC crypto/hash.o CC crypto/hash-glib.o CC crypto/aes.o CC crypto/cipher.o CC crypto/desrfb.o CC crypto/tlscreds.o CC crypto/tlscredsanon.o CC crypto/tlscredsx509.o CC crypto/secret.o CC crypto/tlssession.o CC crypto/random-platform.o CC crypto/pbkdf.o CC crypto/ivgen.o CC crypto/ivgen-essiv.o CC crypto/ivgen-plain64.o CC crypto/ivgen-plain.o CC crypto/afsplit.o CC crypto/xts.o CC crypto/block.o CC crypto/block-qcow.o CC crypto/block-luks.o CC io/channel.o CC io/channel-buffer.o CC io/channel-socket.o CC io/channel-command.o CC io/channel-file.o CC io/channel-tls.o CC io/channel-watch.o CC io/channel-websock.o CC io/task.o CC io/channel-util.o CC qom/container.o CC qom/object.o CC qom/qom-qobject.o CC qom/object_interfaces.o GEN qemu-img-cmds.h CC qemu-bridge-helper.o CC qemu-io.o CC blockdev-nbd.o CC blockdev.o CC iothread.o CC qdev-monitor.o CC device-hotplug.o CC os-posix.o CC qemu-char.o CC page_cache.o CC bt-host.o CC accel.o CC bt-vhci.o CC dma-helpers.o CC vl.o CC tpm.o CC device_tree.o GEN qmp-marshal.c CC qmp.o CC hmp.o CC cpus-common.o CC audio/audio.o CC audio/noaudio.o CC audio/wavaudio.o CC audio/mixeng.o CC audio/sdlaudio.o CC audio/ossaudio.o CC audio/wavcapture.o CC backends/rng.o CC backends/rng-egd.o CC backends/rng-random.o CC backends/msmouse.o CC backends/testdev.o CC backends/tpm.o CC backends/hostmem.o CC backends/hostmem-ram.o CC backends/hostmem-file.o CC backends/cryptodev.o CC block/stream.o CC backends/cryptodev-builtin.o CC disas/arm.o CC disas/i386.o CC fsdev/qemu-fsdev-dummy.o CC fsdev/qemu-fsdev-opts.o CC hw/acpi/core.o CC hw/acpi/piix4.o CC hw/acpi/pcihp.o CC hw/acpi/ich9.o CC hw/acpi/tco.o CC hw/acpi/cpu_hotplug.o CC hw/acpi/memory_hotplug.o CC hw/acpi/memory_hotplug_acpi_table.o CC hw/acpi/cpu.o CC hw/acpi/nvdimm.o CC hw/acpi/acpi_interface.o CC hw/acpi/bios-linker-loader.o CC hw/acpi/aml-build.o CC hw/audio/sb16.o CC hw/acpi/ipmi.o CC hw/audio/ac97.o CC hw/audio/es1370.o CC hw/audio/fmopl.o CC hw/audio/adlib.o CC hw/audio/gus.o CC hw/audio/gusemu_mixer.o CC hw/audio/gusemu_hal.o CC hw/audio/cs4231a.o CC hw/audio/intel-hda.o CC hw/audio/hda-codec.o CC hw/audio/pcspk.o CC hw/audio/pl041.o CC hw/audio/wm8750.o CC hw/audio/lm4549.o CC hw/audio/marvell_88w8618.o CC hw/block/block.o CC hw/block/cdrom.o CC hw/block/hd-geometry.o CC hw/block/m25p80.o CC hw/block/fdc.o CC hw/block/nand.o CC hw/block/pflash_cfi01.o CC hw/block/pflash_cfi02.o CC hw/block/ecc.o CC hw/block/onenand.o CC hw/block/nvme.o CC hw/bt/core.o CC hw/bt/l2cap.o CC hw/bt/sdp.o CC hw/bt/hci.o CC hw/bt/hid.o CC hw/bt/hci-csr.o CC hw/char/ipoctal232.o CC hw/char/parallel.o CC hw/char/pl011.o CC hw/char/serial.o CC hw/char/serial-isa.o CC hw/char/serial-pci.o CC hw/char/virtio-console.o CC hw/char/cadence_uart.o CC hw/char/debugcon.o CC hw/char/imx_serial.o CC hw/core/qdev.o CC hw/core/qdev-properties.o CC hw/core/bus.o CC hw/core/fw-path-provider.o CC hw/core/irq.o CC hw/core/hotplug.o CC hw/core/ptimer.o CC hw/core/sysbus.o CC hw/core/machine.o CC hw/core/null-machine.o CC hw/core/loader.o CC hw/core/qdev-properties-system.o CC hw/core/register.o CC hw/core/or-irq.o CC hw/core/platform-bus.o CC hw/display/ads7846.o CC hw/display/cirrus_vga.o CC hw/display/pl110.o CC hw/display/ssd0303.o CC hw/display/ssd0323.o CC hw/display/vga-pci.o CC hw/display/vga-isa.o CC hw/display/vmware_vga.o CC hw/display/blizzard.o CC hw/display/framebuffer.o CC hw/display/exynos4210_fimd.o CC hw/display/tc6393xb.o CC hw/dma/pl080.o CC hw/dma/pl330.o CC hw/dma/i8257.o CC hw/dma/xlnx-zynq-devcfg.o CC hw/gpio/max7310.o CC hw/gpio/pl061.o CC hw/gpio/zaurus.o CC hw/i2c/core.o CC hw/gpio/gpio_key.o CC hw/i2c/smbus.o CC hw/i2c/smbus_eeprom.o CC hw/i2c/smbus_ich9.o CC hw/i2c/i2c-ddc.o CC hw/i2c/versatile_i2c.o CC hw/i2c/pm_smbus.o CC hw/i2c/bitbang_i2c.o CC hw/i2c/exynos4210_i2c.o CC hw/i2c/imx_i2c.o CC hw/i2c/aspeed_i2c.o CC hw/ide/core.o CC hw/ide/atapi.o CC hw/ide/qdev.o CC hw/ide/pci.o CC hw/ide/isa.o CC hw/ide/piix.o CC hw/ide/microdrive.o CC hw/ide/ahci.o CC hw/ide/ich.o CC hw/input/hid.o CC hw/input/lm832x.o CC hw/input/pckbd.o CC hw/input/pl050.o CC hw/input/ps2.o CC hw/input/stellaris_input.o CC hw/input/tsc2005.o CC hw/input/vmmouse.o CC hw/input/virtio-input.o CC hw/input/virtio-input-hid.o CC hw/input/virtio-input-host.o CC hw/intc/i8259_common.o CC hw/intc/i8259.o CC hw/intc/pl190.o CC hw/intc/imx_avic.o CC hw/intc/realview_gic.o CC hw/intc/ioapic_common.o CC hw/intc/arm_gic_common.o CC hw/intc/arm_gic.o CC hw/intc/arm_gicv2m.o CC hw/intc/arm_gicv3_common.o CC hw/intc/arm_gicv3.o CC hw/intc/arm_gicv3_dist.o CC hw/intc/arm_gicv3_redist.o CC hw/intc/arm_gicv3_its_common.o CC hw/intc/intc.o CC hw/ipack/ipack.o CC hw/ipack/tpci200.o CC hw/ipmi/ipmi_bmc_sim.o CC hw/ipmi/ipmi.o CC hw/ipmi/ipmi_bmc_extern.o CC hw/ipmi/isa_ipmi_kcs.o CC hw/ipmi/isa_ipmi_bt.o CC hw/isa/isa-bus.o CC hw/isa/apm.o CC hw/mem/pc-dimm.o CC hw/mem/nvdimm.o CC hw/misc/applesmc.o CC hw/misc/max111x.o CC hw/misc/tmp105.o CC hw/misc/debugexit.o CC hw/misc/sga.o CC hw/misc/pc-testdev.o CC hw/misc/pci-testdev.o CC hw/misc/arm_l2x0.o CC hw/misc/arm_integrator_debug.o CC hw/misc/a9scu.o CC hw/misc/arm11scu.o CC hw/net/ne2000.o CC hw/net/eepro100.o CC hw/net/pcnet-pci.o CC hw/net/pcnet.o CC hw/net/e1000.o CC hw/net/e1000x_common.o CC hw/net/net_tx_pkt.o CC hw/net/net_rx_pkt.o CC hw/net/e1000e.o CC hw/net/e1000e_core.o CC hw/net/rtl8139.o CC hw/net/vmxnet3.o CC hw/net/smc91c111.o CC hw/net/lan9118.o CC hw/net/ne2000-isa.o CC hw/net/xgmac.o CC hw/net/allwinner_emac.o CC hw/net/imx_fec.o CC hw/net/cadence_gem.o CC hw/net/stellaris_enet.o CC hw/net/rocker/rocker.o CC hw/net/rocker/rocker_fp.o CC hw/net/rocker/rocker_desc.o CC hw/net/rocker/rocker_world.o CC hw/nvram/eeprom93xx.o CC hw/net/rocker/rocker_of_dpa.o CC hw/nvram/fw_cfg.o CC hw/nvram/chrp_nvram.o CC hw/pci-bridge/pci_expander_bridge.o CC hw/pci-bridge/pci_bridge_dev.o CC hw/pci-bridge/xio3130_upstream.o CC hw/pci-bridge/xio3130_downstream.o CC hw/pci-bridge/ioh3420.o CC hw/pci-bridge/i82801b11.o CC hw/pci-host/pam.o CC hw/pci-host/piix.o CC hw/pci-host/versatile.o CC hw/pci-host/q35.o CC hw/pci-host/gpex.o CC hw/pci/pci.o CC hw/pci/pci_bridge.o CC hw/pci/msix.o CC hw/pci/msi.o CC hw/pci/shpc.o CC hw/pci/slotid_cap.o CC hw/pci/pci_host.o CC hw/pci/pcie_host.o CC hw/pci/pcie_aer.o CC hw/pci/pcie.o CC hw/pci/pcie_port.o /tmp/qemu-test/src/hw/nvram/fw_cfg.c: In function ‘fw_cfg_dma_transfer’: /tmp/qemu-test/src/hw/nvram/fw_cfg.c:329: warning: ‘read’ may be used uninitialized in this function CC hw/pcmcia/pcmcia.o CC hw/pci/pci-stub.o CC hw/scsi/scsi-disk.o CC hw/scsi/scsi-generic.o CC hw/scsi/scsi-bus.o CC hw/scsi/lsi53c895a.o CC hw/scsi/mptsas.o CC hw/scsi/mptconfig.o CC hw/scsi/mptendian.o CC hw/scsi/megasas.o CC hw/scsi/esp.o CC hw/scsi/vmw_pvscsi.o CC hw/scsi/esp-pci.o CC hw/sd/pl181.o CC hw/sd/ssi-sd.o CC hw/sd/sd.o CC hw/sd/core.o CC hw/sd/sdhci.o CC hw/smbios/smbios.o CC hw/smbios/smbios_type_38.o CC hw/ssi/pl022.o CC hw/ssi/ssi.o CC hw/ssi/xilinx_spips.o CC hw/ssi/aspeed_smc.o CC hw/ssi/stm32f2xx_spi.o CC hw/timer/arm_timer.o CC hw/timer/arm_mptimer.o CC hw/timer/a9gtimer.o CC hw/timer/cadence_ttc.o CC hw/timer/ds1338.o CC hw/timer/rx8900.o CC hw/timer/hpet.o CC hw/timer/i8254_common.o CC hw/timer/i8254.o CC hw/timer/pl031.o CC hw/timer/twl92230.o CC hw/timer/imx_epit.o CC hw/timer/imx_gpt.o CC hw/timer/aspeed_timer.o CC hw/timer/stm32f2xx_timer.o CC hw/tpm/tpm_tis.o CC hw/tpm/tpm_passthrough.o CC hw/usb/core.o CC hw/tpm/tpm_util.o CC hw/usb/combined-packet.o CC hw/usb/bus.o CC hw/usb/libhw.o CC hw/usb/desc.o CC hw/usb/desc-msos.o CC hw/usb/hcd-ohci.o CC hw/usb/hcd-uhci.o CC hw/usb/hcd-ehci.o CC hw/usb/hcd-ehci-pci.o CC hw/usb/hcd-ehci-sysbus.o CC hw/usb/hcd-xhci.o CC hw/usb/hcd-musb.o CC hw/usb/dev-hub.o CC hw/usb/dev-hid.o CC hw/usb/dev-wacom.o CC hw/usb/dev-storage.o CC hw/usb/dev-uas.o CC hw/usb/dev-audio.o CC hw/usb/dev-serial.o CC hw/usb/dev-network.o CC hw/usb/dev-bluetooth.o CC hw/usb/dev-mtp.o CC hw/usb/dev-smartcard-reader.o CC hw/usb/host-stub.o CC hw/virtio/virtio-bus.o CC hw/virtio/virtio-rng.o CC hw/virtio/virtio-pci.o CC hw/virtio/virtio-mmio.o CC hw/watchdog/watchdog.o CC hw/watchdog/wdt_i6300esb.o CC hw/watchdog/wdt_ib700.o CC migration/migration.o CC migration/socket.o CC migration/fd.o CC migration/exec.o CC migration/tls.o CC migration/colo-comm.o CC migration/colo.o CC migration/colo-failover.o CC migration/vmstate.o CC migration/qemu-file.o CC migration/qemu-file-channel.o CC migration/xbzrle.o CC migration/postcopy-ram.o CC migration/qjson.o CC migration/block.o CC net/net.o CC net/queue.o CC net/util.o CC net/checksum.o CC net/hub.o CC net/dump.o CC net/socket.o CC net/eth.o CC net/l2tpv3.o CC net/tap.o CC net/vhost-user.o CC net/tap-linux.o CC net/slirp.o CC net/filter.o CC net/filter-buffer.o CC net/filter-mirror.o CC net/colo-compare.o CC net/colo.o CC net/filter-rewriter.o CC qom/cpu.o CC replay/replay.o CC replay/replay-internal.o CC replay/replay-events.o CC replay/replay-time.o CC replay/replay-input.o /tmp/qemu-test/src/replay/replay-internal.c: In function ‘replay_put_array’: /tmp/qemu-test/src/replay/replay-internal.c:65: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result CC replay/replay-char.o CC replay/replay-snapshot.o CC slirp/ip6_icmp.o CC slirp/cksum.o CC slirp/if.o CC slirp/ip_icmp.o CC slirp/ip6_input.o CC slirp/ip6_output.o CC slirp/ip_input.o CC slirp/ip_output.o CC slirp/dnssearch.o CC slirp/dhcpv6.o CC slirp/slirp.o CC slirp/mbuf.o CC slirp/misc.o CC slirp/sbuf.o CC slirp/tcp_input.o CC slirp/socket.o CC slirp/tcp_subr.o CC slirp/tcp_output.o CC slirp/udp.o CC slirp/tcp_timer.o CC slirp/udp6.o CC slirp/bootp.o CC slirp/tftp.o CC slirp/arp_table.o CC slirp/ndp_table.o CC ui/console.o CC ui/keymaps.o CC ui/cursor.o CC ui/qemu-pixman.o CC ui/input.o /tmp/qemu-test/src/slirp/tcp_input.c: In function ‘tcp_input’: /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_p’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_len’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_tos’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_id’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_off’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_ttl’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_sum’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_src.s_addr’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_dst.s_addr’ may be used uninitialized in this function /tmp/qemu-test/src/slirp/tcp_input.c:220: warning: ‘save_ip6.ip_nh’ may be used uninitialized in this function CC ui/input-keymap.o CC ui/input-legacy.o CC ui/sdl.o CC ui/input-linux.o CC ui/sdl_zoom.o CC ui/x_keymap.o CC ui/vnc.o CC ui/vnc-enc-zlib.o CC ui/vnc-enc-hextile.o CC ui/vnc-enc-tight.o CC ui/vnc-enc-zrle.o CC ui/vnc-palette.o CC ui/vnc-auth-vencrypt.o CC ui/vnc-ws.o CC ui/vnc-jobs.o LINK tests/qemu-iotests/socket_scm_helper CC qga/guest-agent-command-state.o CC qga/commands.o CC qga/main.o CC qga/commands-posix.o CC qga/channel-posix.o CC qga/qapi-generated/qga-qapi-types.o CC qga/qapi-generated/qga-qapi-visit.o CC qga/qapi-generated/qga-qmp-marshal.o CC qmp-introspect.o CC qapi-types.o CC qapi-visit.o CC qapi-event.o AR libqemustub.a CC qmp-marshal.o CC qemu-img.o CC trace/generated-tracers.o AS optionrom/multiboot.o AS optionrom/linuxboot.o CC optionrom/linuxboot_dma.o AS optionrom/kvmvapic.o cc: unrecognized option '-no-integrated-as' cc: unrecognized option '-no-integrated-as' BUILD optionrom/linuxboot_dma.img BUILD optionrom/linuxboot_dma.raw SIGN optionrom/linuxboot_dma.bin BUILD optionrom/multiboot.img BUILD optionrom/linuxboot.img BUILD optionrom/kvmvapic.img BUILD optionrom/multiboot.raw BUILD optionrom/linuxboot.raw BUILD optionrom/kvmvapic.raw SIGN optionrom/multiboot.bin SIGN optionrom/linuxboot.bin SIGN optionrom/kvmvapic.bin AR libqemuutil.a LINK qemu-ga LINK ivshmem-client LINK ivshmem-server LINK qemu-nbd LINK qemu-img LINK qemu-io LINK qemu-bridge-helper GEN x86_64-softmmu/hmp-commands.h GEN x86_64-softmmu/hmp-commands-info.h GEN x86_64-softmmu/config-target.h CC x86_64-softmmu/exec.o CC x86_64-softmmu/translate-all.o CC x86_64-softmmu/cpu-exec.o CC x86_64-softmmu/translate-common.o CC x86_64-softmmu/cpu-exec-common.o CC x86_64-softmmu/tcg/tcg.o CC x86_64-softmmu/tcg/tcg-op.o CC x86_64-softmmu/tcg/optimize.o CC x86_64-softmmu/tcg/tcg-common.o CC x86_64-softmmu/fpu/softfloat.o CC x86_64-softmmu/disas.o CC x86_64-softmmu/tcg-runtime.o CC x86_64-softmmu/arch_init.o CC x86_64-softmmu/cpus.o CC x86_64-softmmu/monitor.o CC x86_64-softmmu/gdbstub.o GEN aarch64-softmmu/hmp-commands.h CC x86_64-softmmu/balloon.o GEN aarch64-softmmu/hmp-commands-info.h GEN aarch64-softmmu/config-target.h CC x86_64-softmmu/ioport.o CC x86_64-softmmu/numa.o CC x86_64-softmmu/bootdevice.o CC x86_64-softmmu/qtest.o CC x86_64-softmmu/kvm-all.o CC x86_64-softmmu/memory.o CC x86_64-softmmu/cputlb.o CC x86_64-softmmu/memory_mapping.o CC x86_64-softmmu/dump.o CC x86_64-softmmu/migration/ram.o CC x86_64-softmmu/migration/savevm.o CC x86_64-softmmu/xen-common-stub.o CC x86_64-softmmu/xen-hvm-stub.o CC x86_64-softmmu/hw/block/virtio-blk.o CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o CC x86_64-softmmu/hw/char/virtio-serial-bus.o CC x86_64-softmmu/hw/core/nmi.o CC x86_64-softmmu/hw/core/generic-loader.o CC x86_64-softmmu/hw/cpu/core.o CC x86_64-softmmu/hw/display/vga.o CC x86_64-softmmu/hw/display/virtio-gpu.o CC x86_64-softmmu/hw/display/virtio-gpu-3d.o CC x86_64-softmmu/hw/display/virtio-gpu-pci.o CC x86_64-softmmu/hw/display/virtio-vga.o CC x86_64-softmmu/hw/intc/apic.o CC x86_64-softmmu/hw/intc/apic_common.o CC x86_64-softmmu/hw/intc/ioapic.o CC x86_64-softmmu/hw/isa/lpc_ich9.o CC x86_64-softmmu/hw/misc/vmport.o CC x86_64-softmmu/hw/misc/ivshmem.o CC x86_64-softmmu/hw/misc/pvpanic.o CC x86_64-softmmu/hw/misc/edu.o CC aarch64-softmmu/exec.o CC x86_64-softmmu/hw/misc/hyperv_testdev.o CC x86_64-softmmu/hw/net/virtio-net.o CC aarch64-softmmu/translate-all.o CC x86_64-softmmu/hw/net/vhost_net.o CC aarch64-softmmu/cpu-exec.o CC x86_64-softmmu/hw/scsi/virtio-scsi.o CC aarch64-softmmu/translate-common.o CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o CC aarch64-softmmu/cpu-exec-common.o CC aarch64-softmmu/tcg/tcg.o CC x86_64-softmmu/hw/scsi/vhost-scsi.o CC x86_64-softmmu/hw/timer/mc146818rtc.o CC aarch64-softmmu/tcg/tcg-op.o CC x86_64-softmmu/hw/vfio/common.o CC x86_64-softmmu/hw/vfio/pci.o CC aarch64-softmmu/tcg/optimize.o CC x86_64-softmmu/hw/vfio/pci-quirks.o CC aarch64-softmmu/tcg/tcg-common.o CC x86_64-softmmu/hw/vfio/platform.o CC aarch64-softmmu/fpu/softfloat.o CC x86_64-softmmu/hw/vfio/calxeda-xgmac.o CC aarch64-softmmu/disas.o CC x86_64-softmmu/hw/vfio/amd-xgbe.o CC aarch64-softmmu/tcg-runtime.o CC x86_64-softmmu/hw/vfio/spapr.o GEN aarch64-softmmu/gdbstub-xml.c CC x86_64-softmmu/hw/virtio/virtio.o CC x86_64-softmmu/hw/virtio/virtio-balloon.o CC aarch64-softmmu/kvm-stub.o CC aarch64-softmmu/arch_init.o CC aarch64-softmmu/cpus.o CC x86_64-softmmu/hw/virtio/vhost.o CC x86_64-softmmu/hw/virtio/vhost-backend.o CC x86_64-softmmu/hw/virtio/vhost-user.o CC aarch64-softmmu/monitor.o CC x86_64-softmmu/hw/virtio/vhost-vsock.o CC aarch64-softmmu/gdbstub.o CC aarch64-softmmu/ioport.o CC aarch64-softmmu/balloon.o CC x86_64-softmmu/hw/virtio/virtio-crypto.o CC aarch64-softmmu/numa.o CC aarch64-softmmu/qtest.o CC x86_64-softmmu/hw/virtio/virtio-crypto-pci.o CC aarch64-softmmu/bootdevice.o CC x86_64-softmmu/hw/i386/multiboot.o CC aarch64-softmmu/memory.o CC x86_64-softmmu/hw/i386/pc.o CC aarch64-softmmu/cputlb.o CC x86_64-softmmu/hw/i386/pc_piix.o CC aarch64-softmmu/memory_mapping.o CC aarch64-softmmu/migration/ram.o CC aarch64-softmmu/dump.o CC x86_64-softmmu/hw/i386/x86-iommu.o CC x86_64-softmmu/hw/i386/pc_q35.o CC x86_64-softmmu/hw/i386/pc_sysfw.o CC aarch64-softmmu/migration/savevm.o CC aarch64-softmmu/xen-common-stub.o /tmp/qemu-test/src/hw/i386/pc_piix.c: In function ‘igd_passthrough_isa_bridge_create’: /tmp/qemu-test/src/hw/i386/pc_piix.c:1046: warning: ‘pch_rev_id’ may be used uninitialized in this function CC aarch64-softmmu/xen-hvm-stub.o CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o CC aarch64-softmmu/hw/block/virtio-blk.o CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o CC x86_64-softmmu/hw/i386/intel_iommu.o CC aarch64-softmmu/hw/char/exynos4210_uart.o CC x86_64-softmmu/hw/i386/amd_iommu.o CC aarch64-softmmu/hw/char/omap_uart.o CC x86_64-softmmu/hw/i386/kvmvapic.o CC aarch64-softmmu/hw/char/digic-uart.o CC aarch64-softmmu/hw/char/stm32f2xx_usart.o CC aarch64-softmmu/hw/char/bcm2835_aux.o CC aarch64-softmmu/hw/core/nmi.o CC aarch64-softmmu/hw/char/virtio-serial-bus.o CC x86_64-softmmu/hw/i386/pci-assign-load-rom.o CC x86_64-softmmu/hw/i386/acpi-build.o CC aarch64-softmmu/hw/core/generic-loader.o CC x86_64-softmmu/hw/i386/kvm/clock.o CC aarch64-softmmu/hw/cpu/arm11mpcore.o CC x86_64-softmmu/hw/i386/kvm/apic.o /tmp/qemu-test/src/hw/i386/acpi-build.c: In function ‘build_append_pci_bus_devices’: /tmp/qemu-test/src/hw/i386/acpi-build.c:501: warning: ‘notify_method’ may be used uninitialized in this function CC x86_64-softmmu/hw/i386/kvm/i8259.o CC x86_64-softmmu/hw/i386/kvm/ioapic.o CC aarch64-softmmu/hw/cpu/realview_mpcore.o CC aarch64-softmmu/hw/cpu/a9mpcore.o CC aarch64-softmmu/hw/cpu/a15mpcore.o CC x86_64-softmmu/hw/i386/kvm/i8254.o CC aarch64-softmmu/hw/display/omap_lcdc.o CC x86_64-softmmu/hw/i386/kvm/pci-assign.o CC aarch64-softmmu/hw/cpu/core.o CC x86_64-softmmu/target-i386/translate.o CC aarch64-softmmu/hw/display/omap_dss.o CC x86_64-softmmu/target-i386/helper.o CC x86_64-softmmu/target-i386/cpu.o CC x86_64-softmmu/target-i386/bpt_helper.o CC aarch64-softmmu/hw/display/pxa2xx_lcd.o CC x86_64-softmmu/target-i386/excp_helper.o CC x86_64-softmmu/target-i386/fpu_helper.o CC x86_64-softmmu/target-i386/cc_helper.o CC x86_64-softmmu/target-i386/int_helper.o CC aarch64-softmmu/hw/display/bcm2835_fb.o CC aarch64-softmmu/hw/display/vga.o CC x86_64-softmmu/target-i386/svm_helper.o CC x86_64-softmmu/target-i386/smm_helper.o CC aarch64-softmmu/hw/display/virtio-gpu.o CC aarch64-softmmu/hw/display/virtio-gpu-3d.o CC aarch64-softmmu/hw/display/virtio-gpu-pci.o CC x86_64-softmmu/target-i386/misc_helper.o CC x86_64-softmmu/target-i386/mem_helper.o CC x86_64-softmmu/target-i386/seg_helper.o CC x86_64-softmmu/target-i386/mpx_helper.o CC x86_64-softmmu/target-i386/gdbstub.o CC aarch64-softmmu/hw/display/dpcd.o CC x86_64-softmmu/target-i386/machine.o CC aarch64-softmmu/hw/display/xlnx_dp.o CC x86_64-softmmu/target-i386/arch_memory_mapping.o CC aarch64-softmmu/hw/dma/xlnx_dpdma.o CC x86_64-softmmu/target-i386/arch_dump.o CC aarch64-softmmu/hw/dma/omap_dma.o CC x86_64-softmmu/target-i386/monitor.o CC x86_64-softmmu/target-i386/kvm.o CC x86_64-softmmu/target-i386/hyperv.o CC aarch64-softmmu/hw/dma/soc_dma.o CC aarch64-softmmu/hw/dma/pxa2xx_dma.o CC aarch64-softmmu/hw/dma/bcm2835_dma.o CC aarch64-softmmu/hw/gpio/omap_gpio.o CC aarch64-softmmu/hw/i2c/omap_i2c.o CC aarch64-softmmu/hw/gpio/imx_gpio.o GEN trace/generated-helpers.c CC x86_64-softmmu/trace/control-target.o CC aarch64-softmmu/hw/input/pxa2xx_keypad.o CC aarch64-softmmu/hw/input/tsc210x.o CC aarch64-softmmu/hw/intc/armv7m_nvic.o CC aarch64-softmmu/hw/intc/exynos4210_gic.o CC aarch64-softmmu/hw/intc/exynos4210_combiner.o CC aarch64-softmmu/hw/intc/bcm2835_ic.o CC aarch64-softmmu/hw/intc/omap_intc.o CC aarch64-softmmu/hw/intc/bcm2836_control.o CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o CC aarch64-softmmu/hw/intc/aspeed_vic.o CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o CC aarch64-softmmu/hw/misc/ivshmem.o CC aarch64-softmmu/hw/misc/arm_sysctl.o CC aarch64-softmmu/hw/misc/cbus.o CC aarch64-softmmu/hw/misc/exynos4210_pmu.o CC aarch64-softmmu/hw/misc/imx_ccm.o CC aarch64-softmmu/hw/misc/imx31_ccm.o CC aarch64-softmmu/hw/misc/imx25_ccm.o CC aarch64-softmmu/hw/misc/imx6_ccm.o CC aarch64-softmmu/hw/misc/imx6_src.o CC aarch64-softmmu/hw/misc/mst_fpga.o CC aarch64-softmmu/hw/misc/omap_clk.o CC aarch64-softmmu/hw/misc/omap_gpmc.o CC aarch64-softmmu/hw/misc/omap_sdrc.o CC aarch64-softmmu/hw/misc/omap_l4.o CC aarch64-softmmu/hw/misc/bcm2835_property.o CC aarch64-softmmu/hw/misc/omap_tap.o CC aarch64-softmmu/hw/misc/bcm2835_mbox.o CC aarch64-softmmu/hw/misc/zynq_slcr.o CC aarch64-softmmu/hw/misc/zynq-xadc.o CC x86_64-softmmu/trace/generated-helpers.o CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o CC aarch64-softmmu/hw/misc/edu.o CC aarch64-softmmu/hw/misc/auxbus.o CC aarch64-softmmu/hw/misc/aspeed_scu.o CC aarch64-softmmu/hw/misc/aspeed_sdmc.o CC aarch64-softmmu/hw/net/virtio-net.o CC aarch64-softmmu/hw/net/vhost_net.o CC aarch64-softmmu/hw/scsi/virtio-scsi.o CC aarch64-softmmu/hw/pcmcia/pxa2xx.o CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o CC aarch64-softmmu/hw/scsi/vhost-scsi.o CC aarch64-softmmu/hw/sd/omap_mmc.o CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o CC aarch64-softmmu/hw/ssi/omap_spi.o CC aarch64-softmmu/hw/ssi/imx_spi.o CC aarch64-softmmu/hw/timer/exynos4210_mct.o CC aarch64-softmmu/hw/timer/exynos4210_pwm.o CC aarch64-softmmu/hw/timer/exynos4210_rtc.o CC aarch64-softmmu/hw/timer/omap_gptimer.o CC aarch64-softmmu/hw/timer/omap_synctimer.o CC aarch64-softmmu/hw/timer/pxa2xx_timer.o CC aarch64-softmmu/hw/timer/digic-timer.o CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o CC aarch64-softmmu/hw/usb/tusb6010.o CC aarch64-softmmu/hw/vfio/common.o CC aarch64-softmmu/hw/vfio/pci.o CC aarch64-softmmu/hw/vfio/pci-quirks.o CC aarch64-softmmu/hw/vfio/platform.o CC aarch64-softmmu/hw/vfio/calxeda-xgmac.o CC aarch64-softmmu/hw/vfio/amd-xgbe.o CC aarch64-softmmu/hw/vfio/spapr.o CC aarch64-softmmu/hw/virtio/virtio.o CC aarch64-softmmu/hw/virtio/virtio-balloon.o CC aarch64-softmmu/hw/virtio/vhost.o LINK x86_64-softmmu/qemu-system-x86_64 CC aarch64-softmmu/hw/virtio/vhost-backend.o CC aarch64-softmmu/hw/virtio/vhost-user.o CC aarch64-softmmu/hw/virtio/vhost-vsock.o CC aarch64-softmmu/hw/virtio/virtio-crypto.o CC aarch64-softmmu/hw/virtio/virtio-crypto-pci.o CC aarch64-softmmu/hw/arm/boot.o CC aarch64-softmmu/hw/arm/collie.o CC aarch64-softmmu/hw/arm/exynos4_boards.o CC aarch64-softmmu/hw/arm/gumstix.o CC aarch64-softmmu/hw/arm/highbank.o CC aarch64-softmmu/hw/arm/digic_boards.o CC aarch64-softmmu/hw/arm/mainstone.o CC aarch64-softmmu/hw/arm/integratorcp.o CC aarch64-softmmu/hw/arm/nseries.o CC aarch64-softmmu/hw/arm/musicpal.o CC aarch64-softmmu/hw/arm/omap_sx1.o CC aarch64-softmmu/hw/arm/palm.o CC aarch64-softmmu/hw/arm/spitz.o CC aarch64-softmmu/hw/arm/realview.o CC aarch64-softmmu/hw/arm/stellaris.o CC aarch64-softmmu/hw/arm/tosa.o CC aarch64-softmmu/hw/arm/versatilepb.o CC aarch64-softmmu/hw/arm/vexpress.o CC aarch64-softmmu/hw/arm/virt.o CC aarch64-softmmu/hw/arm/xilinx_zynq.o CC aarch64-softmmu/hw/arm/z2.o CC aarch64-softmmu/hw/arm/virt-acpi-build.o CC aarch64-softmmu/hw/arm/netduino2.o CC aarch64-softmmu/hw/arm/sysbus-fdt.o CC aarch64-softmmu/hw/arm/armv7m.o CC aarch64-softmmu/hw/arm/exynos4210.o CC aarch64-softmmu/hw/arm/pxa2xx.o CC aarch64-softmmu/hw/arm/pxa2xx_pic.o CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o CC aarch64-softmmu/hw/arm/digic.o CC aarch64-softmmu/hw/arm/omap1.o CC aarch64-softmmu/hw/arm/omap2.o CC aarch64-softmmu/hw/arm/strongarm.o CC aarch64-softmmu/hw/arm/allwinner-a10.o CC aarch64-softmmu/hw/arm/cubieboard.o CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o CC aarch64-softmmu/hw/arm/bcm2836.o CC aarch64-softmmu/hw/arm/raspi.o CC aarch64-softmmu/hw/arm/stm32f205_soc.o CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o CC aarch64-softmmu/hw/arm/fsl-imx25.o CC aarch64-softmmu/hw/arm/xlnx-ep108.o CC aarch64-softmmu/hw/arm/imx25_pdk.o CC aarch64-softmmu/hw/arm/kzm.o CC aarch64-softmmu/hw/arm/fsl-imx31.o CC aarch64-softmmu/hw/arm/fsl-imx6.o CC aarch64-softmmu/hw/arm/sabrelite.o CC aarch64-softmmu/hw/arm/aspeed_soc.o CC aarch64-softmmu/hw/arm/aspeed.o CC aarch64-softmmu/target-arm/arm-semi.o CC aarch64-softmmu/target-arm/machine.o CC aarch64-softmmu/target-arm/psci.o CC aarch64-softmmu/target-arm/arch_dump.o CC aarch64-softmmu/target-arm/kvm-stub.o CC aarch64-softmmu/target-arm/monitor.o CC aarch64-softmmu/target-arm/translate.o CC aarch64-softmmu/target-arm/op_helper.o CC aarch64-softmmu/target-arm/helper.o CC aarch64-softmmu/target-arm/cpu.o CC aarch64-softmmu/target-arm/neon_helper.o CC aarch64-softmmu/target-arm/gdbstub.o CC aarch64-softmmu/target-arm/iwmmxt_helper.o CC aarch64-softmmu/target-arm/cpu64.o CC aarch64-softmmu/target-arm/translate-a64.o CC aarch64-softmmu/target-arm/helper-a64.o CC aarch64-softmmu/target-arm/arm-powerctl.o CC aarch64-softmmu/target-arm/crypto_helper.o CC aarch64-softmmu/target-arm/gdbstub64.o /tmp/qemu-test/src/target-arm/translate-a64.c: In function ‘handle_shri_with_rndacc’: /tmp/qemu-test/src/target-arm/translate-a64.c:6395: warning: ‘tcg_src_hi’ may be used uninitialized in this function /tmp/qemu-test/src/target-arm/translate-a64.c: In function ‘disas_simd_scalar_two_reg_misc’: /tmp/qemu-test/src/target-arm/translate-a64.c:8122: warning: ‘rmode’ may be used uninitialized in this function GEN trace/generated-helpers.c CC aarch64-softmmu/trace/control-target.o CC aarch64-softmmu/gdbstub-xml.o CC aarch64-softmmu/trace/generated-helpers.o LINK aarch64-softmmu/qemu-system-aarch64 TEST tests/qapi-schema/alternate-any.out TEST tests/qapi-schema/alternate-array.out TEST tests/qapi-schema/alternate-base.out TEST tests/qapi-schema/alternate-clash.out TEST tests/qapi-schema/alternate-conflict-dict.out TEST tests/qapi-schema/alternate-conflict-string.out TEST tests/qapi-schema/alternate-empty.out TEST tests/qapi-schema/alternate-nested.out TEST tests/qapi-schema/alternate-unknown.out TEST tests/qapi-schema/args-alternate.out TEST tests/qapi-schema/args-any.out TEST tests/qapi-schema/args-array-empty.out TEST tests/qapi-schema/args-array-unknown.out TEST tests/qapi-schema/args-bad-boxed.out TEST tests/qapi-schema/args-boxed-anon.out TEST tests/qapi-schema/args-boxed-empty.out TEST tests/qapi-schema/args-boxed-string.out TEST tests/qapi-schema/args-int.out TEST tests/qapi-schema/args-invalid.out TEST tests/qapi-schema/args-member-array-bad.out TEST tests/qapi-schema/args-member-case.out TEST tests/qapi-schema/args-member-unknown.out TEST tests/qapi-schema/args-name-clash.out TEST tests/qapi-schema/args-union.out TEST tests/qapi-schema/args-unknown.out TEST tests/qapi-schema/bad-base.out TEST tests/qapi-schema/bad-data.out TEST tests/qapi-schema/bad-ident.out TEST tests/qapi-schema/bad-type-bool.out TEST tests/qapi-schema/bad-type-dict.out TEST tests/qapi-schema/bad-type-int.out TEST tests/qapi-schema/base-cycle-direct.out TEST tests/qapi-schema/base-cycle-indirect.out TEST tests/qapi-schema/command-int.out TEST tests/qapi-schema/comments.out TEST tests/qapi-schema/double-data.out TEST tests/qapi-schema/double-type.out TEST tests/qapi-schema/duplicate-key.out TEST tests/qapi-schema/empty.out TEST tests/qapi-schema/enum-bad-name.out TEST tests/qapi-schema/enum-bad-prefix.out TEST tests/qapi-schema/enum-clash-member.out TEST tests/qapi-schema/enum-dict-member.out TEST tests/qapi-schema/enum-int-member.out TEST tests/qapi-schema/enum-member-case.out TEST tests/qapi-schema/enum-missing-data.out TEST tests/qapi-schema/enum-wrong-data.out TEST tests/qapi-schema/escape-outside-string.out TEST tests/qapi-schema/escape-too-big.out TEST tests/qapi-schema/escape-too-short.out TEST tests/qapi-schema/event-boxed-empty.out TEST tests/qapi-schema/event-case.out TEST tests/qapi-schema/event-nest-struct.out TEST tests/qapi-schema/flat-union-bad-base.out TEST tests/qapi-schema/flat-union-array-branch.out TEST tests/qapi-schema/flat-union-bad-discriminator.out TEST tests/qapi-schema/flat-union-base-any.out TEST tests/qapi-schema/flat-union-base-union.out TEST tests/qapi-schema/flat-union-clash-member.out TEST tests/qapi-schema/flat-union-empty.out TEST tests/qapi-schema/flat-union-incomplete-branch.out TEST tests/qapi-schema/flat-union-inline.out TEST tests/qapi-schema/flat-union-int-branch.out TEST tests/qapi-schema/flat-union-invalid-branch-key.out TEST tests/qapi-schema/flat-union-invalid-discriminator.out TEST tests/qapi-schema/flat-union-no-base.out TEST tests/qapi-schema/flat-union-optional-discriminator.out TEST tests/qapi-schema/flat-union-string-discriminator.out TEST tests/qapi-schema/funny-char.out TEST tests/qapi-schema/include-before-err.out TEST tests/qapi-schema/ident-with-escape.out TEST tests/qapi-schema/include-cycle.out TEST tests/qapi-schema/include-format-err.out TEST tests/qapi-schema/include-nested-err.out TEST tests/qapi-schema/include-no-file.out TEST tests/qapi-schema/include-non-file.out TEST tests/qapi-schema/include-relpath.out TEST tests/qapi-schema/include-self-cycle.out TEST tests/qapi-schema/include-repetition.out TEST tests/qapi-schema/include-simple.out TEST tests/qapi-schema/indented-expr.out TEST tests/qapi-schema/leading-comma-list.out TEST tests/qapi-schema/leading-comma-object.out TEST tests/qapi-schema/missing-colon.out TEST tests/qapi-schema/missing-comma-list.out TEST tests/qapi-schema/missing-comma-object.out TEST tests/qapi-schema/missing-type.out TEST tests/qapi-schema/nested-struct-data.out TEST tests/qapi-schema/non-objects.out TEST tests/qapi-schema/qapi-schema-test.out TEST tests/qapi-schema/quoted-structural-chars.out TEST tests/qapi-schema/redefined-builtin.out TEST tests/qapi-schema/redefined-command.out TEST tests/qapi-schema/redefined-event.out TEST tests/qapi-schema/redefined-type.out TEST tests/qapi-schema/reserved-command-q.out TEST tests/qapi-schema/reserved-enum-q.out TEST tests/qapi-schema/reserved-member-has.out TEST tests/qapi-schema/reserved-member-q.out TEST tests/qapi-schema/reserved-member-u.out TEST tests/qapi-schema/reserved-member-underscore.out TEST tests/qapi-schema/reserved-type-kind.out TEST tests/qapi-schema/reserved-type-list.out TEST tests/qapi-schema/returns-alternate.out TEST tests/qapi-schema/returns-array-bad.out TEST tests/qapi-schema/returns-dict.out TEST tests/qapi-schema/returns-unknown.out TEST tests/qapi-schema/returns-whitelist.out TEST tests/qapi-schema/struct-base-clash-deep.out TEST tests/qapi-schema/struct-base-clash.out TEST tests/qapi-schema/struct-data-invalid.out TEST tests/qapi-schema/struct-member-invalid.out TEST tests/qapi-schema/trailing-comma-list.out TEST tests/qapi-schema/trailing-comma-object.out TEST tests/qapi-schema/type-bypass-bad-gen.out TEST tests/qapi-schema/unclosed-list.out TEST tests/qapi-schema/unclosed-string.out TEST tests/qapi-schema/unclosed-object.out TEST tests/qapi-schema/unicode-str.out TEST tests/qapi-schema/union-branch-case.out TEST tests/qapi-schema/union-base-no-discriminator.out TEST tests/qapi-schema/union-clash-branches.out TEST tests/qapi-schema/union-empty.out TEST tests/qapi-schema/union-invalid-base.out TEST tests/qapi-schema/union-optional-branch.out TEST tests/qapi-schema/union-unknown.out TEST tests/qapi-schema/unknown-escape.out TEST tests/qapi-schema/unknown-expr-key.out CC tests/check-qdict.o CC tests/test-char.o CC tests/check-qfloat.o CC tests/check-qstring.o CC tests/check-qint.o CC tests/check-qlist.o CC tests/check-qjson.o CC tests/check-qnull.o GEN tests/test-qapi-visit.c CC tests/test-qobject-output-visitor.o GEN tests/test-qapi-types.c GEN tests/test-qmp-introspect.c CC tests/test-clone-visitor.o GEN tests/test-qapi-event.c CC tests/test-qobject-input-visitor.o CC tests/test-qobject-input-strict.o CC tests/test-qmp-commands.o CC tests/test-string-input-visitor.o GEN tests/test-qmp-marshal.c CC tests/test-string-output-visitor.o CC tests/test-qmp-event.o CC tests/test-opts-visitor.o CC tests/test-coroutine.o CC tests/test-visitor-serialization.o CC tests/test-throttle.o CC tests/test-iov.o CC tests/test-aio.o CC tests/test-thread-pool.o CC tests/test-hbitmap.o CC tests/test-blockjob.o CC tests/test-blockjob-txn.o CC tests/test-x86-cpuid.o CC tests/test-xbzrle.o CC tests/test-vmstate.o CC tests/test-cutils.o CC tests/test-mul64.o CC tests/test-int128.o CC tests/rcutorture.o CC tests/test-rcu-list.o CC tests/test-qdist.o CC tests/test-qht.o CC tests/test-qht-par.o CC tests/qht-bench.o /tmp/qemu-test/src/tests/test-int128.c:180: warning: ‘__noclone__’ attribute directive ignored CC tests/test-bitops.o CC tests/check-qom-interface.o CC tests/check-qom-proplist.o CC tests/test-qemu-opts.o CC tests/test-write-threshold.o CC tests/test-crypto-hash.o CC tests/test-crypto-secret.o CC tests/test-crypto-cipher.o CC tests/libqtest.o CC tests/test-qga.o CC tests/test-timed-average.o CC tests/test-io-task.o CC tests/test-io-channel-socket.o CC tests/test-io-channel-file.o CC tests/io-channel-helpers.o CC tests/test-io-channel-command.o CC tests/test-base64.o CC tests/test-io-channel-buffer.o CC tests/test-crypto-ivgen.o CC tests/test-crypto-afsplit.o CC tests/test-crypto-xts.o CC tests/test-crypto-block.o CC tests/test-logging.o CC tests/test-replication.o CC tests/test-bufferiszero.o CC tests/test-uuid.o CC tests/ptimer-test.o CC tests/ptimer-test-stubs.o CC tests/vhost-user-test.o CC tests/libqos/pci.o CC tests/libqos/fw_cfg.o CC tests/libqos/malloc.o CC tests/libqos/i2c.o CC tests/libqos/libqos.o CC tests/libqos/malloc-spapr.o CC tests/libqos/libqos-spapr.o CC tests/libqos/rtas.o CC tests/libqos/pci-spapr.o CC tests/libqos/pci-pc.o CC tests/libqos/malloc-pc.o CC tests/libqos/libqos-pc.o CC tests/libqos/ahci.o CC tests/libqos/virtio.o CC tests/libqos/virtio-pci.o CC tests/libqos/virtio-mmio.o CC tests/libqos/malloc-generic.o CC tests/endianness-test.o CC tests/fdc-test.o CC tests/ide-test.o CC tests/ahci-test.o CC tests/hd-geo-test.o CC tests/boot-order-test.o CC tests/bios-tables-test.o CC tests/boot-sector.o CC tests/boot-serial-test.o CC tests/pxe-test.o CC tests/rtc-test.o CC tests/ipmi-kcs-test.o CC tests/ipmi-bt-test.o CC tests/i440fx-test.o CC tests/fw_cfg-test.o CC tests/drive_del-test.o CC tests/wdt_ib700-test.o CC tests/tco-test.o CC tests/e1000-test.o CC tests/e1000e-test.o CC tests/rtl8139-test.o CC tests/pcnet-test.o CC tests/eepro100-test.o CC tests/ne2000-test.o CC tests/nvme-test.o /tmp/qemu-test/src/tests/ide-test.c: In function ‘cdrom_pio_impl’: /tmp/qemu-test/src/tests/ide-test.c:791: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result /tmp/qemu-test/src/tests/ide-test.c: In function ‘test_cdrom_dma’: /tmp/qemu-test/src/tests/ide-test.c:886: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result CC tests/ac97-test.o CC tests/es1370-test.o CC tests/virtio-net-test.o CC tests/virtio-balloon-test.o CC tests/virtio-blk-test.o CC tests/virtio-rng-test.o CC tests/virtio-scsi-test.o CC tests/virtio-serial-test.o CC tests/virtio-console-test.o CC tests/tpci200-test.o CC tests/ipoctal232-test.o CC tests/display-vga-test.o CC tests/intel-hda-test.o CC tests/ivshmem-test.o CC tests/vmxnet3-test.o CC tests/pvpanic-test.o CC tests/i82801b11-test.o CC tests/ioh3420-test.o CC tests/usb-hcd-ohci-test.o CC tests/libqos/usb.o CC tests/usb-hcd-uhci-test.o CC tests/usb-hcd-ehci-test.o CC tests/usb-hcd-xhci-test.o CC tests/pc-cpu-test.o CC tests/q35-test.o CC tests/test-netfilter.o CC tests/test-filter-redirector.o CC tests/test-filter-mirror.o CC tests/postcopy-test.o CC tests/test-x86-cpuid-compat.o CC tests/device-introspect-test.o CC tests/qom-test.o LINK tests/check-qdict LINK tests/test-char LINK tests/check-qfloat LINK tests/check-qint LINK tests/check-qstring LINK tests/check-qlist LINK tests/check-qnull LINK tests/check-qjson CC tests/test-qapi-visit.o CC tests/test-qapi-types.o CC tests/test-qapi-event.o CC tests/test-qmp-introspect.o CC tests/test-qmp-marshal.o LINK tests/test-coroutine LINK tests/test-iov LINK tests/test-aio LINK tests/test-throttle LINK tests/test-thread-pool LINK tests/test-hbitmap LINK tests/test-blockjob LINK tests/test-blockjob-txn LINK tests/test-x86-cpuid LINK tests/test-xbzrle LINK tests/test-cutils LINK tests/test-vmstate LINK tests/test-mul64 LINK tests/test-int128 LINK tests/rcutorture LINK tests/test-rcu-list LINK tests/test-qdist LINK tests/test-qht LINK tests/qht-bench LINK tests/test-bitops LINK tests/check-qom-interface LINK tests/check-qom-proplist LINK tests/test-qemu-opts LINK tests/test-write-threshold LINK tests/test-crypto-hash LINK tests/test-crypto-cipher LINK tests/test-crypto-secret LINK tests/test-qga LINK tests/test-timed-average LINK tests/test-io-task LINK tests/test-io-channel-socket LINK tests/test-io-channel-file LINK tests/test-io-channel-command LINK tests/test-io-channel-buffer LINK tests/test-base64 LINK tests/test-crypto-ivgen LINK tests/test-crypto-afsplit LINK tests/test-crypto-xts LINK tests/test-crypto-block LINK tests/test-logging LINK tests/test-replication LINK tests/test-bufferiszero LINK tests/test-uuid LINK tests/ptimer-test LINK tests/vhost-user-test LINK tests/endianness-test LINK tests/fdc-test LINK tests/ide-test LINK tests/ahci-test LINK tests/hd-geo-test LINK tests/boot-order-test LINK tests/bios-tables-test LINK tests/boot-serial-test LINK tests/pxe-test LINK tests/rtc-test LINK tests/ipmi-kcs-test LINK tests/ipmi-bt-test LINK tests/i440fx-test LINK tests/fw_cfg-test LINK tests/drive_del-test LINK tests/wdt_ib700-test LINK tests/tco-test LINK tests/e1000-test LINK tests/e1000e-test LINK tests/rtl8139-test LINK tests/pcnet-test LINK tests/eepro100-test LINK tests/ne2000-test LINK tests/nvme-test LINK tests/ac97-test LINK tests/es1370-test LINK tests/virtio-net-test LINK tests/virtio-balloon-test LINK tests/virtio-blk-test LINK tests/virtio-rng-test LINK tests/virtio-scsi-test LINK tests/virtio-serial-test LINK tests/virtio-console-test LINK tests/tpci200-test LINK tests/ipoctal232-test LINK tests/display-vga-test LINK tests/intel-hda-test LINK tests/ivshmem-test LINK tests/vmxnet3-test LINK tests/pvpanic-test LINK tests/i82801b11-test LINK tests/ioh3420-test LINK tests/usb-hcd-ohci-test LINK tests/usb-hcd-uhci-test LINK tests/usb-hcd-ehci-test LINK tests/usb-hcd-xhci-test LINK tests/pc-cpu-test LINK tests/q35-test LINK tests/test-netfilter LINK tests/test-filter-mirror LINK tests/test-filter-redirector LINK tests/postcopy-test LINK tests/test-x86-cpuid-compat LINK tests/device-introspect-test LINK tests/qom-test GTESTER tests/check-qdict GTESTER tests/test-char GTESTER tests/check-qfloat GTESTER tests/check-qint GTESTER tests/check-qstring GTESTER tests/check-qlist GTESTER tests/check-qnull GTESTER tests/check-qjson LINK tests/test-qobject-output-visitor LINK tests/test-clone-visitor LINK tests/test-qobject-input-visitor LINK tests/test-qobject-input-strict LINK tests/test-qmp-commands LINK tests/test-string-input-visitor LINK tests/test-string-output-visitor LINK tests/test-qmp-event LINK tests/test-opts-visitor GTESTER tests/test-coroutine GTESTER tests/test-iov LINK tests/test-visitor-serialization GTESTER tests/test-thread-pool GTESTER tests/test-aio GTESTER tests/test-throttle GTESTER tests/test-hbitmap GTESTER tests/test-blockjob GTESTER tests/test-blockjob-txn GTESTER tests/test-x86-cpuid GTESTER tests/test-xbzrle GTESTER tests/test-vmstate GTESTER tests/test-cutils GTESTER tests/test-mul64 Failed to load simple/primitive:b_1 Failed to load simple/primitive:i64_2 Failed to load simple/primitive:i32_1 Failed to load simple/primitive:i32_1 GTESTER tests/test-int128 GTESTER tests/rcutorture GTESTER tests/test-qdist GTESTER tests/test-rcu-list GTESTER tests/test-qht GTESTER tests/test-bitops LINK tests/test-qht-par GTESTER tests/check-qom-interface GTESTER tests/check-qom-proplist GTESTER tests/test-qemu-opts GTESTER tests/test-write-threshold GTESTER tests/test-crypto-hash GTESTER tests/test-crypto-cipher GTESTER tests/test-crypto-secret GTESTER tests/test-qga GTESTER tests/test-timed-average GTESTER tests/test-io-task GTESTER tests/test-io-channel-socket GTESTER tests/test-io-channel-file GTESTER tests/test-io-channel-command GTESTER tests/test-io-channel-buffer GTESTER tests/test-base64 GTESTER tests/test-crypto-ivgen GTESTER tests/test-crypto-afsplit GTESTER tests/test-crypto-xts GTESTER tests/test-crypto-block GTESTER tests/test-logging GTESTER tests/test-replication GTESTER tests/test-bufferiszero GTESTER tests/test-uuid GTESTER tests/ptimer-test GTESTER check-qtest-aarch64 GTESTER check-qtest-x86_64 GTESTER tests/test-qobject-output-visitor GTESTER tests/test-clone-visitor GTESTER tests/test-qobject-input-visitor GTESTER tests/test-qobject-input-strict GTESTER tests/test-qmp-commands GTESTER tests/test-string-input-visitor ftruncate: Permission denied GTESTER tests/test-string-output-visitor GTESTER tests/test-qmp-event GTESTER tests/test-opts-visitor GTESTER tests/test-visitor-serialization GTESTER tests/test-qht-par ftruncate: Permission denied ftruncate: Permission denied ** ERROR:/tmp/qemu-test/src/tests/vhost-user-test.c:668:test_migrate: assertion failed: (qdict_haskey(rsp, "return")) GTester: last random seed: R02S82c21094fd1914f7844dc82a557a7f63 ftruncate: Permission denied ftruncate: Permission denied ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02S10653628d82a4d7dd0000ffd0a1fcbf3 ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02Sfab4484ab384cb50a4fa218259b16b2f ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02Sc1fa16a0b176aa37f8035bd7b2acbba5 ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02Sdc6b68af13a9f29b38235995184871ed ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02Sab34fc965e9a72cd31e7cf6451222c49 ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02S04d122b9903047df80ea092828095584 ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02S88083ee09374fe237bcfbf83253064ba ** ERROR:/tmp/qemu-test/src/tests/fdc-test.c:102:ack_irq: assertion failed: (get_irq(FLOPPY_IRQ)) GTester: last random seed: R02Se818b55fba0552266e72f76a22a19f14 ** ERROR:/tmp/qemu-test/src/tests/ide-test.c:262:send_dma_request: assertion failed (get_irq(IDE_PRIMARY_IRQ) == !!(status & BM_STS_INTR)): (0 == 1) GTester: last random seed: R02S0971636bf043049bdfdecaa2105d22e5 GTester: last random seed: R02Sdbd5cff9139996dec300a6c4b92a7864 GTester: last random seed: R02Sf88b46f93d072a00c264fc489744b299 GTester: last random seed: R02S622d41f87b6120a62ea0d722a2a13a2b GTester: last random seed: R02S66e9199c226aa71356095f39649e214b GTester: last random seed: R02Sd657de0bc241e37596e89c7f5a89cd03 ** ERROR:/tmp/qemu-test/src/tests/ide-test.c:262:send_dma_request: assertion failed (get_irq(IDE_PRIMARY_IRQ) == !!(status & BM_STS_INTR)): (0 == 1) GTester: last random seed: R02Sd967c7a1c843d37707d4eecfdda089f1 ** ERROR:/tmp/qemu-test/src/tests/ide-test.c:262:send_dma_request: assertion failed (get_irq(IDE_PRIMARY_IRQ) == !!(status & BM_STS_INTR)): (0 == 1) GTester: last random seed: R02Sef278aa93fd36a34724bf6ed9418c97d ** ERROR:/tmp/qemu-test/src/tests/ide-test.c:262:send_dma_request: assertion failed (get_irq(IDE_PRIMARY_IRQ) == !!(status & BM_STS_INTR)): (0 == 1) GTester: last random seed: R02S8202374d565da3835998ca5ebf6548b9 ** ERROR:/tmp/qemu-test/src/tests/ide-test.c:771:ide_wait_intr: code should not be reached GTester: last random seed: R02S3755c5ff8c4147a0a26e6d68a095704d ** ERROR:/tmp/qemu-test/src/tests/ide-test.c:771:ide_wait_intr: code should not be reached GTester: last random seed: R02S491994dd40f7735fcfeb165b95d696cf ** ERROR:/tmp/qemu-test/src/tests/ide-test.c:262:send_dma_request: assertion failed (get_irq(IDE_PRIMARY_IRQ) == !!(status & BM_STS_INTR)): (0 == 1) GTester: last random seed: R02S07ac41a56598ad8f0e849609f0f8f321 Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. ** ERROR:/tmp/qemu-test/src/tests/rtc-test.c:294:alarm_time: assertion failed: (get_irq(RTC_ISA_IRQ)) GTester: last random seed: R02S1f6cbdbd88d5dff203e1287a5c3c0b98 ** ERROR:/tmp/qemu-test/src/tests/ipmi-kcs-test.c:92:kcs_clear_obf: assertion failed: (get_irq(IPMI_IRQ)) GTester: last random seed: R02S88c4909ddc36872139fa54d0b3237780 ** ERROR:/tmp/qemu-test/src/tests/ipmi-bt-test.c:279:bt_cmd: assertion failed: (get_irq(IPMI_IRQ)) GTester: last random seed: R02Sa7dbc65e608d1f3bd3f06e54e412e0c6 Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator. make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-ie51qv7a/src' BUILD fedora make[1]: Entering directory `/var/tmp/patchew-tester-tmp-ie51qv7a/src' ARCHIVE qemu.tgz ARCHIVE dtc.tgz COPY RUNNER RUN test-mingw in qemu:fedora Packages installed: PyYAML-3.11-12.fc24.x86_64 SDL-devel-1.2.15-21.fc24.x86_64 bc-1.06.95-16.fc24.x86_64 bison-3.0.4-4.fc24.x86_64 ccache-3.3.2-1.fc24.x86_64 clang-3.8.0-2.fc24.x86_64 findutils-4.6.0-7.fc24.x86_64 flex-2.6.0-2.fc24.x86_64 gcc-6.2.1-2.fc24.x86_64 gcc-c++-6.2.1-2.fc24.x86_64 git-2.7.4-3.fc24.x86_64 glib2-devel-2.48.2-1.fc24.x86_64 libfdt-devel-1.4.2-1.fc24.x86_64 make-4.1-5.fc24.x86_64 mingw32-SDL-1.2.15-7.fc24.noarch mingw32-bzip2-1.0.6-7.fc24.noarch mingw32-curl-7.47.0-1.fc24.noarch mingw32-glib2-2.48.2-1.fc24.noarch mingw32-gmp-6.1.0-1.fc24.noarch mingw32-gnutls-3.4.14-1.fc24.noarch mingw32-gtk2-2.24.31-1.fc24.noarch mingw32-gtk3-3.20.9-1.fc24.noarch mingw32-libjpeg-turbo-1.5.0-1.fc24.noarch mingw32-libpng-1.6.23-1.fc24.noarch mingw32-libssh2-1.4.3-5.fc24.noarch mingw32-libtasn1-4.5-2.fc24.noarch mingw32-nettle-3.2-1.fc24.noarch mingw32-pixman-0.34.0-1.fc24.noarch mingw32-pkg-config-0.28-6.fc24.x86_64 mingw64-SDL-1.2.15-7.fc24.noarch mingw64-bzip2-1.0.6-7.fc24.noarch mingw64-curl-7.47.0-1.fc24.noarch mingw64-glib2-2.48.2-1.fc24.noarch mingw64-gmp-6.1.0-1.fc24.noarch mingw64-gnutls-3.4.14-1.fc24.noarch mingw64-gtk2-2.24.31-1.fc24.noarch mingw64-gtk3-3.20.9-1.fc24.noarch mingw64-libjpeg-turbo-1.5.0-1.fc24.noarch mingw64-libpng-1.6.23-1.fc24.noarch mingw64-libssh2-1.4.3-5.fc24.noarch mingw64-libtasn1-4.5-2.fc24.noarch mingw64-nettle-3.2-1.fc24.noarch mingw64-pixman-0.34.0-1.fc24.noarch mingw64-pkg-config-0.28-6.fc24.x86_64 perl-5.22.2-362.fc24.x86_64 pixman-devel-0.34.0-2.fc24.x86_64 sparse-0.5.0-7.fc24.x86_64 tar-1.28-7.fc24.x86_64 which-2.20-13.fc24.x86_64 zlib-devel-1.2.8-10.fc24.x86_64 Environment variables: PACKAGES=ccache git tar PyYAML sparse flex bison glib2-devel pixman-devel zlib-devel SDL-devel libfdt-devel gcc gcc-c++ clang make perl which bc findutils mingw32-pixman mingw32-glib2 mingw32-gmp mingw32-SDL mingw32-pkg-config mingw32-gtk2 mingw32-gtk3 mingw32-gnutls mingw32-nettle mingw32-libtasn1 mingw32-libjpeg-turbo mingw32-libpng mingw32-curl mingw32-libssh2 mingw32-bzip2 mingw64-pixman mingw64-glib2 mingw64-gmp mingw64-SDL mingw64-pkg-config mingw64-gtk2 mingw64-gtk3 mingw64-gnutls mingw64-nettle mingw64-libtasn1 mingw64-libjpeg-turbo mingw64-libpng mingw64-curl mingw64-libssh2 mingw64-bzip2 HOSTNAME= TERM=xterm MAKEFLAGS= -j16 HISTSIZE=1000 J=16 USER=root CCACHE_DIR=/var/tmp/ccache EXTRA_CONFIGURE_OPTS= V= SHOW_ENV=1 MAIL=/var/spool/mail/root PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin PWD=/ TARGET_LIST= HISTCONTROL=ignoredups SHLVL=1 HOME=/root TEST_DIR=/tmp/qemu-test LOGNAME=root LESSOPEN=||/usr/bin/lesspipe.sh %s FEATURES=mingw clang pyyaml dtc DEBUG= _=/usr/bin/env Configure options: --enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install --cross-prefix=x86_64-w64-mingw32- --enable-trace-backends=simple --enable-debug --enable-gnutls --enable-nettle --enable-curl --enable-vnc --enable-bzip2 --enable-guest-agent --with-sdlabi=1.2 --with-gtkabi=2.0 Install prefix /var/tmp/qemu-build/install BIOS directory /var/tmp/qemu-build/install binary directory /var/tmp/qemu-build/install library directory /var/tmp/qemu-build/install/lib module directory /var/tmp/qemu-build/install/lib libexec directory /var/tmp/qemu-build/install/libexec include directory /var/tmp/qemu-build/install/include config directory /var/tmp/qemu-build/install local state directory queried at runtime Windows SDK no Source path /tmp/qemu-test/src C compiler x86_64-w64-mingw32-gcc Host C compiler cc C++ compiler x86_64-w64-mingw32-g++ Objective-C compiler clang ARFLAGS rv CFLAGS -g QEMU_CFLAGS -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -mms-bitfields -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 -I/usr/x86_64-w64-mingw32/sys-root/mingw/lib/glib-2.0/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -m64 -mcx16 -mthreads -D__USE_MINGW_ANSI_STDIO=1 -DWIN32_LEAN_AND_MEAN -DWINVER=0x501 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-shift-negative-value -Wmissing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/p11-kit-1 -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/libpng16 LDFLAGS -Wl,--nxcompat -Wl,--no-seh -Wl,--dynamicbase -Wl,--warn-common -m64 -g make make install install python python -B smbd /usr/sbin/smbd module support no host CPU x86_64 host big endian no target list x86_64-softmmu aarch64-softmmu tcg debug enabled yes gprof enabled no sparse enabled no strip binaries no profiler no static build no pixman system SDL support yes (1.2.15) GTK support yes (2.24.31) GTK GL support no VTE support no TLS priority NORMAL GNUTLS support yes GNUTLS rnd yes libgcrypt no libgcrypt kdf no nettle yes (3.2) nettle kdf yes libtasn1 yes curses support no virgl support no curl support yes mingw32 support yes Audio drivers dsound Block whitelist (rw) Block whitelist (ro) VirtFS support no VNC support yes VNC SASL support no VNC JPEG support yes VNC PNG support yes xen support no brlapi support no bluez support no Documentation no PIE no vde support no netmap support no Linux AIO support no ATTR/XATTR support no Install blobs yes KVM support no COLO support yes RDMA support no TCG interpreter no fdt support yes preadv support no fdatasync no madvise no posix_madvise no libcap-ng support no vhost-net support no vhost-scsi support no vhost-vsock support no Trace backends simple Trace output file trace-<pid> spice support no rbd support no xfsctl support no smartcard support no libusb no usb net redir no OpenGL support no OpenGL dmabufs no libiscsi support no libnfs support no build guest agent yes QGA VSS support no QGA w32 disk info yes QGA MSI support no seccomp support no coroutine backend win32 coroutine pool yes debug stack usage no GlusterFS support no Archipelago support no gcov gcov gcov enabled no TPM support yes libssh2 support yes TPM passthrough no QOM debugging yes lzo support no snappy support no bzip2 support yes NUMA host support no tcmalloc support no jemalloc support no avx2 optimization yes replication support yes mkdir -p dtc/libfdt GEN x86_64-softmmu/config-devices.mak.tmp mkdir -p dtc/tests GEN aarch64-softmmu/config-devices.mak.tmp GEN config-host.h GEN qemu-options.def GEN qmp-commands.h GEN qapi-types.h GEN qapi-visit.h GEN qapi-event.h GEN qmp-introspect.h GEN module_block.h GEN tests/test-qapi-types.h GEN tests/test-qapi-visit.h GEN tests/test-qmp-commands.h GEN tests/test-qapi-event.h GEN tests/test-qmp-introspect.h GEN x86_64-softmmu/config-devices.mak GEN aarch64-softmmu/config-devices.mak GEN trace/generated-tracers.h GEN trace/generated-tcg-tracers.h DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c GEN trace/generated-helpers-wrappers.h DEP /tmp/qemu-test/src/dtc/tests/trees.S GEN trace/generated-helpers.h DEP /tmp/qemu-test/src/dtc/tests/testutils.c DEP /tmp/qemu-test/src/dtc/tests/value-labels.c DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c GEN config-all-devices.mak DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c DEP /tmp/qemu-test/src/dtc/tests/incbin.c DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c DEP /tmp/qemu-test/src/dtc/tests/path-references.c DEP /tmp/qemu-test/src/dtc/tests/references.c DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c DEP /tmp/qemu-test/src/dtc/tests/del_node.c DEP /tmp/qemu-test/src/dtc/tests/del_property.c DEP /tmp/qemu-test/src/dtc/tests/setprop.c DEP /tmp/qemu-test/src/dtc/tests/set_name.c DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c DEP /tmp/qemu-test/src/dtc/tests/open_pack.c DEP /tmp/qemu-test/src/dtc/tests/nopulate.c DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c DEP /tmp/qemu-test/src/dtc/tests/nop_node.c DEP /tmp/qemu-test/src/dtc/tests/nop_property.c DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c DEP /tmp/qemu-test/src/dtc/tests/notfound.c DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c DEP /tmp/qemu-test/src/dtc/tests/char_literal.c DEP /tmp/qemu-test/src/dtc/tests/get_alias.c DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c DEP /tmp/qemu-test/src/dtc/tests/get_path.c DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c DEP /tmp/qemu-test/src/dtc/tests/getprop.c DEP /tmp/qemu-test/src/dtc/tests/get_name.c DEP /tmp/qemu-test/src/dtc/tests/path_offset.c DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c DEP /tmp/qemu-test/src/dtc/tests/find_property.c DEP /tmp/qemu-test/src/dtc/tests/root_node.c DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c DEP /tmp/qemu-test/src/dtc/util.c DEP /tmp/qemu-test/src/dtc/fdtput.c DEP /tmp/qemu-test/src/dtc/fdtget.c DEP /tmp/qemu-test/src/dtc/fdtdump.c DEP /tmp/qemu-test/src/dtc/srcpos.c LEX convert-dtsv0-lexer.lex.c BISON dtc-parser.tab.c LEX dtc-lexer.lex.c DEP /tmp/qemu-test/src/dtc/treesource.c DEP /tmp/qemu-test/src/dtc/livetree.c DEP /tmp/qemu-test/src/dtc/fstree.c DEP /tmp/qemu-test/src/dtc/flattree.c DEP /tmp/qemu-test/src/dtc/dtc.c DEP /tmp/qemu-test/src/dtc/data.c DEP /tmp/qemu-test/src/dtc/checks.c DEP convert-dtsv0-lexer.lex.c DEP dtc-parser.tab.c DEP dtc-lexer.lex.c CHK version_gen.h UPD version_gen.h DEP /tmp/qemu-test/src/dtc/util.c CC libfdt/fdt.o CC libfdt/fdt_ro.o CC libfdt/fdt_wip.o CC libfdt/fdt_sw.o CC libfdt/fdt_strerror.o CC libfdt/fdt_rw.o CC libfdt/fdt_empty_tree.o AR libfdt/libfdt.a x86_64-w64-mingw32-ar: creating libfdt/libfdt.a a - libfdt/fdt.o a - libfdt/fdt_ro.o a - libfdt/fdt_wip.o a - libfdt/fdt_sw.o a - libfdt/fdt_rw.o a - libfdt/fdt_strerror.o a - libfdt/fdt_empty_tree.o RC version.lo RC version.o GEN qga/qapi-generated/qga-qapi-types.h GEN qga/qapi-generated/qga-qapi-visit.h GEN qga/qapi-generated/qga-qmp-commands.h GEN qga/qapi-generated/qga-qapi-types.c GEN qga/qapi-generated/qga-qmp-marshal.c GEN qga/qapi-generated/qga-qapi-visit.c GEN qmp-introspect.c GEN qapi-types.c GEN qapi-visit.c GEN qapi-event.c CC qapi/qapi-visit-core.o CC qapi/qapi-dealloc-visitor.o CC qapi/qobject-input-visitor.o CC qapi/qobject-output-visitor.o CC qapi/qmp-registry.o CC qapi/qmp-dispatch.o CC qapi/string-input-visitor.o CC qapi/string-output-visitor.o CC qapi/opts-visitor.o CC qapi/qapi-clone-visitor.o CC qapi/qmp-event.o CC qapi/qapi-util.o CC qobject/qnull.o CC qobject/qint.o CC qobject/qstring.o CC qobject/qdict.o CC qobject/qlist.o CC qobject/qfloat.o CC qobject/qbool.o CC qobject/qjson.o CC qobject/qobject.o CC qobject/json-lexer.o CC qobject/json-streamer.o CC qobject/json-parser.o GEN trace/generated-tracers.c CC trace/simple.o CC trace/control.o CC trace/qmp.o CC util/osdep.o CC util/cutils.o CC util/unicode.o CC util/qemu-timer-common.o CC util/bufferiszero.o CC util/event_notifier-win32.o CC util/oslib-win32.o CC util/qemu-thread-win32.o CC util/envlist.o CC util/path.o CC util/module.o CC util/bitmap.o CC util/bitops.o CC util/hbitmap.o CC util/fifo8.o CC util/acl.o CC util/error.o CC util/qemu-error.o CC util/id.o CC util/iov.o CC util/qemu-config.o CC util/qemu-sockets.o CC util/uri.o CC util/notify.o CC util/qemu-option.o CC util/qemu-progress.o CC util/hexdump.o CC util/crc32c.o CC util/uuid.o CC util/throttle.o CC util/getauxval.o CC util/readline.o CC util/rcu.o CC util/qemu-coroutine.o CC util/qemu-coroutine-lock.o CC util/qemu-coroutine-io.o CC util/qemu-coroutine-sleep.o CC util/coroutine-win32.o CC util/buffer.o CC util/base64.o CC util/timed-average.o CC util/qdist.o CC util/log.o CC util/qht.o CC util/range.o CC crypto/pbkdf-stub.o CC stubs/arch-query-cpu-def.o CC stubs/arch-query-cpu-model-expansion.o CC stubs/arch-query-cpu-model-comparison.o CC stubs/arch-query-cpu-model-baseline.o CC stubs/bdrv-next-monitor-owned.o CC stubs/blk-commit-all.o CC stubs/blockdev-close-all-bdrv-states.o CC stubs/clock-warp.o CC stubs/cpu-get-clock.o CC stubs/cpu-get-icount.o CC stubs/dump.o CC stubs/error-printf.o CC stubs/fdset-add-fd.o CC stubs/fdset-find-fd.o CC stubs/fdset-get-fd.o CC stubs/fdset-remove-fd.o CC stubs/gdbstub.o CC stubs/get-fd.o CC stubs/get-next-serial.o CC stubs/get-vm-name.o CC stubs/iothread.o CC stubs/iothread-lock.o CC stubs/is-daemonized.o CC stubs/machine-init-done.o CC stubs/migr-blocker.o CC stubs/mon-is-qmp.o CC stubs/monitor-init.o CC stubs/notify-event.o CC stubs/qtest.o CC stubs/replay.o CC stubs/replay-user.o CC stubs/reset.o CC stubs/runstate-check.o CC stubs/set-fd-handler.o CC stubs/slirp.o CC stubs/sysbus.o CC stubs/trace-control.o CC stubs/uuid.o CC stubs/vm-stop.o CC stubs/vmstate.o CC stubs/fd-register.o CC stubs/cpus.o CC stubs/kvm.o CC stubs/qmp_pc_dimm_device_list.o CC stubs/target-monitor-defs.o CC stubs/target-get-monitor-def.o CC stubs/vhost.o CC stubs/iohandler.o CC stubs/smbios_type_38.o CC stubs/ipmi.o CC stubs/pc_madt_cpu_entry.o CC stubs/migration-colo.o GEN qemu-img-cmds.h CC async.o CC thread-pool.o CC block.o CC blockjob.o CC main-loop.o CC iohandler.o CC qemu-timer.o CC aio-win32.o CC qemu-io-cmds.o CC replication.o CC block/raw_bsd.o CC block/qcow.o CC block/vdi.o CC block/vmdk.o CC block/cloop.o CC block/bochs.o CC block/vpc.o CC block/vvfat.o CC block/dmg.o CC block/qcow2.o CC block/qcow2-refcount.o CC block/qcow2-cluster.o CC block/qcow2-snapshot.o CC block/qcow2-cache.o CC block/qed.o CC block/qed-gencb.o CC block/qed-l2-cache.o CC block/qed-table.o CC block/qed-cluster.o CC block/qed-check.o CC block/vhdx.o CC block/vhdx-endian.o CC block/vhdx-log.o CC block/quorum.o CC block/parallels.o CC block/blkdebug.o CC block/blkverify.o CC block/blkreplay.o CC block/block-backend.o CC block/snapshot.o CC block/qapi.o CC block/raw-win32.o CC block/win32-aio.o CC block/null.o CC block/mirror.o CC block/commit.o CC block/io.o CC block/throttle-groups.o CC block/nbd-client.o CC block/nbd.o CC block/sheepdog.o CC block/accounting.o CC block/dirty-bitmap.o CC block/write-threshold.o CC block/backup.o CC block/replication.o CC block/crypto.o CC nbd/server.o CC nbd/client.o CC nbd/common.o CC block/curl.o CC block/ssh.o CC block/dmg-bz2.o CC crypto/init.o CC crypto/hash.o CC crypto/hash-nettle.o CC crypto/desrfb.o CC crypto/aes.o CC crypto/cipher.o CC crypto/tlscredsanon.o CC crypto/tlscreds.o CC crypto/tlscredsx509.o CC crypto/tlssession.o CC crypto/secret.o CC crypto/random-gnutls.o CC crypto/pbkdf.o CC crypto/pbkdf-nettle.o CC crypto/ivgen.o CC crypto/ivgen-essiv.o CC crypto/ivgen-plain.o CC crypto/ivgen-plain64.o CC crypto/afsplit.o CC crypto/xts.o CC crypto/block.o CC crypto/block-qcow.o CC io/channel.o CC crypto/block-luks.o CC io/channel-command.o CC io/channel-buffer.o CC io/channel-file.o CC io/channel-socket.o CC io/channel-tls.o CC io/channel-watch.o CC io/channel-websock.o CC io/channel-util.o CC io/task.o CC qom/object.o CC qom/container.o CC qom/qom-qobject.o CC qom/object_interfaces.o CC blockdev.o CC qemu-io.o CC blockdev-nbd.o CC iothread.o CC qdev-monitor.o CC device-hotplug.o CC qemu-char.o CC os-win32.o CC page_cache.o CC accel.o CC bt-host.o CC bt-vhci.o CC dma-helpers.o CC vl.o CC tpm.o GEN qmp-marshal.c CC device_tree.o CC qmp.o CC hmp.o CC audio/audio.o CC cpus-common.o CC audio/noaudio.o CC audio/wavaudio.o CC audio/mixeng.o CC audio/sdlaudio.o CC audio/dsoundaudio.o CC audio/audio_win_int.o CC audio/wavcapture.o CC backends/rng.o CC backends/rng-egd.o CC backends/msmouse.o CC backends/testdev.o CC backends/tpm.o CC backends/hostmem.o CC backends/hostmem-ram.o CC backends/cryptodev.o CC backends/cryptodev-builtin.o CC disas/arm.o CC block/stream.o CXX disas/arm-a64.o CC disas/i386.o CXX disas/libvixl/vixl/utils.o CXX disas/libvixl/vixl/compiler-intrinsics.o CXX disas/libvixl/vixl/a64/instructions-a64.o CXX disas/libvixl/vixl/a64/decoder-a64.o CXX disas/libvixl/vixl/a64/disasm-a64.o CC hw/acpi/core.o CC hw/acpi/piix4.o CC hw/acpi/pcihp.o CC hw/acpi/tco.o CC hw/acpi/ich9.o CC hw/acpi/cpu_hotplug.o CC hw/acpi/memory_hotplug.o CC hw/acpi/memory_hotplug_acpi_table.o CC hw/acpi/cpu.o CC hw/acpi/nvdimm.o CC hw/acpi/acpi_interface.o CC hw/acpi/bios-linker-loader.o CC hw/acpi/aml-build.o CC hw/acpi/ipmi.o CC hw/audio/sb16.o CC hw/audio/es1370.o CC hw/audio/ac97.o CC hw/audio/fmopl.o CC hw/audio/adlib.o CC hw/audio/gus.o CC hw/audio/gusemu_hal.o CC hw/audio/cs4231a.o CC hw/audio/gusemu_mixer.o CC hw/audio/intel-hda.o CC hw/audio/hda-codec.o CC hw/audio/pcspk.o CC hw/audio/wm8750.o CC hw/audio/pl041.o CC hw/audio/lm4549.o CC hw/audio/marvell_88w8618.o CC hw/block/block.o CC hw/block/cdrom.o CC hw/block/hd-geometry.o CC hw/block/fdc.o CC hw/block/m25p80.o CC hw/block/nand.o CC hw/block/pflash_cfi01.o CC hw/block/pflash_cfi02.o CC hw/block/ecc.o CC hw/block/onenand.o CC hw/block/nvme.o CC hw/bt/core.o CC hw/bt/l2cap.o CC hw/bt/sdp.o CC hw/bt/hci.o CC hw/bt/hid.o CC hw/bt/hci-csr.o CC hw/char/ipoctal232.o CC hw/char/parallel.o CC hw/char/pl011.o CC hw/char/serial.o CC hw/char/serial-isa.o CC hw/char/serial-pci.o CC hw/char/virtio-console.o CC hw/char/debugcon.o CC hw/char/cadence_uart.o CC hw/char/imx_serial.o CC hw/core/qdev.o CC hw/core/qdev-properties.o CC hw/core/bus.o CC hw/core/fw-path-provider.o CC hw/core/irq.o CC hw/core/hotplug.o CC hw/core/ptimer.o CC hw/core/sysbus.o CC hw/core/machine.o CC hw/core/null-machine.o CC hw/core/loader.o CC hw/core/qdev-properties-system.o CC hw/core/register.o CC hw/core/or-irq.o CC hw/core/platform-bus.o CC hw/display/ads7846.o CC hw/display/cirrus_vga.o CC hw/display/pl110.o CC hw/display/ssd0303.o CC hw/display/ssd0323.o CC hw/display/vga-pci.o CC hw/display/vga-isa.o CC hw/display/vmware_vga.o CC hw/display/blizzard.o CC hw/display/exynos4210_fimd.o CC hw/display/framebuffer.o CC hw/display/tc6393xb.o CC hw/dma/pl080.o CC hw/dma/pl330.o CC hw/dma/i8257.o CC hw/dma/xlnx-zynq-devcfg.o CC hw/gpio/max7310.o CC hw/gpio/pl061.o CC hw/gpio/zaurus.o CC hw/gpio/gpio_key.o CC hw/i2c/core.o CC hw/i2c/smbus.o CC hw/i2c/smbus_eeprom.o CC hw/i2c/i2c-ddc.o CC hw/i2c/versatile_i2c.o CC hw/i2c/smbus_ich9.o CC hw/i2c/pm_smbus.o CC hw/i2c/bitbang_i2c.o CC hw/i2c/exynos4210_i2c.o CC hw/i2c/imx_i2c.o CC hw/i2c/aspeed_i2c.o CC hw/ide/core.o CC hw/ide/atapi.o CC hw/ide/qdev.o CC hw/ide/pci.o CC hw/ide/isa.o CC hw/ide/microdrive.o CC hw/ide/piix.o CC hw/ide/ahci.o CC hw/ide/ich.o CC hw/input/hid.o CC hw/input/lm832x.o CC hw/input/pckbd.o CC hw/input/pl050.o CC hw/input/ps2.o CC hw/input/stellaris_input.o CC hw/input/tsc2005.o CC hw/input/vmmouse.o CC hw/input/virtio-input.o CC hw/input/virtio-input-hid.o CC hw/intc/i8259_common.o CC hw/intc/i8259.o CC hw/intc/pl190.o CC hw/intc/imx_avic.o CC hw/intc/realview_gic.o CC hw/intc/ioapic_common.o CC hw/intc/arm_gic_common.o CC hw/intc/arm_gic.o CC hw/intc/arm_gicv2m.o CC hw/intc/arm_gicv3_common.o CC hw/intc/arm_gicv3.o CC hw/intc/arm_gicv3_dist.o CC hw/intc/arm_gicv3_redist.o CC hw/intc/arm_gicv3_its_common.o CC hw/intc/intc.o CC hw/ipack/ipack.o CC hw/ipack/tpci200.o CC hw/ipmi/ipmi.o CC hw/ipmi/ipmi_bmc_sim.o CC hw/ipmi/ipmi_bmc_extern.o CC hw/ipmi/isa_ipmi_kcs.o CC hw/ipmi/isa_ipmi_bt.o CC hw/isa/isa-bus.o CC hw/isa/apm.o CC hw/mem/pc-dimm.o CC hw/mem/nvdimm.o CC hw/misc/applesmc.o CC hw/misc/max111x.o CC hw/misc/tmp105.o CC hw/misc/debugexit.o CC hw/misc/sga.o CC hw/misc/pc-testdev.o CC hw/misc/pci-testdev.o CC hw/misc/arm_l2x0.o CC hw/misc/arm_integrator_debug.o CC hw/misc/a9scu.o CC hw/misc/arm11scu.o CC hw/net/ne2000.o CC hw/net/eepro100.o CC hw/net/pcnet-pci.o CC hw/net/pcnet.o CC hw/net/e1000.o CC hw/net/e1000x_common.o CC hw/net/net_tx_pkt.o CC hw/net/net_rx_pkt.o CC hw/net/e1000e.o CC hw/net/e1000e_core.o CC hw/net/rtl8139.o CC hw/net/vmxnet3.o CC hw/net/smc91c111.o CC hw/net/lan9118.o CC hw/net/ne2000-isa.o CC hw/net/xgmac.o CC hw/net/allwinner_emac.o CC hw/net/imx_fec.o CC hw/net/cadence_gem.o CC hw/net/stellaris_enet.o CC hw/net/rocker/rocker.o CC hw/net/rocker/rocker_fp.o CC hw/net/rocker/rocker_desc.o CC hw/net/rocker/rocker_world.o CC hw/net/rocker/rocker_of_dpa.o CC hw/nvram/eeprom93xx.o CC hw/nvram/fw_cfg.o CC hw/nvram/chrp_nvram.o CC hw/pci-bridge/pci_bridge_dev.o CC hw/pci-bridge/pci_expander_bridge.o CC hw/pci-bridge/xio3130_upstream.o CC hw/pci-bridge/xio3130_downstream.o CC hw/pci-bridge/ioh3420.o CC hw/pci-bridge/i82801b11.o CC hw/pci-host/pam.o CC hw/pci-host/versatile.o CC hw/pci-host/piix.o CC hw/pci-host/q35.o CC hw/pci-host/gpex.o CC hw/pci/pci.o CC hw/pci/pci_bridge.o CC hw/pci/msix.o CC hw/pci/msi.o CC hw/pci/shpc.o CC hw/pci/slotid_cap.o CC hw/pci/pci_host.o CC hw/pci/pcie_host.o CC hw/pci/pcie.o CC hw/pci/pcie_aer.o CC hw/pci/pcie_port.o CC hw/pci/pci-stub.o CC hw/pcmcia/pcmcia.o CC hw/scsi/scsi-disk.o CC hw/scsi/scsi-generic.o CC hw/scsi/scsi-bus.o CC hw/scsi/lsi53c895a.o CC hw/scsi/mptsas.o CC hw/scsi/mptconfig.o CC hw/scsi/mptendian.o CC hw/scsi/megasas.o CC hw/scsi/vmw_pvscsi.o CC hw/scsi/esp.o CC hw/scsi/esp-pci.o CC hw/sd/pl181.o CC hw/sd/ssi-sd.o CC hw/sd/sd.o CC hw/sd/core.o CC hw/sd/sdhci.o CC hw/smbios/smbios.o CC hw/smbios/smbios_type_38.o CC hw/ssi/pl022.o CC hw/ssi/ssi.o CC hw/ssi/xilinx_spips.o CC hw/ssi/aspeed_smc.o CC hw/ssi/stm32f2xx_spi.o CC hw/timer/arm_timer.o CC hw/timer/arm_mptimer.o CC hw/timer/a9gtimer.o CC hw/timer/ds1338.o CC hw/timer/cadence_ttc.o CC hw/timer/rx8900.o CC hw/timer/hpet.o CC hw/timer/i8254_common.o CC hw/timer/i8254.o CC hw/timer/pl031.o CC hw/timer/twl92230.o CC hw/timer/imx_epit.o CC hw/timer/imx_gpt.o CC hw/timer/stm32f2xx_timer.o CC hw/timer/aspeed_timer.o CC hw/tpm/tpm_tis.o CC hw/usb/core.o CC hw/usb/combined-packet.o CC hw/usb/bus.o CC hw/usb/libhw.o CC hw/usb/desc.o CC hw/usb/desc-msos.o CC hw/usb/hcd-uhci.o CC hw/usb/hcd-ohci.o CC hw/usb/hcd-ehci.o CC hw/usb/hcd-ehci-pci.o CC hw/usb/hcd-ehci-sysbus.o CC hw/usb/hcd-xhci.o CC hw/usb/hcd-musb.o CC hw/usb/dev-hub.o CC hw/usb/dev-hid.o CC hw/usb/dev-wacom.o CC hw/usb/dev-storage.o CC hw/usb/dev-uas.o CC hw/usb/dev-audio.o CC hw/usb/dev-serial.o CC hw/usb/dev-network.o CC hw/usb/dev-bluetooth.o CC hw/usb/dev-smartcard-reader.o CC hw/usb/host-stub.o CC hw/virtio/virtio-rng.o CC hw/virtio/virtio-pci.o CC hw/virtio/virtio-bus.o CC hw/virtio/virtio-mmio.o CC hw/watchdog/watchdog.o CC hw/watchdog/wdt_i6300esb.o CC hw/watchdog/wdt_ib700.o CC migration/migration.o CC migration/socket.o CC migration/fd.o CC migration/exec.o CC migration/tls.o CC migration/colo-comm.o CC migration/colo.o CC migration/colo-failover.o CC migration/vmstate.o CC migration/qemu-file.o CC migration/qemu-file-channel.o CC migration/xbzrle.o CC migration/postcopy-ram.o CC migration/qjson.o CC migration/block.o CC net/net.o CC net/queue.o CC net/checksum.o CC net/util.o CC net/hub.o CC net/socket.o CC net/dump.o CC net/eth.o CC net/tap-win32.o CC net/slirp.o CC net/filter.o CC net/filter-buffer.o CC net/filter-mirror.o CC net/colo-compare.o CC net/colo.o CC net/filter-rewriter.o CC qom/cpu.o CC replay/replay.o CC replay/replay-internal.o CC replay/replay-events.o CC replay/replay-time.o CC replay/replay-input.o CC replay/replay-char.o CC replay/replay-snapshot.o CC slirp/cksum.o CC slirp/if.o CC slirp/ip_icmp.o CC slirp/ip6_icmp.o CC slirp/ip6_input.o CC slirp/ip6_output.o CC slirp/ip_input.o CC slirp/ip_output.o CC slirp/dnssearch.o CC slirp/dhcpv6.o CC slirp/slirp.o CC slirp/mbuf.o CC slirp/misc.o CC slirp/sbuf.o CC slirp/socket.o CC slirp/tcp_input.o CC slirp/tcp_output.o CC slirp/tcp_subr.o CC slirp/tcp_timer.o CC slirp/udp.o CC slirp/udp6.o CC slirp/bootp.o CC slirp/arp_table.o CC slirp/tftp.o CC slirp/ndp_table.o CC ui/keymaps.o CC ui/console.o CC ui/cursor.o CC ui/qemu-pixman.o CC ui/input.o CC ui/input-keymap.o CC ui/input-legacy.o CC ui/sdl.o CC ui/sdl_zoom.o CC ui/x_keymap.o CC ui/vnc.o CC ui/vnc-enc-zlib.o CC ui/vnc-enc-hextile.o CC ui/vnc-enc-tight.o CC ui/vnc-palette.o CC ui/vnc-enc-zrle.o CC ui/vnc-auth-vencrypt.o CC ui/vnc-ws.o CC ui/vnc-jobs.o CC ui/gtk.o CC qga/commands.o CC qga/guest-agent-command-state.o CC qga/main.o CC qga/commands-win32.o CC qga/channel-win32.o CC qga/service-win32.o CC qga/vss-win32.o CC qga/qapi-generated/qga-qapi-types.o CC qga/qapi-generated/qga-qapi-visit.o CC qga/qapi-generated/qga-qmp-marshal.o CC qmp-introspect.o CC qapi-types.o CC qapi-visit.o CC qapi-event.o AR libqemustub.a CC qemu-img.o CC qmp-marshal.o CC trace/generated-tracers.o AR libqemuutil.a AS optionrom/multiboot.o AS optionrom/linuxboot.o CC optionrom/linuxboot_dma.o AS optionrom/kvmvapic.o BUILD optionrom/linuxboot_dma.img BUILD optionrom/linuxboot_dma.raw SIGN optionrom/linuxboot_dma.bin BUILD optionrom/multiboot.img BUILD optionrom/linuxboot.img BUILD optionrom/kvmvapic.img BUILD optionrom/multiboot.raw BUILD optionrom/linuxboot.raw BUILD optionrom/kvmvapic.raw SIGN optionrom/multiboot.bin SIGN optionrom/linuxboot.bin SIGN optionrom/kvmvapic.bin LINK qemu-ga.exe LINK qemu-img.exe LINK qemu-io.exe ^[[01m^[[K/tmp/qemu-test/src/hw/timer/rx8900.c:33:23:^[[m^[[K ^[[01;31m^[[Kfatal error: ^[[m^[[Kexecinfo.h: No such file or directory #include <execinfo.h> ^[[01;31m^[[K^^[[m^[[K compilation terminated. /tmp/qemu-test/src/rules.mak:60: recipe for target 'hw/timer/rx8900.o' failed make: *** [hw/timer/rx8900.o] Error 1 make: *** Waiting for unfinished jobs.... make[1]: *** [docker-run] Error 2 make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-ie51qv7a/src' make: *** [docker-run-test-mingw@fedora] Error 2 === OUTPUT END === Test command exited with code: 2 --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-devel@freelists.org ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2016-11-24 0:15 UTC | newest] Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-11-17 4:36 [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva 2016-11-17 4:36 ` [Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses Alastair D'Silva 2016-11-17 7:50 ` Cédric Le Goater 2016-11-17 4:36 ` [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts Alastair D'Silva 2016-11-22 17:22 ` Cédric Le Goater 2016-11-22 17:24 ` Paolo Bonzini 2016-11-22 22:31 ` Alastair D'Silva 2016-11-22 22:39 ` Paolo Bonzini 2016-11-22 23:19 ` Alastair D'Silva 2016-11-23 9:43 ` Paolo Bonzini 2016-11-23 10:05 ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias 2016-11-23 10:34 ` Paolo Bonzini 2016-11-17 4:36 ` [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva 2016-11-17 8:29 ` Cédric Le Goater 2016-11-18 0:19 ` Alastair D'Silva 2016-11-18 8:52 ` Cédric Le Goater 2016-11-17 4:36 ` [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board Alastair D'Silva 2016-11-22 16:56 ` Cédric Le Goater 2016-11-23 0:46 ` Alastair D'Silva 2016-11-23 8:48 ` Cédric Le Goater 2016-11-24 0:15 ` Andrew Jeffery 2016-11-17 15:33 ` [Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board no-reply
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