* [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters
@ 2022-03-28 15:49 kan.liang
2022-03-28 15:49 ` [PATCH] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids kan.liang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: kan.liang @ 2022-03-28 15:49 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: eranian, Kan Liang, stable
From: Kan Liang <kan.liang@linux.intel.com>
The INST_RETIRED.PREC_DIST event (0x0100) doesn't count on SPR.
perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
Performance counter stats for 'CPU(s) 0':
607,246 cpu/event=0xc0,umask=0x0/
0 cpu/event=0x0,umask=0x1/
The encoding for INST_RETIRED.PREC_DIST is pseudo-encoding, which
doesn't work on the generic counters. However, current perf extends its
mask to the generic counters.
The pseudo event-code for a fixed counter must be 0x00. Check and avoid
extending the mask for the fixed counter event which using the
pseudo-encoding, e.g., ref-cycles and PREC_DIST event.
With the patch,
perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
Performance counter stats for 'CPU(s) 0':
583,184 cpu/event=0xc0,umask=0x0/
583,048 cpu/event=0x0,umask=0x1/
Fixes: 2de71ee153ef ("perf/x86/intel: Fix ICL/SPR INST_RETIRED.PREC_DIST encodings")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
---
arch/x86/events/intel/core.c | 6 +++++-
arch/x86/include/asm/perf_event.h | 5 +++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index db32ef6..1d2e49d 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5668,7 +5668,11 @@ static void intel_pmu_check_event_constraints(struct event_constraint *event_con
/* Disabled fixed counters which are not in CPUID */
c->idxmsk64 &= intel_ctrl;
- if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
+ /*
+ * Don't extend the pseudo-encoding to the
+ * generic counters
+ */
+ if (!use_fixed_pseudo_encoding(c->code))
c->idxmsk64 |= (1ULL << num_counters) - 1;
}
c->idxmsk64 &=
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 48e6ef56..cd85f03 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -242,6 +242,11 @@ struct x86_pmu_capability {
#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
+static inline bool use_fixed_pseudo_encoding(u64 code)
+{
+ return !(code & 0xff);
+}
+
/*
* We model BTS tracing as another fixed-mode PMC.
*
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
2022-03-28 15:49 [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters kan.liang
@ 2022-03-28 15:49 ` kan.liang
2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2022-03-28 17:11 ` [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters Stephane Eranian
2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2 siblings, 1 reply; 6+ messages in thread
From: kan.liang @ 2022-03-28 15:49 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: eranian, Kan Liang, stable
From: Kan Liang <kan.liang@linux.intel.com>
On Sapphire Rapids, the FRONTEND_RETIRED.MS_FLOWS event requires the
FRONTEND MSR value 0x8. However, the current FRONTEND MSR mask doesn't
support it.
Update intel_spr_extra_regs[] to support it.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
---
arch/x86/events/intel/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 696d036..db32ef6 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -282,7 +282,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
- INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
+ INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
EVENT_EXTRA_END
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters
2022-03-28 15:49 [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters kan.liang
2022-03-28 15:49 ` [PATCH] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids kan.liang
@ 2022-03-28 17:11 ` Stephane Eranian
2022-03-28 18:30 ` Liang, Kan
2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2 siblings, 1 reply; 6+ messages in thread
From: Stephane Eranian @ 2022-03-28 17:11 UTC (permalink / raw)
To: kan.liang; +Cc: peterz, mingo, linux-kernel, stable
On Mon, Mar 28, 2022 at 8:50 AM <kan.liang@linux.intel.com> wrote:
>
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The INST_RETIRED.PREC_DIST event (0x0100) doesn't count on SPR.
> perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
>
> Performance counter stats for 'CPU(s) 0':
>
> 607,246 cpu/event=0xc0,umask=0x0/
> 0 cpu/event=0x0,umask=0x1/
>
> The encoding for INST_RETIRED.PREC_DIST is pseudo-encoding, which
> doesn't work on the generic counters. However, current perf extends its
> mask to the generic counters.
>
> The pseudo event-code for a fixed counter must be 0x00. Check and avoid
> extending the mask for the fixed counter event which using the
> pseudo-encoding, e.g., ref-cycles and PREC_DIST event.
>
> With the patch,
> perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
>
> Performance counter stats for 'CPU(s) 0':
>
> 583,184 cpu/event=0xc0,umask=0x0/
> 583,048 cpu/event=0x0,umask=0x1/
>
> Fixes: 2de71ee153ef ("perf/x86/intel: Fix ICL/SPR INST_RETIRED.PREC_DIST encodings")
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> Cc: stable@vger.kernel.org
> ---
> arch/x86/events/intel/core.c | 6 +++++-
> arch/x86/include/asm/perf_event.h | 5 +++++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index db32ef6..1d2e49d 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -5668,7 +5668,11 @@ static void intel_pmu_check_event_constraints(struct event_constraint *event_con
> /* Disabled fixed counters which are not in CPUID */
> c->idxmsk64 &= intel_ctrl;
>
> - if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
> + /*
> + * Don't extend the pseudo-encoding to the
> + * generic counters
> + */
> + if (!use_fixed_pseudo_encoding(c->code))
> c->idxmsk64 |= (1ULL << num_counters) - 1;
> }
> c->idxmsk64 &=
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 48e6ef56..cd85f03 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -242,6 +242,11 @@ struct x86_pmu_capability {
> #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
> #define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
>
> +static inline bool use_fixed_pseudo_encoding(u64 code)
> +{
> + return !(code & 0xff);
> +}
> +
I ack the problem.
That does not take into account the old encoding for PREC_DIST 0x01c0
which is also forced to
fixed counter0 on ICL and should not be extended.
That also limits the options for the SLOTS events which can be
measured by a GP. Yet to work
with PERF_METRICS, it has to be programmed into fixed counter 3.
> /*
> * We model BTS tracing as another fixed-mode PMC.
> *
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters
2022-03-28 17:11 ` [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters Stephane Eranian
@ 2022-03-28 18:30 ` Liang, Kan
0 siblings, 0 replies; 6+ messages in thread
From: Liang, Kan @ 2022-03-28 18:30 UTC (permalink / raw)
To: Stephane Eranian; +Cc: peterz, mingo, linux-kernel, stable
On 3/28/2022 1:11 PM, Stephane Eranian wrote:
> On Mon, Mar 28, 2022 at 8:50 AM <kan.liang@linux.intel.com> wrote:
>>
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> The INST_RETIRED.PREC_DIST event (0x0100) doesn't count on SPR.
>> perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
>>
>> Performance counter stats for 'CPU(s) 0':
>>
>> 607,246 cpu/event=0xc0,umask=0x0/
>> 0 cpu/event=0x0,umask=0x1/
>>
>> The encoding for INST_RETIRED.PREC_DIST is pseudo-encoding, which
>> doesn't work on the generic counters. However, current perf extends its
>> mask to the generic counters.
>>
>> The pseudo event-code for a fixed counter must be 0x00. Check and avoid
>> extending the mask for the fixed counter event which using the
>> pseudo-encoding, e.g., ref-cycles and PREC_DIST event.
>>
>> With the patch,
>> perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
>>
>> Performance counter stats for 'CPU(s) 0':
>>
>> 583,184 cpu/event=0xc0,umask=0x0/
>> 583,048 cpu/event=0x0,umask=0x1/
>>
>> Fixes: 2de71ee153ef ("perf/x86/intel: Fix ICL/SPR INST_RETIRED.PREC_DIST encodings")
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> Cc: stable@vger.kernel.org
>> ---
>> arch/x86/events/intel/core.c | 6 +++++-
>> arch/x86/include/asm/perf_event.h | 5 +++++
>> 2 files changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index db32ef6..1d2e49d 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -5668,7 +5668,11 @@ static void intel_pmu_check_event_constraints(struct event_constraint *event_con
>> /* Disabled fixed counters which are not in CPUID */
>> c->idxmsk64 &= intel_ctrl;
>>
>> - if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
>> + /*
>> + * Don't extend the pseudo-encoding to the
>> + * generic counters
>> + */
>> + if (!use_fixed_pseudo_encoding(c->code))
>> c->idxmsk64 |= (1ULL << num_counters) - 1;
>> }
>> c->idxmsk64 &=
>> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
>> index 48e6ef56..cd85f03 100644
>> --- a/arch/x86/include/asm/perf_event.h
>> +++ b/arch/x86/include/asm/perf_event.h
>> @@ -242,6 +242,11 @@ struct x86_pmu_capability {
>> #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
>> #define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
>>
>> +static inline bool use_fixed_pseudo_encoding(u64 code)
>> +{
>> + return !(code & 0xff);
>> +}
>> +
> I ack the problem.
>
> That does not take into account the old encoding for PREC_DIST 0x01c0
> which is also forced to
> fixed counter0 on ICL and should not be extended.
The old encoding is not documented in the ICL event list now. The only
PREC_DIST event for ICL is using the pseudo encoding.
{
"EventCode": "0x00",
"UMask": "0x01",
"EventName": "INST_RETIRED.PREC_DIST",
"BriefDescription": "Precise instruction retired event with a
reduced effect of PEBS shadow in IP distribution",
"PublicDescription": "A version of INST_RETIRED that allows for a
more unbiased distribution of samples across instructions retired. It
utilizes the Precise Distribution of Instructions Retired (PDIR) feature
to mitigate some bias in how retired instructions get sampled. Use on
Fixed Counter 0.",
"Counter": "Fixed counter 0",
Ideally, I think we should remove the old encoding 0x01c0 from the
constraints table rather than force it to fixed counter 0 only.
If so, that should be a separate patch.
>
> That also limits the options for the SLOTS events which can be
> measured by a GP. Yet to work
> with PERF_METRICS, it has to be programmed into fixed counter 3.
For the SLOTS event which can only work with PERF_METRICS, the current
perf already limit it as below.
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
No behavior is changed with this patch.
For the GP version of SLOTS, it's 0x01a4. According to the event list,
it can be scheduled on all GP counters. So it's not added into the
constraints table.
"EventCode": "0xa4",
"UMask": "0x01",
"EventName": "TOPDOWN.SLOTS_P",
"BriefDescription": "TMA slots available for an unhalted logical
processor. General counter - architectural event",
"PublicDescription": "Counts the number of available slots for an
unhalted logical processor. The event increments by machine-width of the
narrowest pipeline as employed by the Top-down Microarchitecture
Analysis method. The count is distributed among unhalted logical
processors (hyper-threads) who share the same physical core.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
Even we finally decide to extend the 0x01a4 to the fixed counter 3 and
add an entry FIXED_EVENT_CONSTRAINT(0x01a4, 3) in the constraints table.
This patch doesn't limit it.
Thanks,
Kan
>
>> /*
>> * We model BTS tracing as another fixed-mode PMC.
>> *
>> --
>> 2.7.4
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip: perf/urgent] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
2022-03-28 15:49 ` [PATCH] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids kan.liang
@ 2022-04-05 8:29 ` tip-bot2 for Kan Liang
0 siblings, 0 replies; 6+ messages in thread
From: tip-bot2 for Kan Liang @ 2022-04-05 8:29 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel), stable, x86, linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: e590928de7547454469693da9bc7ffd562e54b7e
Gitweb: https://git.kernel.org/tip/e590928de7547454469693da9bc7ffd562e54b7e
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Mon, 28 Mar 2022 08:49:03 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 05 Apr 2022 09:59:44 +02:00
perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
On Sapphire Rapids, the FRONTEND_RETIRED.MS_FLOWS event requires the
FRONTEND MSR value 0x8. However, the current FRONTEND MSR mask doesn't
support it.
Update intel_spr_extra_regs[] to support it.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1648482543-14923-2-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/intel/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index eb17b96..fc7f458 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -302,7 +302,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
- INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
+ INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
EVENT_EXTRA_END
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [tip: perf/urgent] perf/x86/intel: Don't extend the pseudo-encoding to GP counters
2022-03-28 15:49 [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters kan.liang
2022-03-28 15:49 ` [PATCH] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids kan.liang
2022-03-28 17:11 ` [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters Stephane Eranian
@ 2022-04-05 8:29 ` tip-bot2 for Kan Liang
2 siblings, 0 replies; 6+ messages in thread
From: tip-bot2 for Kan Liang @ 2022-04-05 8:29 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel), stable, x86, linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 4a263bf331c512849062805ef1b4ac40301a9829
Gitweb: https://git.kernel.org/tip/4a263bf331c512849062805ef1b4ac40301a9829
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Mon, 28 Mar 2022 08:49:02 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 05 Apr 2022 09:59:44 +02:00
perf/x86/intel: Don't extend the pseudo-encoding to GP counters
The INST_RETIRED.PREC_DIST event (0x0100) doesn't count on SPR.
perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
Performance counter stats for 'CPU(s) 0':
607,246 cpu/event=0xc0,umask=0x0/
0 cpu/event=0x0,umask=0x1/
The encoding for INST_RETIRED.PREC_DIST is pseudo-encoding, which
doesn't work on the generic counters. However, current perf extends its
mask to the generic counters.
The pseudo event-code for a fixed counter must be 0x00. Check and avoid
extending the mask for the fixed counter event which using the
pseudo-encoding, e.g., ref-cycles and PREC_DIST event.
With the patch,
perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
Performance counter stats for 'CPU(s) 0':
583,184 cpu/event=0xc0,umask=0x0/
583,048 cpu/event=0x0,umask=0x1/
Fixes: 2de71ee153ef ("perf/x86/intel: Fix ICL/SPR INST_RETIRED.PREC_DIST encodings")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/1648482543-14923-1-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/intel/core.c | 6 +++++-
arch/x86/include/asm/perf_event.h | 5 +++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 28f075e..eb17b96 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5536,7 +5536,11 @@ static void intel_pmu_check_event_constraints(struct event_constraint *event_con
/* Disabled fixed counters which are not in CPUID */
c->idxmsk64 &= intel_ctrl;
- if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
+ /*
+ * Don't extend the pseudo-encoding to the
+ * generic counters
+ */
+ if (!use_fixed_pseudo_encoding(c->code))
c->idxmsk64 |= (1ULL << num_counters) - 1;
}
c->idxmsk64 &=
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 58d9e4b..b06e4c5 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -241,6 +241,11 @@ struct x86_pmu_capability {
#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
+static inline bool use_fixed_pseudo_encoding(u64 code)
+{
+ return !(code & 0xff);
+}
+
/*
* We model BTS tracing as another fixed-mode PMC.
*
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-05 10:50 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-28 15:49 [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters kan.liang
2022-03-28 15:49 ` [PATCH] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids kan.liang
2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2022-03-28 17:11 ` [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters Stephane Eranian
2022-03-28 18:30 ` Liang, Kan
2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.