* [PATCH v12 0/4] Add mmsys and mutex support for MDP
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Change since V11:
- Rebase on v5.17-rc6.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=5f9b5b757e44de47ebdc116c14b90e3cc8bc7acb
[2]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24
[3]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=15f1768365aed810826a61fef4a744437aa5b426
Change since v10:
- For some ISP application scenarios, such as preview and recording
at the same time.
The routing table needs to be discarded, and the calculation result
on the SCP side is used to write a suitable mux setting for
1 input and 2 output.
- Adjust the GCE client register parsing method to avoid redundant warning logs.
Change since v9:
- Add API for MDP getting mutex mod.
Hi,
This patch splits mmsys and mutex settings from Media Data Path 3 (MDP3),
and original mailling list list below:
https://patchwork.kernel.org/project/linux-mediatek/cover/20211201095031.31606-1-moudy.ho@mediatek.com/
Corresponding settings and interfaces are added for MDP operation in the
mmsys and mutex drivers, which increases the independence of the modules
Moudy Ho (4):
soc: mediatek: mmsys: add CMDQ write register function
soc: mediatek: mmsys: add support for ISP control
soc: mediatek: mutex: add support for MDP
soc: mediatek: mutex: add functions that operate registers by CMDQ
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mt8183-mmsys.h | 26 +++++
drivers/soc/mediatek/mtk-mmsys.c | 145 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 2 +
drivers/soc/mediatek/mtk-mutex.c | 140 +++++++++++++++++++++++-
include/linux/soc/mediatek/mtk-mmsys.h | 80 ++++++++++++++
include/linux/soc/mediatek/mtk-mutex.h | 9 ++
7 files changed, 401 insertions(+), 2 deletions(-)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v12 0/4] Add mmsys and mutex support for MDP
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Change since V11:
- Rebase on v5.17-rc6.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=5f9b5b757e44de47ebdc116c14b90e3cc8bc7acb
[2]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24
[3]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=15f1768365aed810826a61fef4a744437aa5b426
Change since v10:
- For some ISP application scenarios, such as preview and recording
at the same time.
The routing table needs to be discarded, and the calculation result
on the SCP side is used to write a suitable mux setting for
1 input and 2 output.
- Adjust the GCE client register parsing method to avoid redundant warning logs.
Change since v9:
- Add API for MDP getting mutex mod.
Hi,
This patch splits mmsys and mutex settings from Media Data Path 3 (MDP3),
and original mailling list list below:
https://patchwork.kernel.org/project/linux-mediatek/cover/20211201095031.31606-1-moudy.ho@mediatek.com/
Corresponding settings and interfaces are added for MDP operation in the
mmsys and mutex drivers, which increases the independence of the modules
Moudy Ho (4):
soc: mediatek: mmsys: add CMDQ write register function
soc: mediatek: mmsys: add support for ISP control
soc: mediatek: mutex: add support for MDP
soc: mediatek: mutex: add functions that operate registers by CMDQ
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mt8183-mmsys.h | 26 +++++
drivers/soc/mediatek/mtk-mmsys.c | 145 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 2 +
drivers/soc/mediatek/mtk-mutex.c | 140 +++++++++++++++++++++++-
include/linux/soc/mediatek/mtk-mmsys.h | 80 ++++++++++++++
include/linux/soc/mediatek/mtk-mutex.h | 9 ++
7 files changed, 401 insertions(+), 2 deletions(-)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
2022-03-01 10:02 ` Moudy Ho
(?)
@ 2022-03-01 10:02 ` Moudy Ho
-1 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Adding the interface of writing MMSYS register via CMDQ,
users do not need to parse related dts information.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 50 ++++++++++++++++++++++++++
4 files changed, 82 insertions(+)
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..172bc7828aca 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -69,6 +69,7 @@ config MTK_MMSYS
bool "MediaTek MMSYS Support"
default ARCH_MEDIATEK
depends on HAS_IOMEM
+ select MTK_CMDQ
help
Say yes here to add support for the MediaTek Multimedia
Subsystem (MMSYS).
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 50c797d70ddd..04c0c7de395e 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -8,9 +8,11 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
@@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .has_gce_client_reg = true,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -81,6 +84,8 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ struct cmdq_client_reg cmdq_base;
+ phys_addr_t addr;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 offset, u32 value, u32 mask)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
+ mmsys->addr + offset, value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
@@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
+ struct resource res;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ if (of_address_to_resource(dev->of_node, 0, &res) < 0)
+ mmsys->addr = 0L;
+ else
+ mmsys->addr = res.start;
+
+ if (mmsys->data->has_gce_client_reg) {
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret) {
+ dev_err(dev, "No mediatek,gce-client-reg!\n");
+ return ret;
+ }
+ }
+
mmsys->data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, mmsys);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..9fce400507d2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ bool has_gce_client_reg;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..7f8ecc98d023 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -7,8 +7,14 @@
#define __MTK_MMSYS_H
enum mtk_ddp_comp_id;
+enum mtk_mdp_comp_id;
struct device;
+struct mmsys_cmdq_cmd {
+ struct cmdq_pkt *pkt;
+ s32 *event;
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
@@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mdp_comp_id {
+ MDP_COMP_NONE = -1, /* Invalid engine */
+
+ /* ISP */
+ MDP_COMP_WPEI = 0,
+ MDP_COMP_WPEO, /* 1 */
+ MDP_COMP_WPEI2, /* 2 */
+ MDP_COMP_WPEO2, /* 3 */
+ MDP_COMP_ISP_IMGI, /* 4 */
+ MDP_COMP_ISP_IMGO, /* 5 */
+ MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MDP_COMP_IPUI, /* 7 */
+ MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MDP_COMP_CAMIN, /* 9 */
+ MDP_COMP_CAMIN2, /* 10 */
+ MDP_COMP_RDMA0, /* 11 */
+ MDP_COMP_AAL0, /* 12 */
+ MDP_COMP_CCORR0, /* 13 */
+ MDP_COMP_RSZ0, /* 14 */
+ MDP_COMP_RSZ1, /* 15 */
+ MDP_COMP_TDSHP0, /* 16 */
+ MDP_COMP_COLOR0, /* 17 */
+ MDP_COMP_PATH0_SOUT, /* 18 */
+ MDP_COMP_PATH1_SOUT, /* 19 */
+ MDP_COMP_WROT0, /* 20 */
+ MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MDP_COMP_RDMA1, /* 22 */
+ MDP_COMP_RSZ2, /* 23 */
+ MDP_COMP_TDSHP1, /* 24 */
+ MDP_COMP_WROT1, /* 25 */
+
+ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Adding the interface of writing MMSYS register via CMDQ,
users do not need to parse related dts information.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 50 ++++++++++++++++++++++++++
4 files changed, 82 insertions(+)
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..172bc7828aca 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -69,6 +69,7 @@ config MTK_MMSYS
bool "MediaTek MMSYS Support"
default ARCH_MEDIATEK
depends on HAS_IOMEM
+ select MTK_CMDQ
help
Say yes here to add support for the MediaTek Multimedia
Subsystem (MMSYS).
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 50c797d70ddd..04c0c7de395e 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -8,9 +8,11 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
@@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .has_gce_client_reg = true,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -81,6 +84,8 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ struct cmdq_client_reg cmdq_base;
+ phys_addr_t addr;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 offset, u32 value, u32 mask)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
+ mmsys->addr + offset, value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
@@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
+ struct resource res;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ if (of_address_to_resource(dev->of_node, 0, &res) < 0)
+ mmsys->addr = 0L;
+ else
+ mmsys->addr = res.start;
+
+ if (mmsys->data->has_gce_client_reg) {
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret) {
+ dev_err(dev, "No mediatek,gce-client-reg!\n");
+ return ret;
+ }
+ }
+
mmsys->data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, mmsys);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..9fce400507d2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ bool has_gce_client_reg;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..7f8ecc98d023 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -7,8 +7,14 @@
#define __MTK_MMSYS_H
enum mtk_ddp_comp_id;
+enum mtk_mdp_comp_id;
struct device;
+struct mmsys_cmdq_cmd {
+ struct cmdq_pkt *pkt;
+ s32 *event;
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
@@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mdp_comp_id {
+ MDP_COMP_NONE = -1, /* Invalid engine */
+
+ /* ISP */
+ MDP_COMP_WPEI = 0,
+ MDP_COMP_WPEO, /* 1 */
+ MDP_COMP_WPEI2, /* 2 */
+ MDP_COMP_WPEO2, /* 3 */
+ MDP_COMP_ISP_IMGI, /* 4 */
+ MDP_COMP_ISP_IMGO, /* 5 */
+ MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MDP_COMP_IPUI, /* 7 */
+ MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MDP_COMP_CAMIN, /* 9 */
+ MDP_COMP_CAMIN2, /* 10 */
+ MDP_COMP_RDMA0, /* 11 */
+ MDP_COMP_AAL0, /* 12 */
+ MDP_COMP_CCORR0, /* 13 */
+ MDP_COMP_RSZ0, /* 14 */
+ MDP_COMP_RSZ1, /* 15 */
+ MDP_COMP_TDSHP0, /* 16 */
+ MDP_COMP_COLOR0, /* 17 */
+ MDP_COMP_PATH0_SOUT, /* 18 */
+ MDP_COMP_PATH1_SOUT, /* 19 */
+ MDP_COMP_WROT0, /* 20 */
+ MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MDP_COMP_RDMA1, /* 22 */
+ MDP_COMP_RSZ2, /* 23 */
+ MDP_COMP_TDSHP1, /* 24 */
+ MDP_COMP_WROT1, /* 25 */
+
+ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Adding the interface of writing MMSYS register via CMDQ,
users do not need to parse related dts information.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 50 ++++++++++++++++++++++++++
4 files changed, 82 insertions(+)
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..172bc7828aca 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -69,6 +69,7 @@ config MTK_MMSYS
bool "MediaTek MMSYS Support"
default ARCH_MEDIATEK
depends on HAS_IOMEM
+ select MTK_CMDQ
help
Say yes here to add support for the MediaTek Multimedia
Subsystem (MMSYS).
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 50c797d70ddd..04c0c7de395e 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -8,9 +8,11 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
@@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .has_gce_client_reg = true,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -81,6 +84,8 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ struct cmdq_client_reg cmdq_base;
+ phys_addr_t addr;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 offset, u32 value, u32 mask)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
+ mmsys->addr + offset, value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
@@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
+ struct resource res;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ if (of_address_to_resource(dev->of_node, 0, &res) < 0)
+ mmsys->addr = 0L;
+ else
+ mmsys->addr = res.start;
+
+ if (mmsys->data->has_gce_client_reg) {
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret) {
+ dev_err(dev, "No mediatek,gce-client-reg!\n");
+ return ret;
+ }
+ }
+
mmsys->data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, mmsys);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..9fce400507d2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ bool has_gce_client_reg;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..7f8ecc98d023 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -7,8 +7,14 @@
#define __MTK_MMSYS_H
enum mtk_ddp_comp_id;
+enum mtk_mdp_comp_id;
struct device;
+struct mmsys_cmdq_cmd {
+ struct cmdq_pkt *pkt;
+ s32 *event;
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
@@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mdp_comp_id {
+ MDP_COMP_NONE = -1, /* Invalid engine */
+
+ /* ISP */
+ MDP_COMP_WPEI = 0,
+ MDP_COMP_WPEO, /* 1 */
+ MDP_COMP_WPEI2, /* 2 */
+ MDP_COMP_WPEO2, /* 3 */
+ MDP_COMP_ISP_IMGI, /* 4 */
+ MDP_COMP_ISP_IMGO, /* 5 */
+ MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MDP_COMP_IPUI, /* 7 */
+ MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MDP_COMP_CAMIN, /* 9 */
+ MDP_COMP_CAMIN2, /* 10 */
+ MDP_COMP_RDMA0, /* 11 */
+ MDP_COMP_AAL0, /* 12 */
+ MDP_COMP_CCORR0, /* 13 */
+ MDP_COMP_RSZ0, /* 14 */
+ MDP_COMP_RSZ1, /* 15 */
+ MDP_COMP_TDSHP0, /* 16 */
+ MDP_COMP_COLOR0, /* 17 */
+ MDP_COMP_PATH0_SOUT, /* 18 */
+ MDP_COMP_PATH1_SOUT, /* 19 */
+ MDP_COMP_WROT0, /* 20 */
+ MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MDP_COMP_RDMA1, /* 22 */
+ MDP_COMP_RSZ2, /* 23 */
+ MDP_COMP_TDSHP1, /* 24 */
+ MDP_COMP_WROT1, /* 25 */
+
+ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
2022-03-01 10:02 ` Moudy Ho
@ 2022-03-01 10:06 ` moudy.ho
-1 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-01 10:06 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
We have proposed some support for MDP in mmsys and mutex.
Is there any chance that you can give us some suggestions?
We also need your approvement if this series is acceptable.
Also, if the patch is not proper for you, please let us know.
Thanks for your help.
Thanks,
Moudy Ho
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> Adding the interface of writing MMSYS register via CMDQ,
> users do not need to parse related dts information.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/Kconfig | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 50
> ++++++++++++++++++++++++++
> 4 files changed, 82 insertions(+)
>
> diff --git a/drivers/soc/mediatek/Kconfig
> b/drivers/soc/mediatek/Kconfig
> index fdd8bc08569e..172bc7828aca 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -69,6 +69,7 @@ config MTK_MMSYS
> bool "MediaTek MMSYS Support"
> default ARCH_MEDIATEK
> depends on HAS_IOMEM
> + select MTK_CMDQ
> help
> Say yes here to add support for the MediaTek Multimedia
> Subsystem (MMSYS).
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 50c797d70ddd..04c0c7de395e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -8,9 +8,11 @@
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> @@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .has_gce_client_reg = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =
> {
> @@ -81,6 +84,8 @@ struct mtk_mmsys {
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + struct cmdq_client_reg cmdq_base;
> + phys_addr_t addr;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 offset, u32 value, u32 mask)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> + mmsys->addr + offset, value, mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> +
> static int mtk_mmsys_reset_update(struct reset_controller_dev
> *rcdev, unsigned long id,
> bool assert)
> {
> @@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> struct platform_device *clks;
> struct platform_device *drm;
> struct mtk_mmsys *mmsys;
> + struct resource res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> return ret;
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> + mmsys->addr = 0L;
> + else
> + mmsys->addr = res.start;
> +
> + if (mmsys->data->has_gce_client_reg) {
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base,
> 0);
> + if (ret) {
> + dev_err(dev, "No mediatek,gce-client-reg!\n");
> + return ret;
> + }
> + }
> +
> mmsys->data = of_device_get_match_data(&pdev->dev);
> platform_set_drvdata(pdev, mmsys);
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..9fce400507d2 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + bool has_gce_client_reg;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..7f8ecc98d023 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -7,8 +7,14 @@
> #define __MTK_MMSYS_H
>
> enum mtk_ddp_comp_id;
> +enum mtk_mdp_comp_id;
> struct device;
>
> +struct mmsys_cmdq_cmd {
> + struct cmdq_pkt *pkt;
> + s32 *event;
> +};
> +
> enum mtk_ddp_comp_id {
> DDP_COMPONENT_AAL0,
> DDP_COMPONENT_AAL1,
> @@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mdp_comp_id {
> + MDP_COMP_NONE = -1, /* Invalid engine */
> +
> + /* ISP */
> + MDP_COMP_WPEI = 0,
> + MDP_COMP_WPEO, /* 1 */
> + MDP_COMP_WPEI2, /* 2 */
> + MDP_COMP_WPEO2, /* 3 */
> + MDP_COMP_ISP_IMGI, /* 4 */
> + MDP_COMP_ISP_IMGO, /* 5 */
> + MDP_COMP_ISP_IMG2O, /* 6 */
> +
> + /* IPU */
> + MDP_COMP_IPUI, /* 7 */
> + MDP_COMP_IPUO, /* 8 */
> +
> + /* MDP */
> + MDP_COMP_CAMIN, /* 9 */
> + MDP_COMP_CAMIN2, /* 10 */
> + MDP_COMP_RDMA0, /* 11 */
> + MDP_COMP_AAL0, /* 12 */
> + MDP_COMP_CCORR0, /* 13 */
> + MDP_COMP_RSZ0, /* 14 */
> + MDP_COMP_RSZ1, /* 15 */
> + MDP_COMP_TDSHP0, /* 16 */
> + MDP_COMP_COLOR0, /* 17 */
> + MDP_COMP_PATH0_SOUT, /* 18 */
> + MDP_COMP_PATH1_SOUT, /* 19 */
> + MDP_COMP_WROT0, /* 20 */
> + MDP_COMP_WDMA, /* 21 */
> +
> + /* Dummy Engine */
> + MDP_COMP_RDMA1, /* 22 */
> + MDP_COMP_RSZ2, /* 23 */
> + MDP_COMP_TDSHP1, /* 24 */
> + MDP_COMP_WROT1, /* 25 */
> +
> + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask);
> +
> #endif /* __MTK_MMSYS_H */
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
@ 2022-03-01 10:06 ` moudy.ho
0 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-01 10:06 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
We have proposed some support for MDP in mmsys and mutex.
Is there any chance that you can give us some suggestions?
We also need your approvement if this series is acceptable.
Also, if the patch is not proper for you, please let us know.
Thanks for your help.
Thanks,
Moudy Ho
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> Adding the interface of writing MMSYS register via CMDQ,
> users do not need to parse related dts information.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/Kconfig | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 50
> ++++++++++++++++++++++++++
> 4 files changed, 82 insertions(+)
>
> diff --git a/drivers/soc/mediatek/Kconfig
> b/drivers/soc/mediatek/Kconfig
> index fdd8bc08569e..172bc7828aca 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -69,6 +69,7 @@ config MTK_MMSYS
> bool "MediaTek MMSYS Support"
> default ARCH_MEDIATEK
> depends on HAS_IOMEM
> + select MTK_CMDQ
> help
> Say yes here to add support for the MediaTek Multimedia
> Subsystem (MMSYS).
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 50c797d70ddd..04c0c7de395e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -8,9 +8,11 @@
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> @@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .has_gce_client_reg = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =
> {
> @@ -81,6 +84,8 @@ struct mtk_mmsys {
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + struct cmdq_client_reg cmdq_base;
> + phys_addr_t addr;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 offset, u32 value, u32 mask)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> + mmsys->addr + offset, value, mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> +
> static int mtk_mmsys_reset_update(struct reset_controller_dev
> *rcdev, unsigned long id,
> bool assert)
> {
> @@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> struct platform_device *clks;
> struct platform_device *drm;
> struct mtk_mmsys *mmsys;
> + struct resource res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> return ret;
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> + mmsys->addr = 0L;
> + else
> + mmsys->addr = res.start;
> +
> + if (mmsys->data->has_gce_client_reg) {
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base,
> 0);
> + if (ret) {
> + dev_err(dev, "No mediatek,gce-client-reg!\n");
> + return ret;
> + }
> + }
> +
> mmsys->data = of_device_get_match_data(&pdev->dev);
> platform_set_drvdata(pdev, mmsys);
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..9fce400507d2 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + bool has_gce_client_reg;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..7f8ecc98d023 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -7,8 +7,14 @@
> #define __MTK_MMSYS_H
>
> enum mtk_ddp_comp_id;
> +enum mtk_mdp_comp_id;
> struct device;
>
> +struct mmsys_cmdq_cmd {
> + struct cmdq_pkt *pkt;
> + s32 *event;
> +};
> +
> enum mtk_ddp_comp_id {
> DDP_COMPONENT_AAL0,
> DDP_COMPONENT_AAL1,
> @@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mdp_comp_id {
> + MDP_COMP_NONE = -1, /* Invalid engine */
> +
> + /* ISP */
> + MDP_COMP_WPEI = 0,
> + MDP_COMP_WPEO, /* 1 */
> + MDP_COMP_WPEI2, /* 2 */
> + MDP_COMP_WPEO2, /* 3 */
> + MDP_COMP_ISP_IMGI, /* 4 */
> + MDP_COMP_ISP_IMGO, /* 5 */
> + MDP_COMP_ISP_IMG2O, /* 6 */
> +
> + /* IPU */
> + MDP_COMP_IPUI, /* 7 */
> + MDP_COMP_IPUO, /* 8 */
> +
> + /* MDP */
> + MDP_COMP_CAMIN, /* 9 */
> + MDP_COMP_CAMIN2, /* 10 */
> + MDP_COMP_RDMA0, /* 11 */
> + MDP_COMP_AAL0, /* 12 */
> + MDP_COMP_CCORR0, /* 13 */
> + MDP_COMP_RSZ0, /* 14 */
> + MDP_COMP_RSZ1, /* 15 */
> + MDP_COMP_TDSHP0, /* 16 */
> + MDP_COMP_COLOR0, /* 17 */
> + MDP_COMP_PATH0_SOUT, /* 18 */
> + MDP_COMP_PATH1_SOUT, /* 19 */
> + MDP_COMP_WROT0, /* 20 */
> + MDP_COMP_WDMA, /* 21 */
> +
> + /* Dummy Engine */
> + MDP_COMP_RDMA1, /* 22 */
> + MDP_COMP_RSZ2, /* 23 */
> + MDP_COMP_TDSHP1, /* 24 */
> + MDP_COMP_WROT1, /* 25 */
> +
> + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask);
> +
> #endif /* __MTK_MMSYS_H */
_______________________________________________
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
2022-03-01 10:02 ` Moudy Ho
@ 2022-03-03 7:59 ` CK Hu
-1 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 7:59 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> Adding the interface of writing MMSYS register via CMDQ,
> users do not need to parse related dts information.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/Kconfig | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 50
> ++++++++++++++++++++++++++
> 4 files changed, 82 insertions(+)
>
> diff --git a/drivers/soc/mediatek/Kconfig
> b/drivers/soc/mediatek/Kconfig
> index fdd8bc08569e..172bc7828aca 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -69,6 +69,7 @@ config MTK_MMSYS
> bool "MediaTek MMSYS Support"
> default ARCH_MEDIATEK
> depends on HAS_IOMEM
> + select MTK_CMDQ
In MT8173, mmsys could work without CMDQ, so I think mmsys should not
select CMDQ.
> help
> Say yes here to add support for the MediaTek Multimedia
> Subsystem (MMSYS).
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 50c797d70ddd..04c0c7de395e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -8,9 +8,11 @@
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> @@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .has_gce_client_reg = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =
> {
> @@ -81,6 +84,8 @@ struct mtk_mmsys {
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + struct cmdq_client_reg cmdq_base;
> + phys_addr_t addr;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 offset, u32 value, u32 mask)
I would like mmsys provide high level interface rather than such low
level interface.
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> + mmsys->addr + offset, value, mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> +
> static int mtk_mmsys_reset_update(struct reset_controller_dev
> *rcdev, unsigned long id,
> bool assert)
> {
> @@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> struct platform_device *clks;
> struct platform_device *drm;
> struct mtk_mmsys *mmsys;
> + struct resource res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> return ret;
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> + mmsys->addr = 0L;
> + else
> + mmsys->addr = res.start;
> +
> + if (mmsys->data->has_gce_client_reg) {
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base,
> 0);
Add gce client reg in mmsys binding document [1].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v5.17-rc6
> + if (ret) {
> + dev_err(dev, "No mediatek,gce-client-reg!\n");
> + return ret;
> + }
> + }
> +
> mmsys->data = of_device_get_match_data(&pdev->dev);
> platform_set_drvdata(pdev, mmsys);
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..9fce400507d2 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + bool has_gce_client_reg;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..7f8ecc98d023 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -7,8 +7,14 @@
> #define __MTK_MMSYS_H
>
> enum mtk_ddp_comp_id;
> +enum mtk_mdp_comp_id;
> struct device;
>
> +struct mmsys_cmdq_cmd {
> + struct cmdq_pkt *pkt;
> + s32 *event;
> +};
> +
> enum mtk_ddp_comp_id {
> DDP_COMPONENT_AAL0,
> DDP_COMPONENT_AAL1,
> @@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mdp_comp_id {
> + MDP_COMP_NONE = -1, /* Invalid engine */
> +
> + /* ISP */
> + MDP_COMP_WPEI = 0,
> + MDP_COMP_WPEO, /* 1 */
> + MDP_COMP_WPEI2, /* 2 */
> + MDP_COMP_WPEO2, /* 3 */
> + MDP_COMP_ISP_IMGI, /* 4 */
> + MDP_COMP_ISP_IMGO, /* 5 */
> + MDP_COMP_ISP_IMG2O, /* 6 */
> +
> + /* IPU */
> + MDP_COMP_IPUI, /* 7 */
> + MDP_COMP_IPUO, /* 8 */
> +
> + /* MDP */
> + MDP_COMP_CAMIN, /* 9 */
> + MDP_COMP_CAMIN2, /* 10 */
> + MDP_COMP_RDMA0, /* 11 */
> + MDP_COMP_AAL0, /* 12 */
> + MDP_COMP_CCORR0, /* 13 */
> + MDP_COMP_RSZ0, /* 14 */
> + MDP_COMP_RSZ1, /* 15 */
> + MDP_COMP_TDSHP0, /* 16 */
> + MDP_COMP_COLOR0, /* 17 */
> + MDP_COMP_PATH0_SOUT, /* 18 */
> + MDP_COMP_PATH1_SOUT, /* 19 */
> + MDP_COMP_WROT0, /* 20 */
> + MDP_COMP_WDMA, /* 21 */
> +
> + /* Dummy Engine */
> + MDP_COMP_RDMA1, /* 22 */
> + MDP_COMP_RSZ2, /* 23 */
> + MDP_COMP_TDSHP1, /* 24 */
> + MDP_COMP_WROT1, /* 25 */
> +
> + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> +};
Useless, remove this.
Regards,
CK
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask);
> +
> #endif /* __MTK_MMSYS_H */
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
@ 2022-03-03 7:59 ` CK Hu
0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 7:59 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> Adding the interface of writing MMSYS register via CMDQ,
> users do not need to parse related dts information.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/Kconfig | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 50
> ++++++++++++++++++++++++++
> 4 files changed, 82 insertions(+)
>
> diff --git a/drivers/soc/mediatek/Kconfig
> b/drivers/soc/mediatek/Kconfig
> index fdd8bc08569e..172bc7828aca 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -69,6 +69,7 @@ config MTK_MMSYS
> bool "MediaTek MMSYS Support"
> default ARCH_MEDIATEK
> depends on HAS_IOMEM
> + select MTK_CMDQ
In MT8173, mmsys could work without CMDQ, so I think mmsys should not
select CMDQ.
> help
> Say yes here to add support for the MediaTek Multimedia
> Subsystem (MMSYS).
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 50c797d70ddd..04c0c7de395e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -8,9 +8,11 @@
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> @@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .has_gce_client_reg = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =
> {
> @@ -81,6 +84,8 @@ struct mtk_mmsys {
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + struct cmdq_client_reg cmdq_base;
> + phys_addr_t addr;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 offset, u32 value, u32 mask)
I would like mmsys provide high level interface rather than such low
level interface.
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> + mmsys->addr + offset, value, mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> +
> static int mtk_mmsys_reset_update(struct reset_controller_dev
> *rcdev, unsigned long id,
> bool assert)
> {
> @@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> struct platform_device *clks;
> struct platform_device *drm;
> struct mtk_mmsys *mmsys;
> + struct resource res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> return ret;
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> + mmsys->addr = 0L;
> + else
> + mmsys->addr = res.start;
> +
> + if (mmsys->data->has_gce_client_reg) {
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base,
> 0);
Add gce client reg in mmsys binding document [1].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v5.17-rc6
> + if (ret) {
> + dev_err(dev, "No mediatek,gce-client-reg!\n");
> + return ret;
> + }
> + }
> +
> mmsys->data = of_device_get_match_data(&pdev->dev);
> platform_set_drvdata(pdev, mmsys);
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..9fce400507d2 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + bool has_gce_client_reg;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..7f8ecc98d023 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -7,8 +7,14 @@
> #define __MTK_MMSYS_H
>
> enum mtk_ddp_comp_id;
> +enum mtk_mdp_comp_id;
> struct device;
>
> +struct mmsys_cmdq_cmd {
> + struct cmdq_pkt *pkt;
> + s32 *event;
> +};
> +
> enum mtk_ddp_comp_id {
> DDP_COMPONENT_AAL0,
> DDP_COMPONENT_AAL1,
> @@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mdp_comp_id {
> + MDP_COMP_NONE = -1, /* Invalid engine */
> +
> + /* ISP */
> + MDP_COMP_WPEI = 0,
> + MDP_COMP_WPEO, /* 1 */
> + MDP_COMP_WPEI2, /* 2 */
> + MDP_COMP_WPEO2, /* 3 */
> + MDP_COMP_ISP_IMGI, /* 4 */
> + MDP_COMP_ISP_IMGO, /* 5 */
> + MDP_COMP_ISP_IMG2O, /* 6 */
> +
> + /* IPU */
> + MDP_COMP_IPUI, /* 7 */
> + MDP_COMP_IPUO, /* 8 */
> +
> + /* MDP */
> + MDP_COMP_CAMIN, /* 9 */
> + MDP_COMP_CAMIN2, /* 10 */
> + MDP_COMP_RDMA0, /* 11 */
> + MDP_COMP_AAL0, /* 12 */
> + MDP_COMP_CCORR0, /* 13 */
> + MDP_COMP_RSZ0, /* 14 */
> + MDP_COMP_RSZ1, /* 15 */
> + MDP_COMP_TDSHP0, /* 16 */
> + MDP_COMP_COLOR0, /* 17 */
> + MDP_COMP_PATH0_SOUT, /* 18 */
> + MDP_COMP_PATH1_SOUT, /* 19 */
> + MDP_COMP_WROT0, /* 20 */
> + MDP_COMP_WDMA, /* 21 */
> +
> + /* Dummy Engine */
> + MDP_COMP_RDMA1, /* 22 */
> + MDP_COMP_RSZ2, /* 23 */
> + MDP_COMP_TDSHP1, /* 24 */
> + MDP_COMP_WROT1, /* 25 */
> +
> + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> +};
Useless, remove this.
Regards,
CK
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask);
> +
> #endif /* __MTK_MMSYS_H */
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
2022-03-03 7:59 ` CK Hu
@ 2022-03-09 9:53 ` moudy.ho
-1 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 9:53 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 15:59 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > Adding the interface of writing MMSYS register via CMDQ,
> > users do not need to parse related dts information.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/Kconfig | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 50
> > ++++++++++++++++++++++++++
> > 4 files changed, 82 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/Kconfig
> > b/drivers/soc/mediatek/Kconfig
> > index fdd8bc08569e..172bc7828aca 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -69,6 +69,7 @@ config MTK_MMSYS
> > bool "MediaTek MMSYS Support"
> > default ARCH_MEDIATEK
> > depends on HAS_IOMEM
> > + select MTK_CMDQ
>
> In MT8173, mmsys could work without CMDQ, so I think mmsys should not
> select CMDQ.
>
Hi CK,
Thanks for the reminder, I will use "IS_REACHABLE" macro instead of
config select operation.
> > help
> > Say yes here to add support for the MediaTek Multimedia
> > Subsystem (MMSYS).
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 50c797d70ddd..04c0c7de395e 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -8,9 +8,11 @@
> > #include <linux/device.h>
> > #include <linux/io.h>
> > #include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > #include <linux/platform_device.h>
> > #include <linux/reset-controller.h>
> > #include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> >
> > #include "mtk-mmsys.h"
> > #include "mt8167-mmsys.h"
> > @@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > + .has_gce_client_reg = true,
> > };
> >
> > static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data
> > =
> > {
> > @@ -81,6 +84,8 @@ struct mtk_mmsys {
> > const struct mtk_mmsys_driver_data *data;
> > spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > struct reset_controller_dev rcdev;
> > + struct cmdq_client_reg cmdq_base;
> > + phys_addr_t addr;
> > };
> >
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > @@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> > + struct mmsys_cmdq_cmd *cmd,
> > + u32 offset, u32 value, u32 mask)
>
> I would like mmsys provide high level interface rather than such low
> level interface.
>
Thank you for your suggestion, we will adjust MDP flow to avoid
frequent use of MMSYS API to operate CMDQ, so we can remove this
unnecessary API in the next version.
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> > + mmsys->addr + offset, value, mask);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> > +
> > static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> > bool assert)
> > {
> > @@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct
> > platform_device
> > *pdev)
> > struct platform_device *clks;
> > struct platform_device *drm;
> > struct mtk_mmsys *mmsys;
> > + struct resource res;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> > + mmsys->addr = 0L;
> > + else
> > + mmsys->addr = res.start;
> > +
> > + if (mmsys->data->has_gce_client_reg) {
> > + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base,
> > 0);
>
> Add gce client reg in mmsys binding document [1].
>
> [1]
>
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v5.17-rc6
>
Thanks for the reminder, I will fill in the missing parts in the next
version.
> > + if (ret) {
> > + dev_err(dev, "No mediatek,gce-client-reg!\n");
> > + return ret;
> > + }
> > + }
> > +
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > platform_set_drvdata(pdev, mmsys);
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 8b0ed05117ea..9fce400507d2 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > + bool has_gce_client_reg;
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..7f8ecc98d023 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -7,8 +7,14 @@
> > #define __MTK_MMSYS_H
> >
> > enum mtk_ddp_comp_id;
> > +enum mtk_mdp_comp_id;
> > struct device;
> >
> > +struct mmsys_cmdq_cmd {
> > + struct cmdq_pkt *pkt;
> > + s32 *event;
> > +};
> > +
> > enum mtk_ddp_comp_id {
> > DDP_COMPONENT_AAL0,
> > DDP_COMPONENT_AAL1,
> > @@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > +enum mtk_mdp_comp_id {
> > + MDP_COMP_NONE = -1, /* Invalid engine */
> > +
> > + /* ISP */
> > + MDP_COMP_WPEI = 0,
> > + MDP_COMP_WPEO, /* 1 */
> > + MDP_COMP_WPEI2, /* 2 */
> > + MDP_COMP_WPEO2, /* 3 */
> > + MDP_COMP_ISP_IMGI, /* 4 */
> > + MDP_COMP_ISP_IMGO, /* 5 */
> > + MDP_COMP_ISP_IMG2O, /* 6 */
> > +
> > + /* IPU */
> > + MDP_COMP_IPUI, /* 7 */
> > + MDP_COMP_IPUO, /* 8 */
> > +
> > + /* MDP */
> > + MDP_COMP_CAMIN, /* 9 */
> > + MDP_COMP_CAMIN2, /* 10 */
> > + MDP_COMP_RDMA0, /* 11 */
> > + MDP_COMP_AAL0, /* 12 */
> > + MDP_COMP_CCORR0, /* 13 */
> > + MDP_COMP_RSZ0, /* 14 */
> > + MDP_COMP_RSZ1, /* 15 */
> > + MDP_COMP_TDSHP0, /* 16 */
> > + MDP_COMP_COLOR0, /* 17 */
> > + MDP_COMP_PATH0_SOUT, /* 18 */
> > + MDP_COMP_PATH1_SOUT, /* 19 */
> > + MDP_COMP_WROT0, /* 20 */
> > + MDP_COMP_WDMA, /* 21 */
> > +
> > + /* Dummy Engine */
> > + MDP_COMP_RDMA1, /* 22 */
> > + MDP_COMP_RSZ2, /* 23 */
> > + MDP_COMP_TDSHP1, /* 24 */
> > + MDP_COMP_WROT1, /* 25 */
> > +
> > + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> > +};
>
> Useless, remove this.
>
> Regards,
> CK
>
In order to cooperate with the operation of MUTEX and maintain the MOD
define in the corresponding driver(used in mtk_mutex_get_mdp_mod), it
is necessary to move the MDP component ID to a higher-level module to
communicate across modules.
Can this setting be kept here?
Thanks & Regards,
Moudy Ho
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> >
> > +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> > + struct mmsys_cmdq_cmd *cmd,
> > + u32 alias_id, u32 value, u32 mask);
> > +
> > #endif /* __MTK_MMSYS_H */
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 1/4] soc: mediatek: mmsys: add CMDQ write register function
@ 2022-03-09 9:53 ` moudy.ho
0 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 9:53 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 15:59 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > Adding the interface of writing MMSYS register via CMDQ,
> > users do not need to parse related dts information.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/Kconfig | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 30 ++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 50
> > ++++++++++++++++++++++++++
> > 4 files changed, 82 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/Kconfig
> > b/drivers/soc/mediatek/Kconfig
> > index fdd8bc08569e..172bc7828aca 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -69,6 +69,7 @@ config MTK_MMSYS
> > bool "MediaTek MMSYS Support"
> > default ARCH_MEDIATEK
> > depends on HAS_IOMEM
> > + select MTK_CMDQ
>
> In MT8173, mmsys could work without CMDQ, so I think mmsys should not
> select CMDQ.
>
Hi CK,
Thanks for the reminder, I will use "IS_REACHABLE" macro instead of
config select operation.
> > help
> > Say yes here to add support for the MediaTek Multimedia
> > Subsystem (MMSYS).
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 50c797d70ddd..04c0c7de395e 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -8,9 +8,11 @@
> > #include <linux/device.h>
> > #include <linux/io.h>
> > #include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > #include <linux/platform_device.h>
> > #include <linux/reset-controller.h>
> > #include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> >
> > #include "mtk-mmsys.h"
> > #include "mt8167-mmsys.h"
> > @@ -55,6 +57,7 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > + .has_gce_client_reg = true,
> > };
> >
> > static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data
> > =
> > {
> > @@ -81,6 +84,8 @@ struct mtk_mmsys {
> > const struct mtk_mmsys_driver_data *data;
> > spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > struct reset_controller_dev rcdev;
> > + struct cmdq_client_reg cmdq_base;
> > + phys_addr_t addr;
> > };
> >
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > @@ -120,6 +125,17 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> > + struct mmsys_cmdq_cmd *cmd,
> > + u32 offset, u32 value, u32 mask)
>
> I would like mmsys provide high level interface rather than such low
> level interface.
>
Thank you for your suggestion, we will adjust MDP flow to avoid
frequent use of MMSYS API to operate CMDQ, so we can remove this
unnecessary API in the next version.
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> > + mmsys->addr + offset, value, mask);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> > +
> > static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> > bool assert)
> > {
> > @@ -178,6 +194,7 @@ static int mtk_mmsys_probe(struct
> > platform_device
> > *pdev)
> > struct platform_device *clks;
> > struct platform_device *drm;
> > struct mtk_mmsys *mmsys;
> > + struct resource res;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -203,6 +220,19 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> > + mmsys->addr = 0L;
> > + else
> > + mmsys->addr = res.start;
> > +
> > + if (mmsys->data->has_gce_client_reg) {
> > + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base,
> > 0);
>
> Add gce client reg in mmsys binding document [1].
>
> [1]
>
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v5.17-rc6
>
Thanks for the reminder, I will fill in the missing parts in the next
version.
> > + if (ret) {
> > + dev_err(dev, "No mediatek,gce-client-reg!\n");
> > + return ret;
> > + }
> > + }
> > +
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > platform_set_drvdata(pdev, mmsys);
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 8b0ed05117ea..9fce400507d2 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > + bool has_gce_client_reg;
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..7f8ecc98d023 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -7,8 +7,14 @@
> > #define __MTK_MMSYS_H
> >
> > enum mtk_ddp_comp_id;
> > +enum mtk_mdp_comp_id;
> > struct device;
> >
> > +struct mmsys_cmdq_cmd {
> > + struct cmdq_pkt *pkt;
> > + s32 *event;
> > +};
> > +
> > enum mtk_ddp_comp_id {
> > DDP_COMPONENT_AAL0,
> > DDP_COMPONENT_AAL1,
> > @@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > +enum mtk_mdp_comp_id {
> > + MDP_COMP_NONE = -1, /* Invalid engine */
> > +
> > + /* ISP */
> > + MDP_COMP_WPEI = 0,
> > + MDP_COMP_WPEO, /* 1 */
> > + MDP_COMP_WPEI2, /* 2 */
> > + MDP_COMP_WPEO2, /* 3 */
> > + MDP_COMP_ISP_IMGI, /* 4 */
> > + MDP_COMP_ISP_IMGO, /* 5 */
> > + MDP_COMP_ISP_IMG2O, /* 6 */
> > +
> > + /* IPU */
> > + MDP_COMP_IPUI, /* 7 */
> > + MDP_COMP_IPUO, /* 8 */
> > +
> > + /* MDP */
> > + MDP_COMP_CAMIN, /* 9 */
> > + MDP_COMP_CAMIN2, /* 10 */
> > + MDP_COMP_RDMA0, /* 11 */
> > + MDP_COMP_AAL0, /* 12 */
> > + MDP_COMP_CCORR0, /* 13 */
> > + MDP_COMP_RSZ0, /* 14 */
> > + MDP_COMP_RSZ1, /* 15 */
> > + MDP_COMP_TDSHP0, /* 16 */
> > + MDP_COMP_COLOR0, /* 17 */
> > + MDP_COMP_PATH0_SOUT, /* 18 */
> > + MDP_COMP_PATH1_SOUT, /* 19 */
> > + MDP_COMP_WROT0, /* 20 */
> > + MDP_COMP_WDMA, /* 21 */
> > +
> > + /* Dummy Engine */
> > + MDP_COMP_RDMA1, /* 22 */
> > + MDP_COMP_RSZ2, /* 23 */
> > + MDP_COMP_TDSHP1, /* 24 */
> > + MDP_COMP_WROT1, /* 25 */
> > +
> > + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> > +};
>
> Useless, remove this.
>
> Regards,
> CK
>
In order to cooperate with the operation of MUTEX and maintain the MOD
define in the corresponding driver(used in mtk_mutex_get_mdp_mod), it
is necessary to move the MDP component ID to a higher-level module to
communicate across modules.
Can this setting be kept here?
Thanks & Regards,
Moudy Ho
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -53,4 +99,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> >
> > +void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> > + struct mmsys_cmdq_cmd *cmd,
> > + u32 alias_id, u32 value, u32 mask);
> > +
> > #endif /* __MTK_MMSYS_H */
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
2022-03-01 10:02 ` Moudy Ho
(?)
@ 2022-03-01 10:02 ` Moudy Ho
-1 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
This patch adds 8183 ISP settings in MMSYS domain and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
drivers/soc/mediatek/mtk-mmsys.c | 115 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
4 files changed, 172 insertions(+)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..179d5996c659 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -13,6 +13,18 @@
#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
+#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
+#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
+#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
+#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
+#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
+#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
+#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
+
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
@@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
}
};
+static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
+ [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
+ [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
+ [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
+ [ISP_REG_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
+ [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
+ [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
+ [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
+ [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
+ [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
+ [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 04c0c7de395e..0e271d1a86e5 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.has_gce_client_reg = true,
+ .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ /* Direct link */
+ if (id == MDP_COMP_CAMIN) {
+ /* Reset MDP_DL_ASYNC_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ }
+
+ /* Reset MDP_DL_ASYNC_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+
+ if (id == MDP_COMP_CAMIN2) {
+ /* Reset MDP_DL_ASYNC2_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ }
+
+ /* Reset MDP_DL_ASYNC2_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ /* Config for direct link */
+ if (id == MDP_COMP_CAMIN) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+ if (id == MDP_COMP_CAMIN2) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 9fce400507d2..ad8b92389b54 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
bool has_gce_client_reg;
+ const unsigned int *mdp_isp_ctrl;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 7f8ecc98d023..45e77d1cd6c1 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
+enum mtk_mdp_pipe_id {
+ MDP_PIPE_RDMA0,
+ MDP_PIPE_IMGI,
+ MDP_PIPE_WPEI,
+ MDP_PIPE_WPEI2,
+ MDP_PIPE_MAX
+};
+
+enum mtk_isp_ctrl {
+ ISP_REG_MMSYS_SW0_RST_B,
+ ISP_REG_MMSYS_SW1_RST_B,
+ ISP_REG_MDP_ASYNC_CFG_WD,
+ ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ ISP_REG_ISP_RELAY_CFG_WD,
+ ISP_REG_IPU_RELAY_CFG_WD,
+ ISP_BIT_MDP_DL_ASYNC_TX,
+ ISP_BIT_MDP_DL_ASYNC_TX2,
+ ISP_BIT_MDP_DL_ASYNC_RX,
+ ISP_BIT_MDP_DL_ASYNC_RX2,
+ ISP_BIT_NO_SOF_MODE,
+ ISP_CTRL_MAX
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
struct mmsys_cmdq_cmd *cmd,
u32 alias_id, u32 value, u32 mask);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id,
+ u32 camin_w, u32 camin_h);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
This patch adds 8183 ISP settings in MMSYS domain and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
drivers/soc/mediatek/mtk-mmsys.c | 115 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
4 files changed, 172 insertions(+)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..179d5996c659 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -13,6 +13,18 @@
#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
+#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
+#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
+#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
+#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
+#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
+#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
+#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
+
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
@@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
}
};
+static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
+ [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
+ [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
+ [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
+ [ISP_REG_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
+ [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
+ [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
+ [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
+ [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
+ [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
+ [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 04c0c7de395e..0e271d1a86e5 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.has_gce_client_reg = true,
+ .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ /* Direct link */
+ if (id == MDP_COMP_CAMIN) {
+ /* Reset MDP_DL_ASYNC_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ }
+
+ /* Reset MDP_DL_ASYNC_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+
+ if (id == MDP_COMP_CAMIN2) {
+ /* Reset MDP_DL_ASYNC2_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ }
+
+ /* Reset MDP_DL_ASYNC2_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ /* Config for direct link */
+ if (id == MDP_COMP_CAMIN) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+ if (id == MDP_COMP_CAMIN2) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 9fce400507d2..ad8b92389b54 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
bool has_gce_client_reg;
+ const unsigned int *mdp_isp_ctrl;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 7f8ecc98d023..45e77d1cd6c1 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
+enum mtk_mdp_pipe_id {
+ MDP_PIPE_RDMA0,
+ MDP_PIPE_IMGI,
+ MDP_PIPE_WPEI,
+ MDP_PIPE_WPEI2,
+ MDP_PIPE_MAX
+};
+
+enum mtk_isp_ctrl {
+ ISP_REG_MMSYS_SW0_RST_B,
+ ISP_REG_MMSYS_SW1_RST_B,
+ ISP_REG_MDP_ASYNC_CFG_WD,
+ ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ ISP_REG_ISP_RELAY_CFG_WD,
+ ISP_REG_IPU_RELAY_CFG_WD,
+ ISP_BIT_MDP_DL_ASYNC_TX,
+ ISP_BIT_MDP_DL_ASYNC_TX2,
+ ISP_BIT_MDP_DL_ASYNC_RX,
+ ISP_BIT_MDP_DL_ASYNC_RX2,
+ ISP_BIT_NO_SOF_MODE,
+ ISP_CTRL_MAX
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
struct mmsys_cmdq_cmd *cmd,
u32 alias_id, u32 value, u32 mask);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id,
+ u32 camin_w, u32 camin_h);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
This patch adds 8183 ISP settings in MMSYS domain and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
drivers/soc/mediatek/mtk-mmsys.c | 115 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
4 files changed, 172 insertions(+)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..179d5996c659 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -13,6 +13,18 @@
#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
+#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
+#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
+#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
+#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
+#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
+#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
+#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
+
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
@@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
}
};
+static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
+ [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
+ [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
+ [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
+ [ISP_REG_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
+ [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
+ [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
+ [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
+ [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
+ [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
+ [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 04c0c7de395e..0e271d1a86e5 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.has_gce_client_reg = true,
+ .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ /* Direct link */
+ if (id == MDP_COMP_CAMIN) {
+ /* Reset MDP_DL_ASYNC_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ }
+
+ /* Reset MDP_DL_ASYNC_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+
+ if (id == MDP_COMP_CAMIN2) {
+ /* Reset MDP_DL_ASYNC2_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ }
+
+ /* Reset MDP_DL_ASYNC2_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ /* Config for direct link */
+ if (id == MDP_COMP_CAMIN) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+ if (id == MDP_COMP_CAMIN2) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 9fce400507d2..ad8b92389b54 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
bool has_gce_client_reg;
+ const unsigned int *mdp_isp_ctrl;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 7f8ecc98d023..45e77d1cd6c1 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
+enum mtk_mdp_pipe_id {
+ MDP_PIPE_RDMA0,
+ MDP_PIPE_IMGI,
+ MDP_PIPE_WPEI,
+ MDP_PIPE_WPEI2,
+ MDP_PIPE_MAX
+};
+
+enum mtk_isp_ctrl {
+ ISP_REG_MMSYS_SW0_RST_B,
+ ISP_REG_MMSYS_SW1_RST_B,
+ ISP_REG_MDP_ASYNC_CFG_WD,
+ ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ ISP_REG_ISP_RELAY_CFG_WD,
+ ISP_REG_IPU_RELAY_CFG_WD,
+ ISP_BIT_MDP_DL_ASYNC_TX,
+ ISP_BIT_MDP_DL_ASYNC_TX2,
+ ISP_BIT_MDP_DL_ASYNC_RX,
+ ISP_BIT_MDP_DL_ASYNC_RX2,
+ ISP_BIT_NO_SOF_MODE,
+ ISP_CTRL_MAX
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
struct mmsys_cmdq_cmd *cmd,
u32 alias_id, u32 value, u32 mask);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id,
+ u32 camin_w, u32 camin_h);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
2022-03-01 10:02 ` Moudy Ho
(?)
@ 2022-03-03 9:03 ` CK Hu
-1 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 9:03 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> This patch adds 8183 ISP settings in MMSYS domain and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
> drivers/soc/mediatek/mtk-mmsys.c | 115
> +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
> 4 files changed, 172 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> b/drivers/soc/mediatek/mt8183-mmsys.h
> index 9dee485807c9..179d5996c659 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -13,6 +13,18 @@
> #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
>
> +#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
> +#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
> +#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
> +#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
> +#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
> +#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
> +#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
> +
> #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> #define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> @@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes
> mmsys_mt8183_routing_table[] = {
> }
> };
>
> +static const unsigned int
> mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> + [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
> + [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
> + [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
> + [ISP_REG_MDP_ASYNC_IPU_CFG_WD] =
> MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> + [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
> + [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
> + [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
> + [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
> + [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
> + [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
> + [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 04c0c7de395e..0e271d1a86e5 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> .has_gce_client_reg = true,
> + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =
> {
> @@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
>
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + /* Direct link */
> + if (id == MDP_COMP_CAMIN) {
> + /* Reset MDP_DL_ASYNC_TX */
Why do you reset this hardware by CMDQ? Usually we reset one hardware
before it start or after it stop. In this timing, we could easily use
CPU to reset this hardware.
Regards,
CK
> + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX]);
> + }
> +
> + /* Reset MDP_DL_ASYNC_RX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX]);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_NO_SOF_MOD
> E]);
> + }
> + }
> +
> + if (id == MDP_COMP_CAMIN2) {
> + /* Reset MDP_DL_ASYNC2_TX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2]);
> + }
> +
> + /* Reset MDP_DL_ASYNC2_RX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2]);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_NO_SOF_MOD
> E]);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id, u32 camin_w, u32
> camin_h)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + /* Config for direct link */
> + if (id == MDP_COMP_CAMIN) {
> + if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> +
> + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> + if (id == MDP_COMP_CAMIN2) {
> + if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
> +
> static int mtk_mmsys_reset_update(struct reset_controller_dev
> *rcdev, unsigned long id,
> bool assert)
> {
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index 9fce400507d2..ad8b92389b54 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> bool has_gce_client_reg;
> + const unsigned int *mdp_isp_ctrl;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 7f8ecc98d023..45e77d1cd6c1 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
> MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> };
>
> +enum mtk_mdp_pipe_id {
> + MDP_PIPE_RDMA0,
> + MDP_PIPE_IMGI,
> + MDP_PIPE_WPEI,
> + MDP_PIPE_WPEI2,
> + MDP_PIPE_MAX
> +};
> +
> +enum mtk_isp_ctrl {
> + ISP_REG_MMSYS_SW0_RST_B,
> + ISP_REG_MMSYS_SW1_RST_B,
> + ISP_REG_MDP_ASYNC_CFG_WD,
> + ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> + ISP_REG_ISP_RELAY_CFG_WD,
> + ISP_REG_IPU_RELAY_CFG_WD,
> + ISP_BIT_MDP_DL_ASYNC_TX,
> + ISP_BIT_MDP_DL_ASYNC_TX2,
> + ISP_BIT_MDP_DL_ASYNC_RX,
> + ISP_BIT_MDP_DL_ASYNC_RX2,
> + ISP_BIT_NO_SOF_MODE,
> + ISP_CTRL_MAX
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> *dev,
> struct mmsys_cmdq_cmd *cmd,
> u32 alias_id, u32 value, u32 mask);
>
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id,
> + u32 camin_w, u32 camin_h);
> +
> #endif /* __MTK_MMSYS_H */
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
@ 2022-03-03 9:03 ` CK Hu
0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 9:03 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> This patch adds 8183 ISP settings in MMSYS domain and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
> drivers/soc/mediatek/mtk-mmsys.c | 115
> +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
> 4 files changed, 172 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> b/drivers/soc/mediatek/mt8183-mmsys.h
> index 9dee485807c9..179d5996c659 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -13,6 +13,18 @@
> #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
>
> +#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
> +#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
> +#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
> +#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
> +#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
> +#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
> +#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
> +
> #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> #define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> @@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes
> mmsys_mt8183_routing_table[] = {
> }
> };
>
> +static const unsigned int
> mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> + [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
> + [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
> + [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
> + [ISP_REG_MDP_ASYNC_IPU_CFG_WD] =
> MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> + [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
> + [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
> + [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
> + [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
> + [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
> + [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
> + [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 04c0c7de395e..0e271d1a86e5 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> .has_gce_client_reg = true,
> + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =
> {
> @@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
>
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + /* Direct link */
> + if (id == MDP_COMP_CAMIN) {
> + /* Reset MDP_DL_ASYNC_TX */
Why do you reset this hardware by CMDQ? Usually we reset one hardware
before it start or after it stop. In this timing, we could easily use
CPU to reset this hardware.
Regards,
CK
> + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX]);
> + }
> +
> + /* Reset MDP_DL_ASYNC_RX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX]);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_NO_SOF_MOD
> E]);
> + }
> + }
> +
> + if (id == MDP_COMP_CAMIN2) {
> + /* Reset MDP_DL_ASYNC2_TX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2]);
> + }
> +
> + /* Reset MDP_DL_ASYNC2_RX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2]);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_NO_SOF_MOD
> E]);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id, u32 camin_w, u32
> camin_h)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + /* Config for direct link */
> + if (id == MDP_COMP_CAMIN) {
> + if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> +
> + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> + if (id == MDP_COMP_CAMIN2) {
> + if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
> +
> static int mtk_mmsys_reset_update(struct reset_controller_dev
> *rcdev, unsigned long id,
> bool assert)
> {
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index 9fce400507d2..ad8b92389b54 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> bool has_gce_client_reg;
> + const unsigned int *mdp_isp_ctrl;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 7f8ecc98d023..45e77d1cd6c1 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
> MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> };
>
> +enum mtk_mdp_pipe_id {
> + MDP_PIPE_RDMA0,
> + MDP_PIPE_IMGI,
> + MDP_PIPE_WPEI,
> + MDP_PIPE_WPEI2,
> + MDP_PIPE_MAX
> +};
> +
> +enum mtk_isp_ctrl {
> + ISP_REG_MMSYS_SW0_RST_B,
> + ISP_REG_MMSYS_SW1_RST_B,
> + ISP_REG_MDP_ASYNC_CFG_WD,
> + ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> + ISP_REG_ISP_RELAY_CFG_WD,
> + ISP_REG_IPU_RELAY_CFG_WD,
> + ISP_BIT_MDP_DL_ASYNC_TX,
> + ISP_BIT_MDP_DL_ASYNC_TX2,
> + ISP_BIT_MDP_DL_ASYNC_RX,
> + ISP_BIT_MDP_DL_ASYNC_RX2,
> + ISP_BIT_NO_SOF_MODE,
> + ISP_CTRL_MAX
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> *dev,
> struct mmsys_cmdq_cmd *cmd,
> u32 alias_id, u32 value, u32 mask);
>
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id,
> + u32 camin_w, u32 camin_h);
> +
> #endif /* __MTK_MMSYS_H */
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
@ 2022-03-03 9:03 ` CK Hu
0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 9:03 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> This patch adds 8183 ISP settings in MMSYS domain and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
> drivers/soc/mediatek/mtk-mmsys.c | 115
> +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
> 4 files changed, 172 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> b/drivers/soc/mediatek/mt8183-mmsys.h
> index 9dee485807c9..179d5996c659 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -13,6 +13,18 @@
> #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
>
> +#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
> +#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
> +#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
> +#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
> +#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
> +#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
> +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
> +#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
> +
> #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> #define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> @@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes
> mmsys_mt8183_routing_table[] = {
> }
> };
>
> +static const unsigned int
> mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> + [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
> + [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
> + [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
> + [ISP_REG_MDP_ASYNC_IPU_CFG_WD] =
> MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> + [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
> + [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
> + [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
> + [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
> + [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
> + [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
> + [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 04c0c7de395e..0e271d1a86e5 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> .has_gce_client_reg = true,
> + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> };
>
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =
> {
> @@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
>
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + /* Direct link */
> + if (id == MDP_COMP_CAMIN) {
> + /* Reset MDP_DL_ASYNC_TX */
Why do you reset this hardware by CMDQ? Usually we reset one hardware
before it start or after it stop. In this timing, we could easily use
CPU to reset this hardware.
Regards,
CK
> + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX]);
> + }
> +
> + /* Reset MDP_DL_ASYNC_RX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX]);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_NO_SOF_MOD
> E]);
> + }
> + }
> +
> + if (id == MDP_COMP_CAMIN2) {
> + /* Reset MDP_DL_ASYNC2_TX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_TX2]);
> + }
> +
> + /* Reset MDP_DL_ASYNC2_RX */
> + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2]);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2],
> + isp_ctrl[ISP_BIT_MDP_DL_ASY
> NC_RX2]);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + 0x0,
> + isp_ctrl[ISP_BIT_NO_SOF_MOD
> E]);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id, u32 camin_w, u32
> camin_h)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + /* Config for direct link */
> + if (id == MDP_COMP_CAMIN) {
> + if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> +
> + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> + if (id == MDP_COMP_CAMIN2) {
> + if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr +
> isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> >cmdq_base.subsys, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
> +
> static int mtk_mmsys_reset_update(struct reset_controller_dev
> *rcdev, unsigned long id,
> bool assert)
> {
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index 9fce400507d2..ad8b92389b54 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> bool has_gce_client_reg;
> + const unsigned int *mdp_isp_ctrl;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 7f8ecc98d023..45e77d1cd6c1 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
> MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> };
>
> +enum mtk_mdp_pipe_id {
> + MDP_PIPE_RDMA0,
> + MDP_PIPE_IMGI,
> + MDP_PIPE_WPEI,
> + MDP_PIPE_WPEI2,
> + MDP_PIPE_MAX
> +};
> +
> +enum mtk_isp_ctrl {
> + ISP_REG_MMSYS_SW0_RST_B,
> + ISP_REG_MMSYS_SW1_RST_B,
> + ISP_REG_MDP_ASYNC_CFG_WD,
> + ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> + ISP_REG_ISP_RELAY_CFG_WD,
> + ISP_REG_IPU_RELAY_CFG_WD,
> + ISP_BIT_MDP_DL_ASYNC_TX,
> + ISP_BIT_MDP_DL_ASYNC_TX2,
> + ISP_BIT_MDP_DL_ASYNC_RX,
> + ISP_BIT_MDP_DL_ASYNC_RX2,
> + ISP_BIT_NO_SOF_MODE,
> + ISP_CTRL_MAX
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> *dev,
> struct mmsys_cmdq_cmd *cmd,
> u32 alias_id, u32 value, u32 mask);
>
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id,
> + u32 camin_w, u32 camin_h);
> +
> #endif /* __MTK_MMSYS_H */
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
2022-03-03 9:03 ` CK Hu
@ 2022-03-09 10:02 ` moudy.ho
-1 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 10:02 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 17:03 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > This patch adds 8183 ISP settings in MMSYS domain and interface.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 115
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
> > 4 files changed, 172 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> > b/drivers/soc/mediatek/mt8183-mmsys.h
> > index 9dee485807c9..179d5996c659 100644
> > --- a/drivers/soc/mediatek/mt8183-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> > @@ -13,6 +13,18 @@
> > #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> > #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
> >
> > +#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
> > +#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
> > +#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
> > +#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
> > +#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
> > +#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
> > +#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
> > +
> > #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> > #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> > #define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> > @@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8183_routing_table[] = {
> > }
> > };
> >
> > +static const unsigned int
> > mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> > + [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
> > + [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
> > + [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
> > + [ISP_REG_MDP_ASYNC_IPU_CFG_WD] =
> > MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> > + [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
> > + [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
> > + [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
> > + [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
> > + [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
> > + [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
> > + [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
> > +};
> > +
> > #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 04c0c7de395e..0e271d1a86e5 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .routes = mmsys_mt8183_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > .has_gce_client_reg = true,
> > + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> > };
> >
> > static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data
> > =
> > {
> > @@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct
> > device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> >
> > +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> > + u32 reg;
> > +
> > + /* Direct link */
> > + if (id == MDP_COMP_CAMIN) {
> > + /* Reset MDP_DL_ASYNC_TX */
>
> Why do you reset this hardware by CMDQ? Usually we reset one hardware
> before it start or after it stop. In this timing, we could easily use
> CPU to reset this hardware.
>
> Regards,
> CK
>
Hi CK,
As mentioned in patch 4/4, due to HW limitations, it is currently
necessary to set MUTEX enable and SW reset in each frame to avoid
unpredictable artifacts.
Thanks & Regards,
Moudy Ho
> > + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX]);
> > + }
> > +
> > + /* Reset MDP_DL_ASYNC_RX */
> > + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX]);
> > + }
> > +
> > + /* Enable sof mode */
> > + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_NO_SOF_MOD
> > E]);
> > + }
> > + }
> > +
> > + if (id == MDP_COMP_CAMIN2) {
> > + /* Reset MDP_DL_ASYNC2_TX */
> > + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX2]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX2],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX2]);
> > + }
> > +
> > + /* Reset MDP_DL_ASYNC2_RX */
> > + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX2]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX2],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX2]);
> > + }
> > +
> > + /* Enable sof mode */
> > + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_NO_SOF_MOD
> > E]);
> > + }
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
> > +
> > +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id, u32 camin_w, u32
> > camin_h)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> > + u32 reg;
> > +
> > + /* Config for direct link */
> > + if (id == MDP_COMP_CAMIN) {
> > + if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > +
> > + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + }
> > + if (id == MDP_COMP_CAMIN2) {
> > + if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
> > +
> > static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> > bool assert)
> > {
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 9fce400507d2..ad8b92389b54 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > bool has_gce_client_reg;
> > + const unsigned int *mdp_isp_ctrl;
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 7f8ecc98d023..45e77d1cd6c1 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
> > MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> > };
> >
> > +enum mtk_mdp_pipe_id {
> > + MDP_PIPE_RDMA0,
> > + MDP_PIPE_IMGI,
> > + MDP_PIPE_WPEI,
> > + MDP_PIPE_WPEI2,
> > + MDP_PIPE_MAX
> > +};
> > +
> > +enum mtk_isp_ctrl {
> > + ISP_REG_MMSYS_SW0_RST_B,
> > + ISP_REG_MMSYS_SW1_RST_B,
> > + ISP_REG_MDP_ASYNC_CFG_WD,
> > + ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> > + ISP_REG_ISP_RELAY_CFG_WD,
> > + ISP_REG_IPU_RELAY_CFG_WD,
> > + ISP_BIT_MDP_DL_ASYNC_TX,
> > + ISP_BIT_MDP_DL_ASYNC_TX2,
> > + ISP_BIT_MDP_DL_ASYNC_RX,
> > + ISP_BIT_MDP_DL_ASYNC_RX2,
> > + ISP_BIT_NO_SOF_MODE,
> > + ISP_CTRL_MAX
> > +};
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> > *dev,
> > struct mmsys_cmdq_cmd *cmd,
> > u32 alias_id, u32 value, u32 mask);
> >
> > +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id);
> > +
> > +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id,
> > + u32 camin_w, u32 camin_h);
> > +
> > #endif /* __MTK_MMSYS_H */
>
>
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 2/4] soc: mediatek: mmsys: add support for ISP control
@ 2022-03-09 10:02 ` moudy.ho
0 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 10:02 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 17:03 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > This patch adds 8183 ISP settings in MMSYS domain and interface.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 115
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
> > 4 files changed, 172 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> > b/drivers/soc/mediatek/mt8183-mmsys.h
> > index 9dee485807c9..179d5996c659 100644
> > --- a/drivers/soc/mediatek/mt8183-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> > @@ -13,6 +13,18 @@
> > #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> > #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
> >
> > +#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
> > +#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
> > +#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
> > +#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
> > +#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
> > +#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
> > +#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
> > +#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
> > +
> > #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> > #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> > #define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> > @@ -57,5 +69,19 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8183_routing_table[] = {
> > }
> > };
> >
> > +static const unsigned int
> > mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> > + [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
> > + [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
> > + [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
> > + [ISP_REG_MDP_ASYNC_IPU_CFG_WD] =
> > MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> > + [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
> > + [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
> > + [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
> > + [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
> > + [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
> > + [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
> > + [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
> > +};
> > +
> > #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 04c0c7de395e..0e271d1a86e5 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .routes = mmsys_mt8183_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > .has_gce_client_reg = true,
> > + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> > };
> >
> > static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data
> > =
> > {
> > @@ -136,6 +137,120 @@ void mtk_mmsys_write_reg_by_cmdq(struct
> > device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg_by_cmdq);
> >
> > +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> > + u32 reg;
> > +
> > + /* Direct link */
> > + if (id == MDP_COMP_CAMIN) {
> > + /* Reset MDP_DL_ASYNC_TX */
>
> Why do you reset this hardware by CMDQ? Usually we reset one hardware
> before it start or after it stop. In this timing, we could easily use
> CPU to reset this hardware.
>
> Regards,
> CK
>
Hi CK,
As mentioned in patch 4/4, due to HW limitations, it is currently
necessary to set MUTEX enable and SW reset in each frame to avoid
unpredictable artifacts.
Thanks & Regards,
Moudy Ho
> > + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX]);
> > + }
> > +
> > + /* Reset MDP_DL_ASYNC_RX */
> > + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX]);
> > + }
> > +
> > + /* Enable sof mode */
> > + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_NO_SOF_MOD
> > E]);
> > + }
> > + }
> > +
> > + if (id == MDP_COMP_CAMIN2) {
> > + /* Reset MDP_DL_ASYNC2_TX */
> > + if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX2]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX2],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_TX2]);
> > + }
> > +
> > + /* Reset MDP_DL_ASYNC2_RX */
> > + if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX2]);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX2],
> > + isp_ctrl[ISP_BIT_MDP_DL_ASY
> > NC_RX2]);
> > + }
> > +
> > + /* Enable sof mode */
> > + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + 0x0,
> > + isp_ctrl[ISP_BIT_NO_SOF_MOD
> > E]);
> > + }
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
> > +
> > +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id, u32 camin_w, u32
> > camin_h)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> > + u32 reg;
> > +
> > + /* Config for direct link */
> > + if (id == MDP_COMP_CAMIN) {
> > + if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > +
> > + if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + }
> > + if (id == MDP_COMP_CAMIN2) {
> > + if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys-
> > > cmdq_base.subsys, reg,
> >
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
> > +
> > static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> > bool assert)
> > {
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 9fce400507d2..ad8b92389b54 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > bool has_gce_client_reg;
> > + const unsigned int *mdp_isp_ctrl;
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 7f8ecc98d023..45e77d1cd6c1 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
> > MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> > };
> >
> > +enum mtk_mdp_pipe_id {
> > + MDP_PIPE_RDMA0,
> > + MDP_PIPE_IMGI,
> > + MDP_PIPE_WPEI,
> > + MDP_PIPE_WPEI2,
> > + MDP_PIPE_MAX
> > +};
> > +
> > +enum mtk_isp_ctrl {
> > + ISP_REG_MMSYS_SW0_RST_B,
> > + ISP_REG_MMSYS_SW1_RST_B,
> > + ISP_REG_MDP_ASYNC_CFG_WD,
> > + ISP_REG_MDP_ASYNC_IPU_CFG_WD,
> > + ISP_REG_ISP_RELAY_CFG_WD,
> > + ISP_REG_IPU_RELAY_CFG_WD,
> > + ISP_BIT_MDP_DL_ASYNC_TX,
> > + ISP_BIT_MDP_DL_ASYNC_TX2,
> > + ISP_BIT_MDP_DL_ASYNC_RX,
> > + ISP_BIT_MDP_DL_ASYNC_RX2,
> > + ISP_BIT_NO_SOF_MODE,
> > + ISP_CTRL_MAX
> > +};
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -103,4 +126,11 @@ void mtk_mmsys_write_reg_by_cmdq(struct device
> > *dev,
> > struct mmsys_cmdq_cmd *cmd,
> > u32 alias_id, u32 value, u32 mask);
> >
> > +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id);
> > +
> > +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id,
> > + u32 camin_w, u32 camin_h);
> > +
> > #endif /* __MTK_MMSYS_H */
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
2022-03-01 10:02 ` Moudy Ho
(?)
@ 2022-03-01 10:02 ` Moudy Ho
-1 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
For the purpose of module independence, related settings should be moved
from MDP to the corresponding driver.
This patch adds more 8183 MDP settings and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mutex.c | 68 ++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-mutex.h | 3 ++
2 files changed, 71 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..a6268ecde240 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -136,6 +136,18 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_MDP_START 5
+#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
+#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2)
+#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4)
+#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5)
+#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6)
+#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7)
+#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8)
+#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
+#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -156,6 +168,10 @@ struct mtk_mutex_data {
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
+ const unsigned int *mutex_mdp_offset;
+ const unsigned int *mutex_mdp_mod;
+ const unsigned int mutex_mdp_mod_mask;
+ const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
};
@@ -243,6 +259,17 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8183_mutex_mdp_mod[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
+ [MDP_COMP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
+ [MDP_COMP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
+ [MDP_COMP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
+ [MDP_COMP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
+ [MDP_COMP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
+ [MDP_COMP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
+ [MDP_COMP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
+};
+
static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
@@ -300,6 +327,14 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/* indicate which mutex is used by each pipepline */
+static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
+ [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
+ [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
+ [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -334,6 +369,10 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_sof = mt8183_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+ .mutex_mdp_offset = mt8183_mutex_mdp_offset,
+ .mutex_mdp_mod = mt8183_mutex_mdp_mod,
+ .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
};
@@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id)
+{
+ struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
+ int i = mtx->data->mutex_mdp_offset[id];
+
+ if (!mtx->mutex[i].claimed) {
+ mtx->mutex[i].claimed = true;
+ return &mtx->mutex[i];
+ }
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
+
void mtk_mutex_put(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
}
EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ if (mtx->data->mutex_mdp_mod)
+ return mtx->data->mutex_mdp_mod[id];
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 6fe4ffbde290..b2608f4220ee 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -11,9 +11,12 @@ struct device;
struct mtk_mutex;
struct mtk_mutex *mtk_mutex_get(struct device *dev);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id);
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
void mtk_mutex_enable(struct mtk_mutex *mutex);
void mtk_mutex_disable(struct mtk_mutex *mutex);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
--
2.18.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
For the purpose of module independence, related settings should be moved
from MDP to the corresponding driver.
This patch adds more 8183 MDP settings and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mutex.c | 68 ++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-mutex.h | 3 ++
2 files changed, 71 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..a6268ecde240 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -136,6 +136,18 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_MDP_START 5
+#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
+#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2)
+#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4)
+#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5)
+#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6)
+#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7)
+#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8)
+#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
+#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -156,6 +168,10 @@ struct mtk_mutex_data {
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
+ const unsigned int *mutex_mdp_offset;
+ const unsigned int *mutex_mdp_mod;
+ const unsigned int mutex_mdp_mod_mask;
+ const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
};
@@ -243,6 +259,17 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8183_mutex_mdp_mod[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
+ [MDP_COMP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
+ [MDP_COMP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
+ [MDP_COMP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
+ [MDP_COMP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
+ [MDP_COMP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
+ [MDP_COMP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
+ [MDP_COMP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
+};
+
static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
@@ -300,6 +327,14 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/* indicate which mutex is used by each pipepline */
+static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
+ [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
+ [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
+ [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -334,6 +369,10 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_sof = mt8183_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+ .mutex_mdp_offset = mt8183_mutex_mdp_offset,
+ .mutex_mdp_mod = mt8183_mutex_mdp_mod,
+ .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
};
@@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id)
+{
+ struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
+ int i = mtx->data->mutex_mdp_offset[id];
+
+ if (!mtx->mutex[i].claimed) {
+ mtx->mutex[i].claimed = true;
+ return &mtx->mutex[i];
+ }
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
+
void mtk_mutex_put(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
}
EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ if (mtx->data->mutex_mdp_mod)
+ return mtx->data->mutex_mdp_mod[id];
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 6fe4ffbde290..b2608f4220ee 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -11,9 +11,12 @@ struct device;
struct mtk_mutex;
struct mtk_mutex *mtk_mutex_get(struct device *dev);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id);
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
void mtk_mutex_enable(struct mtk_mutex *mutex);
void mtk_mutex_disable(struct mtk_mutex *mutex);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
For the purpose of module independence, related settings should be moved
from MDP to the corresponding driver.
This patch adds more 8183 MDP settings and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mutex.c | 68 ++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-mutex.h | 3 ++
2 files changed, 71 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..a6268ecde240 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -136,6 +136,18 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_MDP_START 5
+#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
+#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2)
+#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4)
+#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5)
+#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6)
+#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7)
+#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8)
+#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
+#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -156,6 +168,10 @@ struct mtk_mutex_data {
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
+ const unsigned int *mutex_mdp_offset;
+ const unsigned int *mutex_mdp_mod;
+ const unsigned int mutex_mdp_mod_mask;
+ const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
};
@@ -243,6 +259,17 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8183_mutex_mdp_mod[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
+ [MDP_COMP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
+ [MDP_COMP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
+ [MDP_COMP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
+ [MDP_COMP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
+ [MDP_COMP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
+ [MDP_COMP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
+ [MDP_COMP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
+};
+
static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
@@ -300,6 +327,14 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/* indicate which mutex is used by each pipepline */
+static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
+ [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
+ [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
+ [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -334,6 +369,10 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_sof = mt8183_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+ .mutex_mdp_offset = mt8183_mutex_mdp_offset,
+ .mutex_mdp_mod = mt8183_mutex_mdp_mod,
+ .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
};
@@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id)
+{
+ struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
+ int i = mtx->data->mutex_mdp_offset[id];
+
+ if (!mtx->mutex[i].claimed) {
+ mtx->mutex[i].claimed = true;
+ return &mtx->mutex[i];
+ }
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
+
void mtk_mutex_put(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
}
EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ if (mtx->data->mutex_mdp_mod)
+ return mtx->data->mutex_mdp_mod[id];
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 6fe4ffbde290..b2608f4220ee 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -11,9 +11,12 @@ struct device;
struct mtk_mutex;
struct mtk_mutex *mtk_mutex_get(struct device *dev);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id);
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
void mtk_mutex_enable(struct mtk_mutex *mutex);
void mtk_mutex_disable(struct mtk_mutex *mutex);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
2022-03-01 10:02 ` Moudy Ho
(?)
@ 2022-03-03 9:33 ` CK Hu
-1 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 9:33 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> For the purpose of module independence, related settings should be
> moved
> from MDP to the corresponding driver.
> This patch adds more 8183 MDP settings and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 68
> ++++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-mutex.h | 3 ++
> 2 files changed, 71 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..a6268ecde240 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -136,6 +136,18 @@
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_S
> OF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_S
> OF_DPI0 << 6)
>
> +#define MT8183_MUTEX_MDP_START 5
> +#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
> +#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
> +#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2)
> +#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4)
> +#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5)
> +#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6)
> +#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7)
> +#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8)
> +#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
> +#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -156,6 +168,10 @@ struct mtk_mutex_data {
> const unsigned int *mutex_sof;
> const unsigned int mutex_mod_reg;
> const unsigned int mutex_sof_reg;
> + const unsigned int *mutex_mdp_offset;
> + const unsigned int *mutex_mdp_mod;
> + const unsigned int mutex_mdp_mod_mask;
Useless, so remove this.
> + const unsigned int mutex_mdp_sof_mask;
Useless, so remove this.
> const bool no_clk;
> };
>
> @@ -243,6 +259,17 @@ static const unsigned int
> mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> +static const unsigned int mt8183_mutex_mdp_mod[MDP_MAX_COMP_COUNT] =
> {
> + [MDP_COMP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
> + [MDP_COMP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
> + [MDP_COMP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
> + [MDP_COMP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
> + [MDP_COMP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
> + [MDP_COMP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
> + [MDP_COMP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
> + [MDP_COMP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
> +};
> +
> static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> @@ -300,6 +327,14 @@ static const unsigned int
> mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 |
> MT8186_MUTEX_EOF_DPI0,
> };
>
> +/* indicate which mutex is used by each pipepline */
> +static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
> + [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> + [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> + [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> + [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -334,6 +369,10 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .mutex_sof = mt8183_mutex_sof,
> .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .mutex_mdp_offset = mt8183_mutex_mdp_offset,
> + .mutex_mdp_mod = mt8183_mutex_mdp_mod,
> + .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> + .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> };
>
> @@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device
> *dev)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get);
>
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id)
For DRM, mutex id does not physically bound to specific hardware, why
do MDP need the pipeline id?
Regards,
CK
> +{
> + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> + int i = mtx->data->mutex_mdp_offset[id];
> +
> + if (!mtx->mutex[i].claimed) {
> + mtx->mutex[i].claimed = true;
> + return &mtx->mutex[i];
> + }
> +
> + return ERR_PTR(-EBUSY);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> +
> void mtk_mutex_put(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex
> *mutex,
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
>
> +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + if (mtx->data->mutex_mdp_mod)
> + return mtx->data->mutex_mdp_mod[id];
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
> +
> void mtk_mutex_enable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index 6fe4ffbde290..b2608f4220ee 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -11,9 +11,12 @@ struct device;
> struct mtk_mutex;
>
> struct mtk_mutex *mtk_mutex_get(struct device *dev);
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id);
> int mtk_mutex_prepare(struct mtk_mutex *mutex);
> void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> void mtk_mutex_disable(struct mtk_mutex *mutex);
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
@ 2022-03-03 9:33 ` CK Hu
0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 9:33 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> For the purpose of module independence, related settings should be
> moved
> from MDP to the corresponding driver.
> This patch adds more 8183 MDP settings and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 68
> ++++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-mutex.h | 3 ++
> 2 files changed, 71 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..a6268ecde240 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -136,6 +136,18 @@
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_S
> OF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_S
> OF_DPI0 << 6)
>
> +#define MT8183_MUTEX_MDP_START 5
> +#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
> +#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
> +#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2)
> +#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4)
> +#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5)
> +#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6)
> +#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7)
> +#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8)
> +#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
> +#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -156,6 +168,10 @@ struct mtk_mutex_data {
> const unsigned int *mutex_sof;
> const unsigned int mutex_mod_reg;
> const unsigned int mutex_sof_reg;
> + const unsigned int *mutex_mdp_offset;
> + const unsigned int *mutex_mdp_mod;
> + const unsigned int mutex_mdp_mod_mask;
Useless, so remove this.
> + const unsigned int mutex_mdp_sof_mask;
Useless, so remove this.
> const bool no_clk;
> };
>
> @@ -243,6 +259,17 @@ static const unsigned int
> mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> +static const unsigned int mt8183_mutex_mdp_mod[MDP_MAX_COMP_COUNT] =
> {
> + [MDP_COMP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
> + [MDP_COMP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
> + [MDP_COMP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
> + [MDP_COMP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
> + [MDP_COMP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
> + [MDP_COMP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
> + [MDP_COMP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
> + [MDP_COMP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
> +};
> +
> static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> @@ -300,6 +327,14 @@ static const unsigned int
> mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 |
> MT8186_MUTEX_EOF_DPI0,
> };
>
> +/* indicate which mutex is used by each pipepline */
> +static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
> + [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> + [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> + [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> + [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -334,6 +369,10 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .mutex_sof = mt8183_mutex_sof,
> .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .mutex_mdp_offset = mt8183_mutex_mdp_offset,
> + .mutex_mdp_mod = mt8183_mutex_mdp_mod,
> + .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> + .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> };
>
> @@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device
> *dev)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get);
>
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id)
For DRM, mutex id does not physically bound to specific hardware, why
do MDP need the pipeline id?
Regards,
CK
> +{
> + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> + int i = mtx->data->mutex_mdp_offset[id];
> +
> + if (!mtx->mutex[i].claimed) {
> + mtx->mutex[i].claimed = true;
> + return &mtx->mutex[i];
> + }
> +
> + return ERR_PTR(-EBUSY);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> +
> void mtk_mutex_put(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex
> *mutex,
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
>
> +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + if (mtx->data->mutex_mdp_mod)
> + return mtx->data->mutex_mdp_mod[id];
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
> +
> void mtk_mutex_enable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index 6fe4ffbde290..b2608f4220ee 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -11,9 +11,12 @@ struct device;
> struct mtk_mutex;
>
> struct mtk_mutex *mtk_mutex_get(struct device *dev);
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id);
> int mtk_mutex_prepare(struct mtk_mutex *mutex);
> void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> void mtk_mutex_disable(struct mtk_mutex *mutex);
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
@ 2022-03-03 9:33 ` CK Hu
0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 9:33 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> For the purpose of module independence, related settings should be
> moved
> from MDP to the corresponding driver.
> This patch adds more 8183 MDP settings and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 68
> ++++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-mutex.h | 3 ++
> 2 files changed, 71 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..a6268ecde240 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -136,6 +136,18 @@
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_S
> OF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_S
> OF_DPI0 << 6)
>
> +#define MT8183_MUTEX_MDP_START 5
> +#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
> +#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
> +#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2)
> +#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4)
> +#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5)
> +#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6)
> +#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7)
> +#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8)
> +#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
> +#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -156,6 +168,10 @@ struct mtk_mutex_data {
> const unsigned int *mutex_sof;
> const unsigned int mutex_mod_reg;
> const unsigned int mutex_sof_reg;
> + const unsigned int *mutex_mdp_offset;
> + const unsigned int *mutex_mdp_mod;
> + const unsigned int mutex_mdp_mod_mask;
Useless, so remove this.
> + const unsigned int mutex_mdp_sof_mask;
Useless, so remove this.
> const bool no_clk;
> };
>
> @@ -243,6 +259,17 @@ static const unsigned int
> mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> +static const unsigned int mt8183_mutex_mdp_mod[MDP_MAX_COMP_COUNT] =
> {
> + [MDP_COMP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
> + [MDP_COMP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
> + [MDP_COMP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
> + [MDP_COMP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
> + [MDP_COMP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
> + [MDP_COMP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
> + [MDP_COMP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
> + [MDP_COMP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
> +};
> +
> static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> @@ -300,6 +327,14 @@ static const unsigned int
> mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 |
> MT8186_MUTEX_EOF_DPI0,
> };
>
> +/* indicate which mutex is used by each pipepline */
> +static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
> + [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> + [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> + [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> + [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -334,6 +369,10 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .mutex_sof = mt8183_mutex_sof,
> .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .mutex_mdp_offset = mt8183_mutex_mdp_offset,
> + .mutex_mdp_mod = mt8183_mutex_mdp_mod,
> + .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> + .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> };
>
> @@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device
> *dev)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get);
>
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id)
For DRM, mutex id does not physically bound to specific hardware, why
do MDP need the pipeline id?
Regards,
CK
> +{
> + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> + int i = mtx->data->mutex_mdp_offset[id];
> +
> + if (!mtx->mutex[i].claimed) {
> + mtx->mutex[i].claimed = true;
> + return &mtx->mutex[i];
> + }
> +
> + return ERR_PTR(-EBUSY);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> +
> void mtk_mutex_put(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex
> *mutex,
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
>
> +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + if (mtx->data->mutex_mdp_mod)
> + return mtx->data->mutex_mdp_mod[id];
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
> +
> void mtk_mutex_enable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index 6fe4ffbde290..b2608f4220ee 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -11,9 +11,12 @@ struct device;
> struct mtk_mutex;
>
> struct mtk_mutex *mtk_mutex_get(struct device *dev);
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id);
> int mtk_mutex_prepare(struct mtk_mutex *mutex);
> void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> void mtk_mutex_disable(struct mtk_mutex *mutex);
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
2022-03-03 9:33 ` CK Hu
@ 2022-03-09 9:14 ` moudy.ho
-1 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 9:14 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 17:33 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > For the purpose of module independence, related settings should be
> > moved
> > from MDP to the corresponding driver.
> > This patch adds more 8183 MDP settings and interface.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 68
> > ++++++++++++++++++++++++++
> > include/linux/soc/mediatek/mtk-mutex.h | 3 ++
> > 2 files changed, 71 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..a6268ecde240 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -136,6 +136,18 @@
(snip)
> > struct mtk_mutex {
> > int id;
> > bool claimed;
> > @@ -156,6 +168,10 @@ struct mtk_mutex_data {
> > const unsigned int *mutex_sof;
> > const unsigned int mutex_mod_reg;
> > const unsigned int mutex_sof_reg;
> > + const unsigned int *mutex_mdp_offset;
> > + const unsigned int *mutex_mdp_mod;
> > + const unsigned int mutex_mdp_mod_mask;
>
> Useless, so remove this.
>
> > + const unsigned int mutex_mdp_sof_mask;
>
> Useless, so remove this.
>
> > const bool no_clk;
> > };
> >
Hi CK,
Thanks for the suggestion, these two can indeed be removed and will be
fixed in the next version.
(snip)
> >
> > @@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device
> > *dev)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_get);
> >
> > +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> > + enum mtk_mdp_pipe_id id)
>
> For DRM, mutex id does not physically bound to specific hardware, why
> do MDP need the pipeline id?
>
> Regards,
> CK
In the next version I will remove this mandatory designation method and
change it to the existing API.
Thanks & Regrads,
Moudy Ho
> > +{
> > + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> > + int i = mtx->data->mutex_mdp_offset[id];
> > +
> > + if (!mtx->mutex[i].claimed) {
> > + mtx->mutex[i].claimed = true;
> > + return &mtx->mutex[i];
> > + }
> > +
> > + return ERR_PTR(-EBUSY);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> > +
> > void mtk_mutex_put(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex
> > *mutex,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
> >
> > +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> > mtk_mdp_comp_id id)
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + if (mtx->data->mutex_mdp_mod)
> > + return mtx->data->mutex_mdp_mod[id];
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
> > +
> > void mtk_mutex_enable(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> > b/include/linux/soc/mediatek/mtk-mutex.h
> > index 6fe4ffbde290..b2608f4220ee 100644
> > --- a/include/linux/soc/mediatek/mtk-mutex.h
> > +++ b/include/linux/soc/mediatek/mtk-mutex.h
> > @@ -11,9 +11,12 @@ struct device;
> > struct mtk_mutex;
> >
> > struct mtk_mutex *mtk_mutex_get(struct device *dev);
> > +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> > + enum mtk_mdp_pipe_id id);
> > int mtk_mutex_prepare(struct mtk_mutex *mutex);
> > void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> > mtk_mdp_comp_id id);
> > void mtk_mutex_enable(struct mtk_mutex *mutex);
> > void mtk_mutex_disable(struct mtk_mutex *mutex);
> > void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
>
>
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 3/4] soc: mediatek: mutex: add support for MDP
@ 2022-03-09 9:14 ` moudy.ho
0 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 9:14 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 17:33 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > For the purpose of module independence, related settings should be
> > moved
> > from MDP to the corresponding driver.
> > This patch adds more 8183 MDP settings and interface.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 68
> > ++++++++++++++++++++++++++
> > include/linux/soc/mediatek/mtk-mutex.h | 3 ++
> > 2 files changed, 71 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..a6268ecde240 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -136,6 +136,18 @@
(snip)
> > struct mtk_mutex {
> > int id;
> > bool claimed;
> > @@ -156,6 +168,10 @@ struct mtk_mutex_data {
> > const unsigned int *mutex_sof;
> > const unsigned int mutex_mod_reg;
> > const unsigned int mutex_sof_reg;
> > + const unsigned int *mutex_mdp_offset;
> > + const unsigned int *mutex_mdp_mod;
> > + const unsigned int mutex_mdp_mod_mask;
>
> Useless, so remove this.
>
> > + const unsigned int mutex_mdp_sof_mask;
>
> Useless, so remove this.
>
> > const bool no_clk;
> > };
> >
Hi CK,
Thanks for the suggestion, these two can indeed be removed and will be
fixed in the next version.
(snip)
> >
> > @@ -366,6 +405,21 @@ struct mtk_mutex *mtk_mutex_get(struct device
> > *dev)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_get);
> >
> > +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> > + enum mtk_mdp_pipe_id id)
>
> For DRM, mutex id does not physically bound to specific hardware, why
> do MDP need the pipeline id?
>
> Regards,
> CK
In the next version I will remove this mandatory designation method and
change it to the existing API.
Thanks & Regrads,
Moudy Ho
> > +{
> > + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> > + int i = mtx->data->mutex_mdp_offset[id];
> > +
> > + if (!mtx->mutex[i].claimed) {
> > + mtx->mutex[i].claimed = true;
> > + return &mtx->mutex[i];
> > + }
> > +
> > + return ERR_PTR(-EBUSY);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> > +
> > void mtk_mutex_put(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -485,6 +539,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex
> > *mutex,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
> >
> > +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> > mtk_mdp_comp_id id)
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + if (mtx->data->mutex_mdp_mod)
> > + return mtx->data->mutex_mdp_mod[id];
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
> > +
> > void mtk_mutex_enable(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> > b/include/linux/soc/mediatek/mtk-mutex.h
> > index 6fe4ffbde290..b2608f4220ee 100644
> > --- a/include/linux/soc/mediatek/mtk-mutex.h
> > +++ b/include/linux/soc/mediatek/mtk-mutex.h
> > @@ -11,9 +11,12 @@ struct device;
> > struct mtk_mutex;
> >
> > struct mtk_mutex *mtk_mutex_get(struct device *dev);
> > +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> > + enum mtk_mdp_pipe_id id);
> > int mtk_mutex_prepare(struct mtk_mutex *mutex);
> > void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > +u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> > mtk_mdp_comp_id id);
> > void mtk_mutex_enable(struct mtk_mutex *mutex);
> > void mtk_mutex_disable(struct mtk_mutex *mutex);
> > void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
2022-03-01 10:02 ` Moudy Ho
(?)
@ 2022-03-01 10:02 ` Moudy Ho
-1 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Considering that some functions have timing requirements
in specific situation, this patch adds several interface that
operate registers by CMDQ.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mutex.c | 72 +++++++++++++++++++++++++-
include/linux/soc/mediatek/mtk-mutex.h | 6 +++
2 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index a6268ecde240..a45864183cd1 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -7,10 +7,14 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#define MTK_MUTEX_ENABLE BIT(0)
#define MT2701_MUTEX0_MOD0 0x2c
#define MT2701_MUTEX0_SOF0 0x30
@@ -173,6 +177,7 @@ struct mtk_mutex_data {
const unsigned int mutex_mdp_mod_mask;
const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
+ const bool has_gce_client_reg;
};
struct mtk_mutex_ctx {
@@ -181,6 +186,8 @@ struct mtk_mutex_ctx {
void __iomem *regs;
struct mtk_mutex mutex[10];
const struct mtk_mutex_data *data;
+ phys_addr_t addr;
+ struct cmdq_client_reg cmdq_reg;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -374,6 +381,7 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
.mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
+ .has_gce_client_reg = true,
};
static const struct mtk_mutex_data mt8186_mutex_driver_data = {
@@ -553,6 +561,25 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+ unsigned int offset;
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ mod, mtx->data->mutex_mdp_mod_mask);
+
+ offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ 0, mtx->data->mutex_mdp_sof_mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_enable);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
+
void mtk_mutex_disable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_disable);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x0, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
+
void mtk_mutex_acquire(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_mutex_ctx *mtx;
- struct resource *regs;
- int i;
+ struct resource *regs, addr;
+ int i, ret;
mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
if (!mtx)
@@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct platform_device *pdev)
}
}
+ if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
+ mtx->addr = 0L;
+ else
+ mtx->addr = addr.start;
+
+ if (mtx->data->has_gce_client_reg) {
+ ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
+ if (ret) {
+ dev_err(dev, "No mediatek,gce-client-reg!\n");
+ return ret;
+ }
+ }
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtx->regs = devm_ioremap_resource(dev, regs);
if (IS_ERR(mtx->regs)) {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index b2608f4220ee..05de7ad4a124 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_disable(struct mtk_mutex *mutex);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
--
2.18.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Considering that some functions have timing requirements
in specific situation, this patch adds several interface that
operate registers by CMDQ.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mutex.c | 72 +++++++++++++++++++++++++-
include/linux/soc/mediatek/mtk-mutex.h | 6 +++
2 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index a6268ecde240..a45864183cd1 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -7,10 +7,14 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#define MTK_MUTEX_ENABLE BIT(0)
#define MT2701_MUTEX0_MOD0 0x2c
#define MT2701_MUTEX0_SOF0 0x30
@@ -173,6 +177,7 @@ struct mtk_mutex_data {
const unsigned int mutex_mdp_mod_mask;
const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
+ const bool has_gce_client_reg;
};
struct mtk_mutex_ctx {
@@ -181,6 +186,8 @@ struct mtk_mutex_ctx {
void __iomem *regs;
struct mtk_mutex mutex[10];
const struct mtk_mutex_data *data;
+ phys_addr_t addr;
+ struct cmdq_client_reg cmdq_reg;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -374,6 +381,7 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
.mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
+ .has_gce_client_reg = true,
};
static const struct mtk_mutex_data mt8186_mutex_driver_data = {
@@ -553,6 +561,25 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+ unsigned int offset;
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ mod, mtx->data->mutex_mdp_mod_mask);
+
+ offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ 0, mtx->data->mutex_mdp_sof_mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_enable);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
+
void mtk_mutex_disable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_disable);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x0, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
+
void mtk_mutex_acquire(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_mutex_ctx *mtx;
- struct resource *regs;
- int i;
+ struct resource *regs, addr;
+ int i, ret;
mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
if (!mtx)
@@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct platform_device *pdev)
}
}
+ if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
+ mtx->addr = 0L;
+ else
+ mtx->addr = addr.start;
+
+ if (mtx->data->has_gce_client_reg) {
+ ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
+ if (ret) {
+ dev_err(dev, "No mediatek,gce-client-reg!\n");
+ return ret;
+ }
+ }
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtx->regs = devm_ioremap_resource(dev, regs);
if (IS_ERR(mtx->regs)) {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index b2608f4220ee..05de7ad4a124 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_disable(struct mtk_mutex *mutex);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
@ 2022-03-01 10:02 ` Moudy Ho
0 siblings, 0 replies; 36+ messages in thread
From: Moudy Ho @ 2022-03-01 10:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Considering that some functions have timing requirements
in specific situation, this patch adds several interface that
operate registers by CMDQ.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mutex.c | 72 +++++++++++++++++++++++++-
include/linux/soc/mediatek/mtk-mutex.h | 6 +++
2 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index a6268ecde240..a45864183cd1 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -7,10 +7,14 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#define MTK_MUTEX_ENABLE BIT(0)
#define MT2701_MUTEX0_MOD0 0x2c
#define MT2701_MUTEX0_SOF0 0x30
@@ -173,6 +177,7 @@ struct mtk_mutex_data {
const unsigned int mutex_mdp_mod_mask;
const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
+ const bool has_gce_client_reg;
};
struct mtk_mutex_ctx {
@@ -181,6 +186,8 @@ struct mtk_mutex_ctx {
void __iomem *regs;
struct mtk_mutex mutex[10];
const struct mtk_mutex_data *data;
+ phys_addr_t addr;
+ struct cmdq_client_reg cmdq_reg;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -374,6 +381,7 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
.mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
+ .has_gce_client_reg = true,
};
static const struct mtk_mutex_data mt8186_mutex_driver_data = {
@@ -553,6 +561,25 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+ unsigned int offset;
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ mod, mtx->data->mutex_mdp_mod_mask);
+
+ offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ 0, mtx->data->mutex_mdp_sof_mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_enable);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
+
void mtk_mutex_disable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_disable);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x0, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
+
void mtk_mutex_acquire(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_mutex_ctx *mtx;
- struct resource *regs;
- int i;
+ struct resource *regs, addr;
+ int i, ret;
mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
if (!mtx)
@@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct platform_device *pdev)
}
}
+ if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
+ mtx->addr = 0L;
+ else
+ mtx->addr = addr.start;
+
+ if (mtx->data->has_gce_client_reg) {
+ ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
+ if (ret) {
+ dev_err(dev, "No mediatek,gce-client-reg!\n");
+ return ret;
+ }
+ }
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtx->regs = devm_ioremap_resource(dev, regs);
if (IS_ERR(mtx->regs)) {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index b2608f4220ee..05de7ad4a124 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_disable(struct mtk_mutex *mutex);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
2022-03-01 10:02 ` Moudy Ho
(?)
@ 2022-03-03 10:01 ` CK Hu
-1 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 10:01 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> Considering that some functions have timing requirements
> in specific situation, this patch adds several interface that
> operate registers by CMDQ.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 72
> +++++++++++++++++++++++++-
> include/linux/soc/mediatek/mtk-mutex.h | 6 +++
> 2 files changed, 76 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index a6268ecde240..a45864183cd1 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -7,10 +7,14 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> #include <linux/soc/mediatek/mtk-mutex.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#define MTK_MUTEX_ENABLE BIT(0)
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> @@ -173,6 +177,7 @@ struct mtk_mutex_data {
> const unsigned int mutex_mdp_mod_mask;
> const unsigned int mutex_mdp_sof_mask;
> const bool no_clk;
> + const bool has_gce_client_reg;
> };
>
> struct mtk_mutex_ctx {
> @@ -181,6 +186,8 @@ struct mtk_mutex_ctx {
> void __iomem *regs;
> struct mtk_mutex mutex[10];
> const struct mtk_mutex_data *data;
> + phys_addr_t addr;
> + struct cmdq_client_reg cmdq_reg;
> };
>
> static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -374,6 +381,7 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> + .has_gce_client_reg = true,
> };
>
> static const struct mtk_mutex_data mt8186_mutex_driver_data = {
> @@ -553,6 +561,25 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex
> *mutex, enum mtk_mdp_comp_id id)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
>
> +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> + unsigned int offset;
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + mod, mtx->data->mutex_mdp_mod_mask);
> +
> + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + 0, mtx->data->mutex_mdp_sof_mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
> +
> void mtk_mutex_enable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_enable);
>
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
There are 10 mutex and you could bind each pipeline to one mutex and
always enable it. I think it's not necessary to frequently
enable/disable mutex.
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> +
> void mtk_mutex_disable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_disable);
>
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x0, MTK_MUTEX_ENABLE);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> +
> void mtk_mutex_acquire(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct platform_device
> *pdev)
> {
> struct device *dev = &pdev->dev;
> struct mtk_mutex_ctx *mtx;
> - struct resource *regs;
> - int i;
> + struct resource *regs, addr;
> + int i, ret;
>
> mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> if (!mtx)
> @@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct
> platform_device *pdev)
> }
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> + mtx->addr = 0L;
> + else
> + mtx->addr = addr.start;
> +
> + if (mtx->data->has_gce_client_reg) {
> + ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
Add gce client reg in binding document [1]
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml?h=next-20220302
Regards,
CK
> + if (ret) {
> + dev_err(dev, "No mediatek,gce-client-reg!\n");
> + return ret;
> + }
> + }
> +
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> mtx->regs = devm_ioremap_resource(dev, regs);
> if (IS_ERR(mtx->regs)) {
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index b2608f4220ee..05de7ad4a124 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
> void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_disable(struct mtk_mutex *mutex);
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> void mtk_mutex_unprepare(struct mtk_mutex *mutex);
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
@ 2022-03-03 10:01 ` CK Hu
0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 10:01 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> Considering that some functions have timing requirements
> in specific situation, this patch adds several interface that
> operate registers by CMDQ.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 72
> +++++++++++++++++++++++++-
> include/linux/soc/mediatek/mtk-mutex.h | 6 +++
> 2 files changed, 76 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index a6268ecde240..a45864183cd1 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -7,10 +7,14 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> #include <linux/soc/mediatek/mtk-mutex.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#define MTK_MUTEX_ENABLE BIT(0)
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> @@ -173,6 +177,7 @@ struct mtk_mutex_data {
> const unsigned int mutex_mdp_mod_mask;
> const unsigned int mutex_mdp_sof_mask;
> const bool no_clk;
> + const bool has_gce_client_reg;
> };
>
> struct mtk_mutex_ctx {
> @@ -181,6 +186,8 @@ struct mtk_mutex_ctx {
> void __iomem *regs;
> struct mtk_mutex mutex[10];
> const struct mtk_mutex_data *data;
> + phys_addr_t addr;
> + struct cmdq_client_reg cmdq_reg;
> };
>
> static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -374,6 +381,7 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> + .has_gce_client_reg = true,
> };
>
> static const struct mtk_mutex_data mt8186_mutex_driver_data = {
> @@ -553,6 +561,25 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex
> *mutex, enum mtk_mdp_comp_id id)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
>
> +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> + unsigned int offset;
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + mod, mtx->data->mutex_mdp_mod_mask);
> +
> + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + 0, mtx->data->mutex_mdp_sof_mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
> +
> void mtk_mutex_enable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_enable);
>
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
There are 10 mutex and you could bind each pipeline to one mutex and
always enable it. I think it's not necessary to frequently
enable/disable mutex.
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> +
> void mtk_mutex_disable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_disable);
>
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x0, MTK_MUTEX_ENABLE);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> +
> void mtk_mutex_acquire(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct platform_device
> *pdev)
> {
> struct device *dev = &pdev->dev;
> struct mtk_mutex_ctx *mtx;
> - struct resource *regs;
> - int i;
> + struct resource *regs, addr;
> + int i, ret;
>
> mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> if (!mtx)
> @@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct
> platform_device *pdev)
> }
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> + mtx->addr = 0L;
> + else
> + mtx->addr = addr.start;
> +
> + if (mtx->data->has_gce_client_reg) {
> + ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
Add gce client reg in binding document [1]
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml?h=next-20220302
Regards,
CK
> + if (ret) {
> + dev_err(dev, "No mediatek,gce-client-reg!\n");
> + return ret;
> + }
> + }
> +
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> mtx->regs = devm_ioremap_resource(dev, regs);
> if (IS_ERR(mtx->regs)) {
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index b2608f4220ee..05de7ad4a124 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
> void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_disable(struct mtk_mutex *mutex);
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> void mtk_mutex_unprepare(struct mtk_mutex *mutex);
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
@ 2022-03-03 10:01 ` CK Hu
0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2022-03-03 10:01 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi, Moudy:
On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> Considering that some functions have timing requirements
> in specific situation, this patch adds several interface that
> operate registers by CMDQ.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 72
> +++++++++++++++++++++++++-
> include/linux/soc/mediatek/mtk-mutex.h | 6 +++
> 2 files changed, 76 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index a6268ecde240..a45864183cd1 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -7,10 +7,14 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> #include <linux/soc/mediatek/mtk-mutex.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#define MTK_MUTEX_ENABLE BIT(0)
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> @@ -173,6 +177,7 @@ struct mtk_mutex_data {
> const unsigned int mutex_mdp_mod_mask;
> const unsigned int mutex_mdp_sof_mask;
> const bool no_clk;
> + const bool has_gce_client_reg;
> };
>
> struct mtk_mutex_ctx {
> @@ -181,6 +186,8 @@ struct mtk_mutex_ctx {
> void __iomem *regs;
> struct mtk_mutex mutex[10];
> const struct mtk_mutex_data *data;
> + phys_addr_t addr;
> + struct cmdq_client_reg cmdq_reg;
> };
>
> static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -374,6 +381,7 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> + .has_gce_client_reg = true,
> };
>
> static const struct mtk_mutex_data mt8186_mutex_driver_data = {
> @@ -553,6 +561,25 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex
> *mutex, enum mtk_mdp_comp_id id)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
>
> +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> + unsigned int offset;
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + mod, mtx->data->mutex_mdp_mod_mask);
> +
> + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + 0, mtx->data->mutex_mdp_sof_mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
> +
> void mtk_mutex_enable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_enable);
>
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
There are 10 mutex and you could bind each pipeline to one mutex and
always enable it. I think it's not necessary to frequently
enable/disable mutex.
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> +
> void mtk_mutex_disable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_disable);
>
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x0, MTK_MUTEX_ENABLE);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> +
> void mtk_mutex_acquire(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> @@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct platform_device
> *pdev)
> {
> struct device *dev = &pdev->dev;
> struct mtk_mutex_ctx *mtx;
> - struct resource *regs;
> - int i;
> + struct resource *regs, addr;
> + int i, ret;
>
> mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> if (!mtx)
> @@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct
> platform_device *pdev)
> }
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> + mtx->addr = 0L;
> + else
> + mtx->addr = addr.start;
> +
> + if (mtx->data->has_gce_client_reg) {
> + ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
Add gce client reg in binding document [1]
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml?h=next-20220302
Regards,
CK
> + if (ret) {
> + dev_err(dev, "No mediatek,gce-client-reg!\n");
> + return ret;
> + }
> + }
> +
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> mtx->regs = devm_ioremap_resource(dev, regs);
> if (IS_ERR(mtx->regs)) {
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index b2608f4220ee..05de7ad4a124 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
> void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_disable(struct mtk_mutex *mutex);
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> void mtk_mutex_unprepare(struct mtk_mutex *mutex);
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
2022-03-03 10:01 ` CK Hu
@ 2022-03-09 9:29 ` moudy.ho
-1 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 9:29 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 18:01 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > Considering that some functions have timing requirements
> > in specific situation, this patch adds several interface that
> > operate registers by CMDQ.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 72
> > +++++++++++++++++++++++++-
> > include/linux/soc/mediatek/mtk-mutex.h | 6 +++
> > 2 files changed, 76 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index a6268ecde240..a45864183cd1 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -7,10 +7,14 @@
(snip)
> > +
> > void mtk_mutex_enable(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_enable);
> >
> > +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd)
>
> There are 10 mutex and you could bind each pipeline to one mutex and
> always enable it. I think it's not necessary to frequently
> enable/disable mutex.
Hi CK,
Due to HW limitations, MDP is necessary to enable MUTEX in each frame
for SOF triggering and cooperate with CMDQ control to reduce the amount
of interrupts generated(also, reduce frame latency).
Thanks & Regards,
Moudy Ho
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> > + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> > + MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> > +
> > void mtk_mutex_disable(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex
> > *mutex)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_disable);
> >
> > +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd)
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> > + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> > + 0x0, MTK_MUTEX_ENABLE);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> > +
> > void mtk_mutex_acquire(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct
> > platform_device
> > *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > struct mtk_mutex_ctx *mtx;
> > - struct resource *regs;
> > - int i;
> > + struct resource *regs, addr;
> > + int i, ret;
> >
> > mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> > if (!mtx)
> > @@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct
> > platform_device *pdev)
> > }
> > }
> >
> > + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> > + mtx->addr = 0L;
> > + else
> > + mtx->addr = addr.start;
> > +
> > + if (mtx->data->has_gce_client_reg) {
> > + ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
>
> Add gce client reg in binding document [1]
>
> [1]
>
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml?h=next-20220302
>
> Regards,
> CK
Thanks for the reminder, I will fill in the missing parts in the next
version.
> > + if (ret) {
> > + dev_err(dev, "No mediatek,gce-client-reg!\n");
> > + return ret;
> > + }
> > + }
> > +
> > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > mtx->regs = devm_ioremap_resource(dev, regs);
> > if (IS_ERR(mtx->regs)) {
> > diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> > b/include/linux/soc/mediatek/mtk-mutex.h
> > index b2608f4220ee..05de7ad4a124 100644
> > --- a/include/linux/soc/mediatek/mtk-mutex.h
> > +++ b/include/linux/soc/mediatek/mtk-mutex.h
> > @@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
> > void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> > mtk_mdp_comp_id id);
> > +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_enable(struct mtk_mutex *mutex);
> > +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_disable(struct mtk_mutex *mutex);
> > +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > void mtk_mutex_unprepare(struct mtk_mutex *mutex);
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v12 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
@ 2022-03-09 9:29 ` moudy.ho
0 siblings, 0 replies; 36+ messages in thread
From: moudy.ho @ 2022-03-09 9:29 UTC (permalink / raw)
To: CK Hu, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-03-03 at 18:01 +0800, CK Hu wrote:
> Hi, Moudy:
>
> On Tue, 2022-03-01 at 18:02 +0800, Moudy Ho wrote:
> > Considering that some functions have timing requirements
> > in specific situation, this patch adds several interface that
> > operate registers by CMDQ.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 72
> > +++++++++++++++++++++++++-
> > include/linux/soc/mediatek/mtk-mutex.h | 6 +++
> > 2 files changed, 76 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index a6268ecde240..a45864183cd1 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -7,10 +7,14 @@
(snip)
> > +
> > void mtk_mutex_enable(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -564,6 +591,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_enable);
> >
> > +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd)
>
> There are 10 mutex and you could bind each pipeline to one mutex and
> always enable it. I think it's not necessary to frequently
> enable/disable mutex.
Hi CK,
Due to HW limitations, MDP is necessary to enable MUTEX in each frame
for SOF triggering and cooperate with CMDQ control to reduce the amount
of interrupts generated(also, reduce frame latency).
Thanks & Regards,
Moudy Ho
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> > + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> > + MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> > +
> > void mtk_mutex_disable(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -575,6 +616,20 @@ void mtk_mutex_disable(struct mtk_mutex
> > *mutex)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_disable);
> >
> > +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd)
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys,
> > + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> > + 0x0, MTK_MUTEX_ENABLE);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> > +
> > void mtk_mutex_acquire(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -602,8 +657,8 @@ static int mtk_mutex_probe(struct
> > platform_device
> > *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > struct mtk_mutex_ctx *mtx;
> > - struct resource *regs;
> > - int i;
> > + struct resource *regs, addr;
> > + int i, ret;
> >
> > mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> > if (!mtx)
> > @@ -623,6 +678,19 @@ static int mtk_mutex_probe(struct
> > platform_device *pdev)
> > }
> > }
> >
> > + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> > + mtx->addr = 0L;
> > + else
> > + mtx->addr = addr.start;
> > +
> > + if (mtx->data->has_gce_client_reg) {
> > + ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
>
> Add gce client reg in binding document [1]
>
> [1]
>
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml?h=next-20220302
>
> Regards,
> CK
Thanks for the reminder, I will fill in the missing parts in the next
version.
> > + if (ret) {
> > + dev_err(dev, "No mediatek,gce-client-reg!\n");
> > + return ret;
> > + }
> > + }
> > +
> > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > mtx->regs = devm_ioremap_resource(dev, regs);
> > if (IS_ERR(mtx->regs)) {
> > diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> > b/include/linux/soc/mediatek/mtk-mutex.h
> > index b2608f4220ee..05de7ad4a124 100644
> > --- a/include/linux/soc/mediatek/mtk-mutex.h
> > +++ b/include/linux/soc/mediatek/mtk-mutex.h
> > @@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
> > void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> > mtk_mdp_comp_id id);
> > +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_enable(struct mtk_mutex *mutex);
> > +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_disable(struct mtk_mutex *mutex);
> > +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > void mtk_mutex_unprepare(struct mtk_mutex *mutex);
>
>
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