* [PATCH v6 00/13] qcom: Add support for GDSCs
@ 2015-07-22 7:10 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
GDSCs (Global Distributed Switch Controllers) control switches
that supply power to an on-chip power domain and hence can be
programmed in SW to safely power collapse and restore power to the
respective PDs. They are part of a considerable number of recent QCOM
SoCs (This series adds support for msm8974, msm8916 and apq8084 devices)
and are part of the Clock control block.
The series implements support for GDSC using the genpd framework
modelling these as SW controllable power domains and uses PM clocks
to control clocks within the gdsc.
* Client drivers which plan to use GDSC can refer to
Documentation/devicetree/bindings/power/power_domain.txt to know
how to hook up the power domain for the device through DT
* Runtime PM specific documentation can be found in
Documentation/power/runtime_pm.txt
* Patches are based of 4.2-rc3
Changes since v5:
* Added support to manage clocks with !CONFIG_PM
* Added RET/OFF support
* Added support to assert/deassert reset while the GDSC is ON
Changes since v4:
* Added clock control support using PM clocks
* Included WA to enable an RCG (needed for Oxili gdsc in 8916)
Changes since v3:
* static inline'd gdsc_register/unregister stubs
* error check fixes in gdsc_register
* dropped oxili_gdsc for 8916 as its broken and needs additional
WA's not part of this series
* split dts and driver changes into seperate patches
* Updated and included Stephanes patch to add gdscs to apq8084 mmcc
in the series
Changes since v2:
* gdsc_unregister added
* gdsc_register/unregister introduced in patch 1/6
Changes since v1:
* added err checks for regmap apis
* added gdsc_register() in gdsc.c
Rajendra Nayak (9):
clk: qcom: gdsc: Prepare common clk probe to register gdscs
clk: qcom: gdsc: Use PM clocks to control gdsc clocks
clk: qcom: gdsc: Manage clocks with !CONFIG_PM
clk: qcom: gdsc: Enable an RCG before turing on the gdsc
clk: qcom: gdsc: Add support for Memory RET/OFF
clk: qcom: gdsc: Add support for ON only state
clk: qcom: gdsc: Add GDSCs in msm8916 GCC
clk: qcom: gdsc: Add GDSCs in apq8084 GCC
arm: dts: qcom: Add #power-domain-cells property
Stephane Viau (1):
clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
Stephen Boyd (3):
clk: qcom: Add support for GDSCs
clk: qcom: gdsc: Add GDSCs in msm8974 GCC
clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/common.c | 17 +-
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/gcc-apq8084.c | 42 ++++
drivers/clk/qcom/gcc-msm8916.c | 52 ++++
drivers/clk/qcom/gcc-msm8974.c | 15 ++
drivers/clk/qcom/gdsc.c | 343 ++++++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 72 ++++++
drivers/clk/qcom/mmcc-apq8084.c | 68 ++++-
drivers/clk/qcom/mmcc-msm8974.c | 72 ++++++
include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 +
include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 +
include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 +
include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 +
include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 +
19 files changed, 729 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/gdsc.c
create mode 100644 drivers/clk/qcom/gdsc.h
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 00/13] qcom: Add support for GDSCs
@ 2015-07-22 7:10 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: linux-arm-kernel
GDSCs (Global Distributed Switch Controllers) control switches
that supply power to an on-chip power domain and hence can be
programmed in SW to safely power collapse and restore power to the
respective PDs. They are part of a considerable number of recent QCOM
SoCs (This series adds support for msm8974, msm8916 and apq8084 devices)
and are part of the Clock control block.
The series implements support for GDSC using the genpd framework
modelling these as SW controllable power domains and uses PM clocks
to control clocks within the gdsc.
* Client drivers which plan to use GDSC can refer to
Documentation/devicetree/bindings/power/power_domain.txt to know
how to hook up the power domain for the device through DT
* Runtime PM specific documentation can be found in
Documentation/power/runtime_pm.txt
* Patches are based of 4.2-rc3
Changes since v5:
* Added support to manage clocks with !CONFIG_PM
* Added RET/OFF support
* Added support to assert/deassert reset while the GDSC is ON
Changes since v4:
* Added clock control support using PM clocks
* Included WA to enable an RCG (needed for Oxili gdsc in 8916)
Changes since v3:
* static inline'd gdsc_register/unregister stubs
* error check fixes in gdsc_register
* dropped oxili_gdsc for 8916 as its broken and needs additional
WA's not part of this series
* split dts and driver changes into seperate patches
* Updated and included Stephanes patch to add gdscs to apq8084 mmcc
in the series
Changes since v2:
* gdsc_unregister added
* gdsc_register/unregister introduced in patch 1/6
Changes since v1:
* added err checks for regmap apis
* added gdsc_register() in gdsc.c
Rajendra Nayak (9):
clk: qcom: gdsc: Prepare common clk probe to register gdscs
clk: qcom: gdsc: Use PM clocks to control gdsc clocks
clk: qcom: gdsc: Manage clocks with !CONFIG_PM
clk: qcom: gdsc: Enable an RCG before turing on the gdsc
clk: qcom: gdsc: Add support for Memory RET/OFF
clk: qcom: gdsc: Add support for ON only state
clk: qcom: gdsc: Add GDSCs in msm8916 GCC
clk: qcom: gdsc: Add GDSCs in apq8084 GCC
arm: dts: qcom: Add #power-domain-cells property
Stephane Viau (1):
clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
Stephen Boyd (3):
clk: qcom: Add support for GDSCs
clk: qcom: gdsc: Add GDSCs in msm8974 GCC
clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/common.c | 17 +-
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/gcc-apq8084.c | 42 ++++
drivers/clk/qcom/gcc-msm8916.c | 52 ++++
drivers/clk/qcom/gcc-msm8974.c | 15 ++
drivers/clk/qcom/gdsc.c | 343 ++++++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 72 ++++++
drivers/clk/qcom/mmcc-apq8084.c | 68 ++++-
drivers/clk/qcom/mmcc-msm8974.c | 72 ++++++
include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 +
include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 +
include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 +
include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 +
include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 +
19 files changed, 729 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/gdsc.c
create mode 100644 drivers/clk/qcom/gdsc.h
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 01/13] clk: qcom: Add support for GDSCs
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:10 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
From: Stephen Boyd <sboyd@codeaurora.org>
GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller register
space, its best to have the support added through the clock driver.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 5 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gdsc.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 45 +++++++++++++
4 files changed, 218 insertions(+)
create mode 100644 drivers/clk/qcom/gdsc.c
create mode 100644 drivers/clk/qcom/gdsc.h
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 59d1666..a7c2eea 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -39,6 +39,11 @@ config IPQ_LCC_806X
Say Y if you want to use audio devices such as i2s, pcm,
S/PDIF, etc.
+config QCOM_GDSC
+ bool
+ select PM_GENERIC_DOMAINS if PM
+ depends on COMMON_CLK_QCOM
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 50b337a..fe62523 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += reset.o
+clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
new file mode 100644
index 0000000..a59655b
--- /dev/null
+++ b/drivers/clk/qcom/gdsc.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include "gdsc.h"
+
+#define PWR_ON_MASK BIT(31)
+#define EN_REST_WAIT_MASK GENMASK(23, 20)
+#define EN_FEW_WAIT_MASK GENMASK(19, 16)
+#define CLK_DIS_WAIT_MASK GENMASK(15, 12)
+#define SW_OVERRIDE_MASK BIT(2)
+#define HW_CONTROL_MASK BIT(1)
+#define SW_COLLAPSE_MASK BIT(0)
+
+/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
+#define EN_REST_WAIT_VAL (0x2 << 20)
+#define EN_FEW_WAIT_VAL (0x8 << 16)
+#define CLK_DIS_WAIT_VAL (0x2 << 12)
+
+#define TIMEOUT_US 100
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+static int gdsc_is_enabled(struct gdsc *sc)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_read(sc->regmap, sc->gdscr, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & PWR_ON_MASK);
+}
+
+static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+{
+ int ret;
+ u32 val = en ? 0 : SW_COLLAPSE_MASK;
+ u32 check = en ? PWR_ON_MASK : 0;
+ unsigned long timeout;
+
+ ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
+ if (ret)
+ return ret;
+
+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+ do {
+ ret = regmap_read(sc->regmap, sc->gdscr, &val);
+ if (ret)
+ return ret;
+
+ if ((val & PWR_ON_MASK) == check)
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ ret = regmap_read(sc->regmap, sc->gdscr, &val);
+ if (ret)
+ return ret;
+
+ if ((val & PWR_ON_MASK) == check)
+ return 0;
+
+ return -ETIMEDOUT;
+}
+
+static int gdsc_enable(struct generic_pm_domain *domain)
+{
+ struct gdsc *sc = domain_to_gdsc(domain);
+ int ret;
+
+ ret = gdsc_toggle_logic(sc, true);
+ if (ret)
+ return ret;
+ /*
+ * If clocks to this power domain were already on, they will take an
+ * additional 4 clock cycles to re-enable after the power domain is
+ * enabled. Delay to account for this. A delay is also needed to ensure
+ * clocks are not enabled within 400ns of enabling power to the
+ * memories.
+ */
+ udelay(1);
+
+ return 0;
+}
+
+static int gdsc_disable(struct generic_pm_domain *domain)
+{
+ struct gdsc *sc = domain_to_gdsc(domain);
+
+ return gdsc_toggle_logic(sc, false);
+}
+
+static int gdsc_init(struct gdsc *sc)
+{
+ u32 mask, val;
+ int on, ret;
+
+ /*
+ * Disable HW trigger: collapse/restore occur based on registers writes.
+ * Disable SW override: Use hardware state-machine for sequencing.
+ * Configure wait time between states.
+ */
+ mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
+ EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
+ val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
+ ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
+ if (ret)
+ return ret;
+
+ on = gdsc_is_enabled(sc);
+ if (on < 0)
+ return on;
+
+ sc->pd.power_off = gdsc_disable;
+ sc->pd.power_on = gdsc_enable;
+ pm_genpd_init(&sc->pd, NULL, !on);
+
+ return 0;
+}
+
+int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
+ struct regmap *regmap)
+{
+ int i, ret;
+ struct genpd_onecell_data *data;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
+ GFP_KERNEL);
+ if (!data->domains)
+ return -ENOMEM;
+
+ data->num_domains = num;
+ for (i = 0; i < num; i++) {
+ if (!scs[i])
+ continue;
+ scs[i]->regmap = regmap;
+ ret = gdsc_init(scs[i]);
+ if (ret)
+ return ret;
+ data->domains[i] = &scs[i]->pd;
+ }
+
+ return of_genpd_add_provider_onecell(dev->of_node, data);
+}
+
+void gdsc_unregister(struct device *dev)
+{
+ of_genpd_del_provider(dev->of_node);
+}
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
new file mode 100644
index 0000000..e26a496
--- /dev/null
+++ b/drivers/clk/qcom/gdsc.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+#include <linux/regmap.h>
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * @pd: generic power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+ struct generic_pm_domain pd;
+ struct regmap *regmap;
+ unsigned int gdscr;
+};
+
+#ifdef CONFIG_QCOM_GDSC
+int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *);
+void gdsc_unregister(struct device *);
+#else
+static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
+ struct regmap *r)
+{
+ return -ENOSYS;
+}
+
+static inline void gdsc_unregister(struct device *d)
+{};
+#endif /* CONFIG_QCOM_GDSC */
+#endif /* __QCOM_GDSC_H__ */
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 01/13] clk: qcom: Add support for GDSCs
@ 2015-07-22 7:10 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Boyd <sboyd@codeaurora.org>
GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller register
space, its best to have the support added through the clock driver.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 5 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gdsc.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 45 +++++++++++++
4 files changed, 218 insertions(+)
create mode 100644 drivers/clk/qcom/gdsc.c
create mode 100644 drivers/clk/qcom/gdsc.h
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 59d1666..a7c2eea 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -39,6 +39,11 @@ config IPQ_LCC_806X
Say Y if you want to use audio devices such as i2s, pcm,
S/PDIF, etc.
+config QCOM_GDSC
+ bool
+ select PM_GENERIC_DOMAINS if PM
+ depends on COMMON_CLK_QCOM
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 50b337a..fe62523 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += reset.o
+clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
new file mode 100644
index 0000000..a59655b
--- /dev/null
+++ b/drivers/clk/qcom/gdsc.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include "gdsc.h"
+
+#define PWR_ON_MASK BIT(31)
+#define EN_REST_WAIT_MASK GENMASK(23, 20)
+#define EN_FEW_WAIT_MASK GENMASK(19, 16)
+#define CLK_DIS_WAIT_MASK GENMASK(15, 12)
+#define SW_OVERRIDE_MASK BIT(2)
+#define HW_CONTROL_MASK BIT(1)
+#define SW_COLLAPSE_MASK BIT(0)
+
+/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
+#define EN_REST_WAIT_VAL (0x2 << 20)
+#define EN_FEW_WAIT_VAL (0x8 << 16)
+#define CLK_DIS_WAIT_VAL (0x2 << 12)
+
+#define TIMEOUT_US 100
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+static int gdsc_is_enabled(struct gdsc *sc)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_read(sc->regmap, sc->gdscr, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & PWR_ON_MASK);
+}
+
+static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+{
+ int ret;
+ u32 val = en ? 0 : SW_COLLAPSE_MASK;
+ u32 check = en ? PWR_ON_MASK : 0;
+ unsigned long timeout;
+
+ ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
+ if (ret)
+ return ret;
+
+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+ do {
+ ret = regmap_read(sc->regmap, sc->gdscr, &val);
+ if (ret)
+ return ret;
+
+ if ((val & PWR_ON_MASK) == check)
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ ret = regmap_read(sc->regmap, sc->gdscr, &val);
+ if (ret)
+ return ret;
+
+ if ((val & PWR_ON_MASK) == check)
+ return 0;
+
+ return -ETIMEDOUT;
+}
+
+static int gdsc_enable(struct generic_pm_domain *domain)
+{
+ struct gdsc *sc = domain_to_gdsc(domain);
+ int ret;
+
+ ret = gdsc_toggle_logic(sc, true);
+ if (ret)
+ return ret;
+ /*
+ * If clocks to this power domain were already on, they will take an
+ * additional 4 clock cycles to re-enable after the power domain is
+ * enabled. Delay to account for this. A delay is also needed to ensure
+ * clocks are not enabled within 400ns of enabling power to the
+ * memories.
+ */
+ udelay(1);
+
+ return 0;
+}
+
+static int gdsc_disable(struct generic_pm_domain *domain)
+{
+ struct gdsc *sc = domain_to_gdsc(domain);
+
+ return gdsc_toggle_logic(sc, false);
+}
+
+static int gdsc_init(struct gdsc *sc)
+{
+ u32 mask, val;
+ int on, ret;
+
+ /*
+ * Disable HW trigger: collapse/restore occur based on registers writes.
+ * Disable SW override: Use hardware state-machine for sequencing.
+ * Configure wait time between states.
+ */
+ mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
+ EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
+ val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
+ ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
+ if (ret)
+ return ret;
+
+ on = gdsc_is_enabled(sc);
+ if (on < 0)
+ return on;
+
+ sc->pd.power_off = gdsc_disable;
+ sc->pd.power_on = gdsc_enable;
+ pm_genpd_init(&sc->pd, NULL, !on);
+
+ return 0;
+}
+
+int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
+ struct regmap *regmap)
+{
+ int i, ret;
+ struct genpd_onecell_data *data;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
+ GFP_KERNEL);
+ if (!data->domains)
+ return -ENOMEM;
+
+ data->num_domains = num;
+ for (i = 0; i < num; i++) {
+ if (!scs[i])
+ continue;
+ scs[i]->regmap = regmap;
+ ret = gdsc_init(scs[i]);
+ if (ret)
+ return ret;
+ data->domains[i] = &scs[i]->pd;
+ }
+
+ return of_genpd_add_provider_onecell(dev->of_node, data);
+}
+
+void gdsc_unregister(struct device *dev)
+{
+ of_genpd_del_provider(dev->of_node);
+}
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
new file mode 100644
index 0000000..e26a496
--- /dev/null
+++ b/drivers/clk/qcom/gdsc.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+#include <linux/regmap.h>
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * @pd: generic power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+ struct generic_pm_domain pd;
+ struct regmap *regmap;
+ unsigned int gdscr;
+};
+
+#ifdef CONFIG_QCOM_GDSC
+int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *);
+void gdsc_unregister(struct device *);
+#else
+static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
+ struct regmap *r)
+{
+ return -ENOSYS;
+}
+
+static inline void gdsc_unregister(struct device *d)
+{};
+#endif /* CONFIG_QCOM_GDSC */
+#endif /* __QCOM_GDSC_H__ */
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 02/13] clk: qcom: gdsc: Prepare common clk probe to register gdscs
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:10 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/common.c | 16 +++++++++++++++-
drivers/clk/qcom/common.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index f7101e3..2776679 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -21,6 +21,7 @@
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
+#include "gdsc.h"
struct qcom_cc {
struct qcom_reset_controller reset;
@@ -120,8 +121,20 @@ int qcom_cc_really_probe(struct platform_device *pdev,
ret = reset_controller_register(&reset->rcdev);
if (ret)
- of_clk_del_provider(dev->of_node);
+ goto err_reset;
+ if (desc->gdscs && desc->num_gdscs) {
+ ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap);
+ if (ret)
+ goto err_pd;
+ }
+
+ return 0;
+err_pd:
+ dev_err(dev, "Failed to register power domains\n");
+ reset_controller_unregister(&reset->rcdev);
+err_reset:
+ of_clk_del_provider(dev->of_node);
return ret;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
@@ -140,6 +153,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);
void qcom_cc_remove(struct platform_device *pdev)
{
+ gdsc_unregister(&pdev->dev);
of_clk_del_provider(pdev->dev.of_node);
reset_controller_unregister(platform_get_drvdata(pdev));
}
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 7a0e737..2892b71f 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -28,6 +28,8 @@ struct qcom_cc_desc {
size_t num_clks;
const struct qcom_reset_map *resets;
size_t num_resets;
+ struct gdsc **gdscs;
+ size_t num_gdscs;
};
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 02/13] clk: qcom: gdsc: Prepare common clk probe to register gdscs
@ 2015-07-22 7:10 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: linux-arm-kernel
The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/common.c | 16 +++++++++++++++-
drivers/clk/qcom/common.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index f7101e3..2776679 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -21,6 +21,7 @@
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
+#include "gdsc.h"
struct qcom_cc {
struct qcom_reset_controller reset;
@@ -120,8 +121,20 @@ int qcom_cc_really_probe(struct platform_device *pdev,
ret = reset_controller_register(&reset->rcdev);
if (ret)
- of_clk_del_provider(dev->of_node);
+ goto err_reset;
+ if (desc->gdscs && desc->num_gdscs) {
+ ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap);
+ if (ret)
+ goto err_pd;
+ }
+
+ return 0;
+err_pd:
+ dev_err(dev, "Failed to register power domains\n");
+ reset_controller_unregister(&reset->rcdev);
+err_reset:
+ of_clk_del_provider(dev->of_node);
return ret;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
@@ -140,6 +153,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);
void qcom_cc_remove(struct platform_device *pdev)
{
+ gdsc_unregister(&pdev->dev);
of_clk_del_provider(pdev->dev.of_node);
reset_controller_unregister(platform_get_drvdata(pdev));
}
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 7a0e737..2892b71f 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -28,6 +28,8 @@ struct qcom_cc_desc {
size_t num_clks;
const struct qcom_reset_map *resets;
size_t num_resets;
+ struct gdsc **gdscs;
+ size_t num_gdscs;
};
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:10 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
The devices within a gdsc power domain, quite often have additional
clocks to be turned on/off along with the power domain itself.
Once the drivers for these devices are converted to use runtime PM,
it would be possible to remove all clock handling from the drivers if
the gdsc driver can handle it.
Use PM clocks to add support for this. A list of con_ids[] specified
per gdsc would be the clocks turned on/off on every device start/stop
callbacks.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index a59655b..3125809 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -14,6 +14,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/jiffies.h>
+#include <linux/pm_clock.h>
#include <linux/slab.h>
#include "gdsc.h"
@@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)
return gdsc_toggle_logic(sc, false);
}
+static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
+{
+ int ret;
+ struct gdsc *sc = domain_to_gdsc(domain);
+ char **con_id, *con_ids[] = { "core", "iface", NULL };
+
+ ret = pm_clk_create(dev);
+ if (ret) {
+ dev_err(dev, "pm_clk_create failed %d\n", ret);
+ return ret;
+ }
+
+ for (con_id = con_ids; *con_id; con_id++) {
+ ret = pm_clk_add(dev, *con_id);
+ if (ret) {
+ dev_err(dev, "pm_clk_add failed %d\n", ret);
+ goto fail;
+ }
+ }
+ return 0;
+fail:
+ pm_clk_destroy(dev);
+ return ret;
+};
+
+static void gdsc_detach(struct generic_pm_domain *domain, struct device *dev)
+{
+ pm_clk_destroy(dev);
+ return;
+};
+
static int gdsc_init(struct gdsc *sc)
{
u32 mask, val;
@@ -127,6 +159,9 @@ static int gdsc_init(struct gdsc *sc)
sc->pd.power_off = gdsc_disable;
sc->pd.power_on = gdsc_enable;
+ sc->pd.attach_dev = gdsc_attach;
+ sc->pd.detach_dev = gdsc_detach;
+ sc->pd.flags = GENPD_FLAG_PM_CLK;
pm_genpd_init(&sc->pd, NULL, !on);
return 0;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
@ 2015-07-22 7:10 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:10 UTC (permalink / raw)
To: linux-arm-kernel
The devices within a gdsc power domain, quite often have additional
clocks to be turned on/off along with the power domain itself.
Once the drivers for these devices are converted to use runtime PM,
it would be possible to remove all clock handling from the drivers if
the gdsc driver can handle it.
Use PM clocks to add support for this. A list of con_ids[] specified
per gdsc would be the clocks turned on/off on every device start/stop
callbacks.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index a59655b..3125809 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -14,6 +14,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/jiffies.h>
+#include <linux/pm_clock.h>
#include <linux/slab.h>
#include "gdsc.h"
@@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)
return gdsc_toggle_logic(sc, false);
}
+static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
+{
+ int ret;
+ struct gdsc *sc = domain_to_gdsc(domain);
+ char **con_id, *con_ids[] = { "core", "iface", NULL };
+
+ ret = pm_clk_create(dev);
+ if (ret) {
+ dev_err(dev, "pm_clk_create failed %d\n", ret);
+ return ret;
+ }
+
+ for (con_id = con_ids; *con_id; con_id++) {
+ ret = pm_clk_add(dev, *con_id);
+ if (ret) {
+ dev_err(dev, "pm_clk_add failed %d\n", ret);
+ goto fail;
+ }
+ }
+ return 0;
+fail:
+ pm_clk_destroy(dev);
+ return ret;
+};
+
+static void gdsc_detach(struct generic_pm_domain *domain, struct device *dev)
+{
+ pm_clk_destroy(dev);
+ return;
+};
+
static int gdsc_init(struct gdsc *sc)
{
u32 mask, val;
@@ -127,6 +159,9 @@ static int gdsc_init(struct gdsc *sc)
sc->pd.power_off = gdsc_disable;
sc->pd.power_on = gdsc_enable;
+ sc->pd.attach_dev = gdsc_attach;
+ sc->pd.detach_dev = gdsc_detach;
+ sc->pd.flags = GENPD_FLAG_PM_CLK;
pm_genpd_init(&sc->pd, NULL, !on);
return 0;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
With CONFIG_PM disabled, turn the devices clocks on during
driver binding to the device, and turn them off when the
driver is unbound from the device.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 3125809..9ddd2f8 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -16,6 +16,7 @@
#include <linux/jiffies.h>
#include <linux/pm_clock.h>
#include <linux/slab.h>
+#include <linux/platform_device.h>
#include "gdsc.h"
#define PWR_ON_MASK BIT(31)
@@ -200,3 +201,61 @@ void gdsc_unregister(struct device *dev)
{
of_genpd_del_provider(dev->of_node);
}
+
+#ifndef CONFIG_PM
+static void enable_clock(struct device *dev, const char *con_id)
+{
+ struct clk *clk;
+
+ clk = clk_get(dev, con_id);
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+}
+
+static void disable_clock(struct device *dev, const char *con_id)
+{
+ struct clk *clk;
+
+ clk = clk_get(dev, con_id);
+ if (!IS_ERR(clk)) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ }
+}
+
+static int clk_notify(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ int sz;
+ struct device *dev = data;
+ char **con_id, *con_ids[] = { "core", "iface", NULL };
+
+ if (!of_find_property(dev->of_node, "power-domains", &sz))
+ return 0;
+
+ switch (action) {
+ case BUS_NOTIFY_BIND_DRIVER:
+ for (con_id = con_ids; *con_id; con_id++)
+ enable_clock(dev, *con_id);
+ break;
+ case BUS_NOTIFY_UNBOUND_DRIVER:
+ for (con_id = con_ids; *con_id; con_id++)
+ disable_clock(dev, *con_id);
+ break;
+ }
+ return 0;
+}
+
+struct notifier_block nb = {
+ .notifier_call = clk_notify,
+};
+
+int qcom_pm_runtime_init(void)
+{
+ bus_register_notifier(&platform_bus_type, &nb);
+ return 0;
+}
+core_initcall(qcom_pm_runtime_init);
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
With CONFIG_PM disabled, turn the devices clocks on during
driver binding to the device, and turn them off when the
driver is unbound from the device.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 3125809..9ddd2f8 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -16,6 +16,7 @@
#include <linux/jiffies.h>
#include <linux/pm_clock.h>
#include <linux/slab.h>
+#include <linux/platform_device.h>
#include "gdsc.h"
#define PWR_ON_MASK BIT(31)
@@ -200,3 +201,61 @@ void gdsc_unregister(struct device *dev)
{
of_genpd_del_provider(dev->of_node);
}
+
+#ifndef CONFIG_PM
+static void enable_clock(struct device *dev, const char *con_id)
+{
+ struct clk *clk;
+
+ clk = clk_get(dev, con_id);
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+}
+
+static void disable_clock(struct device *dev, const char *con_id)
+{
+ struct clk *clk;
+
+ clk = clk_get(dev, con_id);
+ if (!IS_ERR(clk)) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ }
+}
+
+static int clk_notify(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ int sz;
+ struct device *dev = data;
+ char **con_id, *con_ids[] = { "core", "iface", NULL };
+
+ if (!of_find_property(dev->of_node, "power-domains", &sz))
+ return 0;
+
+ switch (action) {
+ case BUS_NOTIFY_BIND_DRIVER:
+ for (con_id = con_ids; *con_id; con_id++)
+ enable_clock(dev, *con_id);
+ break;
+ case BUS_NOTIFY_UNBOUND_DRIVER:
+ for (con_id = con_ids; *con_id; con_id++)
+ disable_clock(dev, *con_id);
+ break;
+ }
+ return 0;
+}
+
+struct notifier_block nb = {
+ .notifier_call = clk_notify,
+};
+
+int qcom_pm_runtime_init(void)
+{
+ bus_register_notifier(&platform_bus_type, &nb);
+ return 0;
+}
+core_initcall(qcom_pm_runtime_init);
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 05/13] clk: qcom: gdsc: Enable an RCG before turing on the gdsc
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
Some gdsc instances require a certain root clock (RCG) to be turned on
*before* the power domain itself can be turned on. Handle this as part
of the gdsc enable/disable callbacks.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 20 +++++++++++++++++++-
drivers/clk/qcom/gdsc.h | 5 +++++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 9ddd2f8..fc0aa7c 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -84,6 +84,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
struct gdsc *sc = domain_to_gdsc(domain);
int ret;
+ if (sc->root_clk)
+ clk_prepare_enable(sc->root_clk);
+
ret = gdsc_toggle_logic(sc, true);
if (ret)
return ret;
@@ -101,9 +104,15 @@ static int gdsc_enable(struct generic_pm_domain *domain)
static int gdsc_disable(struct generic_pm_domain *domain)
{
+ int ret;
struct gdsc *sc = domain_to_gdsc(domain);
- return gdsc_toggle_logic(sc, false);
+ ret = gdsc_toggle_logic(sc, false);
+
+ if (sc->root_clk)
+ clk_disable_unprepare(sc->root_clk);
+
+ return ret;
}
static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
@@ -125,6 +134,15 @@ static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
goto fail;
}
}
+
+ if (sc->root_con_id) {
+ sc->root_clk = clk_get(dev, sc->root_con_id);
+ if (IS_ERR(sc->root_clk)) {
+ dev_err(dev, "failed to get root clock\n");
+ return PTR_ERR(sc->root_clk);
+ }
+ }
+
return 0;
fail:
pm_clk_destroy(dev);
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index e26a496..a3abbea 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -14,6 +14,7 @@
#ifndef __QCOM_GDSC_H__
#define __QCOM_GDSC_H__
+#include <linux/clk.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
@@ -22,11 +23,15 @@
* @pd: generic power domain
* @regmap: regmap for MMIO accesses
* @gdscr: gsdc control register
+ * @root_con_id: root clock to be enabled
+ * @root_clk: clk handle for the root clk
*/
struct gdsc {
struct generic_pm_domain pd;
struct regmap *regmap;
unsigned int gdscr;
+ char *root_con_id;
+ struct clk *root_clk;
};
#ifdef CONFIG_QCOM_GDSC
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 05/13] clk: qcom: gdsc: Enable an RCG before turing on the gdsc
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Some gdsc instances require a certain root clock (RCG) to be turned on
*before* the power domain itself can be turned on. Handle this as part
of the gdsc enable/disable callbacks.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 20 +++++++++++++++++++-
drivers/clk/qcom/gdsc.h | 5 +++++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 9ddd2f8..fc0aa7c 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -84,6 +84,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
struct gdsc *sc = domain_to_gdsc(domain);
int ret;
+ if (sc->root_clk)
+ clk_prepare_enable(sc->root_clk);
+
ret = gdsc_toggle_logic(sc, true);
if (ret)
return ret;
@@ -101,9 +104,15 @@ static int gdsc_enable(struct generic_pm_domain *domain)
static int gdsc_disable(struct generic_pm_domain *domain)
{
+ int ret;
struct gdsc *sc = domain_to_gdsc(domain);
- return gdsc_toggle_logic(sc, false);
+ ret = gdsc_toggle_logic(sc, false);
+
+ if (sc->root_clk)
+ clk_disable_unprepare(sc->root_clk);
+
+ return ret;
}
static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
@@ -125,6 +134,15 @@ static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
goto fail;
}
}
+
+ if (sc->root_con_id) {
+ sc->root_clk = clk_get(dev, sc->root_con_id);
+ if (IS_ERR(sc->root_clk)) {
+ dev_err(dev, "failed to get root clock\n");
+ return PTR_ERR(sc->root_clk);
+ }
+ }
+
return 0;
fail:
pm_clk_destroy(dev);
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index e26a496..a3abbea 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -14,6 +14,7 @@
#ifndef __QCOM_GDSC_H__
#define __QCOM_GDSC_H__
+#include <linux/clk.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
@@ -22,11 +23,15 @@
* @pd: generic power domain
* @regmap: regmap for MMIO accesses
* @gdscr: gsdc control register
+ * @root_con_id: root clock to be enabled
+ * @root_clk: clk handle for the root clk
*/
struct gdsc {
struct generic_pm_domain pd;
struct regmap *regmap;
unsigned int gdscr;
+ char *root_con_id;
+ struct clk *root_clk;
};
#ifdef CONFIG_QCOM_GDSC
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 06/13] clk: qcom: gdsc: Add support for Memory RET/OFF
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
Along with the GDSC power switch, there is additional control
to either retain all memory (core and peripheral) within a given
powerdomain or to turn them off while the GDSC is powered down.
Add support for these by modelling a RET state where all
memory is retained and an OFF state where all memory gets turned
off.
The controls provided are granular enough to be able to support
various differnt levels of RET states, like a 'shallow RET' with all memory
retained and a 'deep RET' with some memory retained while some others
are lost. The current patch does not support this and considers
just one RET state where all memory is retained. Futher work, if
needed can support multiple different levels of RET state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 33 +++++++++++++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 13 +++++++++++++
2 files changed, 46 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index fc0aa7c..5cc2d63 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -32,6 +32,9 @@
#define EN_FEW_WAIT_VAL (0x8 << 16)
#define CLK_DIS_WAIT_VAL (0x2 << 12)
+#define RETAIN_MEM BIT(14)
+#define RETAIN_PERIPH BIT(13)
+
#define TIMEOUT_US 100
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
@@ -79,6 +82,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
return -ETIMEDOUT;
}
+static inline void gdsc_force_mem_on(struct gdsc *sc)
+{
+ int i;
+ u32 mask = RETAIN_MEM | RETAIN_PERIPH;
+
+ for (i = 0; i < sc->cxc_count; i++)
+ regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
+}
+
+static inline void gdsc_clear_mem_on(struct gdsc *sc)
+{
+ int i;
+ u32 mask = RETAIN_MEM | RETAIN_PERIPH;
+
+ for (i = 0; i < sc->cxc_count; i++)
+ regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
+}
+
static int gdsc_enable(struct generic_pm_domain *domain)
{
struct gdsc *sc = domain_to_gdsc(domain);
@@ -90,6 +111,10 @@ static int gdsc_enable(struct generic_pm_domain *domain)
ret = gdsc_toggle_logic(sc, true);
if (ret)
return ret;
+
+ if (sc->pwrsts & PWRSTS_OFF)
+ gdsc_force_mem_on(sc);
+
/*
* If clocks to this power domain were already on, they will take an
* additional 4 clock cycles to re-enable after the power domain is
@@ -109,6 +134,9 @@ static int gdsc_disable(struct generic_pm_domain *domain)
ret = gdsc_toggle_logic(sc, false);
+ if (sc->pwrsts & PWRSTS_OFF)
+ gdsc_clear_mem_on(sc);
+
if (sc->root_clk)
clk_disable_unprepare(sc->root_clk);
@@ -176,6 +204,11 @@ static int gdsc_init(struct gdsc *sc)
if (on < 0)
return on;
+ if (on || (sc->pwrsts & PWRSTS_RET))
+ gdsc_force_mem_on(sc);
+ else
+ gdsc_clear_mem_on(sc);
+
sc->pd.power_off = gdsc_disable;
sc->pd.power_on = gdsc_enable;
sc->pd.attach_dev = gdsc_attach;
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index a3abbea..87c4ace 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -18,6 +18,13 @@
#include <linux/pm_domain.h>
#include <linux/regmap.h>
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_OFF BIT(0)
+#define PWRSTS_RET BIT(1)
+#define PWRSTS_ON BIT(2)
+#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
+#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
+
/**
* struct gdsc - Globally Distributed Switch Controller
* @pd: generic power domain
@@ -25,6 +32,9 @@
* @gdscr: gsdc control register
* @root_con_id: root clock to be enabled
* @root_clk: clk handle for the root clk
+ * @cxcs: offsets of branch registers to toggle mem/periph bits in
+ * @cxc_count: number of @cxcs
+ * @pwrsts: Possible powerdomain power states
*/
struct gdsc {
struct generic_pm_domain pd;
@@ -32,6 +42,9 @@ struct gdsc {
unsigned int gdscr;
char *root_con_id;
struct clk *root_clk;
+ unsigned int *cxcs;
+ unsigned int cxc_count;
+ const u8 pwrsts;
};
#ifdef CONFIG_QCOM_GDSC
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 06/13] clk: qcom: gdsc: Add support for Memory RET/OFF
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Along with the GDSC power switch, there is additional control
to either retain all memory (core and peripheral) within a given
powerdomain or to turn them off while the GDSC is powered down.
Add support for these by modelling a RET state where all
memory is retained and an OFF state where all memory gets turned
off.
The controls provided are granular enough to be able to support
various differnt levels of RET states, like a 'shallow RET' with all memory
retained and a 'deep RET' with some memory retained while some others
are lost. The current patch does not support this and considers
just one RET state where all memory is retained. Futher work, if
needed can support multiple different levels of RET state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 33 +++++++++++++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 13 +++++++++++++
2 files changed, 46 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index fc0aa7c..5cc2d63 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -32,6 +32,9 @@
#define EN_FEW_WAIT_VAL (0x8 << 16)
#define CLK_DIS_WAIT_VAL (0x2 << 12)
+#define RETAIN_MEM BIT(14)
+#define RETAIN_PERIPH BIT(13)
+
#define TIMEOUT_US 100
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
@@ -79,6 +82,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
return -ETIMEDOUT;
}
+static inline void gdsc_force_mem_on(struct gdsc *sc)
+{
+ int i;
+ u32 mask = RETAIN_MEM | RETAIN_PERIPH;
+
+ for (i = 0; i < sc->cxc_count; i++)
+ regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
+}
+
+static inline void gdsc_clear_mem_on(struct gdsc *sc)
+{
+ int i;
+ u32 mask = RETAIN_MEM | RETAIN_PERIPH;
+
+ for (i = 0; i < sc->cxc_count; i++)
+ regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
+}
+
static int gdsc_enable(struct generic_pm_domain *domain)
{
struct gdsc *sc = domain_to_gdsc(domain);
@@ -90,6 +111,10 @@ static int gdsc_enable(struct generic_pm_domain *domain)
ret = gdsc_toggle_logic(sc, true);
if (ret)
return ret;
+
+ if (sc->pwrsts & PWRSTS_OFF)
+ gdsc_force_mem_on(sc);
+
/*
* If clocks to this power domain were already on, they will take an
* additional 4 clock cycles to re-enable after the power domain is
@@ -109,6 +134,9 @@ static int gdsc_disable(struct generic_pm_domain *domain)
ret = gdsc_toggle_logic(sc, false);
+ if (sc->pwrsts & PWRSTS_OFF)
+ gdsc_clear_mem_on(sc);
+
if (sc->root_clk)
clk_disable_unprepare(sc->root_clk);
@@ -176,6 +204,11 @@ static int gdsc_init(struct gdsc *sc)
if (on < 0)
return on;
+ if (on || (sc->pwrsts & PWRSTS_RET))
+ gdsc_force_mem_on(sc);
+ else
+ gdsc_clear_mem_on(sc);
+
sc->pd.power_off = gdsc_disable;
sc->pd.power_on = gdsc_enable;
sc->pd.attach_dev = gdsc_attach;
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index a3abbea..87c4ace 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -18,6 +18,13 @@
#include <linux/pm_domain.h>
#include <linux/regmap.h>
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_OFF BIT(0)
+#define PWRSTS_RET BIT(1)
+#define PWRSTS_ON BIT(2)
+#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
+#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
+
/**
* struct gdsc - Globally Distributed Switch Controller
* @pd: generic power domain
@@ -25,6 +32,9 @@
* @gdscr: gsdc control register
* @root_con_id: root clock to be enabled
* @root_clk: clk handle for the root clk
+ * @cxcs: offsets of branch registers to toggle mem/periph bits in
+ * @cxc_count: number of @cxcs
+ * @pwrsts: Possible powerdomain power states
*/
struct gdsc {
struct generic_pm_domain pd;
@@ -32,6 +42,9 @@ struct gdsc {
unsigned int gdscr;
char *root_con_id;
struct clk *root_clk;
+ unsigned int *cxcs;
+ unsigned int cxc_count;
+ const u8 pwrsts;
};
#ifdef CONFIG_QCOM_GDSC
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 07/13] clk: qcom: gdsc: Add support for ON only state
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines every time the client
driver would request the GDSC to be powered on/off instead.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/common.c | 3 ++-
drivers/clk/qcom/gdsc.c | 33 ++++++++++++++++++++++++++++++++-
drivers/clk/qcom/gdsc.h | 11 ++++++++++-
3 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 2776679..72d15e6 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -124,7 +124,8 @@ int qcom_cc_really_probe(struct platform_device *pdev,
goto err_reset;
if (desc->gdscs && desc->num_gdscs) {
- ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap);
+ ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs,
+ &reset->rcdev, regmap);
if (ret)
goto err_pd;
}
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 5cc2d63..52c16e3 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -82,6 +82,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
return -ETIMEDOUT;
}
+static inline int gdsc_deassert_reset(struct gdsc *sc)
+{
+ int i;
+
+ for (i = 0; i < sc->reset_count; i++)
+ sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
+ return 0;
+}
+
+static inline int gdsc_assert_reset(struct gdsc *sc)
+{
+ int i;
+
+ for (i = 0; i < sc->reset_count; i++)
+ sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
+ return 0;
+}
+
static inline void gdsc_force_mem_on(struct gdsc *sc)
{
int i;
@@ -105,6 +123,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
struct gdsc *sc = domain_to_gdsc(domain);
int ret;
+ if (sc->pwrsts == PWRSTS_ON)
+ return gdsc_deassert_reset(sc);
+
if (sc->root_clk)
clk_prepare_enable(sc->root_clk);
@@ -132,6 +153,9 @@ static int gdsc_disable(struct generic_pm_domain *domain)
int ret;
struct gdsc *sc = domain_to_gdsc(domain);
+ if (sc->pwrsts == PWRSTS_ON)
+ return gdsc_assert_reset(sc);
+
ret = gdsc_toggle_logic(sc, false);
if (sc->pwrsts & PWRSTS_OFF)
@@ -200,6 +224,12 @@ static int gdsc_init(struct gdsc *sc)
if (ret)
return ret;
+ /* Force gdsc ON if only ON state is supported */
+ if (sc->pwrsts == PWRSTS_ON)
+ ret = gdsc_toggle_logic(sc, true);
+ if (ret)
+ return ret;
+
on = gdsc_is_enabled(sc);
if (on < 0)
return on;
@@ -220,7 +250,7 @@ static int gdsc_init(struct gdsc *sc)
}
int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
- struct regmap *regmap)
+ struct reset_controller_dev *rcdev, struct regmap *regmap)
{
int i, ret;
struct genpd_onecell_data *data;
@@ -239,6 +269,7 @@ int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
if (!scs[i])
continue;
scs[i]->regmap = regmap;
+ scs[i]->rcdev = rcdev;
ret = gdsc_init(scs[i]);
if (ret)
return ret;
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 87c4ace..0d1c4fb 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -17,6 +17,7 @@
#include <linux/clk.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
+#include <linux/reset-controller.h>
/* Powerdomain allowable state bitfields */
#define PWRSTS_OFF BIT(0)
@@ -34,6 +35,9 @@
* @root_clk: clk handle for the root clk
* @cxcs: offsets of branch registers to toggle mem/periph bits in
* @cxc_count: number of @cxcs
+ * @resets: ids of resets associated with this gdsc
+ * @reset_count: number of @resets
+ * @rcdev: reset controller
* @pwrsts: Possible powerdomain power states
*/
struct gdsc {
@@ -44,14 +48,19 @@ struct gdsc {
struct clk *root_clk;
unsigned int *cxcs;
unsigned int cxc_count;
+ struct reset_controller_dev *rcdev;
+ unsigned int *resets;
+ unsigned int reset_count;
const u8 pwrsts;
};
#ifdef CONFIG_QCOM_GDSC
-int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *);
+int gdsc_register(struct device *, struct gdsc **, size_t n,
+ struct reset_controller_dev *, struct regmap *);
void gdsc_unregister(struct device *);
#else
static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
+ struct reset_controller_dev *rcdev,
struct regmap *r)
{
return -ENOSYS;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 07/13] clk: qcom: gdsc: Add support for ON only state
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines every time the client
driver would request the GDSC to be powered on/off instead.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/common.c | 3 ++-
drivers/clk/qcom/gdsc.c | 33 ++++++++++++++++++++++++++++++++-
drivers/clk/qcom/gdsc.h | 11 ++++++++++-
3 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 2776679..72d15e6 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -124,7 +124,8 @@ int qcom_cc_really_probe(struct platform_device *pdev,
goto err_reset;
if (desc->gdscs && desc->num_gdscs) {
- ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap);
+ ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs,
+ &reset->rcdev, regmap);
if (ret)
goto err_pd;
}
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 5cc2d63..52c16e3 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -82,6 +82,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
return -ETIMEDOUT;
}
+static inline int gdsc_deassert_reset(struct gdsc *sc)
+{
+ int i;
+
+ for (i = 0; i < sc->reset_count; i++)
+ sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
+ return 0;
+}
+
+static inline int gdsc_assert_reset(struct gdsc *sc)
+{
+ int i;
+
+ for (i = 0; i < sc->reset_count; i++)
+ sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
+ return 0;
+}
+
static inline void gdsc_force_mem_on(struct gdsc *sc)
{
int i;
@@ -105,6 +123,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
struct gdsc *sc = domain_to_gdsc(domain);
int ret;
+ if (sc->pwrsts == PWRSTS_ON)
+ return gdsc_deassert_reset(sc);
+
if (sc->root_clk)
clk_prepare_enable(sc->root_clk);
@@ -132,6 +153,9 @@ static int gdsc_disable(struct generic_pm_domain *domain)
int ret;
struct gdsc *sc = domain_to_gdsc(domain);
+ if (sc->pwrsts == PWRSTS_ON)
+ return gdsc_assert_reset(sc);
+
ret = gdsc_toggle_logic(sc, false);
if (sc->pwrsts & PWRSTS_OFF)
@@ -200,6 +224,12 @@ static int gdsc_init(struct gdsc *sc)
if (ret)
return ret;
+ /* Force gdsc ON if only ON state is supported */
+ if (sc->pwrsts == PWRSTS_ON)
+ ret = gdsc_toggle_logic(sc, true);
+ if (ret)
+ return ret;
+
on = gdsc_is_enabled(sc);
if (on < 0)
return on;
@@ -220,7 +250,7 @@ static int gdsc_init(struct gdsc *sc)
}
int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
- struct regmap *regmap)
+ struct reset_controller_dev *rcdev, struct regmap *regmap)
{
int i, ret;
struct genpd_onecell_data *data;
@@ -239,6 +269,7 @@ int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
if (!scs[i])
continue;
scs[i]->regmap = regmap;
+ scs[i]->rcdev = rcdev;
ret = gdsc_init(scs[i]);
if (ret)
return ret;
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 87c4ace..0d1c4fb 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -17,6 +17,7 @@
#include <linux/clk.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
+#include <linux/reset-controller.h>
/* Powerdomain allowable state bitfields */
#define PWRSTS_OFF BIT(0)
@@ -34,6 +35,9 @@
* @root_clk: clk handle for the root clk
* @cxcs: offsets of branch registers to toggle mem/periph bits in
* @cxc_count: number of @cxcs
+ * @resets: ids of resets associated with this gdsc
+ * @reset_count: number of @resets
+ * @rcdev: reset controller
* @pwrsts: Possible powerdomain power states
*/
struct gdsc {
@@ -44,14 +48,19 @@ struct gdsc {
struct clk *root_clk;
unsigned int *cxcs;
unsigned int cxc_count;
+ struct reset_controller_dev *rcdev;
+ unsigned int *resets;
+ unsigned int reset_count;
const u8 pwrsts;
};
#ifdef CONFIG_QCOM_GDSC
-int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *);
+int gdsc_register(struct device *, struct gdsc **, size_t n,
+ struct reset_controller_dev *, struct regmap *);
void gdsc_unregister(struct device *);
#else
static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
+ struct reset_controller_dev *rcdev,
struct regmap *r)
{
return -ENOSYS;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 08/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-msm8916.c | 52 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 +++++
3 files changed, 61 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index a7c2eea..0fad2eb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -54,6 +54,7 @@ config MSM_GCC_8660
config MSM_GCC_8916
tristate "MSM8916 Global Clock Controller"
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on msm8916 devices.
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index c66f7bc..991a1cf 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
},
};
+static struct gdsc venus_gdsc = {
+ .gdscr = 0x4c018,
+ .pd = {
+ .name = "venus",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x4d078,
+ .pd = {
+ .name = "mdss",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc jpeg_gdsc = {
+ .gdscr = 0x5701c,
+ .pd = {
+ .name = "jpeg",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc vfe_gdsc = {
+ .gdscr = 0x58034,
+ .pd = {
+ .name = "vfe",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+ .gdscr = 0x5901c,
+ .pd = {
+ .name = "oxili",
+ },
+ .root_con_id = "gfx3d_clk_src",
+ .pwrsts = PWRDM_OFF_ON,
+};
+
static struct clk_regmap *gcc_msm8916_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@@ -2703,6 +2745,14 @@ static struct clk_regmap *gcc_msm8916_clocks[] = {
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
};
+static struct gdsc *gcc_msm8916_gdscs[] = {
+ [VENUS_GDSC] = &venus_gdsc,
+ [MDSS_GDSC] = &mdss_gdsc,
+ [JPEG_GDSC] = &jpeg_gdsc,
+ [VFE_GDSC] = &vfe_gdsc,
+ [OXILI_GDSC] = &oxili_gdsc,
+};
+
static const struct qcom_reset_map gcc_msm8916_resets[] = {
[GCC_BLSP1_BCR] = { 0x01000 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
@@ -2810,6 +2860,8 @@ static const struct qcom_cc_desc gcc_msm8916_desc = {
.num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
.resets = gcc_msm8916_resets,
.num_resets = ARRAY_SIZE(gcc_msm8916_resets),
+ .gdscs = gcc_msm8916_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
};
static const struct of_device_id gcc_msm8916_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
index e430f64..11566c5 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -153,4 +153,12 @@
#define GCC_VENUS0_AXI_CLK 136
#define GCC_VENUS0_VCODEC0_CLK 137
+/* Indexes for GDSCs */
+#define BIMC_GDSC 0
+#define VENUS_GDSC 1
+#define MDSS_GDSC 2
+#define JPEG_GDSC 3
+#define VFE_GDSC 4
+#define OXILI_GDSC 5
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 08/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-msm8916.c | 52 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 +++++
3 files changed, 61 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index a7c2eea..0fad2eb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -54,6 +54,7 @@ config MSM_GCC_8660
config MSM_GCC_8916
tristate "MSM8916 Global Clock Controller"
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on msm8916 devices.
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index c66f7bc..991a1cf 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
},
};
+static struct gdsc venus_gdsc = {
+ .gdscr = 0x4c018,
+ .pd = {
+ .name = "venus",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x4d078,
+ .pd = {
+ .name = "mdss",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc jpeg_gdsc = {
+ .gdscr = 0x5701c,
+ .pd = {
+ .name = "jpeg",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc vfe_gdsc = {
+ .gdscr = 0x58034,
+ .pd = {
+ .name = "vfe",
+ },
+ .pwrsts = PWRDM_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+ .gdscr = 0x5901c,
+ .pd = {
+ .name = "oxili",
+ },
+ .root_con_id = "gfx3d_clk_src",
+ .pwrsts = PWRDM_OFF_ON,
+};
+
static struct clk_regmap *gcc_msm8916_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@@ -2703,6 +2745,14 @@ static struct clk_regmap *gcc_msm8916_clocks[] = {
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
};
+static struct gdsc *gcc_msm8916_gdscs[] = {
+ [VENUS_GDSC] = &venus_gdsc,
+ [MDSS_GDSC] = &mdss_gdsc,
+ [JPEG_GDSC] = &jpeg_gdsc,
+ [VFE_GDSC] = &vfe_gdsc,
+ [OXILI_GDSC] = &oxili_gdsc,
+};
+
static const struct qcom_reset_map gcc_msm8916_resets[] = {
[GCC_BLSP1_BCR] = { 0x01000 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
@@ -2810,6 +2860,8 @@ static const struct qcom_cc_desc gcc_msm8916_desc = {
.num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
.resets = gcc_msm8916_resets,
.num_resets = ARRAY_SIZE(gcc_msm8916_resets),
+ .gdscs = gcc_msm8916_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
};
static const struct of_device_id gcc_msm8916_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
index e430f64..11566c5 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -153,4 +153,12 @@
#define GCC_VENUS0_AXI_CLK 136
#define GCC_VENUS0_VCODEC0_CLK 137
+/* Indexes for GDSCs */
+#define BIMC_GDSC 0
+#define VENUS_GDSC 1
+#define MDSS_GDSC 2
+#define JPEG_GDSC 3
+#define VFE_GDSC 4
+#define OXILI_GDSC 5
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 09/13] clk: qcom: gdsc: Add GDSCs in msm8974 GCC
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
From: Stephen Boyd <sboyd@codeaurora.org>
Theres just one GDSC as part of the msm8974 GCC block.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-msm8974.c | 15 +++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 +++
3 files changed, 19 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0fad2eb..c8a0863 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -89,6 +89,7 @@ config MSM_MMCC_8960
config MSM_GCC_8974
tristate "MSM8974 Global Clock Controller"
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on msm8974 devices.
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index c39d098..2c3c26f 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -2431,6 +2432,14 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
},
};
+static struct gdsc usb_hs_hsic_gdsc = {
+ .gdscr = 0x404,
+ .pd = {
+ .name = "usb_hs_hsic",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *gcc_msm8974_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@@ -2660,6 +2669,10 @@ static const struct qcom_reset_map gcc_msm8974_resets[] = {
[GCC_VENUS_RESTART] = { 0x1740 },
};
+static struct gdsc *gcc_msm8974_gdscs[] = {
+ [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
+};
+
static const struct regmap_config gcc_msm8974_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2674,6 +2687,8 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
.num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
.resets = gcc_msm8974_resets,
.num_resets = ARRAY_SIZE(gcc_msm8974_resets),
+ .gdscs = gcc_msm8974_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
};
static const struct of_device_id gcc_msm8974_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
index 51e51c8..81d32f6 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -321,4 +321,7 @@
#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304
#define GCC_SDCC1_CDCCAL_FF_CLK 305
+/* gdscs */
+#define USB_HS_HSIC_GDSC 0
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 09/13] clk: qcom: gdsc: Add GDSCs in msm8974 GCC
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Boyd <sboyd@codeaurora.org>
Theres just one GDSC as part of the msm8974 GCC block.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-msm8974.c | 15 +++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 +++
3 files changed, 19 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0fad2eb..c8a0863 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -89,6 +89,7 @@ config MSM_MMCC_8960
config MSM_GCC_8974
tristate "MSM8974 Global Clock Controller"
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on msm8974 devices.
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index c39d098..2c3c26f 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -2431,6 +2432,14 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
},
};
+static struct gdsc usb_hs_hsic_gdsc = {
+ .gdscr = 0x404,
+ .pd = {
+ .name = "usb_hs_hsic",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *gcc_msm8974_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@@ -2660,6 +2669,10 @@ static const struct qcom_reset_map gcc_msm8974_resets[] = {
[GCC_VENUS_RESTART] = { 0x1740 },
};
+static struct gdsc *gcc_msm8974_gdscs[] = {
+ [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
+};
+
static const struct regmap_config gcc_msm8974_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2674,6 +2687,8 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
.num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
.resets = gcc_msm8974_resets,
.num_resets = ARRAY_SIZE(gcc_msm8974_resets),
+ .gdscs = gcc_msm8974_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
};
static const struct of_device_id gcc_msm8974_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
index 51e51c8..81d32f6 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -321,4 +321,7 @@
#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304
#define GCC_SDCC1_CDCCAL_FF_CLK 305
+/* gdscs */
+#define USB_HS_HSIC_GDSC 0
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 10/13] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
From: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/mmcc-msm8974.c | 72 +++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 +++
3 files changed, 81 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index c8a0863..34945fa 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -99,6 +99,7 @@ config MSM_GCC_8974
config MSM_MMCC_8974
tristate "MSM8974 Multimedia Clock Controller"
select MSM_GCC_8974
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the multimedia clock controller on msm8974 devices.
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 07f4cc1..0b95063 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -2349,6 +2350,66 @@ static struct pll_config mmpll3_config = {
.aux_output_mask = BIT(1),
};
+static struct gdsc venus0_gdsc = {
+ .gdscr = 0x1024,
+ .cxcs = (unsigned int []){ 0x1028 },
+ .cxc_count = 1,
+ .resets = (unsigned int []){ VENUS0_RESET },
+ .reset_count = 1,
+ .pd = {
+ .name = "venus0",
+ },
+ .pwrsts = PWRSTS_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x2304,
+ .cxcs = (unsigned int []){ 0x231c, 0x2320 },
+ .cxc_count = 2,
+ .pd = {
+ .name = "mdss",
+ },
+ .pwrsts = PWRSTS_RET_ON,
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+ .gdscr = 0x35a4,
+ .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
+ .cxc_count = 3,
+ .pd = {
+ .name = "camss_jpeg",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_vfe_gdsc = {
+ .gdscr = 0x36a4,
+ .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
+ .cxc_count = 5,
+ .pd = {
+ .name = "camss_vfe",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+ .gdscr = 0x4024,
+ .cxcs = (unsigned int []){ 0x4028 },
+ .cxc_count = 1,
+ .pd = {
+ .name = "oxili",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxilicx_gdsc = {
+ .gdscr = 0x4034,
+ .pd = {
+ .name = "oxilicx",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *mmcc_msm8974_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -2525,6 +2586,15 @@ static const struct qcom_reset_map mmcc_msm8974_resets[] = {
[OCMEMNOC_RESET] = { 0x50b0 },
};
+static struct gdsc *mmcc_msm8974_gdscs[] = {
+ [VENUS0_GDSC] = &venus0_gdsc,
+ [MDSS_GDSC] = &mdss_gdsc,
+ [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
+ [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+ [OXILI_GDSC] = &oxili_gdsc,
+ [OXILICX_GDSC] = &oxilicx_gdsc,
+};
+
static const struct regmap_config mmcc_msm8974_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2539,6 +2609,8 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = {
.num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
.resets = mmcc_msm8974_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
+ .gdscs = mmcc_msm8974_gdscs,
+ .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
};
static const struct of_device_id mmcc_msm8974_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
index 032ed87..28651e5 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
@@ -158,4 +158,12 @@
#define SPDM_RM_AXI 141
#define SPDM_RM_OCMEMNOC 142
+/* gdscs */
+#define VENUS0_GDSC 0
+#define MDSS_GDSC 1
+#define CAMSS_JPEG_GDSC 2
+#define CAMSS_VFE_GDSC 3
+#define OXILI_GDSC 4
+#define OXILICX_GDSC 5
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 10/13] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/mmcc-msm8974.c | 72 +++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 +++
3 files changed, 81 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index c8a0863..34945fa 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -99,6 +99,7 @@ config MSM_GCC_8974
config MSM_MMCC_8974
tristate "MSM8974 Multimedia Clock Controller"
select MSM_GCC_8974
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the multimedia clock controller on msm8974 devices.
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 07f4cc1..0b95063 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -2349,6 +2350,66 @@ static struct pll_config mmpll3_config = {
.aux_output_mask = BIT(1),
};
+static struct gdsc venus0_gdsc = {
+ .gdscr = 0x1024,
+ .cxcs = (unsigned int []){ 0x1028 },
+ .cxc_count = 1,
+ .resets = (unsigned int []){ VENUS0_RESET },
+ .reset_count = 1,
+ .pd = {
+ .name = "venus0",
+ },
+ .pwrsts = PWRSTS_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x2304,
+ .cxcs = (unsigned int []){ 0x231c, 0x2320 },
+ .cxc_count = 2,
+ .pd = {
+ .name = "mdss",
+ },
+ .pwrsts = PWRSTS_RET_ON,
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+ .gdscr = 0x35a4,
+ .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
+ .cxc_count = 3,
+ .pd = {
+ .name = "camss_jpeg",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_vfe_gdsc = {
+ .gdscr = 0x36a4,
+ .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
+ .cxc_count = 5,
+ .pd = {
+ .name = "camss_vfe",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+ .gdscr = 0x4024,
+ .cxcs = (unsigned int []){ 0x4028 },
+ .cxc_count = 1,
+ .pd = {
+ .name = "oxili",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxilicx_gdsc = {
+ .gdscr = 0x4034,
+ .pd = {
+ .name = "oxilicx",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *mmcc_msm8974_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -2525,6 +2586,15 @@ static const struct qcom_reset_map mmcc_msm8974_resets[] = {
[OCMEMNOC_RESET] = { 0x50b0 },
};
+static struct gdsc *mmcc_msm8974_gdscs[] = {
+ [VENUS0_GDSC] = &venus0_gdsc,
+ [MDSS_GDSC] = &mdss_gdsc,
+ [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
+ [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+ [OXILI_GDSC] = &oxili_gdsc,
+ [OXILICX_GDSC] = &oxilicx_gdsc,
+};
+
static const struct regmap_config mmcc_msm8974_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2539,6 +2609,8 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = {
.num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
.resets = mmcc_msm8974_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
+ .gdscs = mmcc_msm8974_gdscs,
+ .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
};
static const struct of_device_id mmcc_msm8974_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
index 032ed87..28651e5 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
@@ -158,4 +158,12 @@
#define SPDM_RM_AXI 141
#define SPDM_RM_OCMEMNOC 142
+/* gdscs */
+#define VENUS0_GDSC 0
+#define MDSS_GDSC 1
+#define CAMSS_JPEG_GDSC 2
+#define CAMSS_VFE_GDSC 3
+#define OXILI_GDSC 4
+#define OXILICX_GDSC 5
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 11/13] clk: qcom: gdsc: Add GDSCs in apq8084 GCC
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
Add the GDSC instances that exist as part of apq8084 GCC block
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-apq8084.c | 42 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 ++++
3 files changed, 49 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 34945fa..7dcb7e5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -7,6 +7,7 @@ config COMMON_CLK_QCOM
config APQ_GCC_8084
tristate "APQ8084 Global Clock Controller"
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on apq8084 devices.
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index 54a756b9..91c6bd9c 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -3253,6 +3254,38 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
},
};
+static struct gdsc usb_hs_hsic_gdsc = {
+ .gdscr = 0x404,
+ .pd = {
+ .name = "usb_hs_hsic",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie0_gdsc = {
+ .gdscr = 0x1ac4,
+ .pd = {
+ .name = "pcie0",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie1_gdsc = {
+ .gdscr = 0x1b44,
+ .pd = {
+ .name = "pcie1",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb30_gdsc = {
+ .gdscr = 0x1e84,
+ .pd = {
+ .name = "usb30",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *gcc_apq8084_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@@ -3446,6 +3479,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
};
+static struct gdsc *gcc_apq8084_gdscs[] = {
+ [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
+ [PCIE0_GDSC] = &pcie0_gdsc,
+ [PCIE1_GDSC] = &pcie1_gdsc,
+ [USB30_GDSC] = &usb30_gdsc,
+};
+
static const struct qcom_reset_map gcc_apq8084_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
[GCC_CONFIG_NOC_BCR] = { 0x0140 },
@@ -3554,6 +3594,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = {
.num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
.resets = gcc_apq8084_resets,
.num_resets = ARRAY_SIZE(gcc_apq8084_resets),
+ .gdscs = gcc_apq8084_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
};
static const struct of_device_id gcc_apq8084_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
index 2c0da56..5aa7ebe 100644
--- a/include/dt-bindings/clock/qcom,gcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -348,4 +348,10 @@
#define GCC_PCIE_1_PIPE_CLK 331
#define GCC_PCIE_1_SLV_AXI_CLK 332
+/* gdscs */
+#define USB_HS_HSIC_GDSC 0
+#define PCIE0_GDSC 1
+#define PCIE1_GDSC 2
+#define USB30_GDSC 3
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 11/13] clk: qcom: gdsc: Add GDSCs in apq8084 GCC
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Add the GDSC instances that exist as part of apq8084 GCC block
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-apq8084.c | 42 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 ++++
3 files changed, 49 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 34945fa..7dcb7e5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -7,6 +7,7 @@ config COMMON_CLK_QCOM
config APQ_GCC_8084
tristate "APQ8084 Global Clock Controller"
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on apq8084 devices.
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index 54a756b9..91c6bd9c 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -31,6 +31,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -3253,6 +3254,38 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
},
};
+static struct gdsc usb_hs_hsic_gdsc = {
+ .gdscr = 0x404,
+ .pd = {
+ .name = "usb_hs_hsic",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie0_gdsc = {
+ .gdscr = 0x1ac4,
+ .pd = {
+ .name = "pcie0",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie1_gdsc = {
+ .gdscr = 0x1b44,
+ .pd = {
+ .name = "pcie1",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb30_gdsc = {
+ .gdscr = 0x1e84,
+ .pd = {
+ .name = "usb30",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *gcc_apq8084_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@@ -3446,6 +3479,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
};
+static struct gdsc *gcc_apq8084_gdscs[] = {
+ [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
+ [PCIE0_GDSC] = &pcie0_gdsc,
+ [PCIE1_GDSC] = &pcie1_gdsc,
+ [USB30_GDSC] = &usb30_gdsc,
+};
+
static const struct qcom_reset_map gcc_apq8084_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
[GCC_CONFIG_NOC_BCR] = { 0x0140 },
@@ -3554,6 +3594,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = {
.num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
.resets = gcc_apq8084_resets,
.num_resets = ARRAY_SIZE(gcc_apq8084_resets),
+ .gdscs = gcc_apq8084_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
};
static const struct of_device_id gcc_apq8084_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
index 2c0da56..5aa7ebe 100644
--- a/include/dt-bindings/clock/qcom,gcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -348,4 +348,10 @@
#define GCC_PCIE_1_PIPE_CLK 331
#define GCC_PCIE_1_SLV_AXI_CLK 332
+/* gdscs */
+#define USB_HS_HSIC_GDSC 0
+#define PCIE0_GDSC 1
+#define PCIE1_GDSC 2
+#define USB30_GDSC 3
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 12/13] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
From: Stephane Viau <sviau@codeaurora.org>
Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/mmcc-apq8084.c | 68 ++++++++++++++++++++++++++-
include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 ++++
3 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7dcb7e5..8b6c49d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -17,6 +17,7 @@ config APQ_GCC_8084
config APQ_MMCC_8084
tristate "APQ8084 Multimedia Clock Controller"
select APQ_GCC_8084
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the multimedia clock controller on apq8084 devices.
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 1b17df2..56c18aa 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -26,6 +26,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -3077,6 +3078,60 @@ static const struct pll_config mmpll3_config = {
.aux_output_mask = BIT(1),
};
+static struct gdsc venus0_gdsc = {
+ .gdscr = 0x1024,
+ .pd = {
+ .name = "venus0",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x2304,
+ .cxcs = (unsigned int []){ 0x231c, 0x2320 },
+ .cxc_count = 2,
+ .pd = {
+ .name = "mdss",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+ .gdscr = 0x35a4,
+ .pd = {
+ .name = "camss_jpeg",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_vfe_gdsc = {
+ .gdscr = 0x36a4,
+ .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
+ .cxc_count = 3,
+ .pd = {
+ .name = "camss_vfe",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+ .gdscr = 0x4024,
+ .cxcs = (unsigned int []){ 0x4028 },
+ .cxc_count = 1,
+ .pd = {
+ .name = "oxili",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxilicx_gdsc = {
+ .gdscr = 0x4034,
+ .pd = {
+ .name = "oxilicx",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *mmcc_apq8084_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -3294,6 +3349,15 @@ static const struct qcom_reset_map mmcc_apq8084_resets[] = {
[MMSSNOCAXI_RESET] = { 0x5060 },
};
+static struct gdsc *mmcc_apq8084_gdscs[] = {
+ [VENUS0_GDSC] = &venus0_gdsc,
+ [MDSS_GDSC] = &mdss_gdsc,
+ [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
+ [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+ [OXILI_GDSC] = &oxili_gdsc,
+ [OXILICX_GDSC] = &oxilicx_gdsc,
+};
+
static const struct regmap_config mmcc_apq8084_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -3308,6 +3372,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc = {
.num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
.resets = mmcc_apq8084_resets,
.num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
+ .gdscs = mmcc_apq8084_gdscs,
+ .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
};
static const struct of_device_id mmcc_apq8084_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
index d72b5b3..21fec5d 100644
--- a/include/dt-bindings/clock/qcom,mmcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -180,4 +180,12 @@
#define VPU_SLEEP_CLK 163
#define VPU_VDP_CLK 164
+/* GDSCs */
+#define VENUS0_GDSC 0
+#define MDSS_GDSC 1
+#define CAMSS_JPEG_GDSC 2
+#define CAMSS_VFE_GDSC 3
+#define OXILI_GDSC 4
+#define OXILICX_GDSC 5
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 12/13] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephane Viau <sviau@codeaurora.org>
Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/mmcc-apq8084.c | 68 ++++++++++++++++++++++++++-
include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 ++++
3 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7dcb7e5..8b6c49d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -17,6 +17,7 @@ config APQ_GCC_8084
config APQ_MMCC_8084
tristate "APQ8084 Multimedia Clock Controller"
select APQ_GCC_8084
+ select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the multimedia clock controller on apq8084 devices.
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 1b17df2..56c18aa 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -26,6 +26,7 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
+#include "gdsc.h"
enum {
P_XO,
@@ -3077,6 +3078,60 @@ static const struct pll_config mmpll3_config = {
.aux_output_mask = BIT(1),
};
+static struct gdsc venus0_gdsc = {
+ .gdscr = 0x1024,
+ .pd = {
+ .name = "venus0",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x2304,
+ .cxcs = (unsigned int []){ 0x231c, 0x2320 },
+ .cxc_count = 2,
+ .pd = {
+ .name = "mdss",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+ .gdscr = 0x35a4,
+ .pd = {
+ .name = "camss_jpeg",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_vfe_gdsc = {
+ .gdscr = 0x36a4,
+ .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
+ .cxc_count = 3,
+ .pd = {
+ .name = "camss_vfe",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+ .gdscr = 0x4024,
+ .cxcs = (unsigned int []){ 0x4028 },
+ .cxc_count = 1,
+ .pd = {
+ .name = "oxili",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxilicx_gdsc = {
+ .gdscr = 0x4034,
+ .pd = {
+ .name = "oxilicx",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *mmcc_apq8084_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -3294,6 +3349,15 @@ static const struct qcom_reset_map mmcc_apq8084_resets[] = {
[MMSSNOCAXI_RESET] = { 0x5060 },
};
+static struct gdsc *mmcc_apq8084_gdscs[] = {
+ [VENUS0_GDSC] = &venus0_gdsc,
+ [MDSS_GDSC] = &mdss_gdsc,
+ [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
+ [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+ [OXILI_GDSC] = &oxili_gdsc,
+ [OXILICX_GDSC] = &oxilicx_gdsc,
+};
+
static const struct regmap_config mmcc_apq8084_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -3308,6 +3372,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc = {
.num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
.resets = mmcc_apq8084_resets,
.num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
+ .gdscs = mmcc_apq8084_gdscs,
+ .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
};
static const struct of_device_id mmcc_apq8084_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
index d72b5b3..21fec5d 100644
--- a/include/dt-bindings/clock/qcom,mmcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -180,4 +180,12 @@
#define VPU_SLEEP_CLK 163
#define VPU_VDP_CLK 164
+/* GDSCs */
+#define VENUS0_GDSC 0
+#define MDSS_GDSC 1
+#define CAMSS_JPEG_GDSC 2
+#define CAMSS_VFE_GDSC 3
+#define OXILI_GDSC 4
+#define OXILICX_GDSC 5
+
#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 13/13] arm: dts: qcom: Add #power-domain-cells property
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-22 7:11 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-arm-msm, linux-arm-kernel, linux-pm, georgi.djakov,
svarbanov, srinivas.kandagatla, sviau, Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which
implement gdsc powerdomains. Add the #power-domain-cells property
to them.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 7084010..1cdb568 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -221,6 +221,7 @@
compatible = "qcom,gcc-apq8084";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 37b47b5..8a2dfa6 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -217,6 +217,7 @@
compatible = "qcom,gcc-msm8974";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
};
@@ -224,6 +225,7 @@
compatible = "qcom,mmcc-msm8974";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfd8c0000 0x6000>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0f49ebd..3b0645a 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -120,6 +120,7 @@
compatible = "qcom,gcc-msm8916";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0x1800000 0x80000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [PATCH v6 13/13] arm: dts: qcom: Add #power-domain-cells property
@ 2015-07-22 7:11 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-22 7:11 UTC (permalink / raw)
To: linux-arm-kernel
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which
implement gdsc powerdomains. Add the #power-domain-cells property
to them.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 7084010..1cdb568 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -221,6 +221,7 @@
compatible = "qcom,gcc-apq8084";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 37b47b5..8a2dfa6 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -217,6 +217,7 @@
compatible = "qcom,gcc-msm8974";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
};
@@ -224,6 +225,7 @@
compatible = "qcom,mmcc-msm8974";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfd8c0000 0x6000>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0f49ebd..3b0645a 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -120,6 +120,7 @@
compatible = "qcom,gcc-msm8916";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0x1800000 0x80000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 68+ messages in thread
* Re: [PATCH v6 01/13] clk: qcom: Add support for GDSCs
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-23 0:25 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 0:25 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 59d1666..a7c2eea 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -39,6 +39,11 @@ config IPQ_LCC_806X
> Say Y if you want to use audio devices such as i2s, pcm,
> S/PDIF, etc.
>
> +config QCOM_GDSC
> + bool
> + select PM_GENERIC_DOMAINS if PM
> + depends on COMMON_CLK_QCOM
>
We can drop this depends because it should only be selected if
COMMON_CLK_QCOM anyway.
> +
> config MSM_GCC_8660
> tristate "MSM8660 Global Clock Controller"
> depends on COMMON_CLK_QCOM
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> new file mode 100644
> index 0000000..a59655b
> --- /dev/null
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -0,0 +1,167 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/jiffies.h>
> +#include <linux/slab.h>
#include <linux/bitops.h> for BIT?
#include <linux/kernel.h> for container_of?
Please include linux/pm_domain.h here and linux/regmap.h as well for
completeness even though gdsc.h includes it.
> +#include "gdsc.h"
> +
> +#define PWR_ON_MASK BIT(31)
> +#define EN_REST_WAIT_MASK GENMASK(23, 20)
> +#define EN_FEW_WAIT_MASK GENMASK(19, 16)
> +#define CLK_DIS_WAIT_MASK GENMASK(15, 12)
> +#define SW_OVERRIDE_MASK BIT(2)
> +#define HW_CONTROL_MASK BIT(1)
> +#define SW_COLLAPSE_MASK BIT(0)
> [...]
> +
> +static int gdsc_toggle_logic(struct gdsc *sc, bool en)
> +{
> + int ret;
> + u32 val = en ? 0 : SW_COLLAPSE_MASK;
> + u32 check = en ? PWR_ON_MASK : 0;
> + unsigned long timeout;
> +
> + ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
> + if (ret)
> + return ret;
> +
> + timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
> + do {
> + ret = regmap_read(sc->regmap, sc->gdscr, &val);
> + if (ret)
> + return ret;
> +
> + if ((val & PWR_ON_MASK) == check)
> + return 0;
> + } while (time_before(jiffies, timeout));
> +
> + ret = regmap_read(sc->regmap, sc->gdscr, &val);
Weird double space here.
> + if (ret)
> + return ret;
> +
> + if ((val & PWR_ON_MASK) == check)
> + return 0;
> +
> + return -ETIMEDOUT;
> +}
> +
> [...]
> +
> +int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
> + struct regmap *regmap)
> +{
> + int i, ret;
> + struct genpd_onecell_data *data;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
> + GFP_KERNEL);
> + if (!data->domains)
> + return -ENOMEM;
> +
> + data->num_domains = num;
> + for (i = 0; i < num; i++) {
> + if (!scs[i])
> + continue;
> + scs[i]->regmap = regmap;
> + ret = gdsc_init(scs[i]);
> + if (ret)
> + return ret;
> + data->domains[i] = &scs[i]->pd;
> + }
> +
> + return of_genpd_add_provider_onecell(dev->of_node, data);
> +}
EXPORT_SYMBOL?
> +
> +void gdsc_unregister(struct device *dev)
> +{
> + of_genpd_del_provider(dev->of_node);
> +}
EXPORT_SYMBOL?
> diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
> new file mode 100644
> index 0000000..e26a496
> --- /dev/null
> +++ b/drivers/clk/qcom/gdsc.h
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __QCOM_GDSC_H__
> +#define __QCOM_GDSC_H__
> +
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
Drop this include and forward declare struct regmap.
> +
> +/**
> + * struct gdsc - Globally Distributed Switch Controller
> + * @pd: generic power domain
> + * @regmap: regmap for MMIO accesses
> + * @gdscr: gsdc control register
> + */
> +struct gdsc {
> + struct generic_pm_domain pd;
> + struct regmap *regmap;
> + unsigned int gdscr;
> +};
> +
> +#ifdef CONFIG_QCOM_GDSC
> +int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *);
> +void gdsc_unregister(struct device *);
> +#else
> +static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
> + struct regmap *r)
> +{
> + return -ENOSYS;
We need err.h for this one...
> +}
> +
> +static inline void gdsc_unregister(struct device *d)
> +{};
one line instead of two for this?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 01/13] clk: qcom: Add support for GDSCs
@ 2015-07-23 0:25 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 0:25 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 59d1666..a7c2eea 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -39,6 +39,11 @@ config IPQ_LCC_806X
> Say Y if you want to use audio devices such as i2s, pcm,
> S/PDIF, etc.
>
> +config QCOM_GDSC
> + bool
> + select PM_GENERIC_DOMAINS if PM
> + depends on COMMON_CLK_QCOM
>
We can drop this depends because it should only be selected if
COMMON_CLK_QCOM anyway.
> +
> config MSM_GCC_8660
> tristate "MSM8660 Global Clock Controller"
> depends on COMMON_CLK_QCOM
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> new file mode 100644
> index 0000000..a59655b
> --- /dev/null
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -0,0 +1,167 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/jiffies.h>
> +#include <linux/slab.h>
#include <linux/bitops.h> for BIT?
#include <linux/kernel.h> for container_of?
Please include linux/pm_domain.h here and linux/regmap.h as well for
completeness even though gdsc.h includes it.
> +#include "gdsc.h"
> +
> +#define PWR_ON_MASK BIT(31)
> +#define EN_REST_WAIT_MASK GENMASK(23, 20)
> +#define EN_FEW_WAIT_MASK GENMASK(19, 16)
> +#define CLK_DIS_WAIT_MASK GENMASK(15, 12)
> +#define SW_OVERRIDE_MASK BIT(2)
> +#define HW_CONTROL_MASK BIT(1)
> +#define SW_COLLAPSE_MASK BIT(0)
> [...]
> +
> +static int gdsc_toggle_logic(struct gdsc *sc, bool en)
> +{
> + int ret;
> + u32 val = en ? 0 : SW_COLLAPSE_MASK;
> + u32 check = en ? PWR_ON_MASK : 0;
> + unsigned long timeout;
> +
> + ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
> + if (ret)
> + return ret;
> +
> + timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
> + do {
> + ret = regmap_read(sc->regmap, sc->gdscr, &val);
> + if (ret)
> + return ret;
> +
> + if ((val & PWR_ON_MASK) == check)
> + return 0;
> + } while (time_before(jiffies, timeout));
> +
> + ret = regmap_read(sc->regmap, sc->gdscr, &val);
Weird double space here.
> + if (ret)
> + return ret;
> +
> + if ((val & PWR_ON_MASK) == check)
> + return 0;
> +
> + return -ETIMEDOUT;
> +}
> +
> [...]
> +
> +int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
> + struct regmap *regmap)
> +{
> + int i, ret;
> + struct genpd_onecell_data *data;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
> + GFP_KERNEL);
> + if (!data->domains)
> + return -ENOMEM;
> +
> + data->num_domains = num;
> + for (i = 0; i < num; i++) {
> + if (!scs[i])
> + continue;
> + scs[i]->regmap = regmap;
> + ret = gdsc_init(scs[i]);
> + if (ret)
> + return ret;
> + data->domains[i] = &scs[i]->pd;
> + }
> +
> + return of_genpd_add_provider_onecell(dev->of_node, data);
> +}
EXPORT_SYMBOL?
> +
> +void gdsc_unregister(struct device *dev)
> +{
> + of_genpd_del_provider(dev->of_node);
> +}
EXPORT_SYMBOL?
> diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
> new file mode 100644
> index 0000000..e26a496
> --- /dev/null
> +++ b/drivers/clk/qcom/gdsc.h
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __QCOM_GDSC_H__
> +#define __QCOM_GDSC_H__
> +
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
Drop this include and forward declare struct regmap.
> +
> +/**
> + * struct gdsc - Globally Distributed Switch Controller
> + * @pd: generic power domain
> + * @regmap: regmap for MMIO accesses
> + * @gdscr: gsdc control register
> + */
> +struct gdsc {
> + struct generic_pm_domain pd;
> + struct regmap *regmap;
> + unsigned int gdscr;
> +};
> +
> +#ifdef CONFIG_QCOM_GDSC
> +int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *);
> +void gdsc_unregister(struct device *);
> +#else
> +static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n,
> + struct regmap *r)
> +{
> + return -ENOSYS;
We need err.h for this one...
> +}
> +
> +static inline void gdsc_unregister(struct device *d)
> +{};
one line instead of two for this?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 02/13] clk: qcom: gdsc: Prepare common clk probe to register gdscs
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-23 0:27 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 0:27 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
> @@ -120,8 +121,20 @@ int qcom_cc_really_probe(struct platform_device *pdev,
>
> ret = reset_controller_register(&reset->rcdev);
> if (ret)
> - of_clk_del_provider(dev->of_node);
> + goto err_reset;
>
> + if (desc->gdscs && desc->num_gdscs) {
> + ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap);
> + if (ret)
> + goto err_pd;
> + }
> +
> + return 0;
> +err_pd:
> + dev_err(dev, "Failed to register power domains\n");
Let's just stay silent like we've been doing before.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 02/13] clk: qcom: gdsc: Prepare common clk probe to register gdscs
@ 2015-07-23 0:27 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 0:27 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
> @@ -120,8 +121,20 @@ int qcom_cc_really_probe(struct platform_device *pdev,
>
> ret = reset_controller_register(&reset->rcdev);
> if (ret)
> - of_clk_del_provider(dev->of_node);
> + goto err_reset;
>
> + if (desc->gdscs && desc->num_gdscs) {
> + ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap);
> + if (ret)
> + goto err_pd;
> + }
> +
> + return 0;
> +err_pd:
> + dev_err(dev, "Failed to register power domains\n");
Let's just stay silent like we've been doing before.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
2015-07-22 7:10 ` Rajendra Nayak
@ 2015-07-23 1:01 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:01 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)
> return gdsc_toggle_logic(sc, false);
> }
>
> +static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
> +{
> + int ret;
> + struct gdsc *sc = domain_to_gdsc(domain);
> + char **con_id, *con_ids[] = { "core", "iface", NULL };
const?
This is where I get scared of sniffing too much SoC glue. What's to
enforce the "core", and "iface" naming scheme? What's to enforce there
being two clocks vs. one? Maybe a better approach would be to use
of_clk_get() and iterate through all clocks of the device, or to encode
the clock names in the gdsc structure.
The problem I'm getting at is that we're going through the consumer
struct device's mapping of names to clks when we're inside this SoC glue
code that has to know about what the consumer has decided to do. This
code becomes tightly coupled with that decision that doesn't seem to be
under the glue code's control. Using of_clk_get() sidesteps that
problem, with the loss of flexibility of deciding which clock does what
so at least it's a step in the right direction. But if we want to
control individual clocks then we have to know which clock is which.
Maybe we should associate clk_hw pointers with the gdscs and then export
__clk_hw_create_clk() so that drivers can turn clk_hw pointers into clocks?
> +
> + ret = pm_clk_create(dev);
> + if (ret) {
> + dev_err(dev, "pm_clk_create failed %d\n", ret);
Who cares? debug?
> + return ret;
> + }
> +
> + for (con_id = con_ids; *con_id; con_id++) {
> + ret = pm_clk_add(dev, *con_id);
> + if (ret) {
> + dev_err(dev, "pm_clk_add failed %d\n", ret);
Who cares? debug?
> + goto fail;
> + }
> + }
> + return 0;
> +fail:
> + pm_clk_destroy(dev);
> + return ret;
> +};
> +
> +static void gdsc_detach(struct generic_pm_domain *domain, struct device *dev)
> +{
> + pm_clk_destroy(dev);
> + return;
useless return
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
@ 2015-07-23 1:01 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:01 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)
> return gdsc_toggle_logic(sc, false);
> }
>
> +static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
> +{
> + int ret;
> + struct gdsc *sc = domain_to_gdsc(domain);
> + char **con_id, *con_ids[] = { "core", "iface", NULL };
const?
This is where I get scared of sniffing too much SoC glue. What's to
enforce the "core", and "iface" naming scheme? What's to enforce there
being two clocks vs. one? Maybe a better approach would be to use
of_clk_get() and iterate through all clocks of the device, or to encode
the clock names in the gdsc structure.
The problem I'm getting at is that we're going through the consumer
struct device's mapping of names to clks when we're inside this SoC glue
code that has to know about what the consumer has decided to do. This
code becomes tightly coupled with that decision that doesn't seem to be
under the glue code's control. Using of_clk_get() sidesteps that
problem, with the loss of flexibility of deciding which clock does what
so at least it's a step in the right direction. But if we want to
control individual clocks then we have to know which clock is which.
Maybe we should associate clk_hw pointers with the gdscs and then export
__clk_hw_create_clk() so that drivers can turn clk_hw pointers into clocks?
> +
> + ret = pm_clk_create(dev);
> + if (ret) {
> + dev_err(dev, "pm_clk_create failed %d\n", ret);
Who cares? debug?
> + return ret;
> + }
> +
> + for (con_id = con_ids; *con_id; con_id++) {
> + ret = pm_clk_add(dev, *con_id);
> + if (ret) {
> + dev_err(dev, "pm_clk_add failed %d\n", ret);
Who cares? debug?
> + goto fail;
> + }
> + }
> + return 0;
> +fail:
> + pm_clk_destroy(dev);
> + return ret;
> +};
> +
> +static void gdsc_detach(struct generic_pm_domain *domain, struct device *dev)
> +{
> + pm_clk_destroy(dev);
> + return;
useless return
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
2015-07-22 7:11 ` Rajendra Nayak
@ 2015-07-23 1:03 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:03 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> With CONFIG_PM disabled, turn the devices clocks on during
> driver binding to the device, and turn them off when the
> driver is unbound from the device.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
> drivers/clk/qcom/gdsc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index 3125809..9ddd2f8 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -16,6 +16,7 @@
> #include <linux/jiffies.h>
> #include <linux/pm_clock.h>
> #include <linux/slab.h>
> +#include <linux/platform_device.h>
#include <linux/clk.h>?
> #include "gdsc.h"
>
> #define PWR_ON_MASK BIT(31)
> @@ -200,3 +201,61 @@ void gdsc_unregister(struct device *dev)
> {
> of_genpd_del_provider(dev->of_node);
> }
> +
> +#ifndef CONFIG_PM
> +static void enable_clock(struct device *dev, const char *con_id)
> +{
> + struct clk *clk;
> +
> + clk = clk_get(dev, con_id);
> + if (!IS_ERR(clk)) {
> + clk_prepare_enable(clk);
> + clk_put(clk);
> + }
> +}
> +
> +static void disable_clock(struct device *dev, const char *con_id)
> +{
> + struct clk *clk;
> +
> + clk = clk_get(dev, con_id);
> + if (!IS_ERR(clk)) {
> + clk_disable_unprepare(clk);
> + clk_put(clk);
> + }
> +}
Is there a reason why this whole patch isn't generic code? I recall some
discussion but I forgot now and there isn't any mention of why this
isn't generic code in the commit text.
> +
> +static int clk_notify(struct notifier_block *nb, unsigned long action,
> + void *data)
> +{
> + int sz;
> + struct device *dev = data;
> + char **con_id, *con_ids[] = { "core", "iface", NULL };
This again?
> +
> + if (!of_find_property(dev->of_node, "power-domains", &sz))
> + return 0;
> +
> + switch (action) {
> + case BUS_NOTIFY_BIND_DRIVER:
> + for (con_id = con_ids; *con_id; con_id++)
> + enable_clock(dev, *con_id);
> + break;
> + case BUS_NOTIFY_UNBOUND_DRIVER:
> + for (con_id = con_ids; *con_id; con_id++)
> + disable_clock(dev, *con_id);
> + break;
> + }
> + return 0;
> +}
> +
> +struct notifier_block nb = {
static?
> + .notifier_call = clk_notify,
> +};
> +
> +int qcom_pm_runtime_init(void)
static? __init?
> +{
> + bus_register_notifier(&platform_bus_type, &nb);
> + return 0;
return bus_register_notifier()?
> +}
> +core_initcall(qcom_pm_runtime_init);
> +#endif
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
@ 2015-07-23 1:03 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:03 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> With CONFIG_PM disabled, turn the devices clocks on during
> driver binding to the device, and turn them off when the
> driver is unbound from the device.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
> drivers/clk/qcom/gdsc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index 3125809..9ddd2f8 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -16,6 +16,7 @@
> #include <linux/jiffies.h>
> #include <linux/pm_clock.h>
> #include <linux/slab.h>
> +#include <linux/platform_device.h>
#include <linux/clk.h>?
> #include "gdsc.h"
>
> #define PWR_ON_MASK BIT(31)
> @@ -200,3 +201,61 @@ void gdsc_unregister(struct device *dev)
> {
> of_genpd_del_provider(dev->of_node);
> }
> +
> +#ifndef CONFIG_PM
> +static void enable_clock(struct device *dev, const char *con_id)
> +{
> + struct clk *clk;
> +
> + clk = clk_get(dev, con_id);
> + if (!IS_ERR(clk)) {
> + clk_prepare_enable(clk);
> + clk_put(clk);
> + }
> +}
> +
> +static void disable_clock(struct device *dev, const char *con_id)
> +{
> + struct clk *clk;
> +
> + clk = clk_get(dev, con_id);
> + if (!IS_ERR(clk)) {
> + clk_disable_unprepare(clk);
> + clk_put(clk);
> + }
> +}
Is there a reason why this whole patch isn't generic code? I recall some
discussion but I forgot now and there isn't any mention of why this
isn't generic code in the commit text.
> +
> +static int clk_notify(struct notifier_block *nb, unsigned long action,
> + void *data)
> +{
> + int sz;
> + struct device *dev = data;
> + char **con_id, *con_ids[] = { "core", "iface", NULL };
This again?
> +
> + if (!of_find_property(dev->of_node, "power-domains", &sz))
> + return 0;
> +
> + switch (action) {
> + case BUS_NOTIFY_BIND_DRIVER:
> + for (con_id = con_ids; *con_id; con_id++)
> + enable_clock(dev, *con_id);
> + break;
> + case BUS_NOTIFY_UNBOUND_DRIVER:
> + for (con_id = con_ids; *con_id; con_id++)
> + disable_clock(dev, *con_id);
> + break;
> + }
> + return 0;
> +}
> +
> +struct notifier_block nb = {
static?
> + .notifier_call = clk_notify,
> +};
> +
> +int qcom_pm_runtime_init(void)
static? __init?
> +{
> + bus_register_notifier(&platform_bus_type, &nb);
> + return 0;
return bus_register_notifier()?
> +}
> +core_initcall(qcom_pm_runtime_init);
> +#endif
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 08/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC
2015-07-22 7:11 ` Rajendra Nayak
@ 2015-07-23 1:07 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:07 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> @@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
> },
> };
>
> +static struct gdsc venus_gdsc = {
> + .gdscr = 0x4c018,
> + .pd = {
> + .name = "venus",
> + },
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
> +static struct gdsc mdss_gdsc = {
> + .gdscr = 0x4d078,
> + .pd = {
> + .name = "mdss",
> + },
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
> +static struct gdsc jpeg_gdsc = {
> + .gdscr = 0x5701c,
> + .pd = {
> + .name = "jpeg",
> + },
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
> +static struct gdsc vfe_gdsc = {
> + .gdscr = 0x58034,
> + .pd = {
> + .name = "vfe",
> + },
> + .pwrsts = PWRDM_OFF_ON,
Is this supposed to tbe PWRSTS_OFF_ON?
> +};
> +
> +static struct gdsc oxili_gdsc = {
> + .gdscr = 0x5901c,
> + .pd = {
> + .name = "oxili",
> + },
> + .root_con_id = "gfx3d_clk_src",
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 08/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC
@ 2015-07-23 1:07 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:07 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> @@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
> },
> };
>
> +static struct gdsc venus_gdsc = {
> + .gdscr = 0x4c018,
> + .pd = {
> + .name = "venus",
> + },
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
> +static struct gdsc mdss_gdsc = {
> + .gdscr = 0x4d078,
> + .pd = {
> + .name = "mdss",
> + },
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
> +static struct gdsc jpeg_gdsc = {
> + .gdscr = 0x5701c,
> + .pd = {
> + .name = "jpeg",
> + },
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
> +static struct gdsc vfe_gdsc = {
> + .gdscr = 0x58034,
> + .pd = {
> + .name = "vfe",
> + },
> + .pwrsts = PWRDM_OFF_ON,
Is this supposed to tbe PWRSTS_OFF_ON?
> +};
> +
> +static struct gdsc oxili_gdsc = {
> + .gdscr = 0x5901c,
> + .pd = {
> + .name = "oxili",
> + },
> + .root_con_id = "gfx3d_clk_src",
> + .pwrsts = PWRDM_OFF_ON,
> +};
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 09/13] clk: qcom: gdsc: Add GDSCs in msm8974 GCC
2015-07-22 7:11 ` Rajendra Nayak
@ 2015-07-23 1:08 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:08 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> From: Stephen Boyd <sboyd@codeaurora.org>
>
> Theres just one GDSC as part of the msm8974 GCC block.
s/Theres/There's/
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 09/13] clk: qcom: gdsc: Add GDSCs in msm8974 GCC
@ 2015-07-23 1:08 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:08 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> From: Stephen Boyd <sboyd@codeaurora.org>
>
> Theres just one GDSC as part of the msm8974 GCC block.
s/Theres/There's/
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 10/13] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
2015-07-22 7:11 ` Rajendra Nayak
@ 2015-07-23 1:09 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:09 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> From: Stephen Boyd <sboyd@codeaurora.org>
>
> Add the GDSC instances that exist as part of msm8974 MMCC block
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>
From here on it looks fine, just routine data additions.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 10/13] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
@ 2015-07-23 1:09 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:09 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> From: Stephen Boyd <sboyd@codeaurora.org>
>
> Add the GDSC instances that exist as part of msm8974 MMCC block
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>
From here on it looks fine, just routine data additions.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 07/13] clk: qcom: gdsc: Add support for ON only state
2015-07-22 7:11 ` Rajendra Nayak
@ 2015-07-23 1:11 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:11 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> @@ -200,6 +224,12 @@ static int gdsc_init(struct gdsc *sc)
> if (ret)
> return ret;
>
> + /* Force gdsc ON if only ON state is supported */
> + if (sc->pwrsts == PWRSTS_ON)
> + ret = gdsc_toggle_logic(sc, true);
> + if (ret)
> + return ret;
This is missing braces. Please test :)
> +
> on = gdsc_is_enabled(sc);
> if (on < 0)
> return on;
>
> diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
> index 87c4ace..0d1c4fb 100644
> --- a/drivers/clk/qcom/gdsc.h
> +++ b/drivers/clk/qcom/gdsc.h
> @@ -17,6 +17,7 @@
> #include <linux/clk.h>
> #include <linux/pm_domain.h>
> #include <linux/regmap.h>
> +#include <linux/reset-controller.h>
Do we need this include either? Just forward declare stuff. Same comment
goes for the clk include.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 07/13] clk: qcom: gdsc: Add support for ON only state
@ 2015-07-23 1:11 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 1:11 UTC (permalink / raw)
To: linux-arm-kernel
On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
> @@ -200,6 +224,12 @@ static int gdsc_init(struct gdsc *sc)
> if (ret)
> return ret;
>
> + /* Force gdsc ON if only ON state is supported */
> + if (sc->pwrsts == PWRSTS_ON)
> + ret = gdsc_toggle_logic(sc, true);
> + if (ret)
> + return ret;
This is missing braces. Please test :)
> +
> on = gdsc_is_enabled(sc);
> if (on < 0)
> return on;
>
> diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
> index 87c4ace..0d1c4fb 100644
> --- a/drivers/clk/qcom/gdsc.h
> +++ b/drivers/clk/qcom/gdsc.h
> @@ -17,6 +17,7 @@
> #include <linux/clk.h>
> #include <linux/pm_domain.h>
> #include <linux/regmap.h>
> +#include <linux/reset-controller.h>
Do we need this include either? Just forward declare stuff. Same comment
goes for the clk include.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
2015-07-23 1:01 ` Stephen Boyd
@ 2015-07-23 8:34 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:34 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/23/2015 06:31 AM, Stephen Boyd wrote:
> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain
>> *domain)
>> return gdsc_toggle_logic(sc, false);
>> }
>> +static int gdsc_attach(struct generic_pm_domain *domain, struct
>> device *dev)
>> +{
>> + int ret;
>> + struct gdsc *sc = domain_to_gdsc(domain);
>> + char **con_id, *con_ids[] = { "core", "iface", NULL };
>
> const?
>
> This is where I get scared of sniffing too much SoC glue. What's to
> enforce the "core", and "iface" naming scheme? What's to enforce there
> being two clocks vs. one? Maybe a better approach would be to use
> of_clk_get() and iterate through all clocks of the device, or to encode
> the clock names in the gdsc structure.
I had the clock names in the gdsc structure in v5. I should probably go
back to having it that way.
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
@ 2015-07-23 8:34 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:34 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2015 06:31 AM, Stephen Boyd wrote:
> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain
>> *domain)
>> return gdsc_toggle_logic(sc, false);
>> }
>> +static int gdsc_attach(struct generic_pm_domain *domain, struct
>> device *dev)
>> +{
>> + int ret;
>> + struct gdsc *sc = domain_to_gdsc(domain);
>> + char **con_id, *con_ids[] = { "core", "iface", NULL };
>
> const?
>
> This is where I get scared of sniffing too much SoC glue. What's to
> enforce the "core", and "iface" naming scheme? What's to enforce there
> being two clocks vs. one? Maybe a better approach would be to use
> of_clk_get() and iterate through all clocks of the device, or to encode
> the clock names in the gdsc structure.
I had the clock names in the gdsc structure in v5. I should probably go
back to having it that way.
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
2015-07-23 1:03 ` Stephen Boyd
@ 2015-07-23 8:35 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:35 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
[]..
>> +
>> +#ifndef CONFIG_PM
>> +static void enable_clock(struct device *dev, const char *con_id)
>> +{
>> + struct clk *clk;
>> +
>> + clk = clk_get(dev, con_id);
>> + if (!IS_ERR(clk)) {
>> + clk_prepare_enable(clk);
>> + clk_put(clk);
>> + }
>> +}
>> +
>> +static void disable_clock(struct device *dev, const char *con_id)
>> +{
>> + struct clk *clk;
>> +
>> + clk = clk_get(dev, con_id);
>> + if (!IS_ERR(clk)) {
>> + clk_disable_unprepare(clk);
>> + clk_put(clk);
>> + }
>> +}
>
> Is there a reason why this whole patch isn't generic code? I recall some
> discussion but I forgot now and there isn't any mention of why this
> isn't generic code in the commit text.
If by generic code, you mean using PM clocks, then this thread should
give some context..
http://www.spinics.net/lists/arm-kernel/msg414072.html
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
@ 2015-07-23 8:35 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:35 UTC (permalink / raw)
To: linux-arm-kernel
[]..
>> +
>> +#ifndef CONFIG_PM
>> +static void enable_clock(struct device *dev, const char *con_id)
>> +{
>> + struct clk *clk;
>> +
>> + clk = clk_get(dev, con_id);
>> + if (!IS_ERR(clk)) {
>> + clk_prepare_enable(clk);
>> + clk_put(clk);
>> + }
>> +}
>> +
>> +static void disable_clock(struct device *dev, const char *con_id)
>> +{
>> + struct clk *clk;
>> +
>> + clk = clk_get(dev, con_id);
>> + if (!IS_ERR(clk)) {
>> + clk_disable_unprepare(clk);
>> + clk_put(clk);
>> + }
>> +}
>
> Is there a reason why this whole patch isn't generic code? I recall some
> discussion but I forgot now and there isn't any mention of why this
> isn't generic code in the commit text.
If by generic code, you mean using PM clocks, then this thread should
give some context..
http://www.spinics.net/lists/arm-kernel/msg414072.html
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 08/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC
2015-07-23 1:07 ` Stephen Boyd
@ 2015-07-23 8:36 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:36 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/23/2015 06:37 AM, Stephen Boyd wrote:
> On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
>> @@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk
>> = {
>> },
>> };
>> +static struct gdsc venus_gdsc = {
>> + .gdscr = 0x4c018,
>> + .pd = {
>> + .name = "venus",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>> +};
>> +
>> +static struct gdsc mdss_gdsc = {
>> + .gdscr = 0x4d078,
>> + .pd = {
>> + .name = "mdss",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>> +};
>> +
>> +static struct gdsc jpeg_gdsc = {
>> + .gdscr = 0x5701c,
>> + .pd = {
>> + .name = "jpeg",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>> +};
>> +
>> +static struct gdsc vfe_gdsc = {
>> + .gdscr = 0x58034,
>> + .pd = {
>> + .name = "vfe",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>
> Is this supposed to tbe PWRSTS_OFF_ON?
indeed, will fix.
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 08/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC
@ 2015-07-23 8:36 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:36 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2015 06:37 AM, Stephen Boyd wrote:
> On 07/22/2015 12:11 AM, Rajendra Nayak wrote:
>> @@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk
>> = {
>> },
>> };
>> +static struct gdsc venus_gdsc = {
>> + .gdscr = 0x4c018,
>> + .pd = {
>> + .name = "venus",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>> +};
>> +
>> +static struct gdsc mdss_gdsc = {
>> + .gdscr = 0x4d078,
>> + .pd = {
>> + .name = "mdss",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>> +};
>> +
>> +static struct gdsc jpeg_gdsc = {
>> + .gdscr = 0x5701c,
>> + .pd = {
>> + .name = "jpeg",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>> +};
>> +
>> +static struct gdsc vfe_gdsc = {
>> + .gdscr = 0x58034,
>> + .pd = {
>> + .name = "vfe",
>> + },
>> + .pwrsts = PWRDM_OFF_ON,
>
> Is this supposed to tbe PWRSTS_OFF_ON?
indeed, will fix.
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 01/13] clk: qcom: Add support for GDSCs
2015-07-23 0:25 ` Stephen Boyd
@ 2015-07-23 8:37 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:37 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/23/2015 05:55 AM, Stephen Boyd wrote:
> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 59d1666..a7c2eea 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -39,6 +39,11 @@ config IPQ_LCC_806X
>> Say Y if you want to use audio devices such as i2s, pcm,
>> S/PDIF, etc.
>> +config QCOM_GDSC
>> + bool
>> + select PM_GENERIC_DOMAINS if PM
>> + depends on COMMON_CLK_QCOM
>>
>
> We can drop this depends because it should only be selected if
> COMMON_CLK_QCOM anyway.
Stephen, thanks for the review. I'll fix up this and others you pointed
to in this patch and others in the series.
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 01/13] clk: qcom: Add support for GDSCs
@ 2015-07-23 8:37 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 8:37 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2015 05:55 AM, Stephen Boyd wrote:
> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 59d1666..a7c2eea 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -39,6 +39,11 @@ config IPQ_LCC_806X
>> Say Y if you want to use audio devices such as i2s, pcm,
>> S/PDIF, etc.
>> +config QCOM_GDSC
>> + bool
>> + select PM_GENERIC_DOMAINS if PM
>> + depends on COMMON_CLK_QCOM
>>
>
> We can drop this depends because it should only be selected if
> COMMON_CLK_QCOM anyway.
Stephen, thanks for the review. I'll fix up this and others you pointed
to in this patch and others in the series.
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 01/13] clk: qcom: Add support for GDSCs
2015-07-23 0:25 ` Stephen Boyd
@ 2015-07-23 9:09 ` Stanimir Varbanov
-1 siblings, 0 replies; 68+ messages in thread
From: Stanimir Varbanov @ 2015-07-23 9:09 UTC (permalink / raw)
To: Stephen Boyd, Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, srinivas.kandagatla, sviau
<snip>
>> +
>> +int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
>> + struct regmap *regmap)
>> +{
>> + int i, ret;
>> + struct genpd_onecell_data *data;
>> +
>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
>> + GFP_KERNEL);
>> + if (!data->domains)
>> + return -ENOMEM;
>> +
>> + data->num_domains = num;
>> + for (i = 0; i < num; i++) {
>> + if (!scs[i])
>> + continue;
>> + scs[i]->regmap = regmap;
>> + ret = gdsc_init(scs[i]);
>> + if (ret)
>> + return ret;
>> + data->domains[i] = &scs[i]->pd;
>> + }
>> +
>> + return of_genpd_add_provider_onecell(dev->of_node, data);
>> +}
>
> EXPORT_SYMBOL?
>
>> +
>> +void gdsc_unregister(struct device *dev)
>> +{
>> + of_genpd_del_provider(dev->of_node);
>> +}
>
> EXPORT_SYMBOL?
Stephen, gdsc_register/unregister are internal to the qcom clk driver
why to export them?
--
regards,
Stan
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 01/13] clk: qcom: Add support for GDSCs
@ 2015-07-23 9:09 ` Stanimir Varbanov
0 siblings, 0 replies; 68+ messages in thread
From: Stanimir Varbanov @ 2015-07-23 9:09 UTC (permalink / raw)
To: linux-arm-kernel
<snip>
>> +
>> +int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
>> + struct regmap *regmap)
>> +{
>> + int i, ret;
>> + struct genpd_onecell_data *data;
>> +
>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
>> + GFP_KERNEL);
>> + if (!data->domains)
>> + return -ENOMEM;
>> +
>> + data->num_domains = num;
>> + for (i = 0; i < num; i++) {
>> + if (!scs[i])
>> + continue;
>> + scs[i]->regmap = regmap;
>> + ret = gdsc_init(scs[i]);
>> + if (ret)
>> + return ret;
>> + data->domains[i] = &scs[i]->pd;
>> + }
>> +
>> + return of_genpd_add_provider_onecell(dev->of_node, data);
>> +}
>
> EXPORT_SYMBOL?
>
>> +
>> +void gdsc_unregister(struct device *dev)
>> +{
>> + of_genpd_del_provider(dev->of_node);
>> +}
>
> EXPORT_SYMBOL?
Stephen, gdsc_register/unregister are internal to the qcom clk driver
why to export them?
--
regards,
Stan
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
2015-07-23 8:34 ` Rajendra Nayak
@ 2015-07-23 9:22 ` Stanimir Varbanov
-1 siblings, 0 replies; 68+ messages in thread
From: Stanimir Varbanov @ 2015-07-23 9:22 UTC (permalink / raw)
To: Rajendra Nayak, Stephen Boyd
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, srinivas.kandagatla, sviau
On 07/23/2015 11:34 AM, Rajendra Nayak wrote:
> On 07/23/2015 06:31 AM, Stephen Boyd wrote:
>> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>>> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain
>>> *domain)
>>> return gdsc_toggle_logic(sc, false);
>>> }
>>> +static int gdsc_attach(struct generic_pm_domain *domain, struct
>>> device *dev)
>>> +{
>>> + int ret;
>>> + struct gdsc *sc = domain_to_gdsc(domain);
>>> + char **con_id, *con_ids[] = { "core", "iface", NULL };
>>
>> const?
>>
>> This is where I get scared of sniffing too much SoC glue. What's to
>> enforce the "core", and "iface" naming scheme? What's to enforce there
>> being two clocks vs. one? Maybe a better approach would be to use
>> of_clk_get() and iterate through all clocks of the device, or to encode
>> the clock names in the gdsc structure.
>
> I had the clock names in the gdsc structure in v5. I should probably go
> back to having it that way.
Rajendra, If you decide to go back please look at that comment [1], as well.
--
regards,
Stan
[1] http://www.spinics.net/lists/linux-arm-msm/msg15040.html
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
@ 2015-07-23 9:22 ` Stanimir Varbanov
0 siblings, 0 replies; 68+ messages in thread
From: Stanimir Varbanov @ 2015-07-23 9:22 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2015 11:34 AM, Rajendra Nayak wrote:
> On 07/23/2015 06:31 AM, Stephen Boyd wrote:
>> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>>> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain
>>> *domain)
>>> return gdsc_toggle_logic(sc, false);
>>> }
>>> +static int gdsc_attach(struct generic_pm_domain *domain, struct
>>> device *dev)
>>> +{
>>> + int ret;
>>> + struct gdsc *sc = domain_to_gdsc(domain);
>>> + char **con_id, *con_ids[] = { "core", "iface", NULL };
>>
>> const?
>>
>> This is where I get scared of sniffing too much SoC glue. What's to
>> enforce the "core", and "iface" naming scheme? What's to enforce there
>> being two clocks vs. one? Maybe a better approach would be to use
>> of_clk_get() and iterate through all clocks of the device, or to encode
>> the clock names in the gdsc structure.
>
> I had the clock names in the gdsc structure in v5. I should probably go
> back to having it that way.
Rajendra, If you decide to go back please look at that comment [1], as well.
--
regards,
Stan
[1] http://www.spinics.net/lists/linux-arm-msm/msg15040.html
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
2015-07-23 9:22 ` Stanimir Varbanov
@ 2015-07-23 10:28 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 10:28 UTC (permalink / raw)
To: Stanimir Varbanov, Stephen Boyd
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, srinivas.kandagatla, sviau
On 07/23/2015 02:52 PM, Stanimir Varbanov wrote:
> On 07/23/2015 11:34 AM, Rajendra Nayak wrote:
>> On 07/23/2015 06:31 AM, Stephen Boyd wrote:
>>> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>>>> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain
>>>> *domain)
>>>> return gdsc_toggle_logic(sc, false);
>>>> }
>>>> +static int gdsc_attach(struct generic_pm_domain *domain, struct
>>>> device *dev)
>>>> +{
>>>> + int ret;
>>>> + struct gdsc *sc = domain_to_gdsc(domain);
>>>> + char **con_id, *con_ids[] = { "core", "iface", NULL };
>>>
>>> const?
>>>
>>> This is where I get scared of sniffing too much SoC glue. What's to
>>> enforce the "core", and "iface" naming scheme? What's to enforce there
>>> being two clocks vs. one? Maybe a better approach would be to use
>>> of_clk_get() and iterate through all clocks of the device, or to encode
>>> the clock names in the gdsc structure.
>>
>> I had the clock names in the gdsc structure in v5. I should probably go
>> back to having it that way.
>
> Rajendra, If you decide to go back please look at that comment [1], as well.
yes, thanks, I will.
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks
@ 2015-07-23 10:28 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-23 10:28 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2015 02:52 PM, Stanimir Varbanov wrote:
> On 07/23/2015 11:34 AM, Rajendra Nayak wrote:
>> On 07/23/2015 06:31 AM, Stephen Boyd wrote:
>>> On 07/22/2015 12:10 AM, Rajendra Nayak wrote:
>>>> @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain
>>>> *domain)
>>>> return gdsc_toggle_logic(sc, false);
>>>> }
>>>> +static int gdsc_attach(struct generic_pm_domain *domain, struct
>>>> device *dev)
>>>> +{
>>>> + int ret;
>>>> + struct gdsc *sc = domain_to_gdsc(domain);
>>>> + char **con_id, *con_ids[] = { "core", "iface", NULL };
>>>
>>> const?
>>>
>>> This is where I get scared of sniffing too much SoC glue. What's to
>>> enforce the "core", and "iface" naming scheme? What's to enforce there
>>> being two clocks vs. one? Maybe a better approach would be to use
>>> of_clk_get() and iterate through all clocks of the device, or to encode
>>> the clock names in the gdsc structure.
>>
>> I had the clock names in the gdsc structure in v5. I should probably go
>> back to having it that way.
>
> Rajendra, If you decide to go back please look at that comment [1], as well.
yes, thanks, I will.
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 01/13] clk: qcom: Add support for GDSCs
2015-07-23 9:09 ` Stanimir Varbanov
@ 2015-07-23 18:04 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 18:04 UTC (permalink / raw)
To: Stanimir Varbanov
Cc: Rajendra Nayak, mturquette, linux-arm-msm, linux-arm-kernel,
linux-pm, georgi.djakov, srinivas.kandagatla, sviau
On 07/23/2015 02:09 AM, Stanimir Varbanov wrote:
> <snip>
>
>>
>> +
>> +void gdsc_unregister(struct device *dev)
>> +{
>> + of_genpd_del_provider(dev->of_node);
>> +}
>> EXPORT_SYMBOL?
> Stephen, gdsc_register/unregister are internal to the qcom clk driver
> why to export them?
>
Ah, I thought this was being called from outside the clk-qcom.ko module.
As long as we don't call them from a SoC specific driver then it should
be ok to leave them unexported. Perhaps we should remove the export on
qcom_find_freq() too?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 01/13] clk: qcom: Add support for GDSCs
@ 2015-07-23 18:04 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-23 18:04 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2015 02:09 AM, Stanimir Varbanov wrote:
> <snip>
>
>>
>> +
>> +void gdsc_unregister(struct device *dev)
>> +{
>> + of_genpd_del_provider(dev->of_node);
>> +}
>> EXPORT_SYMBOL?
> Stephen, gdsc_register/unregister are internal to the qcom clk driver
> why to export them?
>
Ah, I thought this was being called from outside the clk-qcom.ko module.
As long as we don't call them from a SoC specific driver then it should
be ok to leave them unexported. Perhaps we should remove the export on
qcom_find_freq() too?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
2015-07-23 8:35 ` Rajendra Nayak
@ 2015-07-29 1:04 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-29 1:04 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/23/2015 01:35 AM, Rajendra Nayak wrote:
> []..
>
>>> +
>>> +#ifndef CONFIG_PM
>>> +static void enable_clock(struct device *dev, const char *con_id)
>>> +{
>>> + struct clk *clk;
>>> +
>>> + clk = clk_get(dev, con_id);
>>> + if (!IS_ERR(clk)) {
>>> + clk_prepare_enable(clk);
>>> + clk_put(clk);
>>> + }
>>> +}
>>> +
>>> +static void disable_clock(struct device *dev, const char *con_id)
>>> +{
>>> + struct clk *clk;
>>> +
>>> + clk = clk_get(dev, con_id);
>>> + if (!IS_ERR(clk)) {
>>> + clk_disable_unprepare(clk);
>>> + clk_put(clk);
>>> + }
>>> +}
>>
>> Is there a reason why this whole patch isn't generic code? I recall some
>> discussion but I forgot now and there isn't any mention of why this
>> isn't generic code in the commit text.
>
> If by generic code, you mean using PM clocks, then this thread should
> give some context..
> http://www.spinics.net/lists/arm-kernel/msg414072.html
Sorry, I read the thread and I tried to understand what was going on but
I'm still lost. Can you clarify further in the commit text somehow?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
@ 2015-07-29 1:04 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-29 1:04 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2015 01:35 AM, Rajendra Nayak wrote:
> []..
>
>>> +
>>> +#ifndef CONFIG_PM
>>> +static void enable_clock(struct device *dev, const char *con_id)
>>> +{
>>> + struct clk *clk;
>>> +
>>> + clk = clk_get(dev, con_id);
>>> + if (!IS_ERR(clk)) {
>>> + clk_prepare_enable(clk);
>>> + clk_put(clk);
>>> + }
>>> +}
>>> +
>>> +static void disable_clock(struct device *dev, const char *con_id)
>>> +{
>>> + struct clk *clk;
>>> +
>>> + clk = clk_get(dev, con_id);
>>> + if (!IS_ERR(clk)) {
>>> + clk_disable_unprepare(clk);
>>> + clk_put(clk);
>>> + }
>>> +}
>>
>> Is there a reason why this whole patch isn't generic code? I recall some
>> discussion but I forgot now and there isn't any mention of why this
>> isn't generic code in the commit text.
>
> If by generic code, you mean using PM clocks, then this thread should
> give some context..
> http://www.spinics.net/lists/arm-kernel/msg414072.html
Sorry, I read the thread and I tried to understand what was going on but
I'm still lost. Can you clarify further in the commit text somehow?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
2015-07-29 1:04 ` Stephen Boyd
@ 2015-07-29 4:37 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-29 4:37 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/29/2015 06:34 AM, Stephen Boyd wrote:
> On 07/23/2015 01:35 AM, Rajendra Nayak wrote:
>> []..
>>
>>>> +
>>>> +#ifndef CONFIG_PM
>>>> +static void enable_clock(struct device *dev, const char *con_id)
>>>> +{
>>>> + struct clk *clk;
>>>> +
>>>> + clk = clk_get(dev, con_id);
>>>> + if (!IS_ERR(clk)) {
>>>> + clk_prepare_enable(clk);
>>>> + clk_put(clk);
>>>> + }
>>>> +}
>>>> +
>>>> +static void disable_clock(struct device *dev, const char *con_id)
>>>> +{
>>>> + struct clk *clk;
>>>> +
>>>> + clk = clk_get(dev, con_id);
>>>> + if (!IS_ERR(clk)) {
>>>> + clk_disable_unprepare(clk);
>>>> + clk_put(clk);
>>>> + }
>>>> +}
>>>
>>> Is there a reason why this whole patch isn't generic code? I recall some
>>> discussion but I forgot now and there isn't any mention of why this
>>> isn't generic code in the commit text.
>>
>> If by generic code, you mean using PM clocks, then this thread should
>> give some context..
>> http://www.spinics.net/lists/arm-kernel/msg414072.html
>
> Sorry, I read the thread and I tried to understand what was going on but
> I'm still lost. Can you clarify further in the commit text somehow?
So I can add this in the commit text, if it seems fine
"The use of pm_clk_add_notifier() isn't appropriate here since we need
to only manage clocks with valid power domain associations done via
DT, instead of what pm_clk_add_notifier() does, which is manage clocks
for all on SoC/off SoC devices associating all of them to a dummy power
domain instead"
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
@ 2015-07-29 4:37 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-29 4:37 UTC (permalink / raw)
To: linux-arm-kernel
On 07/29/2015 06:34 AM, Stephen Boyd wrote:
> On 07/23/2015 01:35 AM, Rajendra Nayak wrote:
>> []..
>>
>>>> +
>>>> +#ifndef CONFIG_PM
>>>> +static void enable_clock(struct device *dev, const char *con_id)
>>>> +{
>>>> + struct clk *clk;
>>>> +
>>>> + clk = clk_get(dev, con_id);
>>>> + if (!IS_ERR(clk)) {
>>>> + clk_prepare_enable(clk);
>>>> + clk_put(clk);
>>>> + }
>>>> +}
>>>> +
>>>> +static void disable_clock(struct device *dev, const char *con_id)
>>>> +{
>>>> + struct clk *clk;
>>>> +
>>>> + clk = clk_get(dev, con_id);
>>>> + if (!IS_ERR(clk)) {
>>>> + clk_disable_unprepare(clk);
>>>> + clk_put(clk);
>>>> + }
>>>> +}
>>>
>>> Is there a reason why this whole patch isn't generic code? I recall some
>>> discussion but I forgot now and there isn't any mention of why this
>>> isn't generic code in the commit text.
>>
>> If by generic code, you mean using PM clocks, then this thread should
>> give some context..
>> http://www.spinics.net/lists/arm-kernel/msg414072.html
>
> Sorry, I read the thread and I tried to understand what was going on but
> I'm still lost. Can you clarify further in the commit text somehow?
So I can add this in the commit text, if it seems fine
"The use of pm_clk_add_notifier() isn't appropriate here since we need
to only manage clocks with valid power domain associations done via
DT, instead of what pm_clk_add_notifier() does, which is manage clocks
for all on SoC/off SoC devices associating all of them to a dummy power
domain instead"
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
2015-07-29 4:37 ` Rajendra Nayak
@ 2015-07-30 0:13 ` Stephen Boyd
-1 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-30 0:13 UTC (permalink / raw)
To: Rajendra Nayak
Cc: mturquette, linux-arm-msm, linux-arm-kernel, linux-pm,
georgi.djakov, svarbanov, srinivas.kandagatla, sviau
On 07/29, Rajendra Nayak wrote:
>
> On 07/29/2015 06:34 AM, Stephen Boyd wrote:
> >
> >Sorry, I read the thread and I tried to understand what was going on but
> >I'm still lost. Can you clarify further in the commit text somehow?
>
> So I can add this in the commit text, if it seems fine
>
> "The use of pm_clk_add_notifier() isn't appropriate here since we need
> to only manage clocks with valid power domain associations done via
> DT, instead of what pm_clk_add_notifier() does, which is manage clocks
> for all on SoC/off SoC devices associating all of them to a dummy
> power domain instead"
>
Yes that's good, thanks. But I still wonder why the code isn't
generic so that we don't have lots of drivers duplicating the
same logic. I guess we can consolidate another day.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
@ 2015-07-30 0:13 ` Stephen Boyd
0 siblings, 0 replies; 68+ messages in thread
From: Stephen Boyd @ 2015-07-30 0:13 UTC (permalink / raw)
To: linux-arm-kernel
On 07/29, Rajendra Nayak wrote:
>
> On 07/29/2015 06:34 AM, Stephen Boyd wrote:
> >
> >Sorry, I read the thread and I tried to understand what was going on but
> >I'm still lost. Can you clarify further in the commit text somehow?
>
> So I can add this in the commit text, if it seems fine
>
> "The use of pm_clk_add_notifier() isn't appropriate here since we need
> to only manage clocks with valid power domain associations done via
> DT, instead of what pm_clk_add_notifier() does, which is manage clocks
> for all on SoC/off SoC devices associating all of them to a dummy
> power domain instead"
>
Yes that's good, thanks. But I still wonder why the code isn't
generic so that we don't have lots of drivers duplicating the
same logic. I guess we can consolidate another day.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
2015-07-30 0:13 ` Stephen Boyd
@ 2015-07-30 1:39 ` Rajendra Nayak
-1 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-30 1:39 UTC (permalink / raw)
To: Stephen Boyd
Cc: Rajendra Nayak, mturquette, linux-arm-msm, linux-arm-kernel,
linux-pm, georgi.djakov, svarbanov, srinivas.kandagatla, sviau
> On 07/29, Rajendra Nayak wrote:
>>
>> On 07/29/2015 06:34 AM, Stephen Boyd wrote:
>> >
>> >Sorry, I read the thread and I tried to understand what was going on
>> but
>> >I'm still lost. Can you clarify further in the commit text somehow?
>>
>> So I can add this in the commit text, if it seems fine
>>
>> "The use of pm_clk_add_notifier() isn't appropriate here since we need
>> to only manage clocks with valid power domain associations done via
>> DT, instead of what pm_clk_add_notifier() does, which is manage clocks
>> for all on SoC/off SoC devices associating all of them to a dummy
>> power domain instead"
>>
>
> Yes that's good, thanks. But I still wonder why the code isn't
> generic so that we don't have lots of drivers duplicating the
> same logic. I guess we can consolidate another day.
Yes, the code is quite generic and probably needs to be some
place so it can be resued across drivers. For now I don;t
see anyone else needing it, maybe sh mobile might plan to use
something like it at a later time which is when we should probably
consolidate.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM
@ 2015-07-30 1:39 ` Rajendra Nayak
0 siblings, 0 replies; 68+ messages in thread
From: Rajendra Nayak @ 2015-07-30 1:39 UTC (permalink / raw)
To: linux-arm-kernel
> On 07/29, Rajendra Nayak wrote:
>>
>> On 07/29/2015 06:34 AM, Stephen Boyd wrote:
>> >
>> >Sorry, I read the thread and I tried to understand what was going on
>> but
>> >I'm still lost. Can you clarify further in the commit text somehow?
>>
>> So I can add this in the commit text, if it seems fine
>>
>> "The use of pm_clk_add_notifier() isn't appropriate here since we need
>> to only manage clocks with valid power domain associations done via
>> DT, instead of what pm_clk_add_notifier() does, which is manage clocks
>> for all on SoC/off SoC devices associating all of them to a dummy
>> power domain instead"
>>
>
> Yes that's good, thanks. But I still wonder why the code isn't
> generic so that we don't have lots of drivers duplicating the
> same logic. I guess we can consolidate another day.
Yes, the code is quite generic and probably needs to be some
place so it can be resued across drivers. For now I don;t
see anyone else needing it, maybe sh mobile might plan to use
something like it at a later time which is when we should probably
consolidate.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 68+ messages in thread
end of thread, other threads:[~2015-07-30 1:39 UTC | newest]
Thread overview: 68+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-22 7:10 [PATCH v6 00/13] qcom: Add support for GDSCs Rajendra Nayak
2015-07-22 7:10 ` Rajendra Nayak
2015-07-22 7:10 ` [PATCH v6 01/13] clk: " Rajendra Nayak
2015-07-22 7:10 ` Rajendra Nayak
2015-07-23 0:25 ` Stephen Boyd
2015-07-23 0:25 ` Stephen Boyd
2015-07-23 8:37 ` Rajendra Nayak
2015-07-23 8:37 ` Rajendra Nayak
2015-07-23 9:09 ` Stanimir Varbanov
2015-07-23 9:09 ` Stanimir Varbanov
2015-07-23 18:04 ` Stephen Boyd
2015-07-23 18:04 ` Stephen Boyd
2015-07-22 7:10 ` [PATCH v6 02/13] clk: qcom: gdsc: Prepare common clk probe to register gdscs Rajendra Nayak
2015-07-22 7:10 ` Rajendra Nayak
2015-07-23 0:27 ` Stephen Boyd
2015-07-23 0:27 ` Stephen Boyd
2015-07-22 7:10 ` [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks Rajendra Nayak
2015-07-22 7:10 ` Rajendra Nayak
2015-07-23 1:01 ` Stephen Boyd
2015-07-23 1:01 ` Stephen Boyd
2015-07-23 8:34 ` Rajendra Nayak
2015-07-23 8:34 ` Rajendra Nayak
2015-07-23 9:22 ` Stanimir Varbanov
2015-07-23 9:22 ` Stanimir Varbanov
2015-07-23 10:28 ` Rajendra Nayak
2015-07-23 10:28 ` Rajendra Nayak
2015-07-22 7:11 ` [PATCH v6 04/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-23 1:03 ` Stephen Boyd
2015-07-23 1:03 ` Stephen Boyd
2015-07-23 8:35 ` Rajendra Nayak
2015-07-23 8:35 ` Rajendra Nayak
2015-07-29 1:04 ` Stephen Boyd
2015-07-29 1:04 ` Stephen Boyd
2015-07-29 4:37 ` Rajendra Nayak
2015-07-29 4:37 ` Rajendra Nayak
2015-07-30 0:13 ` Stephen Boyd
2015-07-30 0:13 ` Stephen Boyd
2015-07-30 1:39 ` Rajendra Nayak
2015-07-30 1:39 ` Rajendra Nayak
2015-07-22 7:11 ` [PATCH v6 05/13] clk: qcom: gdsc: Enable an RCG before turing on the gdsc Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-22 7:11 ` [PATCH v6 06/13] clk: qcom: gdsc: Add support for Memory RET/OFF Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-22 7:11 ` [PATCH v6 07/13] clk: qcom: gdsc: Add support for ON only state Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-23 1:11 ` Stephen Boyd
2015-07-23 1:11 ` Stephen Boyd
2015-07-22 7:11 ` [PATCH v6 08/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-23 1:07 ` Stephen Boyd
2015-07-23 1:07 ` Stephen Boyd
2015-07-23 8:36 ` Rajendra Nayak
2015-07-23 8:36 ` Rajendra Nayak
2015-07-22 7:11 ` [PATCH v6 09/13] clk: qcom: gdsc: Add GDSCs in msm8974 GCC Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-23 1:08 ` Stephen Boyd
2015-07-23 1:08 ` Stephen Boyd
2015-07-22 7:11 ` [PATCH v6 10/13] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-23 1:09 ` Stephen Boyd
2015-07-23 1:09 ` Stephen Boyd
2015-07-22 7:11 ` [PATCH v6 11/13] clk: qcom: gdsc: Add GDSCs in apq8084 GCC Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-22 7:11 ` [PATCH v6 12/13] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
2015-07-22 7:11 ` [PATCH v6 13/13] arm: dts: qcom: Add #power-domain-cells property Rajendra Nayak
2015-07-22 7:11 ` Rajendra Nayak
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