* [PATCH] cxl/pci: Fix irq oneshot expectations
@ 2023-01-31 0:08 Dan Williams
2023-01-31 15:21 ` Dave Jiang
0 siblings, 1 reply; 2+ messages in thread
From: Dan Williams @ 2023-01-31 0:08 UTC (permalink / raw)
To: linux-cxl; +Cc: kernel test robot, Julia Lawall, Davidlohr Bueso, Ira Weiny
The IRQ core expects that users of the default hardirq handler specify
IRQF_ONESHOT to keep interrupts disabled until the threaded handler
runs. That meets the CXL driver's expectations since it is an edge
triggered MSI and this flag would have been passed by default using
pci_request_irq() instead of devm_request_threaded_irq().
Fixes: a49aa8141b65 ("cxl/mem: Wire up event interrupts")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index ad2ebe7bfaeb..4cf9a2191602 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -509,7 +509,8 @@ static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting)
return irq;
return devm_request_threaded_irq(dev, irq, NULL, cxl_event_thread,
- IRQF_SHARED, NULL, dev_id);
+ IRQF_SHARED | IRQF_ONESHOT, NULL,
+ dev_id);
}
static int cxl_event_get_int_policy(struct cxl_dev_state *cxlds,
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] cxl/pci: Fix irq oneshot expectations
2023-01-31 0:08 [PATCH] cxl/pci: Fix irq oneshot expectations Dan Williams
@ 2023-01-31 15:21 ` Dave Jiang
0 siblings, 0 replies; 2+ messages in thread
From: Dave Jiang @ 2023-01-31 15:21 UTC (permalink / raw)
To: Dan Williams, linux-cxl
Cc: kernel test robot, Julia Lawall, Davidlohr Bueso, Ira Weiny
On 1/30/23 5:08 PM, Dan Williams wrote:
> The IRQ core expects that users of the default hardirq handler specify
> IRQF_ONESHOT to keep interrupts disabled until the threaded handler
> runs. That meets the CXL driver's expectations since it is an edge
> triggered MSI and this flag would have been passed by default using
> pci_request_irq() instead of devm_request_threaded_irq().
>
> Fixes: a49aa8141b65 ("cxl/mem: Wire up event interrupts")
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Julia Lawall <julia.lawall@lip6.fr>
> Cc: Davidlohr Bueso <dave@stgolabs.net>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/pci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index ad2ebe7bfaeb..4cf9a2191602 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -509,7 +509,8 @@ static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting)
> return irq;
>
> return devm_request_threaded_irq(dev, irq, NULL, cxl_event_thread,
> - IRQF_SHARED, NULL, dev_id);
> + IRQF_SHARED | IRQF_ONESHOT, NULL,
> + dev_id);
> }
>
> static int cxl_event_get_int_policy(struct cxl_dev_state *cxlds,
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-01-31 15:21 ` Dave Jiang
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