[PATCH v3 0/4] target/arm: Add support for FEAT_DIT, Data Independent Timing

[PATCH v3 0/4] target/arm: Add support for FEAT_DIT, Data Independent Timing

[Rebecca Cran]

Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4.

Changes from v2 to v3:

o Fixed PSTATE_SS patch:
  - Reverted the singlestep removal.
  - Fixed saving cpsr into spsr.

o Added DIT to the max 32-bit CPU.

Rebecca Cran (4):
  target/arm: Remove PSTATE_SS from cpsr and move it into env->pstate.
  target/arm: Add support for FEAT_DIT, Data Independent Timing
  target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64
    CPU
  target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU

 target/arm/cpu.c           |  4 ++++
 target/arm/cpu.h           | 12 ++++++++++
 target/arm/cpu64.c         |  5 ++++
 target/arm/helper-a64.c    |  2 +-
 target/arm/helper.c        | 24 +++++++++++++++++++-
 target/arm/internals.h     |  6 +++++
 target/arm/op_helper.c     |  9 +-------
 target/arm/translate-a64.c | 12 ++++++++++
 8 files changed, 64 insertions(+), 10 deletions(-)

-- 
2.26.2

[PATCH v3 1/4] target/arm: Remove PSTATE_SS from cpsr and move it into env->pstate.

[Rebecca Cran]

cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/helper-a64.c | 2 +-
 target/arm/helper.c     | 2 +-
 target/arm/op_helper.c  | 9 +--------
 3 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index c426c23d2c4e..a6b162049806 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -1001,7 +1001,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
         cpsr_write(env, spsr, mask, CPSRWriteRaw);
         if (!arm_singlestep_active(env)) {
-            env->uncached_cpsr &= ~PSTATE_SS;
+            env->pstate &= ~PSTATE_SS;
         }
         aarch64_sync_64_to_32(env);
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2ead3fcbdbd..7b7e72ba878c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9402,7 +9402,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
      * For exceptions taken to AArch32 we must clear the SS bit in both
      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
      */
-    env->uncached_cpsr &= ~PSTATE_SS;
+    env->pstate &= ~PSTATE_SS;
     env->spsr = cpsr_read(env);
     /* Clear IT bits.  */
     env->condexec_bits = 0;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 5e0f123043b5..65cb37d088f8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
 
 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 {
-    /*
-     * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
-     * This is convenient for populating SPSR_ELx, but must be
-     * hidden from aarch32 mode, where it is not visible.
-     *
-     * TODO: ARMv8.4-DIT -- need to move SS somewhere else.
-     */
-    return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
+    return cpsr_read(env) & ~CPSR_EXEC;
 }
 
 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
-- 
2.26.2

[PATCH v3 2/4] target/arm: Add support for FEAT_DIT, Data Independent Timing

[Rebecca Cran]

Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h           | 12 +++++++++++
 target/arm/helper.c        | 22 ++++++++++++++++++++
 target/arm/internals.h     |  6 ++++++
 target/arm/translate-a64.c | 12 +++++++++++
 4 files changed, 52 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df0d6778330f..56b1053dfdec 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1242,6 +1242,7 @@ void pmu_init(ARMCPU *cpu);
 #define CPSR_IT_2_7 (0xfc00U)
 #define CPSR_GE (0xfU << 16)
 #define CPSR_IL (1U << 20)
+#define CPSR_DIT (1U << 21)
 #define CPSR_PAN (1U << 22)
 #define CPSR_J (1U << 24)
 #define CPSR_IT_0_1 (3U << 25)
@@ -1309,6 +1310,7 @@ void pmu_init(ARMCPU *cpu);
 #define PSTATE_SS (1U << 21)
 #define PSTATE_PAN (1U << 22)
 #define PSTATE_UAO (1U << 23)
+#define PSTATE_DIT (1U << 24)
 #define PSTATE_TCO (1U << 25)
 #define PSTATE_V (1U << 28)
 #define PSTATE_C (1U << 29)
@@ -3875,6 +3877,11 @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
 }
 
+static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
@@ -4119,6 +4126,11 @@ static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
 }
 
+static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
+}
+
 /*
  * Feature tests for "does this exist in either 32-bit or 64-bit?"
  */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7b7e72ba878c..435208121e9f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4419,6 +4419,24 @@ static const ARMCPRegInfo uao_reginfo = {
     .readfn = aa64_uao_read, .writefn = aa64_uao_write
 };
 
+static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return env->pstate & PSTATE_DIT;
+}
+
+static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
+{
+    env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT);
+}
+
+static const ARMCPRegInfo dit_reginfo = {
+    .name = "DIT", .state = ARM_CP_STATE_AA64,
+    .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5,
+    .type = ARM_CP_NO_RAW, .access = PL0_RW,
+    .readfn = aa64_dit_read, .writefn = aa64_dit_write
+};
+
 static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
                                               const ARMCPRegInfo *ri,
                                               bool isread)
@@ -8203,6 +8221,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &uao_reginfo);
     }
 
+    if (cpu_isar_feature(aa64_dit, cpu)) {
+        define_one_arm_cp_reg(cpu, &dit_reginfo);
+    }
+
     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
         define_arm_cp_regs(cpu, vhe_reginfo);
     }
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 853fa88fd616..3d11e42d8e1b 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1222,6 +1222,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
     if (isar_feature_aa32_pan(id)) {
         valid |= CPSR_PAN;
     }
+    if (isar_feature_aa32_dit(id)) {
+        valid |= CPSR_DIT;
+    }
 
     return valid;
 }
@@ -1240,6 +1243,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
     if (isar_feature_aa64_uao(id)) {
         valid |= PSTATE_UAO;
     }
+    if (isar_feature_aa64_dit(id)) {
+        valid |= PSTATE_DIT;
+    }
     if (isar_feature_aa64_mte(id)) {
         valid |= PSTATE_TCO;
     }
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ffc060e5d70c..1c4b8d02f3b8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
         tcg_temp_free_i32(t1);
         break;
 
+    case 0x1a: /* DIT */
+        if (!dc_isar_feature(aa64_dit, s)) {
+            goto do_unallocated;
+        }
+        if (crm & 1) {
+            set_pstate_bits(PSTATE_DIT);
+        } else {
+            clear_pstate_bits(PSTATE_DIT);
+        }
+        /* There's no need to rebuild hflags because DIT is a nop */
+        break;
+
     case 0x1e: /* DAIFSet */
         t1 = tcg_const_i32(crm);
         gen_helper_msr_i_daifset(cpu_env, t1);
-- 
2.26.2

[PATCH v3 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU

[Rebecca Cran]

Enable FEAT_DIT for the "max" AARCH64 CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu64.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c592..9a5cfd4fc632 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -666,6 +666,7 @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
         t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
         t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
+        t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
         cpu->isar.id_aa64pfr0 = t;
 
         t = cpu->isar.id_aa64pfr1;
@@ -715,6 +716,10 @@ static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
         cpu->isar.id_isar6 = u;
 
+        u = cpu->isar.id_pfr0;
+        u = FIELD_DP32(u, ID_PFR0, DIT, 1);
+        cpu->isar.id_pfr0 = u;
+
         u = cpu->isar.id_mmfr3;
         u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
         cpu->isar.id_mmfr3 = u;
-- 
2.26.2

[PATCH v3 4/4] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU

[Rebecca Cran]

Enable FEAT_DIT for the "max" 32-bit CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 40142ac141e5..c98f44624423 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2197,6 +2197,10 @@ static void arm_max_initfn(Object *obj)
         t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
         t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
         cpu->isar.id_mmfr4 = t;
+
+        t = cpu->isar.id_pfr0;
+        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+        cpu->isar.id_pfr0 = t;
     }
 #endif
 }
-- 
2.26.2

Re: [PATCH v3 1/4] target/arm: Remove PSTATE_SS from cpsr and move it into env->pstate.

[Richard Henderson]

On 1/27/21 6:45 PM, Rebecca Cran wrote:
> cpsr has been treated as being the same as spsr, but it isn't.
> Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> ---
>  target/arm/helper-a64.c | 2 +-
>  target/arm/helper.c     | 2 +-
>  target/arm/op_helper.c  | 9 +--------
>  3 files changed, 3 insertions(+), 10 deletions(-)

Missing a change to cpu_get_tb_cpu_state to remove pstate_for_ss and simply use
env->pstate.


r~

Re: [PATCH v3 2/4] target/arm: Add support for FEAT_DIT, Data Independent Timing

[Richard Henderson]

On 1/27/21 6:45 PM, Rebecca Cran wrote:
> Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
> feature for ARMv8.4. Since virtual machine execution is largely
> nondeterministic and TCG is outside of the security domain, it's
> implemented as a NOP.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


This misses the convert from AA32 CPSR to AA64 SPSR on exception entry (and
vice-versa on return).

In particular: CPSR.DIT (bit 21) -> SPSR_EL1.DIT (bit 24), and merging
PSTATE.SS into SPSR_EL1.SS (bit 21).


r~

> ---
>  target/arm/cpu.h           | 12 +++++++++++
>  target/arm/helper.c        | 22 ++++++++++++++++++++
>  target/arm/internals.h     |  6 ++++++
>  target/arm/translate-a64.c | 12 +++++++++++
>  4 files changed, 52 insertions(+)
> 
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index df0d6778330f..56b1053dfdec 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1242,6 +1242,7 @@ void pmu_init(ARMCPU *cpu);
>  #define CPSR_IT_2_7 (0xfc00U)
>  #define CPSR_GE (0xfU << 16)
>  #define CPSR_IL (1U << 20)
> +#define CPSR_DIT (1U << 21)
>  #define CPSR_PAN (1U << 22)
>  #define CPSR_J (1U << 24)
>  #define CPSR_IT_0_1 (3U << 25)
> @@ -1309,6 +1310,7 @@ void pmu_init(ARMCPU *cpu);
>  #define PSTATE_SS (1U << 21)
>  #define PSTATE_PAN (1U << 22)
>  #define PSTATE_UAO (1U << 23)
> +#define PSTATE_DIT (1U << 24)
>  #define PSTATE_TCO (1U << 25)
>  #define PSTATE_V (1U << 28)
>  #define PSTATE_C (1U << 29)
> @@ -3875,6 +3877,11 @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
>      return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
>  }
>  
> +static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
> +{
> +    return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
> +}
> +
>  /*
>   * 64-bit feature tests via id registers.
>   */
> @@ -4119,6 +4126,11 @@ static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
>      return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
>  }
>  
> +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
> +{
> +    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
> +}
> +
>  /*
>   * Feature tests for "does this exist in either 32-bit or 64-bit?"
>   */
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7b7e72ba878c..435208121e9f 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4419,6 +4419,24 @@ static const ARMCPRegInfo uao_reginfo = {
>      .readfn = aa64_uao_read, .writefn = aa64_uao_write
>  };
>  
> +static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> +    return env->pstate & PSTATE_DIT;
> +}
> +
> +static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri,
> +                           uint64_t value)
> +{
> +    env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT);
> +}
> +
> +static const ARMCPRegInfo dit_reginfo = {
> +    .name = "DIT", .state = ARM_CP_STATE_AA64,
> +    .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5,
> +    .type = ARM_CP_NO_RAW, .access = PL0_RW,
> +    .readfn = aa64_dit_read, .writefn = aa64_dit_write
> +};
> +
>  static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
>                                                const ARMCPRegInfo *ri,
>                                                bool isread)
> @@ -8203,6 +8221,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          define_one_arm_cp_reg(cpu, &uao_reginfo);
>      }
>  
> +    if (cpu_isar_feature(aa64_dit, cpu)) {
> +        define_one_arm_cp_reg(cpu, &dit_reginfo);
> +    }
> +
>      if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
>          define_arm_cp_regs(cpu, vhe_reginfo);
>      }
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 853fa88fd616..3d11e42d8e1b 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1222,6 +1222,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
>      if (isar_feature_aa32_pan(id)) {
>          valid |= CPSR_PAN;
>      }
> +    if (isar_feature_aa32_dit(id)) {
> +        valid |= CPSR_DIT;
> +    }
>  
>      return valid;
>  }
> @@ -1240,6 +1243,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
>      if (isar_feature_aa64_uao(id)) {
>          valid |= PSTATE_UAO;
>      }
> +    if (isar_feature_aa64_dit(id)) {
> +        valid |= PSTATE_DIT;
> +    }
>      if (isar_feature_aa64_mte(id)) {
>          valid |= PSTATE_TCO;
>      }
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index ffc060e5d70c..1c4b8d02f3b8 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
>          tcg_temp_free_i32(t1);
>          break;
>  
> +    case 0x1a: /* DIT */
> +        if (!dc_isar_feature(aa64_dit, s)) {
> +            goto do_unallocated;
> +        }
> +        if (crm & 1) {
> +            set_pstate_bits(PSTATE_DIT);
> +        } else {
> +            clear_pstate_bits(PSTATE_DIT);
> +        }
> +        /* There's no need to rebuild hflags because DIT is a nop */
> +        break;
> +
>      case 0x1e: /* DAIFSet */
>          t1 = tcg_const_i32(crm);
>          gen_helper_msr_i_daifset(cpu_env, t1);
> 

Re: [PATCH v3 4/4] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU

[Richard Henderson]

On 1/27/21 6:45 PM, Rebecca Cran wrote:
> Enable FEAT_DIT for the "max" 32-bit CPU.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> ---
>  target/arm/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 2/4] target/arm: Add support for FEAT_DIT, Data Independent Timing

[Rebecca Cran]

On 1/27/21 10:06 PM, Richard Henderson wrote:
> On 1/27/21 6:45 PM, Rebecca Cran wrote:
>> Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
>> feature for ARMv8.4. Since virtual machine execution is largely
>> nondeterministic and TCG is outside of the security domain, it's
>> implemented as a NOP.
>>
>> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> This misses the convert from AA32 CPSR to AA64 SPSR on exception entry (and
> vice-versa on return).
> 
> In particular: CPSR.DIT (bit 21) -> SPSR_EL1.DIT (bit 24), and merging
> PSTATE.SS into SPSR_EL1.SS (bit 21).

Thanks. I _think_ I'm understanding it better now. Would the following 
work? I don't see where I need to map PSTATE.SS into SPSR_EL1.SS though, 
because isn't that handled automatically since PSTATE maps onto SPSR?


diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index a6b162049806..c1ff24d42f32 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -1003,6 +1003,11 @@ void HELPER(exception_return)(CPUARMState *env, 
uint64_t new_pc)
          if (!arm_singlestep_active(env)) {
              env->pstate &= ~PSTATE_SS;
          }
+
+        if (spsr & PSTATE_DIT) {
+            env->uncached_cpsr |= CPSR_DIT;
+        }
+
          aarch64_sync_64_to_32(env);

          if (spsr & CPSR_T) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 54ac1f476940..1ecfd63d8f70 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9426,6 +9426,12 @@ static void take_aarch32_exception(CPUARMState 
*env, int new_mode,
       */
      env->pstate &= ~PSTATE_SS;
      env->spsr = cpsr_read(env);
+
+    if (env->uncached_cpsr & CPSR_DIT) {
+        env->spsr |= PSTATE_DIT;
+        env->spsr &= ~PSTATE_SS;
+    }
+
      /* Clear IT bits.  */
      env->condexec_bits = 0;
      /* Switch to the new mode, and to the correct instruction set.  */
@@ -9905,6 +9911,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState 
*cs)
          old_mode = cpsr_read(env);
          env->elr_el[new_el] = env->regs[15];

+        if (old_mode & CPSR_DIT) {
+            old_mode |= PSTATE_DIT;
+            old_mode &= ~PSTATE_SS;
+        }
+
          aarch64_sync_32_to_64(env);

          env->condexec_bits = 0;

Re: [PATCH v3 2/4] target/arm: Add support for FEAT_DIT, Data Independent Timing

[Richard Henderson]

On 2/2/21 12:21 PM, Rebecca Cran wrote:
> On 1/27/21 10:06 PM, Richard Henderson wrote:
>> In particular: CPSR.DIT (bit 21) -> SPSR_EL1.DIT (bit 24), and merging
>> PSTATE.SS into SPSR_EL1.SS (bit 21).
> 
> Thanks. I _think_ I'm understanding it better now. Would the following work? I
> don't see where I need to map PSTATE.SS into SPSR_EL1.SS though, because isn't
> that handled automatically since PSTATE maps onto SPSR?
> 
> 
> diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
> index a6b162049806..c1ff24d42f32 100644
> --- a/target/arm/helper-a64.c
> +++ b/target/arm/helper-a64.c
> @@ -1003,6 +1003,11 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
> new_pc)
>          if (!arm_singlestep_active(env)) {
>              env->pstate &= ~PSTATE_SS;
>          }
> +
> +        if (spsr & PSTATE_DIT) {
> +            env->uncached_cpsr |= CPSR_DIT;
> +        }

This is missing the restore of PSTATE_SS for when singlestep *is* active.

> @@ -9426,6 +9426,12 @@ static void take_aarch32_exception(CPUARMState *env, int
> new_mode,
>       */
>      env->pstate &= ~PSTATE_SS;
>      env->spsr = cpsr_read(env);
> +
> +    if (env->uncached_cpsr & CPSR_DIT) {
> +        env->spsr |= PSTATE_DIT;
> +        env->spsr &= ~PSTATE_SS;
> +    }

This one is incorrect because we're not storing to SPSR_ELx format, but SPSR
(the aa32 version), which has DIT at bit 21.

> @@ -9905,6 +9911,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
>          old_mode = cpsr_read(env);
>          env->elr_el[new_el] = env->regs[15];
> 
> +        if (old_mode & CPSR_DIT) {
> +            old_mode |= PSTATE_DIT;
> +            old_mode &= ~PSTATE_SS;

This line would be clearer using CPSR_DIT.  I don't see PSTATE_SS being added
to old_mode.  Is that somewhere else, or simply missing context here?

I think it would be clearer to add some new helpers.  Naming is always
difficult, but how about:

static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
{
    uint32_t ret = cpsr_read(env);

    /* Move DIT to the correct location for SPSR_ELx */
    if (ret & CPSR_DIT) {
        ret &= ~CPSR_DIT;
        ret |= PSTATE_DIT;
    }
    /* Merge PSTATE.SS into SPSR_ELx */
    ret |= env->pstate & PSTATE_SS;

    return ret;
}

static void cpsr_write_from_spsr_elx(CPUARMState *env,
                                     uint32_t val)
{
    uint32_t mask;

    /* Save SPSR_ELx.SS into PSTATE. */
    env->pstate = (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS);
    val &= ~PSTATE_SS;

    /* Move DIT to the correct location for CPSR */
    if (val & PSTATE_DIT) {
        val &= ~PSTATE_DIT;
        val |= CPSR_DIT;
    }

    mask = aarch32_cpsr_valid_mask(env->features, \
        &env_archcpu(env)->isar);
    cpsr_write(env, val, mask, CPSRWriteRaw);
}


r~