[Buildroot] RISC-V support

[Buildroot] RISC-V support

[Anton Kuzmin]

Hello All,

Is anybody already working on adding of the RISC-V [1] support
to buildroot?  If yes, is there any place to discuss/share the progress?
If not, are there any reasons not to do it?

As a starting point, I have made minimal additions resulting in
a successful build of the buildroot toolchain and sdk.
At the moment 64-bit only, gcc-7.3.0, glibc-2.27-57 -- from upstream.


Best regards,

Anton Kuzmin


[1] https://riscv.org/

[Buildroot] RISC-V support

[Arnout Vandecappelle]

On 13-07-18 10:34, Anton Kuzmin wrote:
> Hello All,
> 
> Is anybody already working on adding of the RISC-V [1] support
> to buildroot?  If yes, is there any place to discuss/share the progress?
> If not, are there any reasons not to do it?

 There is definitely no reason not to add support for it RISC-V.


> As a starting point, I have made minimal additions resulting in
> a successful build of the buildroot toolchain and sdk.

 Excellent!

 How about a kernel?

> At the moment 64-bit only, gcc-7.3.0, glibc-2.27-57 -- from upstream.

 64-bit only seems a small constraint, IIUC the 32 and 64 bit variants are
nearly identical, no?

 Constraints on minimal versions of the toolchain components are expected. We
even have BR2_ARCH_NEEDS_GCC_AT_LEAST_7 to handle that. It's used a lot for ARM
subarchitectures.


 The patch series to add RISC-V support could look something like this:

riscv: add RISC-V architecture
 -> adds it to arch/Config.in and arch/Config.in.riscv
    For now, selects BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT.
    Selects the proper atomic etc. toolchain options

toolchain-buildroot: support riscv
 -> everything needed to be able to build an internal toolchain with glibc

uclibc: support riscv

linux: support riscv

configs/qemu_riscv_some_defconfig: new defconfig

support/config-fragments/autobuild: add RISC-V fragment


 Even if you don't do all of this, it is useful if you post some of these
patches, so someone else can take it over.

 Regards,
 Arnout

-- 
Arnout Vandecappelle                          arnout at mind be
Senior Embedded Software Architect            +32-16-286500
Essensium/Mind                                http://www.mind.be
G.Geenslaan 9, 3001 Leuven, Belgium           BE 872 984 063 RPR Leuven
LinkedIn profile: http://www.linkedin.com/in/arnoutvandecappelle
GPG fingerprint:  7493 020B C7E3 8618 8DEC 222C 82EB F404 F9AC 0DDF

[Buildroot] RISC-V support

[Romain Naour]

Hi Anton, Arnout,

Le 13/07/2018 ? 11:10, Arnout Vandecappelle a ?crit?:
> 
> 
> On 13-07-18 10:34, Anton Kuzmin wrote:
>> Hello All,
>>
>> Is anybody already working on adding of the RISC-V [1] support
>> to buildroot?  If yes, is there any place to discuss/share the progress?
>> If not, are there any reasons not to do it?
> 
>  There is definitely no reason not to add support for it RISC-V.

Indeed, patches are welcome :)

> 
> 
>> As a starting point, I have made minimal additions resulting in
>> a successful build of the buildroot toolchain and sdk.
> 
>  Excellent!
> 
>  How about a kernel?
> 
>> At the moment 64-bit only, gcc-7.3.0, glibc-2.27-57 -- from upstream.
> 
>  64-bit only seems a small constraint, IIUC the 32 and 64 bit variants are
> nearly identical, no?
> 
>  Constraints on minimal versions of the toolchain components are expected. We
> even have BR2_ARCH_NEEDS_GCC_AT_LEAST_7 to handle that. It's used a lot for ARM
> subarchitectures.
> 
> 
>  The patch series to add RISC-V support could look something like this:
> 
> riscv: add RISC-V architecture
>  -> adds it to arch/Config.in and arch/Config.in.riscv
>     For now, selects BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT.
>     Selects the proper atomic etc. toolchain options
> 
> toolchain-buildroot: support riscv
>  -> everything needed to be able to build an internal toolchain with glibc
> 
> uclibc: support riscv

musl (if supported)

> 
> linux: support riscv
> 
> configs/qemu_riscv_some_defconfig: new defconfig
> 
> support/config-fragments/autobuild: add RISC-V fragment
> 
> 
>  Even if you don't do all of this, it is useful if you post some of these
> patches, so someone else can take it over.

After this work, we will need some help to fix all issues discovered by this new
architecture/toolchain.

It would be great to have someone able to test on a real hardware, at least we
can test on Qemu (best effort).

Best regards,
Romain

> 
>  Regards,
>  Arnout
> 

[Buildroot] RISC-V support

[Jean-François Têtu]

Hello all,

On Friday, July 13, 2018 10:51:01 AM, Romain Naour wrote:
> Hi Anton, Arnout,
> 
> Le 13/07/2018 ? 11:10, Arnout Vandecappelle a ?crit?:
>> 
>> 
>> On 13-07-18 10:34, Anton Kuzmin wrote:
>>> Hello All,
>>>
>>> Is anybody already working on adding of the RISC-V [1] support
>>> to buildroot?  If yes, is there any place to discuss/share the progress?
>>> If not, are there any reasons not to do it?
>> 
>>  There is definitely no reason not to add support for it RISC-V.
> 
> Indeed, patches are welcome :)
>

Great! Just this week I planned on starting a simple build targeting the
'virt' machine [1]. I noted the upstream versions [2] of the needed tools,
like binutils, gcc, and glibc. We could also help out Michael Clark in 
adding RISC-V support in upstream musl [3].

>> 
>> 
>>> As a starting point, I have made minimal additions resulting in
>>> a successful build of the buildroot toolchain and sdk.
>> 
>>  Excellent!
>> 
>>  How about a kernel?
>> 
>>> At the moment 64-bit only, gcc-7.3.0, glibc-2.27-57 -- from upstream.
>> 
>>  64-bit only seems a small constraint, IIUC the 32 and 64 bit variants are
>> nearly identical, no?
>> 
>>  Constraints on minimal versions of the toolchain components are expected. We
>> even have BR2_ARCH_NEEDS_GCC_AT_LEAST_7 to handle that. It's used a lot for ARM
>> subarchitectures.
>> 
>> 
>>  The patch series to add RISC-V support could look something like this:
>> 
>> riscv: add RISC-V architecture
>>  -> adds it to arch/Config.in and arch/Config.in.riscv
>>     For now, selects BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT.
>>     Selects the proper atomic etc. toolchain options
>> 
>> toolchain-buildroot: support riscv
>>  -> everything needed to be able to build an internal toolchain with glibc
>> 
>> uclibc: support riscv
> 
> musl (if supported)
> 
>> 
>> linux: support riscv
>> 
>> configs/qemu_riscv_some_defconfig: new defconfig
>> 
>> support/config-fragments/autobuild: add RISC-V fragment
>> 
>> 
>>  Even if you don't do all of this, it is useful if you post some of these
>> patches, so someone else can take it over.
> 
> After this work, we will need some help to fix all issues discovered by this new
> architecture/toolchain.
> 
> It would be great to have someone able to test on a real hardware, at least we
> can test on Qemu (best effort).
> 
> Best regards,
> Romain
>

If you want, I would like to help you out with those patches :). Having
a basic toolchain is already an important step. However, I do not have 
access to RISC-V hardware.

>> 
>>  Regards,
>>  Arnout
>> 
> 
> _______________________________________________
> buildroot mailing list
> buildroot at busybox.net
> http://lists.busybox.net/mailman/listinfo/buildroot

[1] https://github.com/riscv/riscv-qemu/wiki#machines
[2] https://riscv.org/software-status/
[3] https://github.com/rv8-io/musl-riscv-toolchain

Regards,

--
Jean-Fran?ois T?tu

[Buildroot] RISC-V support

[Anton Kuzmin]

On 13.07.2018 11:10, Arnout Vandecappelle wrote:
> 
> 
> On 13-07-18 10:34, Anton Kuzmin wrote:
>> Hello All,
>>
>> Is anybody already working on adding of the RISC-V [1] support
>> to buildroot?  If yes, is there any place to discuss/share the progress?
>> If not, are there any reasons not to do it?
> 
>  There is definitely no reason not to add support for it RISC-V.
> 
> 
>> As a starting point, I have made minimal additions resulting in
>> a successful build of the buildroot toolchain and sdk.
> 
>  Excellent!

Thank you and everybody else for a positive and encouraging reaction.

>  How about a kernel?

Not that far yet, perhaps is some weeks.

>> At the moment 64-bit only, gcc-7.3.0, glibc-2.27-57 -- from upstream.
> 
>  64-bit only seems a small constraint, IIUC the 32 and 64 bit variants are
> nearly identical, no?

AFAIK, 32-bit glibc support is available from risc-v repo on github,
but has not been merged upstream yet.  There seems to be some
differencies at least in atomic operations, may be something else.

Frankly, 32-bit toolchain is what I'm interested most at the moment.

>  Constraints on minimal versions of the toolchain components are expected. We
> even have BR2_ARCH_NEEDS_GCC_AT_LEAST_7 to handle that. It's used a lot for ARM
> subarchitectures.

Yes, that's exactly how I've tried to make it.

>  The patch series to add RISC-V support could look something like this:
> 
> riscv: add RISC-V architecture
>  -> adds it to arch/Config.in and arch/Config.in.riscv
>     For now, selects BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT.
>     Selects the proper atomic etc. toolchain options
> 
> toolchain-buildroot: support riscv
>  -> everything needed to be able to build an internal toolchain with glibc

Both patches are submitted minutes ago to the mailinglist.

> uclibc: support riscv
> 
> linux: support riscv
> 
> configs/qemu_riscv_some_defconfig: new defconfig
> 
> support/config-fragments/autobuild: add RISC-V fragment

These things are still to be done.

>  Even if you don't do all of this, it is useful if you post some of these
> patches, so someone else can take it over.

Thanks again.

>  Regards,
>  Arnout
> 

[Buildroot] RISC-V support

[Anton Kuzmin]

On 13.07.2018 16:51, Romain Naour wrote:
>> uclibc: support riscv
> 
> musl (if supported)

Not yet, AFAIK

> After this work, we will need some help to fix all issues discovered by this new
> architecture/toolchain.

Yes, that's understood and expected.  Also I'm primary a hardware/FPGA
developer now and have very limited s/w expertise and bandwidth.

> It would be great to have someone able to test on a real hardware, at least we
> can test on Qemu (best effort).

Currently I have an access to the Arrow Everest evaluation board [1].
The plan is to configure it with [some] RISC-V CPU core/system-on-chip.

[1] https://www.arrow.com/en/campaigns/everest