From: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> To: Aradhya Bhatia <a-bhatia1@ti.com>, Jyri Sarha <jyri.sarha@iki.fi>, Rob Herring <robh+dt@kernel.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>, Rahul T R <r-ravikumar@ti.com>, DRI Development List <dri-devel@lists.freedesktop.org>, Devicetree List <devicetree@vger.kernel.org>, Linux Kernel List <linux-kernel@vger.kernel.org> Subject: Re: [RFC PATCH v5 5/6] drm/tidss: Add IO CTRL and Power support for OLDI TX in am625 Date: Wed, 12 Oct 2022 15:29:40 +0300 [thread overview] Message-ID: <708ae70e-dc1b-1079-8442-06cbea228e99@ideasonboard.com> (raw) In-Reply-To: <20220928175223.15225-6-a-bhatia1@ti.com> On 28/09/2022 20:52, Aradhya Bhatia wrote: > The ctrl mmr module of the AM625 is different from the AM65X SoC. Thus > the ctrl mmr registers that supported the OLDI TX power have become > different in AM625 SoC. > > Add IO CTRL support and control the OLDI TX power for AM625. > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> > --- > drivers/gpu/drm/tidss/tidss_dispc.c | 55 ++++++++++++++++++------ > drivers/gpu/drm/tidss/tidss_dispc_regs.h | 6 +++ > 2 files changed, 49 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c > index 88008ad39b55..68444e0cd8d7 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -921,21 +921,52 @@ int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, > > static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) > { > - u32 val = power ? 0 : OLDI_PWRDN_TX; > + u32 val; > > if (WARN_ON(!dispc->oldi_io_ctrl)) > return; > > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, > - OLDI_PWRDN_TX, val); > + if (dispc->feat->subrev == DISPC_AM65X) { > + val = power ? 0 : OLDI_PWRDN_TX; > + > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, > + OLDI_PWRDN_TX, val); > + > + } else if (dispc->feat->subrev == DISPC_AM625) { > + if (power) { > + switch (dispc->oldi_mode) { > + case OLDI_SINGLE_LINK_SINGLE_MODE: > + /* Power down OLDI TX 1 */ > + val = OLDI1_PWRDN_TX; > + break; > + > + case OLDI_SINGLE_LINK_CLONE_MODE: > + case OLDI_DUAL_LINK_MODE: > + /* No Power down */ > + val = 0; > + break; > + > + default: > + /* Power down both the OLDI TXes */ > + val = OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; > + break; > + } > + } else { > + /* Power down both the OLDI TXes */ > + val = OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; > + } Ugh, I hate power-down bits. So you "enable" it to disable it =). What's the default value or the register here? Or will this always be called? I.e. if we only use DPI, do we power down the OLDIs somewhere (or does it matter)? > + > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_PD_CTRL, > + OLDI0_PWRDN_TX | OLDI1_PWRDN_TX, val); > + } > } > > static void dispc_set_num_datalines(struct dispc_device *dispc, > @@ -2831,7 +2862,7 @@ int dispc_init(struct tidss_device *tidss) > dispc->vp_data[i].gamma_table = gamma_table; > } > > - if (feat->subrev == DISPC_AM65X) { > + if (feat->subrev == DISPC_AM65X || feat->subrev == DISPC_AM625) { > r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); > if (r) > return r; > diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tidss/tidss_dispc_regs.h > index 13feedfe5d6d..510bee70b3b8 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h > +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h > @@ -238,6 +238,12 @@ enum dispc_common_regs { > #define OLDI_DAT3_IO_CTRL 0x0C > #define OLDI_CLK_IO_CTRL 0x10 > > +/* Only for AM625 OLDI TX */ > +#define OLDI_PD_CTRL 0x100 > +#define OLDI_LB_CTRL 0x104 > + > #define OLDI_PWRDN_TX BIT(8) > +#define OLDI0_PWRDN_TX BIT(0) > +#define OLDI1_PWRDN_TX BIT(1) Maybe these (the new and old ones) should be platform-prefixed. And organized so that the register and its bits are together. Tomi
WARNING: multiple messages have this Message-ID (diff)
From: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> To: Aradhya Bhatia <a-bhatia1@ti.com>, Jyri Sarha <jyri.sarha@iki.fi>, Rob Herring <robh+dt@kernel.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Nishanth Menon <nm@ti.com>, Devicetree List <devicetree@vger.kernel.org>, Vignesh Raghavendra <vigneshr@ti.com>, Linux Kernel List <linux-kernel@vger.kernel.org>, DRI Development List <dri-devel@lists.freedesktop.org>, Rahul T R <r-ravikumar@ti.com> Subject: Re: [RFC PATCH v5 5/6] drm/tidss: Add IO CTRL and Power support for OLDI TX in am625 Date: Wed, 12 Oct 2022 15:29:40 +0300 [thread overview] Message-ID: <708ae70e-dc1b-1079-8442-06cbea228e99@ideasonboard.com> (raw) In-Reply-To: <20220928175223.15225-6-a-bhatia1@ti.com> On 28/09/2022 20:52, Aradhya Bhatia wrote: > The ctrl mmr module of the AM625 is different from the AM65X SoC. Thus > the ctrl mmr registers that supported the OLDI TX power have become > different in AM625 SoC. > > Add IO CTRL support and control the OLDI TX power for AM625. > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> > --- > drivers/gpu/drm/tidss/tidss_dispc.c | 55 ++++++++++++++++++------ > drivers/gpu/drm/tidss/tidss_dispc_regs.h | 6 +++ > 2 files changed, 49 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c > index 88008ad39b55..68444e0cd8d7 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -921,21 +921,52 @@ int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, > > static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) > { > - u32 val = power ? 0 : OLDI_PWRDN_TX; > + u32 val; > > if (WARN_ON(!dispc->oldi_io_ctrl)) > return; > > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, > - OLDI_PWRDN_TX, val); > - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, > - OLDI_PWRDN_TX, val); > + if (dispc->feat->subrev == DISPC_AM65X) { > + val = power ? 0 : OLDI_PWRDN_TX; > + > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, > + OLDI_PWRDN_TX, val); > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, > + OLDI_PWRDN_TX, val); > + > + } else if (dispc->feat->subrev == DISPC_AM625) { > + if (power) { > + switch (dispc->oldi_mode) { > + case OLDI_SINGLE_LINK_SINGLE_MODE: > + /* Power down OLDI TX 1 */ > + val = OLDI1_PWRDN_TX; > + break; > + > + case OLDI_SINGLE_LINK_CLONE_MODE: > + case OLDI_DUAL_LINK_MODE: > + /* No Power down */ > + val = 0; > + break; > + > + default: > + /* Power down both the OLDI TXes */ > + val = OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; > + break; > + } > + } else { > + /* Power down both the OLDI TXes */ > + val = OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; > + } Ugh, I hate power-down bits. So you "enable" it to disable it =). What's the default value or the register here? Or will this always be called? I.e. if we only use DPI, do we power down the OLDIs somewhere (or does it matter)? > + > + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_PD_CTRL, > + OLDI0_PWRDN_TX | OLDI1_PWRDN_TX, val); > + } > } > > static void dispc_set_num_datalines(struct dispc_device *dispc, > @@ -2831,7 +2862,7 @@ int dispc_init(struct tidss_device *tidss) > dispc->vp_data[i].gamma_table = gamma_table; > } > > - if (feat->subrev == DISPC_AM65X) { > + if (feat->subrev == DISPC_AM65X || feat->subrev == DISPC_AM625) { > r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); > if (r) > return r; > diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tidss/tidss_dispc_regs.h > index 13feedfe5d6d..510bee70b3b8 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h > +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h > @@ -238,6 +238,12 @@ enum dispc_common_regs { > #define OLDI_DAT3_IO_CTRL 0x0C > #define OLDI_CLK_IO_CTRL 0x10 > > +/* Only for AM625 OLDI TX */ > +#define OLDI_PD_CTRL 0x100 > +#define OLDI_LB_CTRL 0x104 > + > #define OLDI_PWRDN_TX BIT(8) > +#define OLDI0_PWRDN_TX BIT(0) > +#define OLDI1_PWRDN_TX BIT(1) Maybe these (the new and old ones) should be platform-prefixed. And organized so that the register and its bits are together. Tomi
next prev parent reply other threads:[~2022-10-12 12:30 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-28 17:52 [RFC PATCH v5 0/6] Add DSS support for AM625 SoC Aradhya Bhatia 2022-09-28 17:52 ` Aradhya Bhatia 2022-09-28 17:52 ` [RFC PATCH v5 1/6] dt-bindings: display: ti,am65x-dss: Add am625 dss compatible Aradhya Bhatia 2022-09-28 17:52 ` [RFC PATCH v5 1/6] dt-bindings: display: ti, am65x-dss: " Aradhya Bhatia 2022-10-12 11:28 ` [RFC PATCH v5 1/6] dt-bindings: display: ti,am65x-dss: " Tomi Valkeinen 2022-10-12 11:28 ` [RFC PATCH v5 1/6] dt-bindings: display: ti, am65x-dss: " Tomi Valkeinen 2022-09-28 17:52 ` [RFC PATCH v5 2/6] dt-bindings: display: ti: am65x-dss: Add new port for am625-dss Aradhya Bhatia 2022-09-28 17:52 ` Aradhya Bhatia 2022-09-28 18:14 ` Krzysztof Kozlowski 2022-09-28 18:14 ` Krzysztof Kozlowski 2022-09-28 17:52 ` [RFC PATCH v5 3/6] drm/tidss: Add support for AM625 DSS Aradhya Bhatia 2022-09-28 17:52 ` Aradhya Bhatia 2022-10-12 11:40 ` Tomi Valkeinen 2022-10-12 11:40 ` Tomi Valkeinen 2022-10-12 12:09 ` Tomi Valkeinen 2022-10-12 12:09 ` Tomi Valkeinen 2022-09-28 17:52 ` [RFC PATCH v5 4/6] drm/tidss: Add support to configure OLDI mode for am625-dss Aradhya Bhatia 2022-09-28 17:52 ` Aradhya Bhatia 2022-10-12 12:23 ` Tomi Valkeinen 2022-10-12 12:23 ` Tomi Valkeinen 2022-10-18 7:00 ` Aradhya Bhatia 2022-10-18 7:00 ` Aradhya Bhatia 2022-10-24 7:17 ` Tomi Valkeinen 2022-10-24 7:17 ` Tomi Valkeinen 2022-09-28 17:52 ` [RFC PATCH v5 5/6] drm/tidss: Add IO CTRL and Power support for OLDI TX in am625 Aradhya Bhatia 2022-09-28 17:52 ` Aradhya Bhatia 2022-10-12 12:29 ` Tomi Valkeinen [this message] 2022-10-12 12:29 ` Tomi Valkeinen 2022-10-19 17:14 ` Aradhya Bhatia 2022-10-19 17:14 ` Aradhya Bhatia 2022-09-28 17:52 ` [RFC PATCH v5 6/6] drm/tidss: Enable Dual and Duplicate Modes for OLDI Aradhya Bhatia 2022-09-28 17:52 ` Aradhya Bhatia 2022-10-12 12:35 ` Tomi Valkeinen 2022-10-12 12:35 ` Tomi Valkeinen
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=708ae70e-dc1b-1079-8442-06cbea228e99@ideasonboard.com \ --to=tomi.valkeinen@ideasonboard.com \ --cc=a-bhatia1@ti.com \ --cc=airlied@linux.ie \ --cc=daniel@ffwll.ch \ --cc=devicetree@vger.kernel.org \ --cc=dri-devel@lists.freedesktop.org \ --cc=jyri.sarha@iki.fi \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-kernel@vger.kernel.org \ --cc=nm@ti.com \ --cc=r-ravikumar@ti.com \ --cc=robh+dt@kernel.org \ --cc=vigneshr@ti.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.