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From: Dave Hansen <dave.hansen@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v5 1/8] L1TFv4 6
Date: Wed, 23 May 2018 16:15:41 -0700	[thread overview]
Message-ID: <70cc1acf-95a1-6de4-7bc8-46dfd54c686a@linux.intel.com> (raw)
In-Reply-To: <20180523215737.7C50E61169@crypto-ml.lab.linutronix.de>

[-- Attachment #1: Type: text/plain, Size: 2572 bytes --]

On 05/23/2018 02:51 PM, speck for Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
> Subject:  x86, l1tf: Increase 32bit PAE __PHYSICAL_PAGE_MASK
> 
> On 32bit PAE the max PTE mask is currently set to 44 bit because that is
> the limit imposed by 32bit unsigned long PFNs in the VMs.
> 
> The L1TF PROT_NONE protection code uses the PTE masks to determine
> what bits to invert to make sure the higher bits are set for unmapped
> entries to prevent L1TF speculation attacks against EPT inside guests.
> 
> But our inverted mask has to match the host, and the host is likely
> 64bit and may use more than 43 bits of memory. We want to set
> all possible bits to be safe here.
> 
> So increase the mask on 32bit PAE to 52 to match 64bit.
> 
> The real limit is still 44 bits.
> 
> All Linux PTEs are created from unsigned long PFNs, so cannot be
> higher than 44 bits on a 32bit kernel. So these extra PFN
> bits should be never set. The only users of this macro are using
> it to look at PTEs, so it's safe.

I'm scratching my head a bit at this description.  I've written another
summary so I could understand it a bit better.  Could you check if my
understanding is correct.  Feel free to steal any of this for your
description or toss it.

BTW, this reminds me: Let's say we trust guest kernels.  Do we need KVM
code to _prevent_ guests running in 32-bit non-PAE mode?  Wouldn't any
32-bit non-PAE guest effectively have the ability to read the bottom
~4GB of host memory?

If we don't trust guest kernels, then what is the point of this patch? :)

Problem:

This patch is intended to protect against a 32-bit unprivileged guest
application using PROT_NONE on normal guest memory to attack host memory.

Background:

32-bit 'unsigned long' PFNs can only point to 44 bits of memory
(32+PAGE_SHIFT).  We enforce this via __PHYSICAL_PAGE_MASK, but
unfortunately our L1TF workaround bits are also limited by
__PHYSICAL_PAGE_MASK as well.

Example:

Imagine a 32-bit PAE PTE pointing to memory at guest physical address 1GB:

	0x0000000040000067

Then the attacker calls mprotect(PROT_NONE).  We invert the PTE's
physical address bits (and add _PAGE_PROT_NONE), but only those bits set
in __PHYSICAL_PAGE_MASK.  We get:

	0x00000fffbffff100

Which is an address just below 16TB.  This might allow an attacker to
read *host* memory at that address.

The fix:

Increase __PHYSICAL_PAGE_MASK to allow us to set higher address bits in
the inverted PTEs.... and then all the other description you had.


  parent reply	other threads:[~2018-05-23 23:15 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-23 21:51 [MODERATED] [PATCH v5 0/8] L1TFv4 5 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 1/8] L1TFv4 6 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 2/8] L1TFv4 7 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 3/8] L1TFv4 2 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 4/8] L1TFv4 8 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 5/8] L1TFv4 0 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 6/8] L1TFv4 4 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 7/8] L1TFv4 3 Andi Kleen
2018-05-23 21:51 ` [MODERATED] [PATCH v5 8/8] L1TFv4 1 Andi Kleen
     [not found] ` <20180523215658.63CAB61104@crypto-ml.lab.linutronix.de>
2018-05-23 22:22   ` [MODERATED] Re: [PATCH v5 5/8] L1TFv4 0 Borislav Petkov
     [not found] ` <20180523215726.A931B61157@crypto-ml.lab.linutronix.de>
2018-05-23 22:50   ` [MODERATED] Re: [PATCH v5 8/8] L1TFv4 1 Dave Hansen
     [not found] ` <20180523215737.7C50E61169@crypto-ml.lab.linutronix.de>
2018-05-23 23:15   ` Dave Hansen [this message]
2018-05-23 23:52     ` [MODERATED] Re: [PATCH v5 1/8] L1TFv4 6 Andrew Cooper
2018-05-24  9:09     ` Michal Hocko
2018-05-24 15:26     ` Andi Kleen
2018-05-24 17:00       ` Dave Hansen
     [not found] ` <20180523215136.EB16B610ED@crypto-ml.lab.linutronix.de>
2018-05-24  3:34   ` [MODERATED] Re: [PATCH v5 4/8] L1TFv4 8 Josh Poimboeuf
     [not found] ` <20180523215651.BFF82610ED@crypto-ml.lab.linutronix.de>
2018-05-24  4:04   ` [MODERATED] Re: [PATCH v5 6/8] L1TFv4 4 Josh Poimboeuf
2018-05-24 13:35     ` Andi Kleen
2018-05-24 15:45       ` Josh Poimboeuf
2018-05-24 16:53         ` Andi Kleen
2018-05-24 17:53           ` Josh Poimboeuf
2018-05-24 20:32             ` Andi Kleen

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