All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Yunqiang Su" <ysu@wavecomp.com>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	qemu-devel@nongnu.org
Cc: Igor Mammedov <imammedo@redhat.com>,
	Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH 5/7] hw/mips/malta: Introduce the 'malta-phys' machine
Date: Tue, 30 Jun 2020 10:54:22 +0200	[thread overview]
Message-ID: <73404e5a-5c41-5f17-89d9-64cc1f943d1c@amsat.org> (raw)
In-Reply-To: <20200630081322.19146-6-f4bug@amsat.org>

On 6/30/20 10:13 AM, Philippe Mathieu-Daudé wrote:
> Introduce the 'malta-phys' machine, aiming to have the same
> limitations as real hardware. Start by restricting the RAM
> to 1GB, which is the maximum amount of memory the GT-64120A
> north bridge can address.

Oops wrong comment, it ended mixed from previous patch while
rebasing. Corrected:

"Start with 32 MB which is the default on the CoreLV, and
allow up to 256 MB which is the maximum this card can
accept. See MIPS Document Number: MD00051 Revision 01.07"

> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  hw/mips/malta.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 1ca41b44db..013bf9272c 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -1479,11 +1479,32 @@ static void malta_machine_virt_class_init(ObjectClass *oc, void *data)
>      mmc->max_ramsize = 2 * GiB;
>  }
>  
> +static void malta_machine_phys_class_init(ObjectClass *oc, void *data)
> +{
> +    MachineClass *mc = MACHINE_CLASS(oc);
> +    MaltaMachineClass *mmc = MALTA_MACHINE_CLASS(oc);
> +
> +    mc->desc = "MIPS Malta Core LV (physically limited as real hardware)";
> +    mc->block_default_type = IF_PFLASH;
> +    mc->max_cpus = 1;
> +#ifdef TARGET_MIPS64
> +    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kc");
> +#else
> +    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("4Kc");
> +#endif
> +    mc->default_ram_size = 32 * MiB;
> +    mmc->max_ramsize = 256 * MiB; /* 32 MByte PC100 SDRAM DIMMs x 4 slots */
> +};
> +
>  static const TypeInfo malta_machine_types[] = {
>      {
>          .name          = MACHINE_TYPE_NAME("malta-virt"),
>          .parent        = TYPE_MALTA_MACHINE,
>          .class_init    = malta_machine_virt_class_init,
> +    }, {
> +        .name          = MACHINE_TYPE_NAME("malta-phys"),
> +        .parent        = TYPE_MALTA_MACHINE,
> +        .class_init    = malta_machine_phys_class_init,
>      }, {
>          .name          = TYPE_MALTA_MACHINE,
>          .parent        = TYPE_MACHINE,
> 



  reply	other threads:[~2020-06-30  8:55 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-30  8:13 [PATCH 0/7] hw/mips/malta: Rework to allow more than 2GB of RAM on 64-bit Philippe Mathieu-Daudé
2020-06-30  8:13 ` [PATCH 1/7] hw/mips/malta: Trivial code movement Philippe Mathieu-Daudé
2020-06-30  8:13 ` [PATCH 2/7] hw/mips/malta: Register the machine as a TypeInfo Philippe Mathieu-Daudé
2020-06-30  8:13 ` [PATCH 3/7] hw/mips/malta: Rename 'malta' machine as 'malta-virt' Philippe Mathieu-Daudé
2020-06-30  8:13 ` [PATCH 4/7] hw/mips/malta: Introduce MaltaMachineClass::max_ramsize Philippe Mathieu-Daudé
2020-06-30  8:13 ` [PATCH 5/7] hw/mips/malta: Introduce the 'malta-phys' machine Philippe Mathieu-Daudé
2020-06-30  8:54   ` Philippe Mathieu-Daudé [this message]
2020-06-30  8:13 ` [PATCH 6/7] hw/mips/malta: Verify malta-phys machine uses correct DIMM sizes Philippe Mathieu-Daudé
2020-06-30  8:13 ` [PATCH 7/7] hw/mips/malta: Allow more than 2GB on 64-bit malta-virt Philippe Mathieu-Daudé
2020-06-30 10:48 ` [PATCH 0/7] hw/mips/malta: Rework to allow more than 2GB of RAM on 64-bit Aleksandar Markovic
2020-06-30 10:52   ` Philippe Mathieu-Daudé
2020-06-30 10:53     ` Philippe Mathieu-Daudé
2020-06-30 11:01       ` Aleksandar Markovic
2020-06-30 11:04         ` Philippe Mathieu-Daudé
2020-06-30 11:17           ` Aleksandar Markovic
2020-06-30 11:34             ` Philippe Mathieu-Daudé
2020-06-30 11:55               ` Aleksandar Markovic
2020-06-30 11:59                 ` Philippe Mathieu-Daudé
2020-06-30 12:07                   ` Aleksandar Markovic
2020-06-30 13:36             ` Thomas Huth
2020-06-30 13:45               ` Philippe Mathieu-Daudé
2020-06-30 10:54     ` Aleksandar Markovic
2020-06-30 10:58       ` Philippe Mathieu-Daudé
2020-06-30 11:05         ` Aleksandar Markovic

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=73404e5a-5c41-5f17-89d9-64cc1f943d1c@amsat.org \
    --to=f4bug@amsat.org \
    --cc=aleksandar.qemu.devel@gmail.com \
    --cc=aleksandar.rikalo@syrmia.com \
    --cc=aurelien@aurel32.net \
    --cc=imammedo@redhat.com \
    --cc=jiaxun.yang@flygoat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=ysu@wavecomp.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.