* [PATCH V7 01/10] clk: SPEAr13XX: Fix pcie clock name
[not found] <cover.1393568715.git.mohit.kumar@st.com>
@ 2014-02-28 11:54 ` Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 02/10] SPEAr13XX: Fix static mapping table Mohit Kumar
` (7 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
Follow dt clock naming convention for PCIe clocks.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
drivers/clk/spear/spear1310_clock.c | 6 +++---
drivers/clk/spear/spear1340_clock.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.0");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.1");
+ clk_register_clkdev(clk, NULL, "b1800000.pcie");
clk_register_clkdev(clk, NULL, "b1800000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.2");
+ clk_register_clkdev(clk, NULL, "b4000000.pcie");
clk_register_clkdev(clk, NULL, "b4000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
--
1.7.0.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 02/10] SPEAr13XX: Fix static mapping table
[not found] <cover.1393568715.git.mohit.kumar@st.com>
2014-02-28 11:54 ` [PATCH V7 01/10] clk: SPEAr13XX: Fix pcie clock name Mohit Kumar
@ 2014-02-28 11:54 ` Mohit Kumar
[not found] ` <cover.1393568715.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
` (6 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr13XX was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So
change 0xFE000000 to 0xF9000000.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel at list.st.com
Cc: stable at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/mach-spear/include/mach/spear.h | 4 ++--
arch/arm/mach-spear/spear13xx.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..f2d6a01 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
#ifdef CONFIG_ARCH_SPEAR13XX
#define PERIP_GRP2_BASE UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
-#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE IOMEM(0xF9800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8c..89212ff 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)
/*
* Following will create 16MB static virtual/physical mappings
* PHYSICAL VIRTUAL
- * 0xB3000000 0xFE000000
+ * 0xB3000000 0xF9000000
* 0xE0000000 0xFD000000
* 0xEC000000 0xFC000000
* 0xED000000 0xFB000000
--
1.7.0.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 03/10] phy: SPEAr1310/40-miphy: Add binding information
[not found] ` <cover.1393568715.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
@ 2014-02-28 11:54 ` Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 04/10] SPEAr: misc: " Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 06/10] SPEAr13XX: Add binding information for PCIe controller Mohit Kumar
2 siblings, 0 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:54 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Pratyush Anand, Mohit Kumar, Viresh Kumar,
Kishon Vijay Abraham I, spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA
From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
SPEAr1310/40 uses miphy for PCIe, SATA. This patch adds documentation
for the binding on the top of generic phy bindings.
Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 ++++++++++++
.../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +++++++++++
2 files changed, 23 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
new file mode 100644
index 0000000..b9b281a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
@@ -0,0 +1,12 @@
+ST SPEAr1310-miphy DT detail
+===================================
+
+SPEAr1310-miphy is a phy controller supporting PCIe and SATA.
+
+Required properties:
+- compatible : should be "st,spear1310-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - cell[1]: 0 if phy used for SATA, 1 for PCIe.
diff --git a/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
new file mode 100644
index 0000000..7eb5335
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
@@ -0,0 +1,11 @@
+ST SPEAr1340-miphy DT detail
+===================================
+
+SPEAr1340-miphy is a phy controller supporting PCIe and SATA.
+
+Required properties:
+- compatible : should be "st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - cell[1]: 0 if phy used for SATA, 1 for PCIe.
--
1.7.0.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 04/10] SPEAr: misc: Add binding information
[not found] ` <cover.1393568715.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
2014-02-28 11:54 ` [PATCH V7 03/10] phy: SPEAr1310/40-miphy: Add binding information Mohit Kumar
@ 2014-02-28 11:54 ` Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 06/10] SPEAr13XX: Add binding information for PCIe controller Mohit Kumar
2 siblings, 0 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:54 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Pratyush Anand, Mohit Kumar, Viresh Kumar,
spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA
From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
SPEAr SOCs have some miscellaneous registers which are used to configure
few properties of different peripheral controllers.
Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/arm/spear-misc.txt | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..cf64982
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,9 @@
+SPEAr Misc configuration
+===========================
+SPEAr SOCs have some miscellaneous registers which are used to configure
+few properties of different peripheral controllers.
+
+misc node required properties:
+
+- compatible Should be "st,spear1340-misc", "syscon".
+- reg: Address range of misc space upto 8K
--
1.7.0.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 05/10] phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
[not found] <cover.1393568715.git.mohit.kumar@st.com>
` (2 preceding siblings ...)
[not found] ` <cover.1393568715.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
@ 2014-02-28 11:54 ` Mohit Kumar
2014-02-28 11:55 ` [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support Mohit Kumar
` (4 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:54 UTC (permalink / raw)
To: arnd
Cc: Pratyush Anand, Viresh Kumar, Kishon Vijay Abraham I,
spear-devel, linux-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr1310/40 uses miphy for PCIe and SATA phy. This driver adds
support for the same.
AHCI phy hookups from arch specific code has been cleaned up.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel@list.st.com
Cc: linux-kernel@vger.kernel.org
---
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 39 ++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 12 ++-
arch/arm/boot/dts/spear13xx.dtsi | 5 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/spear1340.c | 127 +---------------
drivers/phy/Kconfig | 12 ++
drivers/phy/Makefile | 2 +
drivers/phy/phy-spear1310-miphy.c | 274 ++++++++++++++++++++++++++++++++
drivers/phy/phy-spear1340-miphy.c | 300 +++++++++++++++++++++++++++++++++++
11 files changed, 652 insertions(+), 130 deletions(-)
create mode 100644 drivers/phy/phy-spear1310-miphy.c
create mode 100644 drivers/phy/phy-spear1340-miphy.c
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
cf@b2800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..64e7dd5 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,57 @@
#gpio-cells = <2>;
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy1: miphy@eb804000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb804000 0x4000>;
+ misc = <&misc>;
+ phy-id = <1>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy2: miphy@eb808000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb808000 0x4000>;
+ misc = <&misc>;
+ phy-id = <2>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci@b1800000 {
+ ahci1: ahci@b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
+ phys = <&miphy1 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci@b4000000 {
+ ahci2: ahci@b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
+ phys = <&miphy2 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
dma@ea800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..b8b32c7 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,20 @@
status = "disabled";
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,miphy", "st,spear1340-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
+ misc: syscon@e0700000 {
+ compatible = "st,spear1340-misc", "syscon";
+ reg = <0xe0700000 0x1000>;
+ };
+
gpio0: gpio@e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e..29aee02 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,7 @@ config ARCH_SPEAR13XX
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select USE_OF
+ select MFD_SYSCON
help
Supports for ARM's SPEAR13XX family
@@ -34,12 +35,14 @@ if ARCH_SPEAR13XX
config MACH_SPEAR1310
bool "SPEAr1310 Machine support with Device Tree"
select PINCTRL_SPEAR1310
+ select PHY_ST_SPEAR1310_MIPHY
help
Supports ST SPEAr1310 machine configured via the device-tree
config MACH_SPEAR1340
bool "SPEAr1340 Machine support with Device Tree"
select PINCTRL_SPEAR1340
+ select PHY_ST_SPEAR1340_MIPHY
help
Supports ST SPEAr1340 machine configured via the device-tree
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
* warranty of any kind, whether express or implied.
*/
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
- /* PCIE CFG MASks */
- #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
- #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
- #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
- #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
- #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
- #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
- #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
- #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
- #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
- #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
- #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
- #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
- SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
- SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
- SPEAR1340_PCIE_CFG_POWERUP_RESET | \
- SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
- #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
- SPEAR1340_SATA_CFG_PM_CLK_EN | \
- SPEAR1340_SATA_CFG_POWERUP_RESET | \
- SPEAR1340_SATA_CFG_RX_CLK_EN | \
- SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
- #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
- #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
- #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_CLK_REF_DIV2 | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
- (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
- writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
- writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
- SPEAR1340_PCIE_MIPHY_CFG);
- /* Switch on sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
- /* Disable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
-
- return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
- writel(0, SPEAR1340_PCIE_SATA_CFG);
- writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
- /* Enable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
- /* Switch off sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_FREEZE)
- return 0;
-
- sata_miphy_exit(dev);
-
- return 0;
-}
-
-int sata_resume(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_THAW)
- return 0;
-
- return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
- .init = sata_miphy_init,
- .exit = sata_miphy_exit,
- .suspend = sata_suspend,
- .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
- &sata_pdata),
- {}
-};
static void __init spear1340_dt_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- spear1340_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..a78c059 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,16 @@ config BCM_KONA_USB2_PHY
help
Enable this to support the Broadcom Kona USB 2.0 PHY.
+config PHY_ST_SPEAR1310_MIPHY
+ tristate "ST SPEAR1310-MIPHY driver"
+ select GENERIC_PHY
+ help
+ Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA.
+
+config PHY_ST_SPEAR1340_MIPHY
+ tristate "ST SPEAR1340-MIPHY driver"
+ select GENERIC_PHY
+ help
+ Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..dad2b9a 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,5 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
+obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-spear1310-miphy.c b/drivers/phy/phy-spear1310-miphy.c
new file mode 100644
index 0000000..6136634
--- /dev/null
+++ b/drivers/phy/phy-spear1310-miphy.c
@@ -0,0 +1,274 @@
+/*
+ * ST SPEAr1310-miphy driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ * Mohit Kumar <mohit.kumar@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG 0x3A4
+ #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
+ #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
+ #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
+ #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
+ #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
+ #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
+ #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
+ #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
+ #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
+ #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
+ #define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20)
+ #define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19)
+ #define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18)
+ #define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17)
+ #define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16)
+ #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11)
+ #define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10)
+ #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9)
+ #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8)
+ #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7)
+ #define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6)
+ #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5)
+ #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4)
+ #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3)
+ #define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2)
+ #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1)
+ #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0)
+
+ #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
+ #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+ BIT((x + 29)))
+ #define SPEAR1310_PCIE_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+ SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+ #define SPEAR1310_SATA_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+ SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
+ #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
+ #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28)
+ #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
+ #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15)
+ #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
+ #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
+
+enum spear1310_miphy_mode {
+ SATA,
+ PCIE,
+};
+
+struct spear1310_miphy_priv {
+ /* instance id of this phy */
+ u32 id;
+ /* phy mode: 0 for SATA 1 for PCIe */
+ enum spear1310_miphy_mode mode;
+ /* regmap for any soc specific misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+};
+
+static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv)
+{
+ u32 val;
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+ switch (priv->id) {
+ case 0:
+ val = SPEAR1310_PCIE_CFG_VAL(0);
+ break;
+ case 1:
+ val = SPEAR1310_PCIE_CFG_VAL(1);
+ break;
+ case 2:
+ val = SPEAR1310_PCIE_CFG_VAL(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(priv->id), val);
+
+ return 0;
+}
+
+static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+ return 0;
+}
+
+static int spear1310_miphy_init(struct phy *phy)
+{
+ struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == PCIE)
+ ret = spear1310_miphy_pcie_init(priv);
+
+ return ret;
+}
+
+static int spear1310_miphy_exit(struct phy *phy)
+{
+ struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == PCIE)
+ ret = spear1310_miphy_pcie_exit(priv);
+
+ return ret;
+}
+
+static const struct of_device_id spear1310_miphy_of_match[] = {
+ { .compatible = "st,spear1310-miphy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match);
+
+static struct phy_ops spear1310_miphy_ops = {
+ .init = spear1310_miphy_init,
+ .exit = spear1310_miphy_exit,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *spear1310_miphy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct spear1310_miphy_priv *priv = dev_get_drvdata(dev);
+
+ if (args->args_count < 1) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ priv->mode = args->args[0];
+
+ if (priv->mode != SATA && priv->mode != PCIE) {
+ dev_err(dev, "DT did not pass correct phy mode\n");
+ return NULL;
+ }
+
+ return priv->phy;
+}
+
+static int __init spear1310_miphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spear1310_miphy_priv *priv;
+ struct phy_provider *phy_provider;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(dev, "can't alloc spear1310_miphy private date memory\n");
+ return -ENOMEM;
+ }
+
+ priv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(priv->misc)) {
+ dev_err(dev, "failed to find misc regmap\n");
+ return PTR_ERR(priv->misc);
+ }
+
+ if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) {
+ dev_err(dev, "failed to find phy id\n");
+ return -EINVAL;
+ }
+
+ priv->phy = devm_phy_create(dev, &spear1310_miphy_ops, NULL);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ dev_set_drvdata(dev, priv);
+ phy_set_drvdata(priv->phy, priv);
+
+ phy_provider =
+ devm_of_phy_provider_register(dev, spear1310_miphy_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static struct platform_driver spear1310_miphy_driver = {
+ .probe = spear1310_miphy_probe,
+ .driver = {
+ .name = "spear1310-miphy",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(spear1310_miphy_of_match),
+ },
+};
+
+static int __init spear1310_miphy_phy_init(void)
+{
+ return platform_driver_register(&spear1310_miphy_driver);
+}
+module_init(spear1310_miphy_phy_init);
+
+static void __exit spear1310_miphy_phy_exit(void)
+{
+ platform_driver_unregister(&spear1310_miphy_driver);
+}
+module_exit(spear1310_miphy_phy_exit);
+
+MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-spear1340-miphy.c b/drivers/phy/phy-spear1340-miphy.c
new file mode 100644
index 0000000..cbaf284
--- /dev/null
+++ b/drivers/phy/phy-spear1340-miphy.c
@@ -0,0 +1,300 @@
+/*
+ * ST spear1340-miphy driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ * Mohit Kumar <mohit.kumar@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG 0x100
+ #define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11)
+#define SPEAR1340_PCM_WKUP_CFG 0x104
+#define SPEAR1340_SWITCH_CTR 0x108
+
+#define SPEAR1340_PERIP1_SW_RST 0x318
+ #define SPEAR1340_PERIP1_SW_RSATA BIT(12)
+#define SPEAR1340_PERIP2_SW_RST 0x31C
+#define SPEAR1340_PERIP3_SW_RST 0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG 0x424
+ /* PCIE CFG MASks */
+ #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11)
+ #define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10)
+ #define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9)
+ #define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8)
+ #define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4)
+ #define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3)
+ #define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2)
+ #define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1)
+ #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
+ #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
+ #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
+ #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+ SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+ SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+ SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+ SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+ #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
+ SPEAR1340_SATA_CFG_PM_CLK_EN | \
+ SPEAR1340_SATA_CFG_POWERUP_RESET | \
+ SPEAR1340_SATA_CFG_RX_CLK_EN | \
+ SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG 0x428
+ #define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
+ #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+enum spear1340_miphy_mode {
+ SATA,
+ PCIE,
+};
+
+struct spear1340_miphy_priv {
+ /* phy mode: 0 for SATA 1 for PCIe */
+ enum spear1340_miphy_mode mode;
+ /* regmap for any soc specific misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+};
+
+static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+ /* Switch on sata power domain */
+ regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ msleep(20);
+ /* Disable PCIE SATA Controller reset */
+ regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RSATA, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_miphy_sata_exit(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+ /* Enable PCIE SATA Controller reset */
+ regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RSATA,
+ SPEAR1340_PERIP1_SW_RSATA);
+ msleep(20);
+ /* Switch off sata power domain */
+ regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_miphy_pcie_init(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+ return 0;
+}
+
+static int spear1340_miphy_pcie_exit(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+ return 0;
+}
+
+static int spear1340_miphy_init(struct phy *phy)
+{
+ struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_init(priv);
+ else if (priv->mode == PCIE)
+ ret = spear1340_miphy_pcie_init(priv);
+
+ return ret;
+}
+
+static int spear1340_miphy_exit(struct phy *phy)
+{
+ struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_exit(priv);
+ else if (priv->mode == PCIE)
+ ret = spear1340_miphy_pcie_exit(priv);
+
+ return ret;
+}
+
+static const struct of_device_id spear1340_miphy_of_match[] = {
+ { .compatible = "st,spear1340-miphy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, spear1340_miphy_of_match);
+
+static struct phy_ops spear1340_miphy_ops = {
+ .init = spear1340_miphy_init,
+ .exit = spear1340_miphy_exit,
+ .owner = THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int spear1340_miphy_suspend(struct device *dev)
+{
+ struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_exit(priv);
+
+ return ret;
+}
+
+static int spear1340_miphy_resume(struct device *dev)
+{
+ struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_init(priv);
+
+ return ret;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(spear1340_miphy_pm_ops, spear1340_miphy_suspend,
+ spear1340_miphy_resume);
+
+static struct phy *spear1340_miphy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+
+ if (args->args_count < 1) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ priv->mode = args->args[0];
+
+ if (priv->mode != SATA && priv->mode != PCIE) {
+ dev_err(dev, "DT did not pass correct phy mode\n");
+ return NULL;
+ }
+
+ return priv->phy;
+}
+
+static int __init spear1340_miphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spear1340_miphy_priv *priv;
+ struct phy_provider *phy_provider;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(dev, "can't alloc spear1340_miphy private date memory\n");
+ return -ENOMEM;
+ }
+
+ priv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(priv->misc)) {
+ dev_err(dev, "failed to find misc regmap\n");
+ return PTR_ERR(priv->misc);
+ }
+
+ priv->phy = devm_phy_create(dev, &spear1340_miphy_ops, NULL);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ dev_set_drvdata(dev, priv);
+ phy_set_drvdata(priv->phy, priv);
+
+ phy_provider =
+ devm_of_phy_provider_register(dev, spear1340_miphy_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static struct platform_driver spear1340_miphy_driver = {
+ .probe = spear1340_miphy_probe,
+ .driver = {
+ .name = "spear1340-miphy",
+ .owner = THIS_MODULE,
+ .pm = &spear1340_miphy_pm_ops,
+ .of_match_table = of_match_ptr(spear1340_miphy_of_match),
+ },
+};
+
+static int __init spear1340_miphy_phy_init(void)
+{
+ return platform_driver_register(&spear1340_miphy_driver);
+}
+module_init(spear1340_miphy_phy_init);
+
+static void __exit spear1340_miphy_phy_exit(void)
+{
+ platform_driver_unregister(&spear1340_miphy_driver);
+}
+module_exit(spear1340_miphy_phy_exit);
+
+MODULE_DESCRIPTION("ST SPEAR1340-MIPHY driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
--
1.7.0.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 06/10] SPEAr13XX: Add binding information for PCIe controller
[not found] ` <cover.1393568715.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
2014-02-28 11:54 ` [PATCH V7 03/10] phy: SPEAr1310/40-miphy: Add binding information Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 04/10] SPEAr: misc: " Mohit Kumar
@ 2014-02-28 11:54 ` Mohit Kumar
2 siblings, 0 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:54 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Pratyush Anand, Mohit Kumar, Viresh Kumar,
spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA
From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
SPEAr13XX uses designware PCIe controller. This patch adds information
for the PCIe binding properties which are specific to SPEAr13XX SoC
series.
Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/pci/spear13xx-pcie.txt | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
new file mode 100644
index 0000000..49ea76d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
@@ -0,0 +1,14 @@
+SPEAr13XX PCIe DT detail:
+================================
+
+SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
+controller.
+
+Required properties:
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys : phandle to phy node associated with pcie controller
+- phy-names : must be "pcie-phy"
+- All other definitions as per generic PCI bindings
+
+ Optional properties:
+- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
--
1.7.0.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support
[not found] <cover.1393568715.git.mohit.kumar@st.com>
` (3 preceding siblings ...)
2014-02-28 11:54 ` [PATCH V7 05/10] phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA Mohit Kumar
@ 2014-02-28 11:55 ` Mohit Kumar
2014-03-14 6:01 ` Jingoo Han
2014-04-04 16:42 ` Bjorn Helgaas
2014-02-28 11:55 ` [PATCH V7 09/10] SPEAr13xx: defconfig: Update Mohit Kumar
` (3 subsequent siblings)
8 siblings, 2 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:55 UTC (permalink / raw)
To: arnd
Cc: Pratyush Anand, Mohit Kumar, Jingoo Han, Viresh Kumar,
spear-devel, linux-pci
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
with ahci/sata pins. By default evaluation board of both controller
works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the
necessary modifications on board and enable (okay) pcie and miphy
from respective evb dtsi file.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
arch/arm/boot/dts/spear1310.dtsi | 6 +
arch/arm/boot/dts/spear1340.dtsi | 2 +
arch/arm/boot/dts/spear13xx.dtsi | 4 +-
arch/arm/mach-spear/Kconfig | 1 +
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 414 +++++++++++++++++++++++++++++++++++++
7 files changed, 434 insertions(+), 2 deletions(-)
create mode 100644 drivers/pci/host/pcie-spear13xx.c
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 136a12d..5c1a4d9 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -90,6 +90,8 @@
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 68>;
num-lanes = <1>;
+ phys = <&miphy0 1>;
+ phy-names = "pcie-phy";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -106,6 +108,8 @@
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 69>;
num-lanes = <1>;
+ phys = <&miphy1 1>;
+ phy-names = "pcie-phy";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -122,6 +126,8 @@
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 70>;
num-lanes = <1>;
+ phys = <&miphy2 1>;
+ phy-names = "pcie-phy";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 9af299d..611f1f8 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -55,6 +55,8 @@
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 68>;
num-lanes = <1>;
+ phys = <&miphy0 1>;
+ phy-names = "pcie-phy";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3a72508..a6eb543 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
- 0xb0000000 0xb0000000 0x10000000
- 0xd0000000 0xd0000000 0x02000000
+ 0x80000000 0x80000000 0x20000000
+ 0xb0000000 0xb0000000 0x22000000
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 29aee02..f335702 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -27,6 +27,7 @@ config ARCH_SPEAR13XX
select PINCTRL
select USE_OF
select MFD_SYSCON
+ select MIGHT_HAVE_PCI
help
Supports for ARM's SPEAR13XX family
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..8697dd1 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,12 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCIE_SPEAR13XX
+ tristate "STMicroelectronics SPEAr PCIe controller"
+ depends on ARCH_SPEAR13XX
+ select PCIEPORTBUS
+ select PCIE_DW
+ help
+ Say Y here if you want PCIe support on SPEAr13XX SoCs.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..42a491d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
new file mode 100644
index 0000000..c70d526
--- /dev/null
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -0,0 +1,414 @@
+/*
+ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
+ *
+ * SPEAr13xx PCIe Glue Layer Source Code
+ *
+ * Copyright (C) 2010-2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ * Mohit Kumar <mohit.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include "pcie-designware.h"
+
+struct spear13xx_pcie {
+ void __iomem *app_base;
+ struct phy *phy;
+ struct clk *clk;
+ struct pcie_port pp;
+ bool is_gen1;
+};
+
+struct pcie_app_reg {
+ u32 app_ctrl_0; /*cr0*/
+ u32 app_ctrl_1; /*cr1*/
+ u32 app_status_0; /*cr2*/
+ u32 app_status_1; /*cr3*/
+ u32 msg_status; /*cr4*/
+ u32 msg_payload; /*cr5*/
+ u32 int_sts; /*cr6*/
+ u32 int_clr; /*cr7*/
+ u32 int_mask; /*cr8*/
+ u32 mst_bmisc; /*cr9*/
+ u32 phy_ctrl; /*cr10*/
+ u32 phy_status; /*cr11*/
+ u32 cxpl_debug_info_0; /*cr12*/
+ u32 cxpl_debug_info_1; /*cr13*/
+ u32 ven_msg_ctrl_0; /*cr14*/
+ u32 ven_msg_ctrl_1; /*cr15*/
+ u32 ven_msg_data_0; /*cr16*/
+ u32 ven_msg_data_1; /*cr17*/
+ u32 ven_msi_0; /*cr18*/
+ u32 ven_msi_1; /*cr19*/
+ u32 mst_rmisc; /*cr 20*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID 0
+#define TX_LANE_FLIP_EN_ID 1
+#define SYS_AUX_PWR_DET_ID 2
+#define APP_LTSSM_ENABLE_ID 3
+#define SYS_ATTEN_BUTTON_PRESSED_ID 4
+#define SYS_MRL_SENSOR_STATE_ID 5
+#define SYS_PWR_FAULT_DET_ID 6
+#define SYS_MRL_SENSOR_CHGED_ID 7
+#define SYS_PRE_DET_CHGED_ID 8
+#define SYS_CMD_CPLED_INT_ID 9
+#define APP_INIT_RST_0_ID 11
+#define APP_REQ_ENTR_L1_ID 12
+#define APP_READY_ENTR_L23_ID 13
+#define APP_REQ_EXIT_L1_ID 14
+#define DEVICE_TYPE_EP (0 << 25)
+#define DEVICE_TYPE_LEP (1 << 25)
+#define DEVICE_TYPE_RC (4 << 25)
+#define SYS_INT_ID 29
+#define MISCTRL_EN_ID 30
+#define REG_TRANSLATION_ENABLE 31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID 2
+#define APPS_PM_XMT_PME_ID 5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
+#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
+#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
+#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
+#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
+#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
+#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
+#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
+#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
+#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
+#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
+#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
+#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
+#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
+#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
+#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
+#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
+#define XMLH_LTSSM_STATE_L0 0x11
+#define XMLH_LTSSM_STATE_L0S 0x12
+#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
+#define XMLH_LTSSM_STATE_L1_IDLE 0x14
+#define XMLH_LTSSM_STATE_L2_IDLE 0x15
+#define XMLH_LTSSM_STATE_L2_WAKE 0x16
+#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
+#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
+#define XMLH_LTSSM_STATE_DISABLED 0x19
+#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
+#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
+#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
+#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
+#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
+#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
+#define XMLH_LTSSM_STATE_MASK 0x3F
+#define XMLH_LINK_UP (1 << 6)
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID 18
+
+/*CR6*/
+#define INTA_CTRL_INT (1 << 7)
+#define INTB_CTRL_INT (1 << 8)
+#define INTC_CTRL_INT (1 << 9)
+#define INTD_CTRL_INT (1 << 10)
+#define MSI_CTRL_INT (1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID 11
+#define VEN_MSI_FUN_NUM_ID 8
+#define VEN_MSI_TC_ID 5
+#define VEN_MSI_VECTOR_ID 0
+#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
+
+#define PCI_CAP_ID_EXP_OFFSET 0x70
+
+#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
+
+static int spear13xx_pcie_establish_link(struct pcie_port *pp)
+{
+ u32 val;
+ int count = 0;
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+ u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+
+ if (dw_pcie_link_up(pp)) {
+ dev_err(pp->dev, "Link already up\n");
+ return 0;
+ }
+
+ /* setup root complex */
+ dw_pcie_setup_rc(pp);
+
+ /*
+ * this controller support only 128 bytes read size, however its
+ * default value in capability register is 512 bytes. So force
+ * it to 128 here.
+ */
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+ val &= ~PCI_EXP_DEVCTL_READRQ;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+
+ /* program vid and did for RC */
+ dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
+ dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
+
+ /*
+ * if is_gen1 is set then handle it, so that some buggy card
+ * also works
+ */
+ if (spear13xx_pcie->is_gen1) {
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+ &val);
+ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+ PCI_EXP_LNKCAP, 4, val);
+ }
+
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+ &val);
+ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+ PCI_EXP_LNKCTL2, 4, val);
+ }
+ }
+
+ /* enable ltssm */
+ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+ | (1 << APP_LTSSM_ENABLE_ID)
+ | ((u32)1 << REG_TRANSLATION_ENABLE),
+ &app_reg->app_ctrl_0);
+
+ /* check if the link is up or not */
+ while (!dw_pcie_link_up(pp)) {
+ mdelay(100);
+ count++;
+ if (count == 10) {
+ dev_err(pp->dev, "Link Fail\n");
+ return -EINVAL;
+ }
+ }
+ dev_info(pp->dev, "Link up\n");
+
+ return 0;
+}
+
+static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+ unsigned int status;
+
+ status = readl(&app_reg->int_sts);
+
+ if (status & MSI_CTRL_INT) {
+ if (!IS_ENABLED(CONFIG_PCI_MSI))
+ BUG();
+ dw_handle_msi_irq(pp);
+ }
+
+ writel(status, &app_reg->int_clr);
+
+ return IRQ_HANDLED;
+}
+
+static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+ /* Enable MSI interrupt */
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ dw_pcie_msi_init(pp);
+ writel(readl(&app_reg->int_mask) |
+ MSI_CTRL_INT, &app_reg->int_mask);
+ }
+
+ return;
+}
+
+static int spear13xx_pcie_link_up(struct pcie_port *pp)
+{
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+ if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
+ return 1;
+
+ return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+ spear13xx_pcie_establish_link(pp);
+ spear13xx_pcie_enable_interrupts(pp);
+}
+
+static struct pcie_host_ops spear13xx_pcie_host_ops = {
+ .link_up = spear13xx_pcie_link_up,
+ .host_init = spear13xx_pcie_host_init,
+};
+
+static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pp->irq = platform_get_irq(pdev, 0);
+ if (!pp->irq) {
+ dev_err(dev, "failed to get irq\n");
+ return -ENODEV;
+ }
+ ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
+ IRQF_SHARED, "spear1340-pcie", pp);
+ if (ret) {
+ dev_err(dev, "failed to request irq\n");
+ return ret;
+ }
+
+ pp->root_bus_nr = -1;
+ pp->ops = &spear13xx_pcie_host_ops;
+
+ spin_lock_init(&pp->conf_lock);
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __init spear13xx_pcie_probe(struct platform_device *pdev)
+{
+ struct spear13xx_pcie *spear13xx_pcie;
+ struct pcie_port *pp;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *dbi_base;
+ int ret;
+
+ spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
+ GFP_KERNEL);
+ if (!spear13xx_pcie) {
+ dev_err(dev, "no memory for SPEAr13xx pcie\n");
+ return -ENOMEM;
+ }
+
+ spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
+ if (IS_ERR(spear13xx_pcie->phy)) {
+ ret = PTR_ERR(spear13xx_pcie->phy);
+ switch (ret) {
+ case -EPROBE_DEFER:
+ dev_info(dev, "probe deferred\n");
+ return ret;
+ default:
+ dev_err(dev, "couldn't get pcie-phy\n");
+ return ret;
+ }
+ }
+
+ phy_init(spear13xx_pcie->phy);
+
+ spear13xx_pcie->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(spear13xx_pcie->clk)) {
+ dev_err(dev, "couldn't get clk for pcie\n");
+ return PTR_ERR(spear13xx_pcie->clk);
+ }
+ ret = clk_prepare_enable(spear13xx_pcie->clk);
+ if (ret) {
+ dev_err(dev, "couldn't enable clk for pcie\n");
+ return ret;
+ }
+
+ pp = &spear13xx_pcie->pp;
+
+ pp->dev = dev;
+
+ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
+ if (IS_ERR(pp->dbi_base)) {
+ dev_err(dev, "couldn't remap dbi base\n");
+ ret = PTR_ERR(pp->dbi_base);
+ goto fail_clk;
+ }
+ spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
+
+ if (of_property_read_bool(np, "st,pcie-is-gen1"))
+ spear13xx_pcie->is_gen1 = true;
+
+ ret = add_pcie_port(pp, pdev);
+ if (ret < 0)
+ goto fail_clk;
+
+ platform_set_drvdata(pdev, spear13xx_pcie);
+ return 0;
+
+fail_clk:
+ clk_disable_unprepare(spear13xx_pcie->clk);
+
+ return ret;
+}
+
+static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
+{
+ struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(spear13xx_pcie->clk);
+
+ phy_exit(spear13xx_pcie->phy);
+
+ return 0;
+}
+
+static const struct of_device_id spear13xx_pcie_of_match[] = {
+ { .compatible = "st,spear1340-pcie", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
+
+static struct platform_driver spear13xx_pcie_driver = {
+ .probe = spear13xx_pcie_probe,
+ .remove = spear13xx_pcie_remove,
+ .driver = {
+ .name = "spear-pcie",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
+ },
+};
+
+/* SPEAr13xx PCIe driver does not allow module unload */
+
+static int __init pcie_init(void)
+{
+ return platform_driver_register(&spear13xx_pcie_driver);
+}
+module_init(pcie_init);
+
+MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
--
1.7.0.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 09/10] SPEAr13xx: defconfig: Update
[not found] <cover.1393568715.git.mohit.kumar@st.com>
` (4 preceding siblings ...)
2014-02-28 11:55 ` [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support Mohit Kumar
@ 2014-02-28 11:55 ` Mohit Kumar
2014-02-28 11:55 ` [PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
` (2 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:55 UTC (permalink / raw)
To: linux-arm-kernel
Enable PCIe, EABI, VFP and NFS configs in default configuration file for
SPEAr13xx.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/configs/spear13xx_defconfig | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..d271b26 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
# CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +92,14 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
--
1.7.0.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
[not found] <cover.1393568715.git.mohit.kumar@st.com>
` (5 preceding siblings ...)
2014-02-28 11:55 ` [PATCH V7 09/10] SPEAr13xx: defconfig: Update Mohit Kumar
@ 2014-02-28 11:55 ` Mohit Kumar
2014-04-04 16:44 ` Bjorn Helgaas
2014-03-04 5:41 ` [PATCH V7 07/10 resend] SPEAr13XX: dts: Add PCIe node information Mohit Kumar
[not found] ` <2CC2A0A4A178534D93D5159BF3BCB66189FEB12EE3@EAPEX1MAIL1.st.com>
8 siblings, 1 reply; 22+ messages in thread
From: Mohit Kumar @ 2014-02-28 11:55 UTC (permalink / raw)
To: arnd; +Cc: Mohit Kumar, Pratyush Anand, linux-pci
Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci@vger.kernel.org
---
MAINTAINERS | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index b2cf5cf..ebdca89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6596,6 +6596,12 @@ L: linux-pci@vger.kernel.org
S: Maintained
F: drivers/pci/host/*designware*
+PCIE DRIVER FOR ST SPEAR13XX
+M: Mohit Kumar <mohit.kumar@st.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/pcie-spear13xx.c
+
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
L: linux-pcmcia@lists.infradead.org
--
1.7.0.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
2014-03-04 5:41 ` [PATCH V7 07/10 resend] SPEAr13XX: dts: Add PCIe node information Mohit Kumar
@ 2014-02-28 11:58 ` Arnd Bergmann
2014-03-03 4:45 ` Mohit KUMAR DCG
0 siblings, 1 reply; 22+ messages in thread
From: Arnd Bergmann @ 2014-02-28 11:58 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 28 February 2014 17:25:00 Mohit Kumar wrote:
> + interrupts = <0 68 0x4>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0x0 0 &gic 68>;
>
>From the discussion we just had on the imx version of this driver, I suspect
what you want instead is to drop the interrupts property and fix the interrupt
map to be
interrupt-map = <0x0 0 &gic 0 68 0x4>;
Arnd
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
2014-02-28 11:58 ` [PATCH V7 07/10] " Arnd Bergmann
@ 2014-03-03 4:45 ` Mohit KUMAR DCG
2014-03-14 10:34 ` Arnd Bergmann
0 siblings, 1 reply; 22+ messages in thread
From: Mohit KUMAR DCG @ 2014-03-03 4:45 UTC (permalink / raw)
To: linux-arm-kernel
Hello Arnd,
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Friday, February 28, 2014 5:28 PM
> To: Mohit KUMAR DCG
> Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
>
> On Friday 28 February 2014 17:25:00 Mohit Kumar wrote:
> > + interrupts = <0 68 0x4>;
> > + interrupt-map-mask = <0 0 0 0>;
> > + interrupt-map = <0x0 0 &gic 68>;
> >
>
> From the discussion we just had on the imx version of this driver, I suspect
> what you want instead is to drop the interrupts property and fix the interrupt
> map to be
>
> interrupt-map = <0x0 0 &gic 0 68 0x4>;
>
- yes, I should have fix interrupt map. Pls let us know if any other point needs to be
Incorporated in this series.
Regards
Mohit
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V7 07/10 resend] SPEAr13XX: dts: Add PCIe node information
[not found] <cover.1393568715.git.mohit.kumar@st.com>
` (6 preceding siblings ...)
2014-02-28 11:55 ` [PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
@ 2014-03-04 5:41 ` Mohit Kumar
2014-02-28 11:58 ` [PATCH V7 07/10] " Arnd Bergmann
[not found] ` <2CC2A0A4A178534D93D5159BF3BCB66189FEB12EE3@EAPEX1MAIL1.st.com>
8 siblings, 1 reply; 22+ messages in thread
From: Mohit Kumar @ 2014-03-04 5:41 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr1310 and SPEAr1340 supports 3 and 1 PCIe controller respectively.
These controllers are based on synopsys designware controller.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
Fixed interrupt-map property as per new discussion.
http://www.spinics.net/lists/arm-kernel/msg312036.html
arch/arm/boot/dts/spear1310.dtsi | 48 ++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/spear1340.dtsi | 16 ++++++++++++
2 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 64e7dd5..136a12d 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -83,6 +83,54 @@
status = "disabled";
};
+ pcie0: pcie at b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 68 0x4>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie1: pcie at b1800000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1800000 0x4000>;
+ interrupts = <0 69 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 69 0x4>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie2: pcie at b4000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb4000000 0x4000>;
+ interrupts = <0 70 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 70 0x4>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
gmac1: eth at 5c400000 {
compatible = "st,spear600-gmac";
reg = <0x5c400000 0x8000>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index b8b32c7..9af299d 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -48,6 +48,22 @@
status = "disabled";
};
+ pcie0: pcie at b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 68 0x4>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
i2s-play at b2400000 {
compatible = "snps,designware-i2s";
reg = <0xb2400000 0x10000>;
--
1.7.0.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support
2014-02-28 11:55 ` [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support Mohit Kumar
@ 2014-03-14 6:01 ` Jingoo Han
2014-03-14 11:09 ` Mohit KUMAR DCG
2014-04-04 16:42 ` Bjorn Helgaas
1 sibling, 1 reply; 22+ messages in thread
From: Jingoo Han @ 2014-03-14 6:01 UTC (permalink / raw)
To: 'Mohit Kumar'
Cc: arnd, 'Pratyush Anand', 'Viresh Kumar',
spear-devel, linux-pci, 'Jingoo Han'
On Friday, February 28, 2014 8:55 PM, Mohit Kumar wrote:
>
> From: Pratyush Anand <pratyush.anand@st.com>
>
> SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
> SPEAr13xx PCIe driver based on designware controller driver.
>
> SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
> with ahci/sata pins. By default evaluation board of both controller
> works for ahci mode.
> To use these patches on SPEAr1340/1310 evaluation board, do the
> necessary modifications on board and enable (okay) pcie and miphy
> from respective evb dtsi file.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
For 'drivers/pci/host/pcie-spear13xx.c',
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Best regards,
Jingoo Han
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
> arch/arm/boot/dts/spear1310.dtsi | 6 +
> arch/arm/boot/dts/spear1340.dtsi | 2 +
> arch/arm/boot/dts/spear13xx.dtsi | 4 +-
> arch/arm/mach-spear/Kconfig | 1 +
> drivers/pci/host/Kconfig | 8 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pcie-spear13xx.c | 414 +++++++++++++++++++++++++++++++++++++
> 7 files changed, 434 insertions(+), 2 deletions(-)
> create mode 100644 drivers/pci/host/pcie-spear13xx.c
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
2014-03-03 4:45 ` Mohit KUMAR DCG
@ 2014-03-14 10:34 ` Arnd Bergmann
2014-03-14 11:08 ` Mohit KUMAR DCG
0 siblings, 1 reply; 22+ messages in thread
From: Arnd Bergmann @ 2014-03-14 10:34 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 03 March 2014, Mohit KUMAR DCG wrote:
> Hello Arnd,
>
> > -----Original Message-----
> > From: Arnd Bergmann [mailto:arnd at arndb.de]
> > Sent: Friday, February 28, 2014 5:28 PM
> > To: Mohit KUMAR DCG
> > Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> > kernel at lists.infradead.org
> > Subject: Re: [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
> >
> > On Friday 28 February 2014 17:25:00 Mohit Kumar wrote:
> > > + interrupts = <0 68 0x4>;
> > > + interrupt-map-mask = <0 0 0 0>;
> > > + interrupt-map = <0x0 0 &gic 68>;
> > >
> >
> > From the discussion we just had on the imx version of this driver, I suspect
> > what you want instead is to drop the interrupts property and fix the interrupt
> > map to be
> >
> > interrupt-map = <0x0 0 &gic 0 68 0x4>;
> >
>
> - yes, I should have fix interrupt map. Pls let us know if any other point needs to be
> Incorporated in this series.
>
I just noticed from your code that you use the 68 interrupt both for MSI and
legacy interrupts. Is this what the hardware does? I was asking above that
the 'interrupts' property be dropped, but I guess that won't work if it's
also used for MSI.
Please clarify.
Aside from this, all patches
Acked-by: Arnd Bergmann <arnd@arndb.de>
Arnd
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
2014-03-14 10:34 ` Arnd Bergmann
@ 2014-03-14 11:08 ` Mohit KUMAR DCG
2014-03-24 3:57 ` Mohit KUMAR DCG
0 siblings, 1 reply; 22+ messages in thread
From: Mohit KUMAR DCG @ 2014-03-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Hello Arnd,
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Friday, March 14, 2014 4:04 PM
> To: Mohit KUMAR DCG
> Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
>
> On Monday 03 March 2014, Mohit KUMAR DCG wrote:
> > Hello Arnd,
> >
> > > -----Original Message-----
> > > From: Arnd Bergmann [mailto:arnd at arndb.de]
> > > Sent: Friday, February 28, 2014 5:28 PM
> > > To: Mohit KUMAR DCG
> > > Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> > > kernel at lists.infradead.org
> > > Subject: Re: [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node
> > > information
> > >
> > > On Friday 28 February 2014 17:25:00 Mohit Kumar wrote:
> > > > + interrupts = <0 68 0x4>;
> > > > + interrupt-map-mask = <0 0 0 0>;
> > > > + interrupt-map = <0x0 0 &gic 68>;
> > > >
> > >
> > > From the discussion we just had on the imx version of this driver, I
> > > suspect what you want instead is to drop the interrupts property and
> > > fix the interrupt map to be
> > >
> > > interrupt-map = <0x0 0 &gic 0 68 0x4>;
> > >
> >
> > - yes, I should have fix interrupt map. Pls let us know if any other
> > point needs to be Incorporated in this series.
> >
>
> I just noticed from your code that you use the 68 interrupt both for MSI and
> legacy interrupts. Is this what the hardware does? I was asking above that
> the 'interrupts' property be dropped, but I guess that won't work if it's also
> used for MSI.
>
> Please clarify.
- Yes, single interrupt line for PCIe is shared between MSI and legacy interrupt.
>
> Aside from this, all patches
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
- Thanks :-)
Mohit
>
> Arnd
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support
2014-03-14 6:01 ` Jingoo Han
@ 2014-03-14 11:09 ` Mohit KUMAR DCG
0 siblings, 0 replies; 22+ messages in thread
From: Mohit KUMAR DCG @ 2014-03-14 11:09 UTC (permalink / raw)
To: Jingoo Han
Cc: arnd, Pratyush ANAND, 'Viresh Kumar', spear-devel, linux-pci
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
2014-03-14 11:08 ` Mohit KUMAR DCG
@ 2014-03-24 3:57 ` Mohit KUMAR DCG
0 siblings, 0 replies; 22+ messages in thread
From: Mohit KUMAR DCG @ 2014-03-24 3:57 UTC (permalink / raw)
To: linux-arm-kernel
Hello Bjorn,
Could you pls pick up this series into your tree so that others can rebase there work on the top of it.
Thanks
Mohit
> -----Original Message-----
> From: Mohit KUMAR [mailto:mohit.kumar at st.com]
> Sent: Friday, March 14, 2014 4:39 PM
> To: Arnd Bergmann
> Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> kernel at lists.infradead.org
> Subject: RE: [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node information
>
> Hello Arnd,
>
> > -----Original Message-----
> > From: Arnd Bergmann [mailto:arnd at arndb.de]
> > Sent: Friday, March 14, 2014 4:04 PM
> > To: Mohit KUMAR DCG
> > Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> > kernel at lists.infradead.org
> > Subject: Re: [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node
> > information
> >
> > On Monday 03 March 2014, Mohit KUMAR DCG wrote:
> > > Hello Arnd,
> > >
> > > > -----Original Message-----
> > > > From: Arnd Bergmann [mailto:arnd at arndb.de]
> > > > Sent: Friday, February 28, 2014 5:28 PM
> > > > To: Mohit KUMAR DCG
> > > > Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> > > > kernel at lists.infradead.org
> > > > Subject: Re: [PATCH V7 07/10] SPEAr13XX: dts: Add PCIe node
> > > > information
> > > >
> > > > On Friday 28 February 2014 17:25:00 Mohit Kumar wrote:
> > > > > + interrupts = <0 68 0x4>;
> > > > > + interrupt-map-mask = <0 0 0 0>;
> > > > > + interrupt-map = <0x0 0 &gic 68>;
> > > > >
> > > >
> > > > From the discussion we just had on the imx version of this driver,
> > > > I suspect what you want instead is to drop the interrupts property
> > > > and fix the interrupt map to be
> > > >
> > > > interrupt-map = <0x0 0 &gic 0 68 0x4>;
> > > >
> > >
> > > - yes, I should have fix interrupt map. Pls let us know if any other
> > > point needs to be Incorporated in this series.
> > >
> >
> > I just noticed from your code that you use the 68 interrupt both for
> > MSI and legacy interrupts. Is this what the hardware does? I was
> > asking above that the 'interrupts' property be dropped, but I guess
> > that won't work if it's also used for MSI.
> >
> > Please clarify.
>
> - Yes, single interrupt line for PCIe is shared between MSI and legacy
> interrupt.
>
> >
> > Aside from this, all patches
> >
> > Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> - Thanks :-)
> Mohit
> >
> > Arnd
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V7 00/10] PCI: Add SPEAr13xx PCie support
[not found] ` <CAErSpo4pr5GC65pphxDUJGfep+yY06C8+RBmhygJPPQ7O5CD_g@mail.gmail.com>
@ 2014-03-31 5:25 ` Mohit KUMAR DCG
0 siblings, 0 replies; 22+ messages in thread
From: Mohit KUMAR DCG @ 2014-03-31 5:25 UTC (permalink / raw)
To: Bjorn Helgaas, Mark Nicholson, Arnd Bergmann (arnd@arndb.de)
Cc: Bartlomiej Zolnierkiewicz, spear-devel, linux-pci, linux-arm-kernel
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V7 00/10] PCI: Add SPEAr13xx PCie support
@ 2014-03-31 5:25 ` Mohit KUMAR DCG
0 siblings, 0 replies; 22+ messages in thread
From: Mohit KUMAR DCG @ 2014-03-31 5:25 UTC (permalink / raw)
To: linux-arm-kernel
Hello Arnd,
> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas at google.com]
> Sent: Friday, March 28, 2014 9:56 PM
> To: Mark Nicholson
> Cc: Mohit KUMAR DCG; Arnd Bergmann (arnd at arndb.de); Bartlomiej
> Zolnierkiewicz
> Subject: Re: [PATCH V7 00/10] PCI: Add SPEAr13xx PCie support
>
> Not from me. It should be in patchwork
> (http://patchwork.ozlabs.org/project/linux-pci/list/), where you can
> download patches and apply manually.
>
> If it's *not* in patchwork, it means I discarded it for some reason
> (superseded, changes requested, it wasn't sent to linux-pci, etc., and you
> should resend it so I'll remember to look at it.
>
- Yes, I can find PCIe specific patch#8,10 here. I think rest of the
patches should be coming through your tree.
Regards
Mohit
> On Fri, Mar 28, 2014 at 10:21 AM, Mark Nicholson <mark@nicholnet.com>
> wrote:
> > Great! In the mean time, is there a place to download the patchset?
> >
> > Thanks!
> > ~Mark
> >
> >
> >
> > On Fri, Mar 28, 2014 at 7:53 AM, Bjorn Helgaas <bhelgaas@google.com>
> wrote:
> >>
> >> On Thu, Mar 27, 2014 at 10:37 PM, Mohit KUMAR DCG
> >> <Mohit.KUMAR@st.com>
> >> wrote:
> >> > Gentle Reminder!!
> >> >
> >> > Hello Bjorn,
> >> >
> >> > I am getting multiple queries on the availability of these patches(CC).
> >> > Could you pls pick up this series at least for your tree.
> >>
> >> I'll start merging things for v3.16 next week after v3.14 is released.
> >> Don't worry, it's not forgotten :)
> >>
> >> Bjorn
> >>
> >> >> -----Original Message-----
> >> >> From: Mohit KUMAR DCG
> >> >> Sent: Friday, February 28, 2014 5:25 PM
> >> >> To: arnd at arndb.de
> >> >> Cc: Mohit KUMAR DCG
> >> >> Subject: [PATCH V7 00/10] PCI: Add SPEAr13xx PCie support
> >> >>
> >> >> Patch# 1 and 2: Improvement and fixes for SPEAr13xx support.
> >> >> Patch# 3,4 and 6: Add DT bindings for spear1310/40-miphy, misc and
> >> >> pcie node Patch# 5: Add spear1310/40-miphy driver and support for
> >> >> spear1310/40
> >> >> miphy wrapper.
> >> >> Patch# 7-9: Add SPEAr13xx PCIe driver and dt support.
> >> >>
> >> >> These pathes are tested with linux-3.14-rc1 with following patch
> >> >> on the top of
> >> >> it:
> >> >> Author: Balaji T K <balajitk@ti.com>
> >> >> Date: Mon Jan 20 16:41:27 2014 +0200
> >> >>
> >> >> ata: ahci_platform: Manage SATA PHY
> >> >>
> >> >> Tested with SPEAr1310 evaluation board:
> >> >> - INTEL PRO 100/100 EP card
> >> >> - USB xhci gen2 card
> >> >> - Above cards connected through LeCROY PTC switch
> >> >>
> >> >> Modifications for SATA are tested with SPEAr1340-evb board
> >> >>
> >> >> Changes since v6:
> >> >> - Split miphy driver for SPEAr1310 and SPEAr1340
> >> >> - Some cleanup and incorporated other minor comments Changes
> since v5:
> >> >> - Split DT bindings for misc, miphy-40lp and pcie node into
> >> >> sepearte patches
> >> >> - Merge config options PCIE_SPEAR13XX and PCI_MSI into defconfig
> >> >> patch
> >> >> - Incorporated other minor comments Changes since v4:
> >> >> - Uses per device function pointers passed from .data field to
> >> >> the of_device_id instead of of_device_is_compatible.
> >> >> - Incorporated other minor comments from v4
> >> >>
> >> >> Changes since v3:
> >> >> - Phy driver renamed to phy-miphy40lp
> >> >> - ahci phy hook patch used as suggested by Arnd
> >> >> - Incorporated other minor comments from v3
> >> >>
> >> >> Changes since v2:
> >> >> - Incorporated comments to move SPEAr13xx PCIe and SATA phy
> >> >> specific routines to
> >> >> the phy framework
> >> >> - Modify ahci driver to include phy hooks
> >> >> - phy-core driver modifications for subsys_initcall()
> >> >>
> >> >> Changes since v1:
> >> >> - Few patches of the series are already accepted and applied to
> >> >> mainline e.g.
> >> >> pcie designware driver improvements,fixes for IO translation bug,
> >> >> PCIe dw driver maintainer. So dropped these from v2.
> >> >> - Incorporated comment to move the common/reset PCIe code to the
> >> >> seperate driver
> >> >> - PCIe and SATA share common PHY configuration registers, so move
> >> >> SATA platform code to the system config driver Fourth patch is
> >> >> improves pcie designware driver and fixes the IO translation bug.
> >> >> IO translation bug fix leads to the working of PCIe EP devices
> >> >> connected to RC through switch.
> >> >>
> >> >> Mohit Kumar (2):
> >> >> SPEAr13xx: defconfig: Update
> >> >> MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
> >> >>
> >> >> Pratyush Anand (8):
> >> >> clk: SPEAr13XX: Fix pcie clock name
> >> >> SPEAr13XX: Fix static mapping table
> >> >> phy: SPEAr1310/40-miphy: Add binding information
> >> >> SPEAr: misc: Add binding information
> >> >> phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
> >> >> SPEAr13XX: Add binding information for PCIe controller
> >> >> SPEAr13XX: dts: Add PCIe node information
> >> >> pcie: SPEAr13xx: Add designware wrapper support
> >> >>
> >> >> .../devicetree/bindings/arm/spear-misc.txt | 9 +
> >> >> .../devicetree/bindings/pci/spear13xx-pcie.txt | 14 +
> >> >> .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 +
> >> >> .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +
> >> >> MAINTAINERS | 6 +
> >> >> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> >> >> arch/arm/boot/dts/spear1310.dtsi | 93 +++++-
> >> >> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> >> >> arch/arm/boot/dts/spear1340.dtsi | 30 ++-
> >> >> arch/arm/boot/dts/spear13xx.dtsi | 9 +-
> >> >> arch/arm/configs/spear13xx_defconfig | 16 +
> >> >> arch/arm/mach-spear/Kconfig | 4 +
> >> >> arch/arm/mach-spear/include/mach/spear.h | 4 +-
> >> >> arch/arm/mach-spear/spear1340.c | 127 +------
> >> >> arch/arm/mach-spear/spear13xx.c | 2 +-
> >> >> drivers/clk/spear/spear1310_clock.c | 6 +-
> >> >> drivers/clk/spear/spear1340_clock.c | 2 +-
> >> >> drivers/pci/host/Kconfig | 8 +
> >> >> drivers/pci/host/Makefile | 1 +
> >> >> drivers/pci/host/pcie-spear13xx.c | 414
> >> >> ++++++++++++++++++++
> >> >> drivers/phy/Kconfig | 12 +
> >> >> drivers/phy/Makefile | 2 +
> >> >> drivers/phy/phy-spear1310-miphy.c | 274
> >> >> +++++++++++++
> >> >> drivers/phy/phy-spear1340-miphy.c | 300
> >> >> ++++++++++++++
> >> >> 24 files changed, 1225 insertions(+), 139 deletions(-) create
> >> >> mode
> >> >> 100644
> >> >> Documentation/devicetree/bindings/arm/spear-misc.txt
> >> >> create mode 100644
> >> >> Documentation/devicetree/bindings/pci/spear13xx-
> >> >> pcie.txt
> >> >> create mode 100644 Documentation/devicetree/bindings/phy/st-
> >> >> spear1310-miphy.txt
> >> >> create mode 100644 Documentation/devicetree/bindings/phy/st-
> >> >> spear1340-miphy.txt
> >> >> create mode 100644 drivers/pci/host/pcie-spear13xx.c create mode
> >> >> 100644
> >> >> drivers/phy/phy-spear1310-miphy.c create mode 100644
> >> >> drivers/phy/phy- spear1340-miphy.c
> >> >
> >
> >
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support
2014-02-28 11:55 ` [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support Mohit Kumar
2014-03-14 6:01 ` Jingoo Han
@ 2014-04-04 16:42 ` Bjorn Helgaas
2014-04-07 5:57 ` Mohit KUMAR DCG
1 sibling, 1 reply; 22+ messages in thread
From: Bjorn Helgaas @ 2014-04-04 16:42 UTC (permalink / raw)
To: Mohit Kumar
Cc: arnd, Pratyush Anand, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
On Fri, Feb 28, 2014 at 05:25:01PM +0530, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
> SPEAr13xx PCIe driver based on designware controller driver.
>
> SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
> with ahci/sata pins. By default evaluation board of both controller
> works for ahci mode.
> To use these patches on SPEAr1340/1310 evaluation board, do the
> necessary modifications on board and enable (okay) pcie and miphy
> from respective evb dtsi file.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
> arch/arm/boot/dts/spear1310.dtsi | 6 +
> arch/arm/boot/dts/spear1340.dtsi | 2 +
> arch/arm/boot/dts/spear13xx.dtsi | 4 +-
> arch/arm/mach-spear/Kconfig | 1 +
> drivers/pci/host/Kconfig | 8 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pcie-spear13xx.c | 414 +++++++++++++++++++++++++++++++++++++
This doesn't apply cleanly to my tree (currently at 4a4389abdd98),
apparently because I don't have some of the ARM DTS stuff. If you want to
split this into a PCI-specific part and an arch/arm part, I can apply the
PCI part. Or you can apply the whole thing via whatever ARM tree makes
sense.
I do have a couple minor comments below. With those addressed, here's my
ACK so you can merge it via another tree if that makes the most sense:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 47d46c6..8697dd1 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -33,4 +33,12 @@ config PCI_RCAR_GEN2
> There are 3 internal PCI controllers available with a single
> built-in EHCI/OHCI host controller present on each one.
>
> +config PCIE_SPEAR13XX
> + tristate "STMicroelectronics SPEAr PCIe controller"
> + depends on ARCH_SPEAR13XX
> + select PCIEPORTBUS
> + select PCIE_DW
> + help
> + Say Y here if you want PCIe support on SPEAr13XX SoCs.
> +
> endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 13fb333..42a491d 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
> obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
> obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
> new file mode 100644
> index 0000000..c70d526
> --- /dev/null
> +++ b/drivers/pci/host/pcie-spear13xx.c
> @@ -0,0 +1,414 @@
> +/*
> + * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
> + *
> + * SPEAr13xx PCIe Glue Layer Source Code
> + *
> + * Copyright (C) 2010-2014 ST Microelectronics
> + * Pratyush Anand <pratyush.anand@st.com>
> + * Mohit Kumar <mohit.kumar@st.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pci.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +
> +#include "pcie-designware.h"
> +
> +struct spear13xx_pcie {
> + void __iomem *app_base;
> + struct phy *phy;
> + struct clk *clk;
> + struct pcie_port pp;
> + bool is_gen1;
> +};
> +
> +struct pcie_app_reg {
> + u32 app_ctrl_0; /*cr0*/
> + u32 app_ctrl_1; /*cr1*/
> + u32 app_status_0; /*cr2*/
> + u32 app_status_1; /*cr3*/
> + u32 msg_status; /*cr4*/
> + u32 msg_payload; /*cr5*/
> + u32 int_sts; /*cr6*/
> + u32 int_clr; /*cr7*/
> + u32 int_mask; /*cr8*/
> + u32 mst_bmisc; /*cr9*/
> + u32 phy_ctrl; /*cr10*/
> + u32 phy_status; /*cr11*/
> + u32 cxpl_debug_info_0; /*cr12*/
> + u32 cxpl_debug_info_1; /*cr13*/
> + u32 ven_msg_ctrl_0; /*cr14*/
> + u32 ven_msg_ctrl_1; /*cr15*/
> + u32 ven_msg_data_0; /*cr16*/
> + u32 ven_msg_data_1; /*cr17*/
> + u32 ven_msi_0; /*cr18*/
> + u32 ven_msi_1; /*cr19*/
> + u32 mst_rmisc; /*cr 20*/
Usually people put a space after "/*" and before "*/" (this applies other
places below, too). But at least make the cr20 comment spacing here
consistent with the other ones above.
> +};
> +
> +/*CR0 ID*/
> +#define RX_LANE_FLIP_EN_ID 0
> +#define TX_LANE_FLIP_EN_ID 1
> +#define SYS_AUX_PWR_DET_ID 2
> +#define APP_LTSSM_ENABLE_ID 3
> +#define SYS_ATTEN_BUTTON_PRESSED_ID 4
> +#define SYS_MRL_SENSOR_STATE_ID 5
> +#define SYS_PWR_FAULT_DET_ID 6
> +#define SYS_MRL_SENSOR_CHGED_ID 7
> +#define SYS_PRE_DET_CHGED_ID 8
> +#define SYS_CMD_CPLED_INT_ID 9
> +#define APP_INIT_RST_0_ID 11
> +#define APP_REQ_ENTR_L1_ID 12
> +#define APP_READY_ENTR_L23_ID 13
> +#define APP_REQ_EXIT_L1_ID 14
> +#define DEVICE_TYPE_EP (0 << 25)
> +#define DEVICE_TYPE_LEP (1 << 25)
> +#define DEVICE_TYPE_RC (4 << 25)
> +#define SYS_INT_ID 29
> +#define MISCTRL_EN_ID 30
> +#define REG_TRANSLATION_ENABLE 31
Many of these symbols are defined but never used. Personally, I would just
define the things you use, since they've presumably gotten at least some
testing. Then the list is a clue to the reader about what features the
driver supports, and you can add others when you add more features. I
think they're more likely to get reviewed and tested then. But not a big
deal either way.
> +/*CR1 ID*/
> +#define APPS_PM_XMT_TURNOFF_ID 2
> +#define APPS_PM_XMT_PME_ID 5
> +
> +/*CR3 ID*/
> +#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
> +#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
> +#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
> +#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
> +#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
> +#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
> +#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
> +#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
> +#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
> +#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
> +#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
> +#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
> +#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
> +#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
> +#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
> +#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
> +#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
> +#define XMLH_LTSSM_STATE_L0 0x11
> +#define XMLH_LTSSM_STATE_L0S 0x12
> +#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
> +#define XMLH_LTSSM_STATE_L1_IDLE 0x14
> +#define XMLH_LTSSM_STATE_L2_IDLE 0x15
> +#define XMLH_LTSSM_STATE_L2_WAKE 0x16
> +#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
> +#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
> +#define XMLH_LTSSM_STATE_DISABLED 0x19
> +#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
> +#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
> +#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
> +#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
> +#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
> +#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
> +#define XMLH_LTSSM_STATE_MASK 0x3F
> +#define XMLH_LINK_UP (1 << 6)
> +
> +/*CR4 ID*/
> +#define CFG_MSI_EN_ID 18
> +
> +/*CR6*/
> +#define INTA_CTRL_INT (1 << 7)
> +#define INTB_CTRL_INT (1 << 8)
> +#define INTC_CTRL_INT (1 << 9)
> +#define INTD_CTRL_INT (1 << 10)
> +#define MSI_CTRL_INT (1 << 26)
> +
> +/*CR19 ID*/
> +#define VEN_MSI_REQ_ID 11
> +#define VEN_MSI_FUN_NUM_ID 8
> +#define VEN_MSI_TC_ID 5
> +#define VEN_MSI_VECTOR_ID 0
> +#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
> +#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
> +#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
> +#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
> +
> +#define PCI_CAP_ID_EXP_OFFSET 0x70
> +
> +#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
> +
> +static int spear13xx_pcie_establish_link(struct pcie_port *pp)
> +{
> + u32 val;
> + int count = 0;
> + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> + u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
> +
> + if (dw_pcie_link_up(pp)) {
> + dev_err(pp->dev, "Link already up\n");
Most of your messages start with lowercase; it'd be nice to be consistent.
> + return 0;
> + }
> +
> + /* setup root complex */
Superfluous comment.
> + dw_pcie_setup_rc(pp);
> +
> + /*
> + * this controller support only 128 bytes read size, however its
> + * default value in capability register is 512 bytes. So force
> + * it to 128 here.
> + */
> + dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
> + val &= ~PCI_EXP_DEVCTL_READRQ;
> + dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
> +
> + /* program vid and did for RC */
Superfluous comment.
> + dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
> + dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
> +
> + /*
> + * if is_gen1 is set then handle it, so that some buggy card
> + * also works
> + */
> + if (spear13xx_pcie->is_gen1) {
> + dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
> + &val);
> + if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
> + val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> + val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> + dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> + PCI_EXP_LNKCAP, 4, val);
> + }
> +
> + dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
> + &val);
> + if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
> + val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> + val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> + dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> + PCI_EXP_LNKCTL2, 4, val);
> + }
> + }
> +
> + /* enable ltssm */
> + writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
> + | (1 << APP_LTSSM_ENABLE_ID)
> + | ((u32)1 << REG_TRANSLATION_ENABLE),
> + &app_reg->app_ctrl_0);
> +
> + /* check if the link is up or not */
> + while (!dw_pcie_link_up(pp)) {
> + mdelay(100);
> + count++;
> + if (count == 10) {
> + dev_err(pp->dev, "Link Fail\n");
> + return -EINVAL;
> + }
> + }
> + dev_info(pp->dev, "Link up\n");
> +
> + return 0;
> +}
> +
> +static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
> +{
> + struct pcie_port *pp = arg;
> + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> + unsigned int status;
> +
> + status = readl(&app_reg->int_sts);
> +
> + if (status & MSI_CTRL_INT) {
> + if (!IS_ENABLED(CONFIG_PCI_MSI))
> + BUG();
> + dw_handle_msi_irq(pp);
> + }
> +
> + writel(status, &app_reg->int_clr);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
> +{
> + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> +
> + /* Enable MSI interrupt */
> + if (IS_ENABLED(CONFIG_PCI_MSI)) {
> + dw_pcie_msi_init(pp);
> + writel(readl(&app_reg->int_mask) |
> + MSI_CTRL_INT, &app_reg->int_mask);
> + }
> +
> + return;
Superfluous "return".
> +}
> +
> +static int spear13xx_pcie_link_up(struct pcie_port *pp)
> +{
> + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> +
> + if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
> + return 1;
> +
> + return 0;
> +}
> +
> +static void spear13xx_pcie_host_init(struct pcie_port *pp)
> +{
> + spear13xx_pcie_establish_link(pp);
> + spear13xx_pcie_enable_interrupts(pp);
> +}
> +
> +static struct pcie_host_ops spear13xx_pcie_host_ops = {
> + .link_up = spear13xx_pcie_link_up,
> + .host_init = spear13xx_pcie_host_init,
> +};
> +
> +static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + pp->irq = platform_get_irq(pdev, 0);
> + if (!pp->irq) {
> + dev_err(dev, "failed to get irq\n");
> + return -ENODEV;
> + }
> + ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
> + IRQF_SHARED, "spear1340-pcie", pp);
> + if (ret) {
> + dev_err(dev, "failed to request irq\n");
Please include the IRQ number in this message.
> + return ret;
> + }
> +
> + pp->root_bus_nr = -1;
> + pp->ops = &spear13xx_pcie_host_ops;
> +
> + spin_lock_init(&pp->conf_lock);
> + ret = dw_pcie_host_init(pp);
> + if (ret) {
> + dev_err(dev, "failed to initialize host\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int __init spear13xx_pcie_probe(struct platform_device *pdev)
> +{
> + struct spear13xx_pcie *spear13xx_pcie;
> + struct pcie_port *pp;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = pdev->dev.of_node;
> + struct resource *dbi_base;
> + int ret;
> +
> + spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
> + GFP_KERNEL);
> + if (!spear13xx_pcie) {
> + dev_err(dev, "no memory for SPEAr13xx pcie\n");
> + return -ENOMEM;
> + }
> +
> + spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> + if (IS_ERR(spear13xx_pcie->phy)) {
> + ret = PTR_ERR(spear13xx_pcie->phy);
> + switch (ret) {
> + case -EPROBE_DEFER:
> + dev_info(dev, "probe deferred\n");
> + return ret;
> + default:
> + dev_err(dev, "couldn't get pcie-phy\n");
> + return ret;
> + }
This would be slightly simpler (your choice):
if (ret == -EPROBE_DEFER)
dev_info(...)
else
dev_err(...)
return ret;
> + }
> +
> + phy_init(spear13xx_pcie->phy);
> +
> + spear13xx_pcie->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(spear13xx_pcie->clk)) {
> + dev_err(dev, "couldn't get clk for pcie\n");
> + return PTR_ERR(spear13xx_pcie->clk);
> + }
> + ret = clk_prepare_enable(spear13xx_pcie->clk);
> + if (ret) {
> + dev_err(dev, "couldn't enable clk for pcie\n");
> + return ret;
> + }
> +
> + pp = &spear13xx_pcie->pp;
> +
> + pp->dev = dev;
> +
> + dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
> + if (IS_ERR(pp->dbi_base)) {
> + dev_err(dev, "couldn't remap dbi base\n");
Please include the dbi_base address in the message.
> + ret = PTR_ERR(pp->dbi_base);
> + goto fail_clk;
> + }
> + spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
> +
> + if (of_property_read_bool(np, "st,pcie-is-gen1"))
> + spear13xx_pcie->is_gen1 = true;
> +
> + ret = add_pcie_port(pp, pdev);
> + if (ret < 0)
> + goto fail_clk;
> +
> + platform_set_drvdata(pdev, spear13xx_pcie);
> + return 0;
> +
> +fail_clk:
> + clk_disable_unprepare(spear13xx_pcie->clk);
> +
> + return ret;
> +}
> +
> +static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
> +{
> + struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
> +
> + clk_disable_unprepare(spear13xx_pcie->clk);
> +
> + phy_exit(spear13xx_pcie->phy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id spear13xx_pcie_of_match[] = {
> + { .compatible = "st,spear1340-pcie", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
> +
> +static struct platform_driver spear13xx_pcie_driver = {
> + .probe = spear13xx_pcie_probe,
> + .remove = spear13xx_pcie_remove,
> + .driver = {
> + .name = "spear-pcie",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
> + },
> +};
> +
> +/* SPEAr13xx PCIe driver does not allow module unload */
> +
> +static int __init pcie_init(void)
> +{
> + return platform_driver_register(&spear13xx_pcie_driver);
> +}
> +module_init(pcie_init);
> +
> +MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
> +MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 1.7.0.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
2014-02-28 11:55 ` [PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
@ 2014-04-04 16:44 ` Bjorn Helgaas
0 siblings, 0 replies; 22+ messages in thread
From: Bjorn Helgaas @ 2014-04-04 16:44 UTC (permalink / raw)
To: Mohit Kumar; +Cc: arnd, Pratyush Anand, linux-pci
On Fri, Feb 28, 2014 at 05:25:03PM +0530, Mohit Kumar wrote:
> Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Acked-by: Jingoo Han <jg1.han@samsung.com>
> Cc: linux-pci@vger.kernel.org
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Please merge this along with the drivers/pci/host/pcie-spear13xx.c patch.
> ---
> MAINTAINERS | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b2cf5cf..ebdca89 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6596,6 +6596,12 @@ L: linux-pci@vger.kernel.org
> S: Maintained
> F: drivers/pci/host/*designware*
>
> +PCIE DRIVER FOR ST SPEAR13XX
> +M: Mohit Kumar <mohit.kumar@st.com>
> +L: linux-pci@vger.kernel.org
> +S: Maintained
> +F: drivers/pci/host/pcie-spear13xx.c
> +
> PCMCIA SUBSYSTEM
> P: Linux PCMCIA Team
> L: linux-pcmcia@lists.infradead.org
> --
> 1.7.0.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support
2014-04-04 16:42 ` Bjorn Helgaas
@ 2014-04-07 5:57 ` Mohit KUMAR DCG
0 siblings, 0 replies; 22+ messages in thread
From: Mohit KUMAR DCG @ 2014-04-07 5:57 UTC (permalink / raw)
To: Bjorn Helgaas, arnd
Cc: arnd, Pratyush ANAND, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
Hello Bjorn,
> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> Sent: Friday, April 04, 2014 10:13 PM
> To: Mohit KUMAR DCG
> Cc: arnd@arndb.de; Pratyush ANAND; Jingoo Han; Viresh Kumar; spear-
> devel; linux-pci@vger.kernel.org
> Subject: Re: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper
> support
>
> On Fri, Feb 28, 2014 at 05:25:01PM +0530, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
> > SPEAr13xx PCIe driver based on designware controller driver.
> >
> > SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
> > with ahci/sata pins. By default evaluation board of both controller
> > works for ahci mode.
> > To use these patches on SPEAr1340/1310 evaluation board, do the
> > necessary modifications on board and enable (okay) pcie and miphy from
> > respective evb dtsi file.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-pci@vger.kernel.org
> > ---
> > arch/arm/boot/dts/spear1310.dtsi | 6 +
> > arch/arm/boot/dts/spear1340.dtsi | 2 +
> > arch/arm/boot/dts/spear13xx.dtsi | 4 +-
> > arch/arm/mach-spear/Kconfig | 1 +
> > drivers/pci/host/Kconfig | 8 +
> > drivers/pci/host/Makefile | 1 +
> > drivers/pci/host/pcie-spear13xx.c | 414
> > +++++++++++++++++++++++++++++++++++++
>
> This doesn't apply cleanly to my tree (currently at 4a4389abdd98), apparently
> because I don't have some of the ARM DTS stuff. If you want to split this into
> a PCI-specific part and an arch/arm part, I can apply the PCI part. Or you can
> apply the whole thing via whatever ARM tree makes sense.
>
Arnd,
Pls comment if it can be taken care by you if I resend after rebasing it to your tree?
> I do have a couple minor comments below. With those addressed, here's my
> ACK so you can merge it via another tree if that makes the most sense:
>
- Thanks for your review and comments. I will incorporate these in my resend patch.
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>
Thanks
Mohit
> > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index
> > 47d46c6..8697dd1 100644
> > --- a/drivers/pci/host/Kconfig
> > +++ b/drivers/pci/host/Kconfig
> > @@ -33,4 +33,12 @@ config PCI_RCAR_GEN2
> > There are 3 internal PCI controllers available with a single
> > built-in EHCI/OHCI host controller present on each one.
> >
> > +config PCIE_SPEAR13XX
> > + tristate "STMicroelectronics SPEAr PCIe controller"
> > + depends on ARCH_SPEAR13XX
> > + select PCIEPORTBUS
> > + select PCIE_DW
> > + help
> > + Say Y here if you want PCIe support on SPEAr13XX SoCs.
> > +
> > endmenu
> > diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> > index 13fb333..42a491d 100644
> > --- a/drivers/pci/host/Makefile
> > +++ b/drivers/pci/host/Makefile
> > @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> > obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
> > obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
> > obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> > +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> > diff --git a/drivers/pci/host/pcie-spear13xx.c
> > b/drivers/pci/host/pcie-spear13xx.c
> > new file mode 100644
> > index 0000000..c70d526
> > --- /dev/null
> > +++ b/drivers/pci/host/pcie-spear13xx.c
> > @@ -0,0 +1,414 @@
> > +/*
> > + * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
> > + *
> > + * SPEAr13xx PCIe Glue Layer Source Code
> > + *
> > + * Copyright (C) 2010-2014 ST Microelectronics
> > + * Pratyush Anand <pratyush.anand@st.com>
> > + * Mohit Kumar <mohit.kumar@st.com>
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/pci.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +
> > +#include "pcie-designware.h"
> > +
> > +struct spear13xx_pcie {
> > + void __iomem *app_base;
> > + struct phy *phy;
> > + struct clk *clk;
> > + struct pcie_port pp;
> > + bool is_gen1;
> > +};
> > +
> > +struct pcie_app_reg {
> > + u32 app_ctrl_0; /*cr0*/
> > + u32 app_ctrl_1; /*cr1*/
> > + u32 app_status_0; /*cr2*/
> > + u32 app_status_1; /*cr3*/
> > + u32 msg_status; /*cr4*/
> > + u32 msg_payload; /*cr5*/
> > + u32 int_sts; /*cr6*/
> > + u32 int_clr; /*cr7*/
> > + u32 int_mask; /*cr8*/
> > + u32 mst_bmisc; /*cr9*/
> > + u32 phy_ctrl; /*cr10*/
> > + u32 phy_status; /*cr11*/
> > + u32 cxpl_debug_info_0; /*cr12*/
> > + u32 cxpl_debug_info_1; /*cr13*/
> > + u32 ven_msg_ctrl_0; /*cr14*/
> > + u32 ven_msg_ctrl_1; /*cr15*/
> > + u32 ven_msg_data_0; /*cr16*/
> > + u32 ven_msg_data_1; /*cr17*/
> > + u32 ven_msi_0; /*cr18*/
> > + u32 ven_msi_1; /*cr19*/
> > + u32 mst_rmisc; /*cr 20*/
>
> Usually people put a space after "/*" and before "*/" (this applies other
> places below, too). But at least make the cr20 comment spacing here
> consistent with the other ones above.
>
> > +};
> > +
> > +/*CR0 ID*/
> > +#define RX_LANE_FLIP_EN_ID 0
> > +#define TX_LANE_FLIP_EN_ID 1
> > +#define SYS_AUX_PWR_DET_ID 2
> > +#define APP_LTSSM_ENABLE_ID 3
> > +#define SYS_ATTEN_BUTTON_PRESSED_ID 4
> > +#define SYS_MRL_SENSOR_STATE_ID 5
> > +#define SYS_PWR_FAULT_DET_ID 6
> > +#define SYS_MRL_SENSOR_CHGED_ID 7
> > +#define SYS_PRE_DET_CHGED_ID 8
> > +#define SYS_CMD_CPLED_INT_ID 9
> > +#define APP_INIT_RST_0_ID 11
> > +#define APP_REQ_ENTR_L1_ID 12
> > +#define APP_READY_ENTR_L23_ID 13
> > +#define APP_REQ_EXIT_L1_ID 14
> > +#define DEVICE_TYPE_EP (0 << 25)
> > +#define DEVICE_TYPE_LEP (1 << 25)
> > +#define DEVICE_TYPE_RC (4 << 25)
> > +#define SYS_INT_ID 29
> > +#define MISCTRL_EN_ID 30
> > +#define REG_TRANSLATION_ENABLE 31
>
> Many of these symbols are defined but never used. Personally, I would just
> define the things you use, since they've presumably gotten at least some
> testing. Then the list is a clue to the reader about what features the driver
> supports, and you can add others when you add more features. I think
> they're more likely to get reviewed and tested then. But not a big deal either
> way.
>
> > +/*CR1 ID*/
> > +#define APPS_PM_XMT_TURNOFF_ID 2
> > +#define APPS_PM_XMT_PME_ID 5
> > +
> > +/*CR3 ID*/
> > +#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
> > +#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
> > +#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
> > +#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
> > +#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
> > +#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
> > +#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
> > +#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
> > +#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
> > +#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
> > +#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
> > +#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
> > +#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
> > +#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
> > +#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
> > +#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
> > +#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
> > +#define XMLH_LTSSM_STATE_L0 0x11
> > +#define XMLH_LTSSM_STATE_L0S 0x12
> > +#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
> > +#define XMLH_LTSSM_STATE_L1_IDLE 0x14
> > +#define XMLH_LTSSM_STATE_L2_IDLE 0x15
> > +#define XMLH_LTSSM_STATE_L2_WAKE 0x16
> > +#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
> > +#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
> > +#define XMLH_LTSSM_STATE_DISABLED 0x19
> > +#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
> > +#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
> > +#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
> > +#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
> > +#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
> > +#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
> > +#define XMLH_LTSSM_STATE_MASK 0x3F
> > +#define XMLH_LINK_UP (1 << 6)
> > +
> > +/*CR4 ID*/
> > +#define CFG_MSI_EN_ID 18
> > +
> > +/*CR6*/
> > +#define INTA_CTRL_INT (1 << 7)
> > +#define INTB_CTRL_INT (1 << 8)
> > +#define INTC_CTRL_INT (1 << 9)
> > +#define INTD_CTRL_INT (1 << 10)
> > +#define MSI_CTRL_INT (1 << 26)
> > +
> > +/*CR19 ID*/
> > +#define VEN_MSI_REQ_ID 11
> > +#define VEN_MSI_FUN_NUM_ID 8
> > +#define VEN_MSI_TC_ID 5
> > +#define VEN_MSI_VECTOR_ID 0
> > +#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
> > +#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 <<
> VEN_MSI_FUN_NUM_ID)
> > +#define VEN_MSI_TC_MASK ((u32)0x7 <<
> VEN_MSI_TC_ID)
> > +#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
> > +
> > +#define PCI_CAP_ID_EXP_OFFSET 0x70
> > +
> > +#define to_spear13xx_pcie(x) container_of(x, struct
> spear13xx_pcie, pp)
> > +
> > +static int spear13xx_pcie_establish_link(struct pcie_port *pp) {
> > + u32 val;
> > + int count = 0;
> > + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > + u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
> > +
> > + if (dw_pcie_link_up(pp)) {
> > + dev_err(pp->dev, "Link already up\n");
>
> Most of your messages start with lowercase; it'd be nice to be consistent.
>
> > + return 0;
> > + }
> > +
> > + /* setup root complex */
>
> Superfluous comment.
>
> > + dw_pcie_setup_rc(pp);
> > +
> > + /*
> > + * this controller support only 128 bytes read size, however its
> > + * default value in capability register is 512 bytes. So force
> > + * it to 128 here.
> > + */
> > + dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL,
> 4, &val);
> > + val &= ~PCI_EXP_DEVCTL_READRQ;
> > + dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL,
> 4,
> > +val);
> > +
> > + /* program vid and did for RC */
>
> Superfluous comment.
>
> > + dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
> > + dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
> > +
> > + /*
> > + * if is_gen1 is set then handle it, so that some buggy card
> > + * also works
> > + */
> > + if (spear13xx_pcie->is_gen1) {
> > + dw_pcie_cfg_read(pp->dbi_base, exp_cap_off +
> PCI_EXP_LNKCAP, 4,
> > + &val);
> > + if ((val & PCI_EXP_LNKCAP_SLS) !=
> PCI_EXP_LNKCAP_SLS_2_5GB) {
> > + val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> > + val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> > + dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> > + PCI_EXP_LNKCAP, 4, val);
> > + }
> > +
> > + dw_pcie_cfg_read(pp->dbi_base, exp_cap_off +
> PCI_EXP_LNKCTL2, 4,
> > + &val);
> > + if ((val & PCI_EXP_LNKCAP_SLS) !=
> PCI_EXP_LNKCAP_SLS_2_5GB) {
> > + val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> > + val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> > + dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> > + PCI_EXP_LNKCTL2, 4, val);
> > + }
> > + }
> > +
> > + /* enable ltssm */
> > + writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
> > + | (1 << APP_LTSSM_ENABLE_ID)
> > + | ((u32)1 << REG_TRANSLATION_ENABLE),
> > + &app_reg->app_ctrl_0);
> > +
> > + /* check if the link is up or not */
> > + while (!dw_pcie_link_up(pp)) {
> > + mdelay(100);
> > + count++;
> > + if (count == 10) {
> > + dev_err(pp->dev, "Link Fail\n");
> > + return -EINVAL;
> > + }
> > + }
> > + dev_info(pp->dev, "Link up\n");
> > +
> > + return 0;
> > +}
> > +
> > +static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) {
> > + struct pcie_port *pp = arg;
> > + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > + unsigned int status;
> > +
> > + status = readl(&app_reg->int_sts);
> > +
> > + if (status & MSI_CTRL_INT) {
> > + if (!IS_ENABLED(CONFIG_PCI_MSI))
> > + BUG();
> > + dw_handle_msi_irq(pp);
> > + }
> > +
> > + writel(status, &app_reg->int_clr);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp) {
> > + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > +
> > + /* Enable MSI interrupt */
> > + if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > + dw_pcie_msi_init(pp);
> > + writel(readl(&app_reg->int_mask) |
> > + MSI_CTRL_INT, &app_reg->int_mask);
> > + }
> > +
> > + return;
>
> Superfluous "return".
>
> > +}
> > +
> > +static int spear13xx_pcie_link_up(struct pcie_port *pp) {
> > + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > +
> > + if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
> > + return 1;
> > +
> > + return 0;
> > +}
> > +
> > +static void spear13xx_pcie_host_init(struct pcie_port *pp) {
> > + spear13xx_pcie_establish_link(pp);
> > + spear13xx_pcie_enable_interrupts(pp);
> > +}
> > +
> > +static struct pcie_host_ops spear13xx_pcie_host_ops = {
> > + .link_up = spear13xx_pcie_link_up,
> > + .host_init = spear13xx_pcie_host_init, };
> > +
> > +static int add_pcie_port(struct pcie_port *pp, struct platform_device
> > +*pdev) {
> > + struct device *dev = &pdev->dev;
> > + int ret;
> > +
> > + pp->irq = platform_get_irq(pdev, 0);
> > + if (!pp->irq) {
> > + dev_err(dev, "failed to get irq\n");
> > + return -ENODEV;
> > + }
> > + ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
> > + IRQF_SHARED, "spear1340-pcie", pp);
> > + if (ret) {
> > + dev_err(dev, "failed to request irq\n");
>
> Please include the IRQ number in this message.
>
> > + return ret;
> > + }
> > +
> > + pp->root_bus_nr = -1;
> > + pp->ops = &spear13xx_pcie_host_ops;
> > +
> > + spin_lock_init(&pp->conf_lock);
> > + ret = dw_pcie_host_init(pp);
> > + if (ret) {
> > + dev_err(dev, "failed to initialize host\n");
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int __init spear13xx_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct spear13xx_pcie *spear13xx_pcie;
> > + struct pcie_port *pp;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = pdev->dev.of_node;
> > + struct resource *dbi_base;
> > + int ret;
> > +
> > + spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
> > + GFP_KERNEL);
> > + if (!spear13xx_pcie) {
> > + dev_err(dev, "no memory for SPEAr13xx pcie\n");
> > + return -ENOMEM;
> > + }
> > +
> > + spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> > + if (IS_ERR(spear13xx_pcie->phy)) {
> > + ret = PTR_ERR(spear13xx_pcie->phy);
> > + switch (ret) {
> > + case -EPROBE_DEFER:
> > + dev_info(dev, "probe deferred\n");
> > + return ret;
> > + default:
> > + dev_err(dev, "couldn't get pcie-phy\n");
> > + return ret;
> > + }
>
> This would be slightly simpler (your choice):
>
> if (ret == -EPROBE_DEFER)
> dev_info(...)
> else
> dev_err(...)
> return ret;
>
> > + }
> > +
> > + phy_init(spear13xx_pcie->phy);
> > +
> > + spear13xx_pcie->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(spear13xx_pcie->clk)) {
> > + dev_err(dev, "couldn't get clk for pcie\n");
> > + return PTR_ERR(spear13xx_pcie->clk);
> > + }
> > + ret = clk_prepare_enable(spear13xx_pcie->clk);
> > + if (ret) {
> > + dev_err(dev, "couldn't enable clk for pcie\n");
> > + return ret;
> > + }
> > +
> > + pp = &spear13xx_pcie->pp;
> > +
> > + pp->dev = dev;
> > +
> > + dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
> > + if (IS_ERR(pp->dbi_base)) {
> > + dev_err(dev, "couldn't remap dbi base\n");
>
> Please include the dbi_base address in the message.
>
> > + ret = PTR_ERR(pp->dbi_base);
> > + goto fail_clk;
> > + }
> > + spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
> > +
> > + if (of_property_read_bool(np, "st,pcie-is-gen1"))
> > + spear13xx_pcie->is_gen1 = true;
> > +
> > + ret = add_pcie_port(pp, pdev);
> > + if (ret < 0)
> > + goto fail_clk;
> > +
> > + platform_set_drvdata(pdev, spear13xx_pcie);
> > + return 0;
> > +
> > +fail_clk:
> > + clk_disable_unprepare(spear13xx_pcie->clk);
> > +
> > + return ret;
> > +}
> > +
> > +static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
> > +{
> > + struct spear13xx_pcie *spear13xx_pcie =
> platform_get_drvdata(pdev);
> > +
> > + clk_disable_unprepare(spear13xx_pcie->clk);
> > +
> > + phy_exit(spear13xx_pcie->phy);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id spear13xx_pcie_of_match[] = {
> > + { .compatible = "st,spear1340-pcie", },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
> > +
> > +static struct platform_driver spear13xx_pcie_driver = {
> > + .probe = spear13xx_pcie_probe,
> > + .remove = spear13xx_pcie_remove,
> > + .driver = {
> > + .name = "spear-pcie",
> > + .owner = THIS_MODULE,
> > + .of_match_table =
> of_match_ptr(spear13xx_pcie_of_match),
> > + },
> > +};
> > +
> > +/* SPEAr13xx PCIe driver does not allow module unload */
> > +
> > +static int __init pcie_init(void)
> > +{
> > + return platform_driver_register(&spear13xx_pcie_driver);
> > +}
> > +module_init(pcie_init);
> > +
> > +MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host
> > +controller driver"); MODULE_AUTHOR("Pratyush Anand
> > +<pratyush.anand@st.com>"); MODULE_LICENSE("GPL v2");
> > --
> > 1.7.0.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci"
> > in the body of a message to majordomo@vger.kernel.org More
> majordomo
> > info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2014-04-07 5:57 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <cover.1393568715.git.mohit.kumar@st.com>
2014-02-28 11:54 ` [PATCH V7 01/10] clk: SPEAr13XX: Fix pcie clock name Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 02/10] SPEAr13XX: Fix static mapping table Mohit Kumar
[not found] ` <cover.1393568715.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
2014-02-28 11:54 ` [PATCH V7 03/10] phy: SPEAr1310/40-miphy: Add binding information Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 04/10] SPEAr: misc: " Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 06/10] SPEAr13XX: Add binding information for PCIe controller Mohit Kumar
2014-02-28 11:54 ` [PATCH V7 05/10] phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA Mohit Kumar
2014-02-28 11:55 ` [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support Mohit Kumar
2014-03-14 6:01 ` Jingoo Han
2014-03-14 11:09 ` Mohit KUMAR DCG
2014-04-04 16:42 ` Bjorn Helgaas
2014-04-07 5:57 ` Mohit KUMAR DCG
2014-02-28 11:55 ` [PATCH V7 09/10] SPEAr13xx: defconfig: Update Mohit Kumar
2014-02-28 11:55 ` [PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
2014-04-04 16:44 ` Bjorn Helgaas
2014-03-04 5:41 ` [PATCH V7 07/10 resend] SPEAr13XX: dts: Add PCIe node information Mohit Kumar
2014-02-28 11:58 ` [PATCH V7 07/10] " Arnd Bergmann
2014-03-03 4:45 ` Mohit KUMAR DCG
2014-03-14 10:34 ` Arnd Bergmann
2014-03-14 11:08 ` Mohit KUMAR DCG
2014-03-24 3:57 ` Mohit KUMAR DCG
[not found] ` <2CC2A0A4A178534D93D5159BF3BCB66189FEB12EE3@EAPEX1MAIL1.st.com>
[not found] ` <CAErSpo6vAdXV+ObZNySiQjs-x3_TxEiYLG2ZPscmHVGVspE55w@mail.gmail.com>
[not found] ` <CAAxdfz_pJ3HbKTQmAyFSM1Z+hu=31OOdQCdvdd3Nu_rpr_vC7g@mail.gmail.com>
[not found] ` <CAErSpo4pr5GC65pphxDUJGfep+yY06C8+RBmhygJPPQ7O5CD_g@mail.gmail.com>
2014-03-31 5:25 ` [PATCH V7 00/10] PCI: Add SPEAr13xx PCie support Mohit KUMAR DCG
2014-03-31 5:25 ` Mohit KUMAR DCG
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