* [PATCH 0/2] ARM: dts: at91: sama7g5: fixes for sama7g5
@ 2021-09-15 7:48 ` Claudiu Beznea
0 siblings, 0 replies; 8+ messages in thread
From: Claudiu Beznea @ 2021-09-15 7:48 UTC (permalink / raw)
To: nicolas.ferre, alexandre.belloni, ludovic.desroches, robh+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, Claudiu Beznea
Hi,
The following patches fixes slew rate settings for SAMA7G5's GMACs and
SDMMCs.
Thank you,
Claudiu Beznea
Claudiu Beznea (2):
ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
arch/arm/boot/dts/at91-sama7g5ek.dts | 34 +++++++++++++++++++++++-----
1 file changed, 28 insertions(+), 6 deletions(-)
--
2.25.1
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
2021-09-15 7:48 ` Claudiu Beznea
@ 2021-09-15 7:48 ` Claudiu Beznea
-1 siblings, 0 replies; 8+ messages in thread
From: Claudiu Beznea @ 2021-09-15 7:48 UTC (permalink / raw)
To: nicolas.ferre, alexandre.belloni, ludovic.desroches, robh+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, Claudiu Beznea
Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain
GMAC's MDIO pins should be configured with slew-rate enabled, while the
data + signaling pins should be configured with slew-rate disabled when
GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets
the slew-rate as enabled for all pins. Adapt the device tree to comply
with these.
Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 8b13b031a167..0bed8207d498 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -353,7 +353,10 @@ &gmac0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;
+ pinctrl-0 = <&pinctrl_gmac0_default
+ &pinctrl_gmac0_mdio_default
+ &pinctrl_gmac0_txck_default
+ &pinctrl_gmac0_phy_irq>;
phy-mode = "rgmii-id";
status = "okay";
@@ -368,7 +371,9 @@ &gmac1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;
+ pinctrl-0 = <&pinctrl_gmac1_default
+ &pinctrl_gmac1_mdio_default
+ &pinctrl_gmac1_phy_irq>;
phy-mode = "rmii";
status = "okay";
@@ -423,14 +428,20 @@ pinctrl_gmac0_default: gmac0_default {
<PIN_PA15__G0_TXEN>,
<PIN_PA30__G0_RXCK>,
<PIN_PA18__G0_RXDV>,
- <PIN_PA22__G0_MDC>,
- <PIN_PA23__G0_MDIO>,
<PIN_PA25__G0_125CK>;
+ slew-rate = <0>;
+ bias-disable;
+ };
+
+ pinctrl_gmac0_mdio_default: gmac0_mdio_default {
+ pinmux = <PIN_PA22__G0_MDC>,
+ <PIN_PA23__G0_MDIO>;
bias-disable;
};
pinctrl_gmac0_txck_default: gmac0_txck_default {
pinmux = <PIN_PA24__G0_TXCK>;
+ slew-rate = <0>;
bias-pull-up;
};
@@ -447,8 +458,13 @@ pinctrl_gmac1_default: gmac1_default {
<PIN_PD25__G1_RX0>,
<PIN_PD26__G1_RX1>,
<PIN_PD27__G1_RXER>,
- <PIN_PD24__G1_RXDV>,
- <PIN_PD28__G1_MDC>,
+ <PIN_PD24__G1_RXDV>;
+ slew-rate = <0>;
+ bias-disable;
+ };
+
+ pinctrl_gmac1_mdio_default: gmac1_mdio_default {
+ pinmux = <PIN_PD28__G1_MDC>,
<PIN_PD29__G1_MDIO>;
bias-disable;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 1/2] ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
@ 2021-09-15 7:48 ` Claudiu Beznea
0 siblings, 0 replies; 8+ messages in thread
From: Claudiu Beznea @ 2021-09-15 7:48 UTC (permalink / raw)
To: nicolas.ferre, alexandre.belloni, ludovic.desroches, robh+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, Claudiu Beznea
Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain
GMAC's MDIO pins should be configured with slew-rate enabled, while the
data + signaling pins should be configured with slew-rate disabled when
GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets
the slew-rate as enabled for all pins. Adapt the device tree to comply
with these.
Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 8b13b031a167..0bed8207d498 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -353,7 +353,10 @@ &gmac0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;
+ pinctrl-0 = <&pinctrl_gmac0_default
+ &pinctrl_gmac0_mdio_default
+ &pinctrl_gmac0_txck_default
+ &pinctrl_gmac0_phy_irq>;
phy-mode = "rgmii-id";
status = "okay";
@@ -368,7 +371,9 @@ &gmac1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;
+ pinctrl-0 = <&pinctrl_gmac1_default
+ &pinctrl_gmac1_mdio_default
+ &pinctrl_gmac1_phy_irq>;
phy-mode = "rmii";
status = "okay";
@@ -423,14 +428,20 @@ pinctrl_gmac0_default: gmac0_default {
<PIN_PA15__G0_TXEN>,
<PIN_PA30__G0_RXCK>,
<PIN_PA18__G0_RXDV>,
- <PIN_PA22__G0_MDC>,
- <PIN_PA23__G0_MDIO>,
<PIN_PA25__G0_125CK>;
+ slew-rate = <0>;
+ bias-disable;
+ };
+
+ pinctrl_gmac0_mdio_default: gmac0_mdio_default {
+ pinmux = <PIN_PA22__G0_MDC>,
+ <PIN_PA23__G0_MDIO>;
bias-disable;
};
pinctrl_gmac0_txck_default: gmac0_txck_default {
pinmux = <PIN_PA24__G0_TXCK>;
+ slew-rate = <0>;
bias-pull-up;
};
@@ -447,8 +458,13 @@ pinctrl_gmac1_default: gmac1_default {
<PIN_PD25__G1_RX0>,
<PIN_PD26__G1_RX1>,
<PIN_PD27__G1_RXER>,
- <PIN_PD24__G1_RXDV>,
- <PIN_PD28__G1_MDC>,
+ <PIN_PD24__G1_RXDV>;
+ slew-rate = <0>;
+ bias-disable;
+ };
+
+ pinctrl_gmac1_mdio_default: gmac1_mdio_default {
+ pinmux = <PIN_PD28__G1_MDC>,
<PIN_PD29__G1_MDIO>;
bias-disable;
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
2021-09-15 7:48 ` Claudiu Beznea
@ 2021-09-15 7:48 ` Claudiu Beznea
-1 siblings, 0 replies; 8+ messages in thread
From: Claudiu Beznea @ 2021-09-15 7:48 UTC (permalink / raw)
To: nicolas.ferre, alexandre.belloni, ludovic.desroches, robh+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, Claudiu Beznea
With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate")
and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement")
the slew-rate is enabled by default for each configured pin. The datasheet
specifies at chapter "Output Driver AC Characteristics" that HSIO
drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate
setting but are rather calibrated against an external 1% resistor mounted
on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal
frequency and the external load, it is possible to adjust their target
output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled
at the moment in device tree).
Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 0bed8207d498..624162fec223 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -556,6 +556,7 @@ cmd_data {
<PIN_PA8__SDMMC0_DAT5>,
<PIN_PA9__SDMMC0_DAT6>,
<PIN_PA10__SDMMC0_DAT7>;
+ slew-rate = <0>;
bias-pull-up;
};
@@ -563,6 +564,7 @@ ck_cd_rstn_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA11__SDMMC0_DS>;
+ slew-rate = <0>;
bias-pull-up;
};
};
@@ -574,6 +576,7 @@ cmd_data {
<PIN_PC0__SDMMC1_DAT1>,
<PIN_PC1__SDMMC1_DAT2>,
<PIN_PC2__SDMMC1_DAT3>;
+ slew-rate = <0>;
bias-pull-up;
};
@@ -582,6 +585,7 @@ ck_cd_rstn_vddsel {
<PIN_PB28__SDMMC1_RSTN>,
<PIN_PC5__SDMMC1_1V8SEL>,
<PIN_PC4__SDMMC1_CD>;
+ slew-rate = <0>;
bias-pull-up;
};
};
@@ -593,11 +597,13 @@ cmd_data {
<PIN_PD6__SDMMC2_DAT1>,
<PIN_PD7__SDMMC2_DAT2>,
<PIN_PD8__SDMMC2_DAT3>;
+ slew-rate = <0>;
bias-pull-up;
};
ck {
pinmux = <PIN_PD4__SDMMC2_CK>;
+ slew-rate = <0>;
bias-pull-up;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
@ 2021-09-15 7:48 ` Claudiu Beznea
0 siblings, 0 replies; 8+ messages in thread
From: Claudiu Beznea @ 2021-09-15 7:48 UTC (permalink / raw)
To: nicolas.ferre, alexandre.belloni, ludovic.desroches, robh+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, Claudiu Beznea
With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate")
and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement")
the slew-rate is enabled by default for each configured pin. The datasheet
specifies at chapter "Output Driver AC Characteristics" that HSIO
drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate
setting but are rather calibrated against an external 1% resistor mounted
on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal
frequency and the external load, it is possible to adjust their target
output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled
at the moment in device tree).
Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 0bed8207d498..624162fec223 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -556,6 +556,7 @@ cmd_data {
<PIN_PA8__SDMMC0_DAT5>,
<PIN_PA9__SDMMC0_DAT6>,
<PIN_PA10__SDMMC0_DAT7>;
+ slew-rate = <0>;
bias-pull-up;
};
@@ -563,6 +564,7 @@ ck_cd_rstn_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA11__SDMMC0_DS>;
+ slew-rate = <0>;
bias-pull-up;
};
};
@@ -574,6 +576,7 @@ cmd_data {
<PIN_PC0__SDMMC1_DAT1>,
<PIN_PC1__SDMMC1_DAT2>,
<PIN_PC2__SDMMC1_DAT3>;
+ slew-rate = <0>;
bias-pull-up;
};
@@ -582,6 +585,7 @@ ck_cd_rstn_vddsel {
<PIN_PB28__SDMMC1_RSTN>,
<PIN_PC5__SDMMC1_1V8SEL>,
<PIN_PC4__SDMMC1_CD>;
+ slew-rate = <0>;
bias-pull-up;
};
};
@@ -593,11 +597,13 @@ cmd_data {
<PIN_PD6__SDMMC2_DAT1>,
<PIN_PD7__SDMMC2_DAT2>,
<PIN_PD8__SDMMC2_DAT3>;
+ slew-rate = <0>;
bias-pull-up;
};
ck {
pinmux = <PIN_PD4__SDMMC2_CK>;
+ slew-rate = <0>;
bias-pull-up;
};
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] ARM: dts: at91: sama7g5: fixes for sama7g5
2021-09-15 7:48 ` Claudiu Beznea
@ 2021-10-04 11:13 ` Nicolas Ferre
-1 siblings, 0 replies; 8+ messages in thread
From: Nicolas Ferre @ 2021-10-04 11:13 UTC (permalink / raw)
To: Claudiu Beznea, alexandre.belloni, ludovic.desroches, robh+dt
Cc: linux-arm-kernel, devicetree, linux-kernel
On 15/09/2021 at 09:48, Claudiu Beznea wrote:
> Hi,
>
> The following patches fixes slew rate settings for SAMA7G5's GMACs and
> SDMMCs.
>
> Thank you,
> Claudiu Beznea
>
> Claudiu Beznea (2):
> ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
> ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
For both of them:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
And queued in at91-fixes for second batch of fixes for 5.15.
Best regards,
Nicolas
> arch/arm/boot/dts/at91-sama7g5ek.dts | 34 +++++++++++++++++++++++-----
> 1 file changed, 28 insertions(+), 6 deletions(-)
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] ARM: dts: at91: sama7g5: fixes for sama7g5
@ 2021-10-04 11:13 ` Nicolas Ferre
0 siblings, 0 replies; 8+ messages in thread
From: Nicolas Ferre @ 2021-10-04 11:13 UTC (permalink / raw)
To: Claudiu Beznea, alexandre.belloni, ludovic.desroches, robh+dt
Cc: linux-arm-kernel, devicetree, linux-kernel
On 15/09/2021 at 09:48, Claudiu Beznea wrote:
> Hi,
>
> The following patches fixes slew rate settings for SAMA7G5's GMACs and
> SDMMCs.
>
> Thank you,
> Claudiu Beznea
>
> Claudiu Beznea (2):
> ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
> ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
For both of them:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
And queued in at91-fixes for second batch of fixes for 5.15.
Best regards,
Nicolas
> arch/arm/boot/dts/at91-sama7g5ek.dts | 34 +++++++++++++++++++++++-----
> 1 file changed, 28 insertions(+), 6 deletions(-)
>
--
Nicolas Ferre
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread