* [RFC 0/7] mkwrite_device_info removal
@ 2018-11-12 17:12 Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 1/7] drm/i915: Remove has_pooled_eu static initializer Tvrtko Ursulin
` (9 more replies)
0 siblings, 10 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Some time ago we discussed the long term goal or removing the
mkwrite_device_info hack in favour of splitting device info to a truly read-only
and runtime halfves. This series attempts to do that.
Approach taken is to identify three classes of device info members:
1. Only set in static const tables.
2. Set in static const tables and modified at runtime.
3. Only set at runtime.
First set is left as is.
Third set is moved from const device_info into a newly created
runtime_device_info and all accessors and use sites are converted to look at the
new location.
Second set is duplicated in both device info structures, but the const copy is
only used to copy over the respective members early on driver load. Otherwise
the process is the same as for the third group.
End result is complete removal of mkwrite_device_info and removal of the
embedded copy of device info stored in dev_priv/i915, which is now replaced
with a pointer to the actual read-only/static const table.
Apart from the conceptual cleanup this has the benefit of making the static
tables smaller since they are duplicated by the amount of platforms. And
dev_priv/i915 is also smaller since it doesn't hold a copy of the whole
device info.
On rough edge however is the copying over of group two members on driver load. I
haven't found a nice automatic way to do it so at the moment it relies on
manually adding lines to i915_driver_create.
Last patch of the series if probably best omitted since I think double
underscore protection actually works well for preventing mistakes in any future
work.
Tvrtko Ursulin (7):
drm/i915: Remove has_pooled_eu static initializer
drm/i915: Introduce runtime device info
drm/i915: Move all runtime modified device info fields into runtime
info
drm/i915: Remove mkwrite_device_info
drm/i915: Move gen and platform mask to runtime device info
drm/i915: Introduce subplatform concept
drm/i915: Remove double underscore from static device info member
names
drivers/gpu/drm/i915/i915_debugfs.c | 31 ++-
drivers/gpu/drm/i915/i915_drv.c | 71 +++++--
drivers/gpu/drm/i915/i915_drv.h | 191 ++++++++----------
drivers/gpu/drm/i915/i915_gem.c | 5 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 19 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 5 +-
drivers/gpu/drm/i915/i915_perf.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 190 ++++++++---------
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 178 +++++++++++-----
drivers/gpu/drm/i915/intel_device_info.h | 82 ++++++--
drivers/gpu/drm/i915/intel_display.c | 20 +-
drivers/gpu/drm/i915/intel_display.h | 10 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 9 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_fbdev.c | 4 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 11 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 +-
drivers/gpu/drm/i915/intel_workarounds.c | 6 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 18 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/selftests/intel_guc.c | 4 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 11 +-
34 files changed, 527 insertions(+), 398 deletions(-)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC 1/7] drm/i915: Remove has_pooled_eu static initializer
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
@ 2018-11-12 17:12 ` Tvrtko Ursulin
2018-11-12 17:29 ` Ville Syrjälä
2018-11-12 17:12 ` [RFC 2/7] drm/i915: Introduce runtime device info Tvrtko Ursulin
` (8 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
It is only initialized to zero once so does not need an explicit
initializer.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4ccab8372dd4..e6e7fcdf0ab7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -507,7 +507,6 @@ static const struct intel_device_info intel_skylake_gt4_info = {
.has_fbc = 1, \
.has_psr = 1, \
.has_runtime_pm = 1, \
- .has_pooled_eu = 0, \
.has_csr = 1, \
.has_rc6 = 1, \
.has_dp_mst = 1, \
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC 2/7] drm/i915: Introduce runtime device info
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 1/7] drm/i915: Remove has_pooled_eu static initializer Tvrtko Ursulin
@ 2018-11-12 17:12 ` Tvrtko Ursulin
2018-11-12 17:36 ` Ville Syrjälä
2018-11-12 17:12 ` [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info Tvrtko Ursulin
` (7 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Idea of runtime device info is to contain all fields from the existing
device info which are modified at runtime.
Initially we move there fields which are never set from the static
tables ie.: num_rings, num_sprites, num_scalers,
cs_timestamp_frequency_khz, sseu and has_pooled_eu.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 27 +++---
drivers/gpu/drm/i915/i915_drv.c | 17 ++--
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 19 +++--
drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 82 +++++++++++--------
drivers/gpu/drm/i915/intel_device_info.h | 42 ++++++----
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_display.h | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 14 ++--
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +-
drivers/gpu/drm/i915/intel_workarounds.c | 6 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +-
19 files changed, 144 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 670db5073d70..1b8a3f203b92 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -48,7 +48,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
intel_device_info_dump_flags(info, &p);
- intel_device_info_dump_runtime(info, &p);
+ intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
intel_driver_caps_print(&dev_priv->caps, &p);
kernel_param_lock(THIS_MODULE);
@@ -3289,7 +3289,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
seq_printf(m, "Global active requests: %d\n",
dev_priv->gt.active_requests);
seq_printf(m, "CS timestamp frequency: %u kHz\n",
- dev_priv->info.cs_timestamp_frequency_khz);
+ dev_priv->runtime_info.cs_timestamp_frequency_khz);
p = drm_seq_file_printer(m);
for_each_engine(engine, dev_priv, id)
@@ -3305,7 +3305,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
+ intel_device_info_dump_topology(&dev_priv->runtime_info.sseu, &p);
return 0;
}
@@ -4341,7 +4341,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
#define SS_MAX 6
- const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
int s, ss;
@@ -4397,7 +4397,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
#define SS_MAX 3
- const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
int s, ss;
@@ -4424,8 +4424,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] =
- INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -4459,10 +4458,10 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->eu_per_subslice =
- INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+ dev_priv->runtime_info.sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++) {
sseu->subslice_mask[s] =
- INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+ dev_priv->runtime_info.sseu.subslice_mask[s];
}
sseu->eu_total = sseu->eu_per_subslice *
sseu_subslice_total(sseu);
@@ -4470,7 +4469,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
u8 subslice_7eu =
- INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
+ dev_priv->runtime_info.sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -4523,14 +4522,14 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &dev_priv->runtime_info.sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
- sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
+ sseu.max_slices = dev_priv->runtime_info.sseu.max_slices;
+ sseu.max_subslices = dev_priv->runtime_info.sseu.max_subslices;
sseu.max_eus_per_subslice =
- INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
+ dev_priv->runtime_info.sseu.max_eus_per_subslice;
intel_runtime_pm_get(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b1d23c73c147..9cfd5b145248 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -357,12 +357,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(&dev_priv->runtime_info.sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = INTEL_INFO(dev_priv)->sseu.eu_total;
+ value = dev_priv->runtime_info.sseu.eu_total;
if (!value)
return -ENODEV;
break;
@@ -379,7 +379,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = dev_priv->runtime_info.sseu.min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(&dev_priv->huc);
@@ -429,17 +429,18 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = INTEL_INFO(dev_priv)->sseu.slice_mask;
+ value = dev_priv->runtime_info.sseu.slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = dev_priv->runtime_info.sseu.subslice_mask[0];
if (!value)
return -ENODEV;
break;
case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
- value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
+ value = 1000 *
+ dev_priv->runtime_info.cs_timestamp_frequency_khz;
break;
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
@@ -1372,7 +1373,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
if (i915_inject_load_failure())
return -ENODEV;
- intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
+ intel_device_info_runtime_init(dev_priv);
if (HAS_PPGTT(dev_priv)) {
if (intel_vgpu_active(dev_priv) &&
@@ -1620,7 +1621,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
struct drm_printer p = drm_debug_printer("i915 device info:");
intel_device_info_dump(&dev_priv->info, &p);
- intel_device_info_dump_runtime(&dev_priv->info, &p);
+ intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08d25aa480f7..f677a9936d33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1589,6 +1589,7 @@ struct drm_i915_private {
struct kmem_cache *priorities;
const struct intel_device_info info;
+ struct intel_runtime_device_info runtime_info;
struct intel_driver_caps caps;
/**
@@ -2663,7 +2664,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
#define USES_HUC(dev_priv) intel_uc_is_using_huc()
-#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
+#define HAS_POOLED_EU(dev_priv) ((dev_priv)->runtime_info.has_pooled_eu)
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index c8d8f79688a8..3e872bb1f00a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -589,15 +589,18 @@ static void print_error_obj(struct drm_i915_error_state_buf *m,
err_puts(m, "\n");
}
-static void err_print_capabilities(struct drm_i915_error_state_buf *m,
- const struct intel_device_info *info,
- const struct intel_driver_caps *caps)
+static void
+err_print_capabilities(struct drm_i915_error_state_buf *m,
+ const struct intel_device_info *info,
+ const struct intel_runtime_device_info *runtime_info,
+ const struct intel_driver_caps *caps)
{
struct drm_printer p = i915_error_printer(m);
intel_device_info_dump_flags(info, &p);
+ intel_device_info_dump_runtime(runtime_info, &p);
intel_driver_caps_print(caps, &p);
- intel_device_info_dump_topology(&info->sseu, &p);
+ intel_device_info_dump_topology(&runtime_info->sseu, &p);
}
static void err_print_params(struct drm_i915_error_state_buf *m,
@@ -829,7 +832,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
if (error->display)
intel_display_print_error_state(m, error->display);
- err_print_capabilities(m, &error->device_info, &error->driver_caps);
+ err_print_capabilities(m,
+ &error->device_info,
+ &error->runtime_device_info,
+ &error->driver_caps);
err_print_params(m, &error->params);
err_print_uc(m, &error->uc);
@@ -1751,6 +1757,9 @@ static void capture_gen_state(struct i915_gpu_state *error)
memcpy(&error->device_info,
INTEL_INFO(i915),
sizeof(error->device_info));
+ memcpy(&error->runtime_device_info,
+ &i915->runtime_info,
+ sizeof(error->runtime_device_info));
error->driver_caps = i915->caps;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 8710fb18ed74..ede9aa5ae1a2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -45,6 +45,7 @@ struct i915_gpu_state {
u32 reset_count;
u32 suspend_count;
struct intel_device_info device_info;
+ struct intel_runtime_device_info runtime_device_info;
struct intel_driver_caps driver_caps;
struct i915_params params;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c2b63be7a6c..9054237251c3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2646,7 +2646,8 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
{
return div64_u64(1000000000ULL * (2ULL << exponent),
- 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);
+ 1000ULL *
+ dev_priv->runtime_info.cs_timestamp_frequency_khz);
}
static int
@@ -3505,7 +3506,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
oa_sample_rate_hard_limit = 1000 *
- (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
+ (dev_priv->runtime_info.cs_timestamp_frequency_khz / 2);
dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
mutex_init(&dev_priv->perf.metrics_lock);
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 6fc4b8eeab42..6b2c6e6873d3 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -13,7 +13,7 @@
static int query_topology_info(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
{
- const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
+ const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 89ed3a84a4fa..8385767aaf08 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -79,6 +79,15 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
#undef PRINT_FLAG
}
+void
+intel_runtime_device_info_dump_flags(const struct intel_runtime_device_info *info,
+ struct drm_printer *p)
+{
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
+ DEV_RUNTIME_INFO_FOR_EACH_FLAG(PRINT_FLAG);
+#undef PRINT_FLAG
+}
+
static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
@@ -100,13 +109,16 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
}
-void intel_device_info_dump_runtime(const struct intel_device_info *info,
- struct drm_printer *p)
+void
+intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
+ struct drm_printer *p)
{
sseu_dump(&info->sseu, p);
drm_printf(p, "CS timestamp frequency: %u kHz\n",
info->cs_timestamp_frequency_khz);
+
+ intel_runtime_device_info_dump_flags(info, p);
}
void intel_device_info_dump(const struct intel_device_info *info,
@@ -160,7 +172,7 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
u8 s_en;
u32 ss_en, ss_en_mask;
u8 eu_en;
@@ -199,7 +211,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
const u32 fuse2 = I915_READ(GEN8_FUSE2);
int s, ss;
const int eu_mask = 0xff;
@@ -276,7 +288,7 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
u32 fuse;
fuse = I915_READ(CHV_FUSE_GT);
@@ -329,7 +341,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct intel_runtime_device_info *info = &dev_priv->runtime_info;
struct sseu_dev_info *sseu = &info->sseu;
int s, ss;
u32 fuse2, eu_disable, subslice_mask;
@@ -433,7 +445,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
int s, ss;
u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
@@ -515,8 +527,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
- struct sseu_dev_info *sseu = &info->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
u32 fuse1;
int s, ss;
@@ -524,9 +535,9 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
* There isn't a register to tell us how many slices/subslices. We
* work off the PCI-ids here.
*/
- switch (info->gt) {
+ switch (INTEL_INFO(dev_priv)->gt) {
default:
- MISSING_CASE(info->gt);
+ MISSING_CASE(INTEL_INFO(dev_priv)->gt);
/* fall through */
case 1:
sseu->slice_mask = BIT(0);
@@ -735,29 +746,30 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
* - after the PCH has been detected,
* - before the first usage of the fields it can tweak.
*/
-void intel_device_info_runtime_init(struct intel_device_info *info)
+void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv =
- container_of(info, struct drm_i915_private, info);
+ struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct intel_runtime_device_info *runtime_info =
+ &dev_priv->runtime_info;
enum pipe pipe;
if (INTEL_GEN(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
- info->num_scalers[pipe] = 2;
+ runtime_info->num_scalers[pipe] = 2;
} else if (IS_GEN9(dev_priv)) {
- info->num_scalers[PIPE_A] = 2;
- info->num_scalers[PIPE_B] = 2;
- info->num_scalers[PIPE_C] = 1;
+ runtime_info->num_scalers[PIPE_A] = 2;
+ runtime_info->num_scalers[PIPE_B] = 2;
+ runtime_info->num_scalers[PIPE_C] = 1;
}
BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
if (IS_GEN11(dev_priv))
for_each_pipe(dev_priv, pipe)
- info->num_sprites[pipe] = 6;
+ runtime_info->num_sprites[pipe] = 6;
else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
for_each_pipe(dev_priv, pipe)
- info->num_sprites[pipe] = 3;
+ runtime_info->num_sprites[pipe] = 3;
else if (IS_BROXTON(dev_priv)) {
/*
* Skylake and Broxton currently don't expose the topmost plane as its
@@ -768,15 +780,15 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
* down the line.
*/
- info->num_sprites[PIPE_A] = 2;
- info->num_sprites[PIPE_B] = 2;
- info->num_sprites[PIPE_C] = 1;
+ runtime_info->num_sprites[PIPE_A] = 2;
+ runtime_info->num_sprites[PIPE_B] = 2;
+ runtime_info->num_sprites[PIPE_C] = 1;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
for_each_pipe(dev_priv, pipe)
- info->num_sprites[pipe] = 2;
+ runtime_info->num_sprites[pipe] = 2;
} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
for_each_pipe(dev_priv, pipe)
- info->num_sprites[pipe] = 1;
+ runtime_info->num_sprites[pipe] = 1;
}
if (i915_modparams.disable_display) {
@@ -860,7 +872,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
}
/* Initialize command stream timestamp frequency */
- info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
+ runtime_info->cs_timestamp_frequency_khz =
+ read_timestamp_frequency(dev_priv);
}
void intel_driver_caps_print(const struct intel_driver_caps *caps,
@@ -880,6 +893,8 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
{
struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct intel_runtime_device_info *runtime_info =
+ &dev_priv->runtime_info;
u32 media_fuse;
unsigned int i;
@@ -888,27 +903,28 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
- info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
- info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
+ runtime_info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+ runtime_info->vebox_enable =
+ (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
- DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable);
+ DRM_DEBUG_DRIVER("vdbox enable: %04x\n", runtime_info->vdbox_enable);
for (i = 0; i < I915_MAX_VCS; i++) {
if (!HAS_ENGINE(dev_priv, _VCS(i)))
continue;
- if (!(BIT(i) & info->vdbox_enable)) {
+ if (!(BIT(i) & runtime_info->vdbox_enable)) {
info->ring_mask &= ~ENGINE_MASK(_VCS(i));
DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
}
}
- DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable);
+ DRM_DEBUG_DRIVER("vebox enable: %04x\n", runtime_info->vebox_enable);
for (i = 0; i < I915_MAX_VECS; i++) {
if (!HAS_ENGINE(dev_priv, _VECS(i)))
continue;
- if (!(BIT(i) & info->vebox_enable)) {
+ if (!(BIT(i) & runtime_info->vebox_enable)) {
info->ring_mask &= ~ENGINE_MASK(_VECS(i));
DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 88f97210dc49..83e19ac8e401 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -105,7 +105,6 @@ enum intel_ppgtt {
func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
func(has_overlay); \
- func(has_pooled_eu); \
func(has_psr); \
func(has_rc6); \
func(has_rc6p); \
@@ -154,8 +153,8 @@ struct intel_device_info {
u8 gen;
u8 gt; /* GT number, 0 if undefined */
- u8 num_rings;
intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+ u8 num_pipes;
enum intel_platform platform;
u32 platform_mask;
@@ -165,10 +164,6 @@ struct intel_device_info {
u32 display_mmio_offset;
- u8 num_pipes;
- u8 num_sprites[I915_MAX_PIPES];
- u8 num_scalers[I915_MAX_PIPES];
-
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
@@ -179,19 +174,33 @@ struct intel_device_info {
int trans_offsets[I915_MAX_TRANSCODERS];
int cursor_offsets[I915_MAX_PIPES];
- /* Slice/subslice/EU info */
- struct sseu_dev_info sseu;
+ struct color_luts {
+ u16 degamma_lut_size;
+ u16 gamma_lut_size;
+ } color;
+};
- u32 cs_timestamp_frequency_khz;
+#define DEV_RUNTIME_INFO_FOR_EACH_FLAG(func) \
+ func(has_pooled_eu); \
+
+struct intel_runtime_device_info {
+ unsigned int num_rings;
+
+ u8 num_sprites[I915_MAX_PIPES];
+ u8 num_scalers[I915_MAX_PIPES];
/* Enabled (not fused off) media engine bitmasks. */
u8 vdbox_enable;
u8 vebox_enable;
- struct color_luts {
- u16 degamma_lut_size;
- u16 gamma_lut_size;
- } color;
+ u32 cs_timestamp_frequency_khz;
+
+ /* Slice/subslice/EU info */
+ struct sseu_dev_info sseu;
+
+#define DEFINE_FLAG(name) u8 name:1
+ DEV_RUNTIME_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
+#undef DEFINE_FLAG
};
struct intel_driver_caps {
@@ -248,13 +257,14 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
const char *intel_platform_name(enum intel_platform platform);
-void intel_device_info_runtime_init(struct intel_device_info *info);
+void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(const struct intel_device_info *info,
struct drm_printer *p);
void intel_device_info_dump_flags(const struct intel_device_info *info,
struct drm_printer *p);
-void intel_device_info_dump_runtime(const struct intel_device_info *info,
- struct drm_printer *p);
+void
+intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
+ struct drm_printer *p);
void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a7fa032310ae..cc30bf1172ad 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13892,7 +13892,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int i;
- crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
+ crtc->num_scalers = dev_priv->runtime_info.num_scalers[crtc->pipe];
if (!crtc->num_scalers)
return;
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..607ddc4a0b11 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -105,7 +105,7 @@ enum i9xx_plane_id {
};
#define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
+#define sprite_name(p, s) ((p) * dev_priv->runtime_info.num_sprites[(p)] + (s) + 'A')
/*
* Per-pipe plane identifier.
@@ -294,12 +294,12 @@ struct intel_link_m_n {
#define for_each_universal_plane(__dev_priv, __pipe, __p) \
for ((__p) = 0; \
- (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
+ (__p) < (__dev_priv)->runtime_info.num_sprites[(__pipe)] + 1;\
(__p)++)
#define for_each_sprite(__dev_priv, __p, __s) \
for ((__s) = 0; \
- (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
+ (__s) < (__dev_priv)->runtime_info.num_sprites[(__p)]; \
(__s)++)
#define for_each_port_masked(__port, __ports_mask) \
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index bc147d9e6c92..b464ee0afb85 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -365,7 +365,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
goto cleanup;
}
- device_info->num_rings = hweight32(mask);
+ dev_priv->runtime_info.num_rings = hweight32(mask);
i915_check_and_clear_faults(dev_priv);
@@ -807,7 +807,7 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
{
- const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+ const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
u32 subslice = fls(sseu->subslice_mask[slice]);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 08fd9b12e4d7..cc897f429635 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2343,9 +2343,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
static u32
make_rpcs(struct drm_i915_private *dev_priv)
{
- bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
- u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
- u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
+ bool subslice_pg = dev_priv->runtime_info.sseu.has_subslice_pg;
+ u8 slices = hweight8(dev_priv->runtime_info.sseu.slice_mask);
+ u8 subslices = hweight8(dev_priv->runtime_info.sseu.subslice_mask[0]);
u32 rpcs = 0;
/*
@@ -2393,7 +2393,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+ if (dev_priv->runtime_info.sseu.has_slice_pg) {
u32 mask, val = slices;
if (INTEL_GEN(dev_priv) >= 11) {
@@ -2421,17 +2421,17 @@ make_rpcs(struct drm_i915_private *dev_priv)
rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
}
- if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
+ if (dev_priv->runtime_info.sseu.has_eu_pg) {
u32 val;
- val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
+ val = dev_priv->runtime_info.sseu.eu_per_subslice <<
GEN8_RPCS_EU_MIN_SHIFT;
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
val &= GEN8_RPCS_EU_MIN_MASK;
rpcs |= val;
- val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
+ val = dev_priv->runtime_info.sseu.eu_per_subslice <<
GEN8_RPCS_EU_MAX_SHIFT;
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
val &= GEN8_RPCS_EU_MAX_MASK;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5df7f6e1ab5e..17270d8f1880 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7341,7 +7341,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
- switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
+ switch (dev_priv->runtime_info.sseu.eu_total) {
case 8:
/* (2 * 4) config */
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 87eebc13c0d8..fccebf773461 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1566,7 +1566,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
const int num_rings =
/* Use an extended w/a on gen7 if signalling from other rings */
(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
- INTEL_INFO(i915)->num_rings - 1 :
+ i915->runtime_info.num_rings - 1 :
0;
bool force_restore = false;
int len;
@@ -2231,7 +2231,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
- num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
+ num_rings = dev_priv->runtime_info.num_rings - 1;
engine->emit_breadcrumb_sz += num_rings * 3;
if (num_rings & 1)
engine->emit_breadcrumb_sz++;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8a2270b209b0..db2933d287b8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -94,11 +94,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
#define instdone_slice_mask(dev_priv__) \
(IS_GEN7(dev_priv__) ? \
- 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
+ 1 : (dev_priv__)->runtime_info.sseu.slice_mask)
#define instdone_subslice_mask(dev_priv__) \
(IS_GEN7(dev_priv__) ? \
- 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
+ 1 : (dev_priv__)->runtime_info.sseu.subslice_mask[0])
#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
for ((slice__) = 0, (subslice__) = 0; \
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index d7176213e3ce..110556d0934f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -318,7 +318,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
* Only consider slices where one, and only one, subslice has 7
* EUs
*/
- if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
+ if (!is_power_of_2(dev_priv->runtime_info.sseu.subslice_7eu[i]))
continue;
/*
@@ -327,7 +327,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
*
* -> 0 <= ss <= 3;
*/
- ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
+ ss = ffs(dev_priv->runtime_info.sseu.subslice_7eu[i]) - 1;
vals[i] = 3 - ss;
}
@@ -732,7 +732,7 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
static void wa_init_mcr(struct drm_i915_private *dev_priv)
{
- const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+ const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
u32 mcr;
u32 mcr_slice_subslice_mask;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 7d82043aff10..4ee3fcff815a 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -627,7 +627,7 @@ static int igt_ctx_exec(void *arg)
ncontexts++;
}
pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n",
- ncontexts, INTEL_INFO(i915)->num_rings, ndwords);
+ ncontexts, i915->runtime_info.num_rings, ndwords);
dw = 0;
list_for_each_entry(obj, &objects, st_link) {
@@ -732,7 +732,7 @@ static int igt_ctx_readonly(void *arg)
}
}
pr_info("Submitted %lu dwords (across %u engines)\n",
- ndwords, INTEL_INFO(i915)->num_rings);
+ ndwords, i915->runtime_info.num_rings);
dw = 0;
list_for_each_entry(obj, &objects, st_link) {
@@ -1064,7 +1064,7 @@ static int igt_vm_isolation(void *arg)
count += this;
}
pr_info("Checked %lu scratch offsets across %d engines\n",
- count, INTEL_INFO(i915)->num_rings);
+ count, i915->runtime_info.num_rings);
out_rpm:
intel_runtime_pm_put(i915);
diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c
index 94fc0e5c8766..7237a2474805 100644
--- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
@@ -719,7 +719,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
count, flags,
- INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
+ smoke->i915->runtime_info.num_rings, smoke->ncontext);
return 0;
}
@@ -747,7 +747,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
count, flags,
- INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
+ smoke->i915->runtime_info.num_rings, smoke->ncontext);
return 0;
}
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 1/7] drm/i915: Remove has_pooled_eu static initializer Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 2/7] drm/i915: Introduce runtime device info Tvrtko Ursulin
@ 2018-11-12 17:12 ` Tvrtko Ursulin
2018-11-12 17:24 ` Chris Wilson
2018-11-12 21:22 ` Lucas De Marchi
2018-11-12 17:12 ` [RFC 4/7] drm/i915: Remove mkwrite_device_info Tvrtko Ursulin
` (6 subsequent siblings)
9 siblings, 2 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
After the previous change which cleared the static tables from effectively
unused storage, we now replicate entries which have defaults set from
there, but can be overriden at runtime.
For this class of variables all accessor macros and call sites are changed
to use the runtime version. Therefore at driver load we need to copy over
these variables from static to the runtime table.
We add double prefixes to the affected device info members to signify they
are special and to catch all current and future users.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 38 ++++--
drivers/gpu/drm/i915/i915_drv.h | 18 +--
drivers/gpu/drm/i915/i915_gem.c | 5 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 114 +++++++++---------
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 24 ++--
drivers/gpu/drm/i915/intel_device_info.h | 30 +++--
drivers/gpu/drm/i915/intel_display.c | 18 +--
drivers/gpu/drm/i915/intel_display.h | 4 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_fbdev.c | 4 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 9 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 18 +--
drivers/gpu/drm/i915/selftests/intel_guc.c | 4 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 11 +-
22 files changed, 175 insertions(+), 147 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1b8a3f203b92..74362a1fb2be 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -510,7 +510,7 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
seq_printf(m, "%llu [%pa] gtt total\n",
ggtt->vm.total, &ggtt->mappable_end);
seq_printf(m, "Supported page sizes: %s\n",
- stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
+ stringify_page_sizes(dev_priv->runtime_info.page_sizes,
buf, sizeof(buf)));
seq_putc(m, '\n');
@@ -4144,7 +4144,7 @@ i915_ring_test_irq_set(void *data, u64 val)
if (INTEL_GEN(i915) >= 11)
return -ENODEV;
- val &= INTEL_INFO(i915)->ring_mask;
+ val &= i915->runtime_info.ring_mask;
DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9cfd5b145248..bbdd36119eae 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -287,7 +287,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
* Use PCH_NOP (PCH but no South Display) for PCH platforms without
* display.
*/
- if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
+ if (pch && dev_priv->runtime_info.num_pipes == 0) {
DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
dev_priv->pch_type = PCH_NOP;
dev_priv->pch_id = 0;
@@ -646,9 +646,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (i915_inject_load_failure())
return -ENODEV;
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (dev_priv->runtime_info.num_pipes) {
ret = drm_vblank_init(&dev_priv->drm,
- INTEL_INFO(dev_priv)->num_pipes);
+ dev_priv->runtime_info.num_pipes);
if (ret)
goto out;
}
@@ -697,7 +697,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_overlay_setup(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return 0;
ret = intel_fbdev_init(dev);
@@ -1552,7 +1552,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
} else
DRM_ERROR("Failed to register driver for userspace access!\n");
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (dev_priv->runtime_info.num_pipes) {
/* Must be done after probing outputs */
intel_opregion_register(dev_priv);
acpi_video_register();
@@ -1576,7 +1576,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
* We need to coordinate the hotplugs with the asynchronous fbdev
* configuration, for which we use the fbdev->async_cookie.
*/
- if (INTEL_INFO(dev_priv)->num_pipes)
+ if (dev_priv->runtime_info.num_pipes)
drm_kms_helper_poll_init(dev);
intel_power_domains_enable(dev_priv);
@@ -1637,6 +1637,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
{
const struct intel_device_info *match_info =
(struct intel_device_info *)ent->driver_data;
+ struct intel_runtime_device_info *runtime_info;
struct intel_device_info *device_info;
struct drm_i915_private *i915;
int err;
@@ -1658,11 +1659,30 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
/* Setup the write-once "constant" device info */
device_info = mkwrite_device_info(i915);
memcpy(device_info, match_info, sizeof(*device_info));
- device_info->device_id = pdev->device;
BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
BITS_PER_TYPE(device_info->platform_mask));
- BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
+ BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
+
+ /*
+ * Early setup of the runtime device info.
+ */
+ runtime_info = &i915->runtime_info;
+
+ runtime_info->device_id = pdev->device;
+
+ /*
+ * Copy over entries that are both set statically but can also be
+ * modified at runtime.
+ */
+ runtime_info->gen = device_info->__gen;
+ runtime_info->has_fbc = device_info->__has_fbc;
+ runtime_info->has_rc6 = device_info->__has_rc6;
+ runtime_info->has_rc6p = device_info->__has_rc6p;
+ runtime_info->ppgtt = device_info->__ppgtt;
+ runtime_info->page_sizes = device_info->__page_sizes;
+ runtime_info->ring_mask = device_info->__ring_mask;
+ runtime_info->num_pipes = device_info->__num_pipes;
return i915;
}
@@ -1701,7 +1721,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
return PTR_ERR(dev_priv);
/* Disable nuclear pageflip by default on pre-ILK */
- if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
+ if (!i915_modparams.nuclear_pageflip && match_info->__gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
ret = pci_enable_device(pdev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f677a9936d33..4fabbcd6cfb2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2210,7 +2210,7 @@ static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
/* Iterator over subset of engines selected by mask */
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
- for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
+ for ((tmp__) = (mask__) & (dev_priv__)->runtime_info.ring_mask; \
(tmp__) ? \
((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
0;)
@@ -2358,8 +2358,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define INTEL_INFO(dev_priv) intel_info((dev_priv))
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
-#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
-#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
+#define INTEL_GEN(dev_priv) ((dev_priv)->runtime_info.gen)
+#define INTEL_DEVID(dev_priv) ((dev_priv)->runtime_info.device_id)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
@@ -2557,7 +2557,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define ALL_ENGINES (~0)
#define HAS_ENGINE(dev_priv, id) \
- (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
+ (!!((dev_priv)->runtime_info.ring_mask & ENGINE_MASK(id)))
#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
@@ -2583,7 +2583,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT(dev_priv) ((dev_priv)->runtime_info.ppgtt)
#define HAS_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
@@ -2593,7 +2593,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
- ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
+ ((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \
})
#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
@@ -2623,7 +2623,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
-#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
+#define HAS_FBC(dev_priv) ((dev_priv)->runtime_info.has_fbc)
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
@@ -2634,8 +2634,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
-#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
-#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
+#define HAS_RC6(dev_priv) ((dev_priv)->runtime_info.has_rc6)
+#define HAS_RC6p(dev_priv) ((dev_priv)->runtime_info.has_rc6p)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c55b1f75c980..24fea3bc71d2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2725,7 +2725,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
unsigned int sg_page_sizes)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = i915->runtime_info.page_sizes;
int i;
lockdep_assert_held(&obj->mm.lock);
@@ -5535,8 +5535,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
- mkwrite_device_info(dev_priv)->page_sizes =
- I915_GTT_PAGE_SIZE_4K;
+ dev_priv->runtime_info.page_sizes = I915_GTT_PAGE_SIZE_4K;
dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a98c29147d5e..4fd4bc84996b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -799,7 +799,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
*/
static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
{
- ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->ring_mask;
+ ppgtt->pd_dirty_rings = ppgtt->vm.i915->runtime_info.ring_mask;
}
/* Removes entries from a single page table, releasing it if it's empty.
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d447d7d508f4..8a243069f02a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3322,7 +3322,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
*/
intel_runtime_pm_get(dev_priv);
- engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
+ engine_mask &= dev_priv->runtime_info.ring_mask;
if (flags & I915_ERROR_CAPTURE) {
i915_capture_error_state(dev_priv, engine_mask, msg);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e6e7fcdf0ab7..8eb16c54648f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -30,7 +30,7 @@
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
-#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
+#define GEN(x) .__gen = (x), .gen_mask = BIT((x) - 1)
#define GEN_DEFAULT_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
@@ -60,16 +60,16 @@
/* Keep in gen based order, and chronological order within a gen */
#define GEN_DEFAULT_PAGE_SIZES \
- .page_sizes = I915_GTT_PAGE_SIZE_4K
+ .__page_sizes = I915_GTT_PAGE_SIZE_4K
#define GEN2_FEATURES \
GEN(2), \
- .num_pipes = 1, \
+ .__num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
.has_gmch_display = 1, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .ring_mask = RENDER_RING, \
+ .__ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -80,7 +80,7 @@ static const struct intel_device_info intel_i830_info = {
GEN2_FEATURES,
PLATFORM(INTEL_I830),
.is_mobile = 1, .cursor_needs_physical = 1,
- .num_pipes = 2, /* legal, last one wins */
+ .__num_pipes = 2, /* legal, last one wins */
};
static const struct intel_device_info intel_i845g_info = {
@@ -92,9 +92,9 @@ static const struct intel_device_info intel_i85x_info = {
GEN2_FEATURES,
PLATFORM(INTEL_I85X),
.is_mobile = 1,
- .num_pipes = 2, /* legal, last one wins */
+ .__num_pipes = 2, /* legal, last one wins */
.cursor_needs_physical = 1,
- .has_fbc = 1,
+ .__has_fbc = 1,
};
static const struct intel_device_info intel_i865g_info = {
@@ -104,9 +104,9 @@ static const struct intel_device_info intel_i865g_info = {
#define GEN3_FEATURES \
GEN(3), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_gmch_display = 1, \
- .ring_mask = RENDER_RING, \
+ .__ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -130,7 +130,7 @@ static const struct intel_device_info intel_i915gm_info = {
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
- .has_fbc = 1,
+ .__has_fbc = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -151,7 +151,7 @@ static const struct intel_device_info intel_i945gm_info = {
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
- .has_fbc = 1,
+ .__has_fbc = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -173,10 +173,10 @@ static const struct intel_device_info intel_pineview_info = {
#define GEN4_FEATURES \
GEN(4), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_hotplug = 1, \
.has_gmch_display = 1, \
- .ring_mask = RENDER_RING, \
+ .__ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -194,7 +194,7 @@ static const struct intel_device_info intel_i965g_info = {
static const struct intel_device_info intel_i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
- .is_mobile = 1, .has_fbc = 1,
+ .is_mobile = 1, .__has_fbc = 1,
.has_overlay = 1,
.supports_tv = 1,
.hws_needs_physical = 1,
@@ -204,26 +204,26 @@ static const struct intel_device_info intel_i965gm_info = {
static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
- .ring_mask = RENDER_RING | BSD_RING,
+ .__ring_mask = RENDER_RING | BSD_RING,
};
static const struct intel_device_info intel_gm45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_GM45),
- .is_mobile = 1, .has_fbc = 1,
+ .is_mobile = 1, .__has_fbc = 1,
.supports_tv = 1,
- .ring_mask = RENDER_RING | BSD_RING,
+ .__ring_mask = RENDER_RING | BSD_RING,
};
#define GEN5_FEATURES \
GEN(5), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_hotplug = 1, \
- .ring_mask = RENDER_RING | BSD_RING, \
+ .__ring_mask = RENDER_RING | BSD_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
/* ilk does support rc6, but we do not implement [power] contexts */ \
- .has_rc6 = 0, \
+ .__has_rc6 = 0, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -236,20 +236,20 @@ static const struct intel_device_info intel_ironlake_d_info = {
static const struct intel_device_info intel_ironlake_m_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
- .is_mobile = 1, .has_fbc = 1,
+ .is_mobile = 1, .__has_fbc = 1,
};
#define GEN6_FEATURES \
GEN(6), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_hotplug = 1, \
- .has_fbc = 1, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .__has_fbc = 1, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
- .has_rc6 = 1, \
- .has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_ALIASING, \
+ .__has_rc6 = 1, \
+ .__has_rc6p = 1, \
+ .__ppgtt = INTEL_PPGTT_ALIASING, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -286,15 +286,15 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
#define GEN7_FEATURES \
GEN(7), \
- .num_pipes = 3, \
+ .__num_pipes = 3, \
.has_hotplug = 1, \
- .has_fbc = 1, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .__has_fbc = 1, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
- .has_rc6 = 1, \
- .has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_FULL, \
+ .__has_rc6 = 1, \
+ .__has_rc6p = 1, \
+ .__ppgtt = INTEL_PPGTT_FULL, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
@@ -334,7 +334,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
.gt = 2,
- .num_pipes = 0, /* legal, last one wins */
+ .__num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
@@ -342,15 +342,15 @@ static const struct intel_device_info intel_valleyview_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .num_pipes = 2,
+ .__num_pipes = 2,
.has_runtime_pm = 1,
- .has_rc6 = 1,
+ .__has_rc6 = 1,
.has_gmch_display = 1,
.has_hotplug = 1,
- .ppgtt = INTEL_PPGTT_FULL,
+ .__ppgtt = INTEL_PPGTT_FULL,
.has_snoop = true,
.has_coherent_ggtt = false,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_PIPEOFFSETS,
@@ -359,12 +359,12 @@ static const struct intel_device_info intel_valleyview_info = {
#define G75_FEATURES \
GEN7_FEATURES, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
.has_ddi = 1, \
.has_fpga_dbg = 1, \
.has_psr = 1, \
.has_dp_mst = 1, \
- .has_rc6p = 0 /* RC6p removed-by HSW */, \
+ .__has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
#define HSW_PLATFORM \
@@ -391,10 +391,10 @@ static const struct intel_device_info intel_haswell_gt3_info = {
G75_FEATURES, \
GEN(8), \
BDW_COLORS, \
- .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ .__page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .__ppgtt = INTEL_PPGTT_FULL_4LVL, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -423,22 +423,22 @@ static const struct intel_device_info intel_broadwell_rsvd_info = {
static const struct intel_device_info intel_broadwell_gt3_info = {
BDW_PLATFORM,
.gt = 3,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
static const struct intel_device_info intel_cherryview_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .num_pipes = 3,
+ .__num_pipes = 3,
.has_hotplug = 1,
.is_lp = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.has_64bit_reloc = 1,
.has_runtime_pm = 1,
- .has_rc6 = 1,
+ .__has_rc6 = 1,
.has_logical_ring_contexts = 1,
.has_gmch_display = 1,
- .ppgtt = INTEL_PPGTT_FULL,
+ .__ppgtt = INTEL_PPGTT_FULL,
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
@@ -450,7 +450,7 @@ static const struct intel_device_info intel_cherryview_info = {
};
#define GEN9_DEFAULT_PAGE_SIZES \
- .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ .__page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_64K | \
I915_GTT_PAGE_SIZE_2M
@@ -482,7 +482,7 @@ static const struct intel_device_info intel_skylake_gt2_info = {
#define SKL_GT3_PLUS_PLATFORM \
SKL_PLATFORM, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
static const struct intel_device_info intel_skylake_gt3_info = {
@@ -499,21 +499,21 @@ static const struct intel_device_info intel_skylake_gt4_info = {
GEN(9), \
.is_lp = 1, \
.has_hotplug = 1, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
- .num_pipes = 3, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .__num_pipes = 3, \
.has_64bit_reloc = 1, \
.has_ddi = 1, \
.has_fpga_dbg = 1, \
- .has_fbc = 1, \
+ .__has_fbc = 1, \
.has_psr = 1, \
.has_runtime_pm = 1, \
.has_csr = 1, \
- .has_rc6 = 1, \
+ .__has_rc6 = 1, \
.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .__ppgtt = INTEL_PPGTT_FULL_4LVL, \
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
@@ -553,7 +553,7 @@ static const struct intel_device_info intel_kabylake_gt2_info = {
static const struct intel_device_info intel_kabylake_gt3_info = {
KBL_PLATFORM,
.gt = 3,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
#define CFL_PLATFORM \
@@ -573,7 +573,7 @@ static const struct intel_device_info intel_coffeelake_gt2_info = {
static const struct intel_device_info intel_coffeelake_gt3_info = {
CFL_PLATFORM,
.gt = 3,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
#define GEN10_FEATURES \
@@ -605,7 +605,7 @@ static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
.is_alpha_support = 1,
- .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
+ .__ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
};
#undef GEN
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 0ad2304457ab..c31bfac5201c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1721,7 +1721,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
const struct bdb_header *bdb;
u8 __iomem *bios = NULL;
- if (INTEL_INFO(dev_priv)->num_pipes == 0) {
+ if (dev_priv->runtime_info.num_pipes == 0) {
DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
return;
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8385767aaf08..aeb7b9225b18 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -131,7 +131,7 @@ void intel_device_info_dump(const struct intel_device_info *info,
INTEL_DEVID(dev_priv),
INTEL_REVID(dev_priv),
intel_platform_name(info->platform),
- info->gen);
+ info->__gen);
intel_device_info_dump_flags(info, p);
}
@@ -748,7 +748,6 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
*/
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct intel_runtime_device_info *runtime_info =
&dev_priv->runtime_info;
enum pipe pipe;
@@ -793,8 +792,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (i915_modparams.disable_display) {
DRM_INFO("Display disabled (module parameter)\n");
- info->num_pipes = 0;
- } else if (info->num_pipes > 0 &&
+ runtime_info->num_pipes = 0;
+ } else if (runtime_info->num_pipes > 0 &&
(IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
@@ -814,12 +813,12 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
(HAS_PCH_CPT(dev_priv) &&
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
DRM_INFO("Display fused off, disabling\n");
- info->num_pipes = 0;
+ runtime_info->num_pipes = 0;
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
DRM_INFO("PipeC fused off\n");
- info->num_pipes -= 1;
+ runtime_info->num_pipes -= 1;
}
- } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
+ } else if (runtime_info->num_pipes > 0 && IS_GEN9(dev_priv)) {
u32 dfsm = I915_READ(SKL_DFSM);
u8 disabled_mask = 0;
bool invalid;
@@ -845,11 +844,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
invalid = false;
}
- if (num_bits > info->num_pipes || invalid)
+ if (num_bits > runtime_info->num_pipes || invalid)
DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
disabled_mask);
else
- info->num_pipes -= num_bits;
+ runtime_info->num_pipes -= num_bits;
}
/* Initialize slice/subslice/EU info */
@@ -868,7 +867,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (IS_GEN6(dev_priv) && intel_vtd_active()) {
DRM_INFO("Disabling ppGTT for VT-d support\n");
- info->ppgtt = INTEL_PPGTT_NONE;
+ runtime_info->ppgtt = INTEL_PPGTT_NONE;
}
/* Initialize command stream timestamp frequency */
@@ -892,7 +891,6 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
*/
void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct intel_runtime_device_info *runtime_info =
&dev_priv->runtime_info;
u32 media_fuse;
@@ -914,7 +912,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
continue;
if (!(BIT(i) & runtime_info->vdbox_enable)) {
- info->ring_mask &= ~ENGINE_MASK(_VCS(i));
+ runtime_info->ring_mask &= ~ENGINE_MASK(_VCS(i));
DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
}
}
@@ -925,7 +923,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
continue;
if (!(BIT(i) & runtime_info->vebox_enable)) {
- info->ring_mask &= ~ENGINE_MASK(_VECS(i));
+ runtime_info->ring_mask &= ~ENGINE_MASK(_VECS(i));
DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
}
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 83e19ac8e401..50c8fda20bdd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -93,7 +93,7 @@ enum intel_ppgtt {
func(has_ddi); \
func(has_dp_mst); \
func(has_reset_engine); \
- func(has_fbc); \
+ func(__has_fbc); \
func(has_fpga_dbg); \
func(has_gmch_display); \
func(has_guc); \
@@ -106,8 +106,8 @@ enum intel_ppgtt {
func(has_logical_ring_preemption); \
func(has_overlay); \
func(has_psr); \
- func(has_rc6); \
- func(has_rc6p); \
+ func(__has_rc6); \
+ func(__has_rc6p); \
func(has_runtime_pm); \
func(has_snoop); \
func(has_coherent_ggtt); \
@@ -148,19 +148,18 @@ struct sseu_dev_info {
typedef u8 intel_ring_mask_t;
struct intel_device_info {
- u16 device_id;
u16 gen_mask;
- u8 gen;
+ u8 __gen;
u8 gt; /* GT number, 0 if undefined */
- intel_ring_mask_t ring_mask; /* Rings supported by the HW */
- u8 num_pipes;
+ intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
+ u8 __num_pipes;
enum intel_platform platform;
u32 platform_mask;
- enum intel_ppgtt ppgtt;
- unsigned int page_sizes; /* page sizes supported by the HW */
+ enum intel_ppgtt __ppgtt;
+ unsigned int __page_sizes; /* page sizes supported by the HW */
u32 display_mmio_offset;
@@ -181,11 +180,24 @@ struct intel_device_info {
};
#define DEV_RUNTIME_INFO_FOR_EACH_FLAG(func) \
+ func(has_fbc); \
func(has_pooled_eu); \
+ func(has_rc6); \
+ func(has_rc6p); \
struct intel_runtime_device_info {
+ int gen;
+
unsigned int num_rings;
+ enum intel_ppgtt ppgtt;
+ unsigned int page_sizes; /* page sizes supported by the HW */
+
+ u16 device_id;
+
+ intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+ u8 num_pipes;
+
u8 num_sprites[I915_MAX_PIPES];
u8 num_scalers[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cc30bf1172ad..e87f4fc648de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6372,7 +6372,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
}
}
- if (INTEL_INFO(dev_priv)->num_pipes == 2)
+ if (dev_priv->runtime_info.num_pipes == 2)
return 0;
/* Ivybridge 3 pipe is really complicated */
@@ -8588,7 +8588,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
* clear if it''s a win or loss power wise. No point in doing
* this on ILK at all since it has a fixed DPLL<->pipe mapping.
*/
- if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
+ if (dev_priv->runtime_info.num_pipes == 3 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
dpll |= DPLL_SDVO_HIGH_SPEED;
@@ -12684,7 +12684,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
entries,
- INTEL_INFO(dev_priv)->num_pipes, i))
+ dev_priv->runtime_info.num_pipes, i))
continue;
updated |= cmask;
@@ -14111,7 +14111,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_pps_init(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return;
/*
@@ -15063,8 +15063,8 @@ int intel_modeset_init(struct drm_device *dev)
dev->mode_config.fb_base = ggtt->gmadr.start;
DRM_DEBUG_KMS("%d display pipe%s available.\n",
- INTEL_INFO(dev_priv)->num_pipes,
- INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
+ dev_priv->runtime_info.num_pipes,
+ dev_priv->runtime_info.num_pipes > 1 ? "s" : "");
for_each_pipe(dev_priv, pipe) {
ret = intel_crtc_init(dev_priv, pipe);
@@ -15983,7 +15983,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
};
int i;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
@@ -16024,7 +16024,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
}
/* Note: this does not include DSI transcoders. */
- error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
+ error->num_transcoders = dev_priv->runtime_info.num_pipes;
if (HAS_DDI(dev_priv))
error->num_transcoders++; /* Account for eDP. */
@@ -16063,7 +16063,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
if (!error)
return;
- err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
+ err_printf(m, "Num Pipes: %d\n", dev_priv->runtime_info.num_pipes);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
err_printf(m, "PWR_WELL_CTL2: %08x\n",
error->power_well_driver);
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 607ddc4a0b11..00ef394f08d5 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -282,10 +282,10 @@ struct intel_link_m_n {
};
#define for_each_pipe(__dev_priv, __p) \
- for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
+ for ((__p) = 0; (__p) < (__dev_priv)->runtime_info.num_pipes; (__p)++)
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
- for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
+ for ((__p) = 0; (__p) < (__dev_priv)->runtime_info.num_pipes; (__p)++) \
for_each_if((__mask) & BIT(__p))
#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index b464ee0afb85..ea21bf6730ed 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -325,8 +325,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
*/
int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
- const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
+ const unsigned int ring_mask = dev_priv->runtime_info.ring_mask;
struct intel_engine_cs *engine;
enum intel_engine_id id;
unsigned int mask = 0;
@@ -357,7 +356,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
* engines.
*/
if (WARN_ON(mask != ring_mask))
- device_info->ring_mask = mask;
+ dev_priv->runtime_info.ring_mask = mask;
/* We always presume we have at least RCS available for later probing */
if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) {
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 14cbaf4a0e93..fe925abd1c7a 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1309,7 +1309,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
fbc->active = false;
if (need_fbc_vtd_wa(dev_priv))
- mkwrite_device_info(dev_priv)->has_fbc = false;
+ dev_priv->runtime_info.has_fbc = false;
i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 2480c7d6edee..e3b8f9cf0f25 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -484,7 +484,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
* fbdev helper library.
*/
if (num_connectors_enabled != num_connectors_detected &&
- num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
+ num_connectors_enabled < dev_priv->runtime_info.num_pipes) {
DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
num_connectors_detected);
@@ -672,7 +672,7 @@ int intel_fbdev_init(struct drm_device *dev)
struct intel_fbdev *ifbdev;
int ret;
- if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+ if (WARN_ON(dev_priv->runtime_info.num_pipes == 0))
return -ENODEV;
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 1570dcbe249c..dfe4a5ef1784 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1024,7 +1024,7 @@ static int guc_clients_create(struct intel_guc *guc)
GEM_BUG_ON(guc->preempt_client);
client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ dev_priv->runtime_info.ring_mask,
GUC_CLIENT_PRIORITY_KMD_NORMAL,
dev_priv->kernel_context);
if (IS_ERR(client)) {
@@ -1035,7 +1035,7 @@ static int guc_clients_create(struct intel_guc *guc)
if (dev_priv->preempt_context) {
client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ dev_priv->runtime_info.ring_mask,
GUC_CLIENT_PRIORITY_KMD_HIGH,
dev_priv->preempt_context);
if (IS_ERR(client)) {
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 33d87ab93fdd..5543597ec74a 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -817,7 +817,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
unsigned int pin;
int ret;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c b/drivers/gpu/drm/i915/intel_lpe_audio.c
index 5d5336fbe7b0..22fa3277ee59 100644
--- a/drivers/gpu/drm/i915/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/intel_lpe_audio.c
@@ -111,7 +111,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
pinfo.size_data = sizeof(*pdata);
pinfo.dma_mask = DMA_BIT_MASK(32);
- pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;
+ pdata->num_pipes = dev_priv->runtime_info.num_pipes;
pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
pdata->port[0].pipe = -1;
pdata->port[1].pipe = -1;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 17270d8f1880..176a4a19377e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1899,7 +1899,8 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
for (level = 0; level < wm_state->num_levels; level++) {
const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
- const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
+ const int sr_fifo_size =
+ dev_priv->runtime_info.num_pipes * 512 - 1;
if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
break;
@@ -2632,7 +2633,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
/* HSW allows LP1+ watermarks even with multiple pipes */
if (level == 0 || config->num_pipes_active > 1) {
- fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
+ fifo_size /= dev_priv->runtime_info.num_pipes;
/*
* For some reason the non self refresh
@@ -6886,7 +6887,7 @@ static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
static bool sanitize_rc6(struct drm_i915_private *i915)
{
- struct intel_device_info *info = mkwrite_device_info(i915);
+ struct intel_runtime_device_info *info = &i915->runtime_info;
/* Powersaving is controlled by the host when inside a VM */
if (intel_vgpu_active(i915))
@@ -9498,7 +9499,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (IS_GEN2(dev_priv)) {
- if (INTEL_INFO(dev_priv)->num_pipes == 1) {
+ if (dev_priv->runtime_info.num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
} else {
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 26c065c8d2c0..935ded51adc0 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -341,7 +341,7 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)
static int igt_check_page_sizes(struct i915_vma *vma)
{
struct drm_i915_private *i915 = vma->vm->i915;
- unsigned int supported = INTEL_INFO(i915)->page_sizes;
+ unsigned int supported = i915->runtime_info.page_sizes;
struct drm_i915_gem_object *obj = vma->obj;
int err = 0;
@@ -382,7 +382,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
{
struct i915_hw_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->vm.i915;
- unsigned int saved_mask = INTEL_INFO(i915)->page_sizes;
+ unsigned int saved_mask = i915->runtime_info.page_sizes;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
int i, j, single;
@@ -401,7 +401,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
combination |= page_sizes[j];
}
- mkwrite_device_info(i915)->page_sizes = combination;
+ i915->runtime_info.page_sizes = combination;
for (single = 0; single <= 1; ++single) {
obj = fake_huge_pages_object(i915, combination, !!single);
@@ -452,7 +452,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
out_put:
i915_gem_object_put(obj);
out_device:
- mkwrite_device_info(i915)->page_sizes = saved_mask;
+ i915->runtime_info.page_sizes = saved_mask;
return err;
}
@@ -461,7 +461,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
{
struct i915_hw_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->vm.i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = i915->runtime_info.page_sizes;
struct drm_i915_gem_object *obj;
int bit;
int err;
@@ -1204,7 +1204,7 @@ static int igt_ppgtt_exhaust_huge(void *arg)
{
struct i915_gem_context *ctx = arg;
struct drm_i915_private *i915 = ctx->i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = i915->runtime_info.page_sizes;
static unsigned int pages[ARRAY_SIZE(page_sizes)];
struct drm_i915_gem_object *obj;
unsigned int size_mask;
@@ -1296,7 +1296,7 @@ static int igt_ppgtt_exhaust_huge(void *arg)
i915_gem_object_unpin_pages(obj);
i915_gem_object_put(obj);
out_device:
- mkwrite_device_info(i915)->page_sizes = supported;
+ i915->runtime_info.page_sizes = supported;
return err;
}
@@ -1434,7 +1434,7 @@ static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
struct drm_i915_private *dev_priv = ctx->i915;
- unsigned long supported = INTEL_INFO(dev_priv)->page_sizes;
+ unsigned long supported = dev_priv->runtime_info.page_sizes;
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
@@ -1711,7 +1711,7 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+ dev_priv->runtime_info.ppgtt = INTEL_PPGTT_FULL_4LVL;
pdev = dev_priv->drm.pdev;
dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c
index 32cba4cae31a..65e5e8a64ce2 100644
--- a/drivers/gpu/drm/i915/selftests/intel_guc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
@@ -111,7 +111,7 @@ static int validate_client(struct intel_guc_client *client,
dev_priv->preempt_context : dev_priv->kernel_context;
if (client->owner != ctx_owner ||
- client->engines != INTEL_INFO(dev_priv)->ring_mask ||
+ client->engines != dev_priv->runtime_info.ring_mask ||
client->priority != client_priority ||
client->doorbell_id == GUC_DOORBELL_INVALID)
return -EINVAL;
@@ -259,7 +259,7 @@ static int igt_guc_doorbells(void *arg)
for (i = 0; i < ATTEMPTS; i++) {
clients[i] = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ dev_priv->runtime_info.ring_mask,
i % GUC_CLIENT_PRIORITY_NUM,
dev_priv->kernel_context);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..b6849ca11e01 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -174,12 +174,11 @@ struct drm_i915_private *mock_gem_device(void)
/* Using the global GTT may ask questions about KMS users, so prepare */
drm_mode_config_init(&i915->drm);
- mkwrite_device_info(i915)->gen = -1;
+ i915->runtime_info.gen = -1;
- mkwrite_device_info(i915)->page_sizes =
- I915_GTT_PAGE_SIZE_4K |
- I915_GTT_PAGE_SIZE_64K |
- I915_GTT_PAGE_SIZE_2M;
+ i915->runtime_info.page_sizes = I915_GTT_PAGE_SIZE_4K |
+ I915_GTT_PAGE_SIZE_64K |
+ I915_GTT_PAGE_SIZE_2M;
mock_uncore_init(i915);
i915_gem_init__mm(i915);
@@ -231,7 +230,7 @@ struct drm_i915_private *mock_gem_device(void)
mock_init_ggtt(i915);
- mkwrite_device_info(i915)->ring_mask = BIT(0);
+ i915->runtime_info.ring_mask = BIT(0);
i915->kernel_context = mock_context(i915, NULL);
if (!i915->kernel_context)
goto err_unlock;
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
` (2 preceding siblings ...)
2018-11-12 17:12 ` [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info Tvrtko Ursulin
@ 2018-11-12 17:12 ` Tvrtko Ursulin
2018-11-12 17:25 ` Chris Wilson
2018-11-13 11:45 ` Jani Nikula
2018-11-12 17:12 ` [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info Tvrtko Ursulin
` (5 subsequent siblings)
9 siblings, 2 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Now that we are down to one caller, which does not even modify copied
device info, we can remove the mkwrite_device_info helper and convert the
device info pointer itself to be a pointer to static table instead of a
copy.
Only unfortnate thing is that we need to convert all callsites which were
referencing the device info directly to using the INTEL_INFO helper.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 9 +-
drivers/gpu/drm/i915/i915_drv.h | 107 ++++++-------
drivers/gpu/drm/i915/i915_reg.h | 190 +++++++++++------------
drivers/gpu/drm/i915/intel_device_info.c | 11 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
6 files changed, 151 insertions(+), 170 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bbdd36119eae..77dd7763b334 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1620,7 +1620,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
if (drm_debug & DRM_UT_DRIVER) {
struct drm_printer p = drm_debug_printer("i915 device info:");
- intel_device_info_dump(&dev_priv->info, &p);
+ intel_device_info_dump(dev_priv, &p);
intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
}
@@ -1638,7 +1638,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
const struct intel_device_info *match_info =
(struct intel_device_info *)ent->driver_data;
struct intel_runtime_device_info *runtime_info;
- struct intel_device_info *device_info;
+ const struct intel_device_info *device_info;
struct drm_i915_private *i915;
int err;
@@ -1654,12 +1654,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
i915->drm.pdev = pdev;
i915->drm.dev_private = i915;
+ i915->info = device_info = match_info;
pci_set_drvdata(pdev, &i915->drm);
- /* Setup the write-once "constant" device info */
- device_info = mkwrite_device_info(i915);
- memcpy(device_info, match_info, sizeof(*device_info));
-
BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
BITS_PER_TYPE(device_info->platform_mask));
BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4fabbcd6cfb2..77ef41d53558 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1588,7 +1588,7 @@ struct drm_i915_private {
struct kmem_cache *dependencies;
struct kmem_cache *priorities;
- const struct intel_device_info info;
+ const struct intel_device_info *info;
struct intel_runtime_device_info runtime_info;
struct intel_driver_caps caps;
@@ -2349,13 +2349,7 @@ static inline unsigned int i915_sg_segment_size(void)
return size;
}
-static inline const struct intel_device_info *
-intel_info(const struct drm_i915_private *dev_priv)
-{
- return &dev_priv->info;
-}
-
-#define INTEL_INFO(dev_priv) intel_info((dev_priv))
+#define INTEL_INFO(dev_priv) ((dev_priv)->info)
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
#define INTEL_GEN(dev_priv) ((dev_priv)->runtime_info.gen)
@@ -2371,7 +2365,7 @@ intel_info(const struct drm_i915_private *dev_priv)
/* Returns true if Gen is in inclusive range [Start, End] */
#define IS_GEN(dev_priv, s, e) \
- (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
+ (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
/*
* Return true if revision is in range [since,until] inclusive.
@@ -2381,7 +2375,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
+#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
@@ -2403,7 +2397,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
- (dev_priv)->info.gt == 1)
+ INTEL_INFO(dev_priv)->gt == 1)
#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
@@ -2415,7 +2409,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
+#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
@@ -2426,11 +2420,11 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ INTEL_INFO(dev_priv)->gt == 3)
#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ INTEL_INFO(dev_priv)->gt == 3)
/* ULX machines are also considered ULT. */
#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2453,21 +2447,21 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
INTEL_DEVID(dev_priv) == 0x87C0)
#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 2)
+ INTEL_INFO(dev_priv)->gt == 2)
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ INTEL_INFO(dev_priv)->gt == 3)
#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 4)
+ INTEL_INFO(dev_priv)->gt == 4)
#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 2)
+ INTEL_INFO(dev_priv)->gt == 2)
#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ INTEL_INFO(dev_priv)->gt == 3)
#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
- (dev_priv)->info.gt == 2)
+ INTEL_INFO(dev_priv)->gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ INTEL_INFO(dev_priv)->gt == 3)
#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
@@ -2530,16 +2524,16 @@ intel_info(const struct drm_i915_private *dev_priv)
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
-#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
-#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
-#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
+#define IS_GEN2(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3)))
+#define IS_GEN5(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4)))
+#define IS_GEN6(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5)))
+#define IS_GEN7(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6)))
+#define IS_GEN8(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7)))
+#define IS_GEN9(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8)))
+#define IS_GEN10(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9)))
+#define IS_GEN11(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10)))
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
@@ -2566,20 +2560,20 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
-#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
-#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
+#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
-#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
+#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
- ((dev_priv)->info.has_logical_ring_contexts)
+ (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
- ((dev_priv)->info.has_logical_ring_elsq)
+ (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
- ((dev_priv)->info.has_logical_ring_preemption)
+ (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
@@ -2596,9 +2590,9 @@ intel_info(const struct drm_i915_private *dev_priv)
((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \
})
-#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
+#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
- ((dev_priv)->info.overlay_needs_physical)
+ (INTEL_INFO(dev_priv)->overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
@@ -2619,8 +2613,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
!(IS_I915G(dev_priv) || \
IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
+#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->supports_tv)
+#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->has_hotplug)
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
#define HAS_FBC(dev_priv) ((dev_priv)->runtime_info.has_fbc)
@@ -2628,30 +2622,30 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
-#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
+#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->has_dp_mst)
-#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
-#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
+#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
+#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->has_psr)
#define HAS_RC6(dev_priv) ((dev_priv)->runtime_info.has_rc6)
#define HAS_RC6p(dev_priv) ((dev_priv)->runtime_info.has_rc6p)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
-#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
+#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->has_csr)
-#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
-#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
+#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
+#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
-#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
+#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->has_ipc)
/*
* For now, anything with a GuC requires uCode loading, and then supports
* command submission once loaded. But these are logically independent
* properties, so we have separate macros to test them.
*/
-#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
-#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
+#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
+#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
@@ -2704,12 +2698,12 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
-#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
+#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->has_gmch_display)
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
/* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
+#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2 : HAS_L3_DPF(dev_priv))
@@ -3465,13 +3459,6 @@ static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */
-/* intel_device_info.c */
-static inline struct intel_device_info *
-mkwrite_device_info(struct drm_i915_private *dev_priv)
-{
- return (struct intel_device_info *)&dev_priv->info;
-}
-
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
extern int intel_modeset_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe4b913e46ac..4c0e5b62e7fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -179,15 +179,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
* Device info offset array based helpers for groups of registers with unevenly
* spaced base offsets.
*/
-#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
- dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
- dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
- dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
+#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
+ INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
+ INTEL_INFO(dev_priv)->display_mmio_offset)
+#define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
+ INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
+ INTEL_INFO(dev_priv)->display_mmio_offset)
+#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
+ INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
+ INTEL_INFO(dev_priv)->display_mmio_offset)
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
@@ -3153,9 +3153,9 @@ enum i915_power_well_id {
/*
* Clock control & power management
*/
-#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
-#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
-#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
+#define _DPLL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6014)
+#define _DPLL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6018)
+#define _CHV_DPLL_C (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6030)
#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
#define VGA0 _MMIO(0x6000)
@@ -3252,9 +3252,9 @@ enum i915_power_well_id {
#define SDVO_MULTIPLIER_SHIFT_HIRES 4
#define SDVO_MULTIPLIER_SHIFT_VGA 0
-#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
-#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
-#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
+#define _DPLL_A_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x601c)
+#define _DPLL_B_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6020)
+#define _CHV_DPLL_C_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x603c)
#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
/*
@@ -3326,7 +3326,7 @@ enum i915_power_well_id {
#define DSTATE_PLL_D3_OFF (1 << 3)
#define DSTATE_GFX_CLOCK_GATING (1 << 1)
#define DSTATE_DOT_CLOCK_GATING (1 << 0)
-#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
+#define DSPCLK_GATE_D _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
@@ -3466,7 +3466,7 @@ enum i915_power_well_id {
#define _PALETTE_A 0xa000
#define _PALETTE_B 0xa800
#define _CHV_PALETTE_C 0xc000
-#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \
+#define PALETTE(pipe, i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + \
_PICK((pipe), _PALETTE_A, \
_PALETTE_B, _CHV_PALETTE_C) + \
(i) * 4)
@@ -4295,7 +4295,7 @@ enum {
/* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
+#define PORT_HOTPLUG_EN _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61110)
#define PORTB_HOTPLUG_INT_EN (1 << 29)
#define PORTC_HOTPLUG_INT_EN (1 << 28)
#define PORTD_HOTPLUG_INT_EN (1 << 27)
@@ -4325,7 +4325,7 @@ enum {
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
-#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
+#define PORT_HOTPLUG_STAT _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61114)
/*
* HDMI/DP bits are g4x+
*
@@ -4407,7 +4407,7 @@ enum {
#define PORT_DFT_I9XX _MMIO(0x61150)
#define DC_BALANCE_RESET (1 << 25)
-#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
+#define PORT_DFT2_G4X _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61154)
#define DC_BALANCE_RESET_VLV (1 << 31)
#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
@@ -4680,7 +4680,7 @@ enum {
#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
/* Panel fitting */
-#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
+#define PFIT_CONTROL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61230)
#define PFIT_ENABLE (1 << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
@@ -4698,7 +4698,7 @@ enum {
#define PFIT_SCALING_PROGRAMMED (1 << 26)
#define PFIT_SCALING_PILLAR (2 << 26)
#define PFIT_SCALING_LETTER (3 << 26)
-#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
+#define PFIT_PGM_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61234)
/* Pre-965 */
#define PFIT_VERT_SCALE_SHIFT 20
#define PFIT_VERT_SCALE_MASK 0xfff00000
@@ -4710,25 +4710,25 @@ enum {
#define PFIT_HORIZ_SCALE_SHIFT_965 0
#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
-#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
+#define PFIT_AUTO_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61238)
-#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
-#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
+#define _VLV_BLC_PWM_CTL2_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61350)
#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
_VLV_BLC_PWM_CTL2_B)
-#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
-#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
+#define _VLV_BLC_PWM_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61354)
#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
_VLV_BLC_PWM_CTL_B)
-#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
-#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
+#define _VLV_BLC_HIST_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61360)
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
_VLV_BLC_HIST_CTL_B)
/* Backlight control */
-#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
+#define BLC_PWM_CTL2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250) /* 965+ only */
#define BLM_PWM_ENABLE (1 << 31)
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
#define BLM_PIPE_SELECT (1 << 29)
@@ -4751,7 +4751,7 @@ enum {
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
#define BLM_PHASE_IN_INCR_SHIFT (0)
#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
-#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
+#define BLC_PWM_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
/*
* This is the most significant 15 bits of the number of backlight cycles in a
* complete cycle of the modulated backlight control.
@@ -4773,7 +4773,7 @@ enum {
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
-#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
+#define BLC_HIST_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
#define BLM_HISTOGRAM_ENABLE (1 << 31)
/* New registers for PCH-split platforms. Safe where new bits show up, the
@@ -5397,47 +5397,47 @@ enum {
* is 20 bytes in each direction, hence the 5 fixed
* data registers
*/
-#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
-#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
-#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
-#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
-#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
-#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
-
-#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
-#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
-#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
-#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
-#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
-#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
-
-#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
-#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
-#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
-#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
-#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
-#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
-
-#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
-#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
-#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
-#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
-#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
-#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
-
-#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
-#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
-#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
-#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
-#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
-#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
-
-#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
-#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
-#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
-#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
-#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
-#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
+#define _DPA_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64010)
+#define _DPA_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64110)
+#define _DPB_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64210)
+#define _DPC_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64310)
+#define _DPD_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64314)
+#define _DPD_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64318)
+#define _DPD_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6431c)
+#define _DPD_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64320)
+#define _DPD_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64324)
+
+#define _DPE_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64410)
+#define _DPE_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64414)
+#define _DPE_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64418)
+#define _DPE_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6441c)
+#define _DPE_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64420)
+#define _DPE_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64424)
+
+#define _DPF_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64524)
#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
@@ -5713,7 +5713,7 @@ enum {
#define DPINVGTT_STATUS_MASK 0xff
#define DPINVGTT_STATUS_MASK_CHV 0xfff
-#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
+#define DSPARB _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70030)
#define DSPARB_CSTART_MASK (0x7f << 7)
#define DSPARB_CSTART_SHIFT 7
#define DSPARB_BSTART_MASK (0x7f)
@@ -5748,7 +5748,7 @@ enum {
#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
/* pnv/gen4/g4x/vlv/chv */
-#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
+#define DSPFW1 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70034)
#define DSPFW_SR_SHIFT 23
#define DSPFW_SR_MASK (0x1ff << 23)
#define DSPFW_CURSORB_SHIFT 16
@@ -5759,7 +5759,7 @@ enum {
#define DSPFW_PLANEA_SHIFT 0
#define DSPFW_PLANEA_MASK (0x7f << 0)
#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
-#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
+#define DSPFW2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70038)
#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
#define DSPFW_FBC_SR_SHIFT 28
#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
@@ -5775,7 +5775,7 @@ enum {
#define DSPFW_SPRITEA_SHIFT 0
#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
-#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
+#define DSPFW3 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7003c)
#define DSPFW_HPLL_SR_EN (1 << 31)
#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
#define DSPFW_CURSOR_SR_SHIFT 24
@@ -6191,35 +6191,35 @@ enum {
* [10:1f] all
* [30:32] all
*/
-#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
-#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
-#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
+#define SWF0(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70410 + (i) * 4)
+#define SWF1(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71410 + (i) * 4)
+#define SWF3(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x72414 + (i) * 4)
#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
/* Pipe B */
-#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
-#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
-#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
+#define _PIPEBDSL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71000)
+#define _PIPEBCONF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71008)
+#define _PIPEBSTAT (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71024)
#define _PIPEBFRAMEHIGH 0x71040
#define _PIPEBFRAMEPIXEL 0x71044
-#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_G4X (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_G4X (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71044)
/* Display B control */
-#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
+#define _DSPBCNTR (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71180)
#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
-#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
-#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
-#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
-#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
-#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
-#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
+#define _DSPBADDR (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71184)
+#define _DSPBSTRIDE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71188)
+#define _DSPBPOS (INTEL_INFO(dev_priv)->display_mmio_offset + 0x7118C)
+#define _DSPBSIZE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71190)
+#define _DSPBSURF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x7119C)
+#define _DSPBTILEOFF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBOFFSET (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBSURFLIVE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711AC)
/* ICL DSI 0 and 1 */
#define _PIPEDSI0CONF 0x7b008
@@ -8773,7 +8773,7 @@ enum {
#define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
/* Audio */
-#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
+#define G4X_AUD_VID_DID _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x62020)
#define INTEL_AUDIO_DEVCL 0x808629FB
#define INTEL_AUDIO_DEVBLC 0x80862801
#define INTEL_AUDIO_DEVCTG 0x80862802
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index aeb7b9225b18..00758d11047b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -121,19 +121,16 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
intel_runtime_device_info_dump_flags(info, p);
}
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_dump(struct drm_i915_private *dev_priv,
struct drm_printer *p)
{
- struct drm_i915_private *dev_priv =
- container_of(info, struct drm_i915_private, info);
-
drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
INTEL_DEVID(dev_priv),
INTEL_REVID(dev_priv),
- intel_platform_name(info->platform),
- info->__gen);
+ intel_platform_name(INTEL_INFO(dev_priv)->platform),
+ INTEL_INFO(dev_priv)->__gen);
- intel_device_info_dump_flags(info, p);
+ intel_device_info_dump_flags(INTEL_INFO(dev_priv), p);
}
void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 50c8fda20bdd..9bacd466f4a2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -270,7 +270,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_dump(struct drm_i915_private *dev_priv,
struct drm_printer *p);
void intel_device_info_dump_flags(const struct intel_device_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9289515108c3..def498402bbb 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2256,7 +2256,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
{
- return (dev_priv->info.has_reset_engine &&
+ return (INTEL_INFO(dev_priv)->has_reset_engine &&
i915_modparams.reset >= 2);
}
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
` (3 preceding siblings ...)
2018-11-12 17:12 ` [RFC 4/7] drm/i915: Remove mkwrite_device_info Tvrtko Ursulin
@ 2018-11-12 17:12 ` Tvrtko Ursulin
2018-11-13 11:30 ` Jani Nikula
2018-11-12 17:12 ` [RFC 6/7] drm/i915: Introduce subplatform concept Tvrtko Ursulin
` (4 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
It is more space efficient to store these two at the runtime copy since
both are trivially derived from the static data.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 15 +++++++++----
drivers/gpu/drm/i915/i915_drv.h | 28 ++++++++++++++----------
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.h | 6 ++---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
5 files changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 77dd7763b334..4f5ddc3d2f4d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1657,10 +1657,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
i915->info = device_info = match_info;
pci_set_drvdata(pdev, &i915->drm);
- BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
- BITS_PER_TYPE(device_info->platform_mask));
- BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
-
/*
* Early setup of the runtime device info.
*/
@@ -1681,6 +1677,17 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
runtime_info->ring_mask = device_info->__ring_mask;
runtime_info->num_pipes = device_info->__num_pipes;
+ /*
+ * Initialize GEN and platform masks.
+ */
+ BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+ BITS_PER_TYPE(runtime_info->platform_mask));
+
+ BUG_ON(INTEL_GEN(i915) > BITS_PER_TYPE(runtime_info->gen_mask));
+
+ runtime_info->gen_mask = BIT(INTEL_GEN(i915) - 1);
+ runtime_info->platform_mask = BIT(device_info->platform);
+
return i915;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 77ef41d53558..283592dd7023 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2365,7 +2365,7 @@ static inline unsigned int i915_sg_segment_size(void)
/* Returns true if Gen is in inclusive range [Start, End] */
#define IS_GEN(dev_priv, s, e) \
- (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
+ (!!((dev_priv)->runtime_info.gen_mask & INTEL_GEN_MASK((s), (e))))
/*
* Return true if revision is in range [since,until] inclusive.
@@ -2375,7 +2375,8 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
+#define IS_PLATFORM(dev_priv, p) \
+ ((dev_priv)->runtime_info.platform_mask & BIT(p))
#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
@@ -2524,16 +2525,19 @@ static inline unsigned int i915_sg_segment_size(void)
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6)))
-#define IS_GEN8(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7)))
-#define IS_GEN9(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8)))
-#define IS_GEN10(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10)))
+#define __IS_GEN(dev_priv, g) \
+ (!!((dev_priv)->runtime_info.gen_mask & BIT((g) - 1)))
+
+#define IS_GEN2(dev_priv) __IS_GEN(dev_priv, 2)
+#define IS_GEN3(dev_priv) __IS_GEN(dev_priv, 3)
+#define IS_GEN4(dev_priv) __IS_GEN(dev_priv, 4)
+#define IS_GEN5(dev_priv) __IS_GEN(dev_priv, 5)
+#define IS_GEN6(dev_priv) __IS_GEN(dev_priv, 6)
+#define IS_GEN7(dev_priv) __IS_GEN(dev_priv, 7)
+#define IS_GEN8(dev_priv) __IS_GEN(dev_priv, 8)
+#define IS_GEN9(dev_priv) __IS_GEN(dev_priv, 9)
+#define IS_GEN10(dev_priv) __IS_GEN(dev_priv, 10)
+#define IS_GEN11(dev_priv) __IS_GEN(dev_priv, 11)
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8eb16c54648f..4fff59249932 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -29,8 +29,8 @@
#include "i915_drv.h"
#include "i915_selftest.h"
-#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
-#define GEN(x) .__gen = (x), .gen_mask = BIT((x) - 1)
+#define PLATFORM(x) .platform = (x)
+#define GEN(x) .__gen = (x)
#define GEN_DEFAULT_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 9bacd466f4a2..f9e577ccf775 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -148,15 +148,12 @@ struct sseu_dev_info {
typedef u8 intel_ring_mask_t;
struct intel_device_info {
- u16 gen_mask;
-
u8 __gen;
u8 gt; /* GT number, 0 if undefined */
intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
u8 __num_pipes;
enum intel_platform platform;
- u32 platform_mask;
enum intel_ppgtt __ppgtt;
unsigned int __page_sizes; /* page sizes supported by the HW */
@@ -188,11 +185,14 @@ struct intel_device_info {
struct intel_runtime_device_info {
int gen;
+ u32 platform_mask;
+
unsigned int num_rings;
enum intel_ppgtt ppgtt;
unsigned int page_sizes; /* page sizes supported by the HW */
+ u16 gen_mask;
u16 device_id;
intel_ring_mask_t ring_mask; /* Rings supported by the HW */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index def498402bbb..b226aae22a03 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1683,7 +1683,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
GEM_BUG_ON(entry->size > 8);
GEM_BUG_ON(entry_offset & (entry->size - 1));
- if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
+ if (dev_priv->runtime_info.gen_mask & entry->gen_mask &&
entry_offset == (reg->offset & -entry->size))
break;
entry++;
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
` (4 preceding siblings ...)
2018-11-12 17:12 ` [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info Tvrtko Ursulin
@ 2018-11-12 17:12 ` Tvrtko Ursulin
2018-11-12 17:29 ` Chris Wilson
2018-11-13 11:40 ` Jani Nikula
2018-11-12 17:12 ` [RFC 7/7] drm/i915: Remove double underscore from static device info member names Tvrtko Ursulin
` (3 subsequent siblings)
9 siblings, 2 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Introduce subplatform mask to eliminate throughout the code devid checking
sprinkle, mostly courtesy of IS_*_UL[TX] macros.
Subplatform mask initialization is done at runtime device info init.
v2: Fixed IS_SUBPLATFORM. Updated commit msg.
v3: Chris was right, there is an ordering problem.
v4: Drop mask sharing, rename title, rebase.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 59 +++++++++------------
drivers/gpu/drm/i915/intel_device_info.c | 65 ++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_device_info.h | 18 +++++++
4 files changed, 108 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4f5ddc3d2f4d..14c199438978 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1688,6 +1688,8 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
runtime_info->gen_mask = BIT(INTEL_GEN(i915) - 1);
runtime_info->platform_mask = BIT(device_info->platform);
+ intel_device_info_subplatform_init(i915);
+
return i915;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 283592dd7023..4ec4a6308fe4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2377,6 +2377,10 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_PLATFORM(dev_priv, p) \
((dev_priv)->runtime_info.platform_mask & BIT(p))
+#define IS_SUBPLATFORM(dev_priv, p, s) \
+ (IS_PLATFORM(dev_priv, p) && \
+ ((dev_priv)->runtime_info.subplatform_mask & \
+ BIT(INTEL_SUBPLATFORM_##s)))
#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
@@ -2391,11 +2395,15 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
-#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
-#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
+#define IS_PINEVIEW_G(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_PINEVIEW, PINEVIEW_G)
+#define IS_PINEVIEW_M(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_PINEVIEW, PINEVIEW_M)
#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
-#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
+#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
+#define IS_IRONLAKE_M(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_IRONLAKE, IRONLAKE_M)
#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 1)
@@ -2413,40 +2421,20 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
- ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
- (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
- (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
-/* ULX machines are also considered ULT. */
-#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
+#define IS_BDW_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, ULT)
+#define IS_BDW_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, ULX)
#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
-#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
+#define IS_HSW_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, ULT)
#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
/* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
- INTEL_DEVID(dev_priv) == 0x0A1E)
-#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
- INTEL_DEVID(dev_priv) == 0x1913 || \
- INTEL_DEVID(dev_priv) == 0x1916 || \
- INTEL_DEVID(dev_priv) == 0x1921 || \
- INTEL_DEVID(dev_priv) == 0x1926)
-#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
- INTEL_DEVID(dev_priv) == 0x1915 || \
- INTEL_DEVID(dev_priv) == 0x191E)
-#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
- INTEL_DEVID(dev_priv) == 0x5913 || \
- INTEL_DEVID(dev_priv) == 0x5916 || \
- INTEL_DEVID(dev_priv) == 0x5921 || \
- INTEL_DEVID(dev_priv) == 0x5926)
-#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
- INTEL_DEVID(dev_priv) == 0x5915 || \
- INTEL_DEVID(dev_priv) == 0x591E)
-#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
- INTEL_DEVID(dev_priv) == 0x87C0)
+#define IS_HSW_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, ULX)
+#define IS_SKL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, ULT)
+#define IS_SKL_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, ULX)
+#define IS_KBL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, ULT)
+#define IS_KBL_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, ULX)
+#define IS_AML_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, AML)
#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 2)
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
@@ -2457,14 +2445,13 @@ static inline unsigned int i915_sg_segment_size(void)
INTEL_INFO(dev_priv)->gt == 2)
#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, ULT)
#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
+#define IS_CNL_WITH_PORT_F(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, PORTF)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 00758d11047b..b9d08428f35b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -118,6 +118,8 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
drm_printf(p, "CS timestamp frequency: %u kHz\n",
info->cs_timestamp_frequency_khz);
+ drm_printf(p, "Subplatform mask: %x\n", info->subplatform_mask);
+
intel_runtime_device_info_dump_flags(info, p);
}
@@ -727,6 +729,69 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
return 0;
}
+void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+{
+ struct intel_runtime_device_info *info = &i915->runtime_info;
+ u16 devid = INTEL_DEVID(i915);
+
+ if (IS_PINEVIEW(i915)) {
+ if (devid == 0xa001)
+ info->subplatform_mask =
+ BIT(INTEL_SUBPLATFORM_PINEVIEW_G);
+ else if (devid == 0xa011)
+ info->subplatform_mask =
+ BIT(INTEL_SUBPLATFORM_PINEVIEW_M);
+ } else if (IS_IRONLAKE(i915) && devid == 0x0046) {
+ info->subplatform_mask =
+ BIT(INTEL_SUBPLATFORM_IRONLAKE_M);
+ } else if (IS_HASWELL(i915)) {
+ if ((devid & 0xFF00) == 0x0A00)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
+ /* ULX machines are also considered ULT. */
+ if (devid == 0x0A0E || devid == 0x0A1E)
+ info->subplatform_mask |= BIT(INTEL_SUBPLATFORM_ULX);
+ } else if (IS_BROADWELL(i915)) {
+ if ((devid & 0xf) == 0x6 ||
+ (devid & 0xf) == 0xb ||
+ (devid & 0xf) == 0xe)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
+ /* ULX machines are also considered ULT. */
+ if ((devid & 0xf) == 0xe)
+ info->subplatform_mask |= BIT(INTEL_SUBPLATFORM_ULX);
+ } else if (IS_SKYLAKE(i915)) {
+ if (devid == 0x1906 ||
+ devid == 0x1913 ||
+ devid == 0x1916 ||
+ devid == 0x1921 ||
+ devid == 0x1926)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
+ else if (devid == 0x190E ||
+ devid == 0x1915 ||
+ devid == 0x191E)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULX);
+ } else if (IS_KABYLAKE(i915)) {
+ if (devid == 0x591c ||
+ devid == 0x87c0)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_AML);
+ else if (devid == 0x5906 ||
+ devid == 0x5913 ||
+ devid == 0x5916 ||
+ devid == 0x5921 ||
+ devid == 0x5926)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
+ else if (devid == 0x590E ||
+ devid == 0x5915 ||
+ devid == 0x591E)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULX);
+ } else if (IS_COFFEELAKE(i915)) {
+ if ((devid & 0x00F0) == 0x00A0)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
+ } else if (IS_CANNONLAKE(i915)) {
+ if ((devid & 0x0004) == 0x0004)
+ info->subplatform_mask = BIT(INTEL_SUBPLATFORM_PORTF);
+ }
+}
+
/**
* intel_device_info_runtime_init - initialize runtime info
* @info: intel device info struct
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f9e577ccf775..91f163039949 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -182,10 +182,27 @@ struct intel_device_info {
func(has_rc6); \
func(has_rc6p); \
+/*
+ * Subplatform bits share the same namespace per parent platform. In other words
+ * it is fine for the same bit to be used on multiple parent platform.
+ */
+#define INTEL_SUBPLATFORM_IRONLAKE_M (0)
+
+#define INTEL_SUBPLATFORM_PINEVIEW_G (0)
+#define INTEL_SUBPLATFORM_PINEVIEW_M (1)
+
+/* SKL/KBL */
+#define INTEL_SUBPLATFORM_ULT (0)
+#define INTEL_SUBPLATFORM_ULX (1)
+#define INTEL_SUBPLATFORM_AML (2)
+
+#define INTEL_SUBPLATFORM_PORTF (0)
+
struct intel_runtime_device_info {
int gen;
u32 platform_mask;
+ u32 subplatform_mask;
unsigned int num_rings;
@@ -270,6 +287,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
+void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv,
struct drm_printer *p);
void intel_device_info_dump_flags(const struct intel_device_info *info,
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC 7/7] drm/i915: Remove double underscore from static device info member names
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
` (5 preceding siblings ...)
2018-11-12 17:12 ` [RFC 6/7] drm/i915: Introduce subplatform concept Tvrtko Ursulin
@ 2018-11-12 17:12 ` Tvrtko Ursulin
2018-11-12 17:34 ` ✗ Fi.CI.CHECKPATCH: warning for mkwrite_device_info removal Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-12 17:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Now that the device info data is truly const and all call sites have been
converted we can rely on read-only protection to notify us of any
mistakes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
Or it may be a good idea to leave the double underscore in for protecting
the in flight patches or in fact any future work.
---
drivers/gpu/drm/i915/i915_drv.c | 18 ++--
drivers/gpu/drm/i915/i915_pci.c | 114 +++++++++++------------
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 16 ++--
4 files changed, 75 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 14c199438978..83e711b9f2f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1668,14 +1668,14 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
* Copy over entries that are both set statically but can also be
* modified at runtime.
*/
- runtime_info->gen = device_info->__gen;
- runtime_info->has_fbc = device_info->__has_fbc;
- runtime_info->has_rc6 = device_info->__has_rc6;
- runtime_info->has_rc6p = device_info->__has_rc6p;
- runtime_info->ppgtt = device_info->__ppgtt;
- runtime_info->page_sizes = device_info->__page_sizes;
- runtime_info->ring_mask = device_info->__ring_mask;
- runtime_info->num_pipes = device_info->__num_pipes;
+ runtime_info->gen = device_info->gen;
+ runtime_info->has_fbc = device_info->has_fbc;
+ runtime_info->has_rc6 = device_info->has_rc6;
+ runtime_info->has_rc6p = device_info->has_rc6p;
+ runtime_info->ppgtt = device_info->ppgtt;
+ runtime_info->page_sizes = device_info->page_sizes;
+ runtime_info->ring_mask = device_info->ring_mask;
+ runtime_info->num_pipes = device_info->num_pipes;
/*
* Initialize GEN and platform masks.
@@ -1727,7 +1727,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
return PTR_ERR(dev_priv);
/* Disable nuclear pageflip by default on pre-ILK */
- if (!i915_modparams.nuclear_pageflip && match_info->__gen < 5)
+ if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
ret = pci_enable_device(pdev);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4fff59249932..983f538de519 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -30,7 +30,7 @@
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x)
-#define GEN(x) .__gen = (x)
+#define GEN(x) .gen = (x)
#define GEN_DEFAULT_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
@@ -60,16 +60,16 @@
/* Keep in gen based order, and chronological order within a gen */
#define GEN_DEFAULT_PAGE_SIZES \
- .__page_sizes = I915_GTT_PAGE_SIZE_4K
+ .page_sizes = I915_GTT_PAGE_SIZE_4K
#define GEN2_FEATURES \
GEN(2), \
- .__num_pipes = 1, \
+ .num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
.has_gmch_display = 1, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .__ring_mask = RENDER_RING, \
+ .ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -80,7 +80,7 @@ static const struct intel_device_info intel_i830_info = {
GEN2_FEATURES,
PLATFORM(INTEL_I830),
.is_mobile = 1, .cursor_needs_physical = 1,
- .__num_pipes = 2, /* legal, last one wins */
+ .num_pipes = 2, /* legal, last one wins */
};
static const struct intel_device_info intel_i845g_info = {
@@ -92,9 +92,9 @@ static const struct intel_device_info intel_i85x_info = {
GEN2_FEATURES,
PLATFORM(INTEL_I85X),
.is_mobile = 1,
- .__num_pipes = 2, /* legal, last one wins */
+ .num_pipes = 2, /* legal, last one wins */
.cursor_needs_physical = 1,
- .__has_fbc = 1,
+ .has_fbc = 1,
};
static const struct intel_device_info intel_i865g_info = {
@@ -104,9 +104,9 @@ static const struct intel_device_info intel_i865g_info = {
#define GEN3_FEATURES \
GEN(3), \
- .__num_pipes = 2, \
+ .num_pipes = 2, \
.has_gmch_display = 1, \
- .__ring_mask = RENDER_RING, \
+ .ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -130,7 +130,7 @@ static const struct intel_device_info intel_i915gm_info = {
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
- .__has_fbc = 1,
+ .has_fbc = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -151,7 +151,7 @@ static const struct intel_device_info intel_i945gm_info = {
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
- .__has_fbc = 1,
+ .has_fbc = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -173,10 +173,10 @@ static const struct intel_device_info intel_pineview_info = {
#define GEN4_FEATURES \
GEN(4), \
- .__num_pipes = 2, \
+ .num_pipes = 2, \
.has_hotplug = 1, \
.has_gmch_display = 1, \
- .__ring_mask = RENDER_RING, \
+ .ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -194,7 +194,7 @@ static const struct intel_device_info intel_i965g_info = {
static const struct intel_device_info intel_i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
- .is_mobile = 1, .__has_fbc = 1,
+ .is_mobile = 1, .has_fbc = 1,
.has_overlay = 1,
.supports_tv = 1,
.hws_needs_physical = 1,
@@ -204,26 +204,26 @@ static const struct intel_device_info intel_i965gm_info = {
static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
- .__ring_mask = RENDER_RING | BSD_RING,
+ .ring_mask = RENDER_RING | BSD_RING,
};
static const struct intel_device_info intel_gm45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_GM45),
- .is_mobile = 1, .__has_fbc = 1,
+ .is_mobile = 1, .has_fbc = 1,
.supports_tv = 1,
- .__ring_mask = RENDER_RING | BSD_RING,
+ .ring_mask = RENDER_RING | BSD_RING,
};
#define GEN5_FEATURES \
GEN(5), \
- .__num_pipes = 2, \
+ .num_pipes = 2, \
.has_hotplug = 1, \
- .__ring_mask = RENDER_RING | BSD_RING, \
+ .ring_mask = RENDER_RING | BSD_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
/* ilk does support rc6, but we do not implement [power] contexts */ \
- .__has_rc6 = 0, \
+ .has_rc6 = 0, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -236,20 +236,20 @@ static const struct intel_device_info intel_ironlake_d_info = {
static const struct intel_device_info intel_ironlake_m_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
- .is_mobile = 1, .__has_fbc = 1,
+ .is_mobile = 1, .has_fbc = 1,
};
#define GEN6_FEATURES \
GEN(6), \
- .__num_pipes = 2, \
+ .num_pipes = 2, \
.has_hotplug = 1, \
- .__has_fbc = 1, \
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .has_fbc = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
- .__has_rc6 = 1, \
- .__has_rc6p = 1, \
- .__ppgtt = INTEL_PPGTT_ALIASING, \
+ .has_rc6 = 1, \
+ .has_rc6p = 1, \
+ .ppgtt = INTEL_PPGTT_ALIASING, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -286,15 +286,15 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
#define GEN7_FEATURES \
GEN(7), \
- .__num_pipes = 3, \
+ .num_pipes = 3, \
.has_hotplug = 1, \
- .__has_fbc = 1, \
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .has_fbc = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
- .__has_rc6 = 1, \
- .__has_rc6p = 1, \
- .__ppgtt = INTEL_PPGTT_FULL, \
+ .has_rc6 = 1, \
+ .has_rc6p = 1, \
+ .ppgtt = INTEL_PPGTT_FULL, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
@@ -334,7 +334,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
.gt = 2,
- .__num_pipes = 0, /* legal, last one wins */
+ .num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
@@ -342,15 +342,15 @@ static const struct intel_device_info intel_valleyview_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .__num_pipes = 2,
+ .num_pipes = 2,
.has_runtime_pm = 1,
- .__has_rc6 = 1,
+ .has_rc6 = 1,
.has_gmch_display = 1,
.has_hotplug = 1,
- .__ppgtt = INTEL_PPGTT_FULL,
+ .ppgtt = INTEL_PPGTT_FULL,
.has_snoop = true,
.has_coherent_ggtt = false,
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_PIPEOFFSETS,
@@ -359,12 +359,12 @@ static const struct intel_device_info intel_valleyview_info = {
#define G75_FEATURES \
GEN7_FEATURES, \
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
.has_ddi = 1, \
.has_fpga_dbg = 1, \
.has_psr = 1, \
.has_dp_mst = 1, \
- .__has_rc6p = 0 /* RC6p removed-by HSW */, \
+ .has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
#define HSW_PLATFORM \
@@ -391,10 +391,10 @@ static const struct intel_device_info intel_haswell_gt3_info = {
G75_FEATURES, \
GEN(8), \
BDW_COLORS, \
- .__page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ .page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
- .__ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt = INTEL_PPGTT_FULL_4LVL, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -423,22 +423,22 @@ static const struct intel_device_info intel_broadwell_rsvd_info = {
static const struct intel_device_info intel_broadwell_gt3_info = {
BDW_PLATFORM,
.gt = 3,
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
static const struct intel_device_info intel_cherryview_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .__num_pipes = 3,
+ .num_pipes = 3,
.has_hotplug = 1,
.is_lp = 1,
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.has_64bit_reloc = 1,
.has_runtime_pm = 1,
- .__has_rc6 = 1,
+ .has_rc6 = 1,
.has_logical_ring_contexts = 1,
.has_gmch_display = 1,
- .__ppgtt = INTEL_PPGTT_FULL,
+ .ppgtt = INTEL_PPGTT_FULL,
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
@@ -450,7 +450,7 @@ static const struct intel_device_info intel_cherryview_info = {
};
#define GEN9_DEFAULT_PAGE_SIZES \
- .__page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ .page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_64K | \
I915_GTT_PAGE_SIZE_2M
@@ -482,7 +482,7 @@ static const struct intel_device_info intel_skylake_gt2_info = {
#define SKL_GT3_PLUS_PLATFORM \
SKL_PLATFORM, \
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
static const struct intel_device_info intel_skylake_gt3_info = {
@@ -499,21 +499,21 @@ static const struct intel_device_info intel_skylake_gt4_info = {
GEN(9), \
.is_lp = 1, \
.has_hotplug = 1, \
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
- .__num_pipes = 3, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .num_pipes = 3, \
.has_64bit_reloc = 1, \
.has_ddi = 1, \
.has_fpga_dbg = 1, \
- .__has_fbc = 1, \
+ .has_fbc = 1, \
.has_psr = 1, \
.has_runtime_pm = 1, \
.has_csr = 1, \
- .__has_rc6 = 1, \
+ .has_rc6 = 1, \
.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
- .__ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt = INTEL_PPGTT_FULL_4LVL, \
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
@@ -553,7 +553,7 @@ static const struct intel_device_info intel_kabylake_gt2_info = {
static const struct intel_device_info intel_kabylake_gt3_info = {
KBL_PLATFORM,
.gt = 3,
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
#define CFL_PLATFORM \
@@ -573,7 +573,7 @@ static const struct intel_device_info intel_coffeelake_gt2_info = {
static const struct intel_device_info intel_coffeelake_gt3_info = {
CFL_PLATFORM,
.gt = 3,
- .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
#define GEN10_FEATURES \
@@ -605,7 +605,7 @@ static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
.is_alpha_support = 1,
- .__ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
+ .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
};
#undef GEN
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b9d08428f35b..6c2f6bec6156 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -130,7 +130,7 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv,
INTEL_DEVID(dev_priv),
INTEL_REVID(dev_priv),
intel_platform_name(INTEL_INFO(dev_priv)->platform),
- INTEL_INFO(dev_priv)->__gen);
+ INTEL_GEN(dev_priv));
intel_device_info_dump_flags(INTEL_INFO(dev_priv), p);
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 91f163039949..8060a2713bac 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -93,7 +93,7 @@ enum intel_ppgtt {
func(has_ddi); \
func(has_dp_mst); \
func(has_reset_engine); \
- func(__has_fbc); \
+ func(has_fbc); \
func(has_fpga_dbg); \
func(has_gmch_display); \
func(has_guc); \
@@ -106,8 +106,8 @@ enum intel_ppgtt {
func(has_logical_ring_preemption); \
func(has_overlay); \
func(has_psr); \
- func(__has_rc6); \
- func(__has_rc6p); \
+ func(has_rc6); \
+ func(has_rc6p); \
func(has_runtime_pm); \
func(has_snoop); \
func(has_coherent_ggtt); \
@@ -148,15 +148,15 @@ struct sseu_dev_info {
typedef u8 intel_ring_mask_t;
struct intel_device_info {
- u8 __gen;
+ u8 gen;
u8 gt; /* GT number, 0 if undefined */
- intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
- u8 __num_pipes;
+ intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+ u8 num_pipes;
enum intel_platform platform;
- enum intel_ppgtt __ppgtt;
- unsigned int __page_sizes; /* page sizes supported by the HW */
+ enum intel_ppgtt ppgtt;
+ unsigned int page_sizes; /* page sizes supported by the HW */
u32 display_mmio_offset;
--
2.19.1
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info
2018-11-12 17:12 ` [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info Tvrtko Ursulin
@ 2018-11-12 17:24 ` Chris Wilson
2018-11-13 9:13 ` Tvrtko Ursulin
2018-11-12 21:22 ` Lucas De Marchi
1 sibling, 1 reply; 39+ messages in thread
From: Chris Wilson @ 2018-11-12 17:24 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin; +Cc: Jani Nikula
Quoting Tvrtko Ursulin (2018-11-12 17:12:38)
> struct intel_device_info {
> - u16 device_id;
> u16 gen_mask;
>
> - u8 gen;
> + u8 __gen;
> u8 gt; /* GT number, 0 if undefined */
> - intel_ring_mask_t ring_mask; /* Rings supported by the HW */
> - u8 num_pipes;
> + intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
> + u8 __num_pipes;
>
> enum intel_platform platform;
> u32 platform_mask;
>
> - enum intel_ppgtt ppgtt;
> - unsigned int page_sizes; /* page sizes supported by the HW */
> + enum intel_ppgtt __ppgtt;
ppgtt mode is static.
-Chris
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-12 17:12 ` [RFC 4/7] drm/i915: Remove mkwrite_device_info Tvrtko Ursulin
@ 2018-11-12 17:25 ` Chris Wilson
2018-11-13 9:16 ` Tvrtko Ursulin
2018-11-13 11:45 ` Jani Nikula
1 sibling, 1 reply; 39+ messages in thread
From: Chris Wilson @ 2018-11-12 17:25 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin; +Cc: Jani Nikula
Quoting Tvrtko Ursulin (2018-11-12 17:12:39)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Now that we are down to one caller, which does not even modify copied
> device info, we can remove the mkwrite_device_info helper and convert the
> device info pointer itself to be a pointer to static table instead of a
> copy.
The copy was deliberate to avoid the extra pointer. How does the change
in code size now compare?
-Chris
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-12 17:12 ` [RFC 6/7] drm/i915: Introduce subplatform concept Tvrtko Ursulin
@ 2018-11-12 17:29 ` Chris Wilson
2018-11-13 9:17 ` Tvrtko Ursulin
2018-11-13 11:40 ` Jani Nikula
1 sibling, 1 reply; 39+ messages in thread
From: Chris Wilson @ 2018-11-12 17:29 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin; +Cc: Jani Nikula
Quoting Tvrtko Ursulin (2018-11-12 17:12:41)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 00758d11047b..b9d08428f35b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -118,6 +118,8 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
> drm_printf(p, "CS timestamp frequency: %u kHz\n",
> info->cs_timestamp_frequency_khz);
>
> + drm_printf(p, "Subplatform mask: %x\n", info->subplatform_mask);
Any chance for a magic decoder ring? Quick identification of ult/ulx I
think would be very nice.
-Chris
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 1/7] drm/i915: Remove has_pooled_eu static initializer
2018-11-12 17:12 ` [RFC 1/7] drm/i915: Remove has_pooled_eu static initializer Tvrtko Ursulin
@ 2018-11-12 17:29 ` Ville Syrjälä
0 siblings, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2018-11-12 17:29 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx
On Mon, Nov 12, 2018 at 05:12:36PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> It is only initialized to zero once so does not need an explicit
> initializer.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 4ccab8372dd4..e6e7fcdf0ab7 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -507,7 +507,6 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> .has_fbc = 1, \
> .has_psr = 1, \
> .has_runtime_pm = 1, \
> - .has_pooled_eu = 0, \
> .has_csr = 1, \
> .has_rc6 = 1, \
> .has_dp_mst = 1, \
I'm always a bit wary with the way we inherit these macros. But this
one looks safe since it's only ever unitialized at runtime, and also
this macro (GEN9_LP_FEATURES despite what diff says) doesn't currently
inherit anything.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
PS. I wonder if there any magic trick we could do to make these
diffs actually legible?
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 39+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for mkwrite_device_info removal
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
` (6 preceding siblings ...)
2018-11-12 17:12 ` [RFC 7/7] drm/i915: Remove double underscore from static device info member names Tvrtko Ursulin
@ 2018-11-12 17:34 ` Patchwork
2018-11-12 17:37 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-12 17:50 ` ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2018-11-12 17:34 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: mkwrite_device_info removal
URL : https://patchwork.freedesktop.org/series/52381/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5d13c3c4a414 drm/i915: Remove has_pooled_eu static initializer
fb31d94b767b drm/i915: Introduce runtime device info
-:315: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#315: FILE: drivers/gpu/drm/i915/intel_device_info.c:86:
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
-:315: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#315: FILE: drivers/gpu/drm/i915/intel_device_info.c:86:
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
-:571: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#571: FILE: drivers/gpu/drm/i915/intel_device_info.h:183:
+#define DEV_RUNTIME_INFO_FOR_EACH_FLAG(func) \
+ func(has_pooled_eu); \
+
-:639: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#639: FILE: drivers/gpu/drm/i915/intel_display.h:108:
+#define sprite_name(p, s) ((p) * dev_priv->runtime_info.num_sprites[(p)] + (s) + 'A')
total: 0 errors, 2 warnings, 2 checks, 709 lines checked
4048ffe0db39 drm/i915: Move all runtime modified device info fields into runtime info
-:9: WARNING:TYPO_SPELLING: 'overriden' may be misspelled - perhaps 'overridden'?
#9:
there, but can be overriden at runtime.
-:113: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#113: FILE: drivers/gpu/drm/i915/i915_drv.c:1665:
+ BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
-:275: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#275: FILE: drivers/gpu/drm/i915/i915_pci.c:33:
+#define GEN(x) .__gen = (x), .gen_mask = BIT((x) - 1)
total: 0 errors, 2 warnings, 1 checks, 972 lines checked
0f083e1ac103 drm/i915: Remove mkwrite_device_info
-:44: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#44: FILE: drivers/gpu/drm/i915/i915_drv.c:1657:
+ i915->info = device_info = match_info;
-:329: WARNING:LONG_LINE: line over 100 characters
#329: FILE: drivers/gpu/drm/i915/i915_reg.h:186:
+ INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
-:332: WARNING:LONG_LINE: line over 100 characters
#332: FILE: drivers/gpu/drm/i915/i915_reg.h:189:
+ INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
total: 0 errors, 2 warnings, 1 checks, 636 lines checked
5df06a41ec00 drm/i915: Move gen and platform mask to runtime device info
-:38: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#38: FILE: drivers/gpu/drm/i915/i915_drv.c:1686:
+ BUG_ON(INTEL_GEN(i915) > BITS_PER_TYPE(runtime_info->gen_mask));
total: 0 errors, 1 warnings, 0 checks, 120 lines checked
f2178767efa7 drm/i915: Introduce subplatform concept
-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#41: FILE: drivers/gpu/drm/i915/i915_drv.h:2380:
+#define IS_SUBPLATFORM(dev_priv, p, s) \
+ (IS_PLATFORM(dev_priv, p) && \
+ ((dev_priv)->runtime_info.subplatform_mask & \
+ BIT(INTEL_SUBPLATFORM_##s)))
-:164: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 24)
#164: FILE: drivers/gpu/drm/i915/intel_device_info.c:744:
+ } else if (IS_IRONLAKE(i915) && devid == 0x0046) {
+ info->subplatform_mask =
total: 0 errors, 1 warnings, 1 checks, 213 lines checked
a5943656b1ec drm/i915: Remove double underscore from static device info member names
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 2/7] drm/i915: Introduce runtime device info
2018-11-12 17:12 ` [RFC 2/7] drm/i915: Introduce runtime device info Tvrtko Ursulin
@ 2018-11-12 17:36 ` Ville Syrjälä
2018-11-13 9:11 ` Tvrtko Ursulin
0 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjälä @ 2018-11-12 17:36 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx
On Mon, Nov 12, 2018 at 05:12:37PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Idea of runtime device info is to contain all fields from the existing
> device info which are modified at runtime.
>
> Initially we move there fields which are never set from the static
> tables ie.: num_rings, num_sprites, num_scalers,
If we accept that num_sprites[fused_off_pipe] can be non-zero
we could keep num_sprites and num_scalers in the static info.
I don't *think* we have any code that would rely on those being
zero.
> cs_timestamp_frequency_khz, sseu and has_pooled_eu.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 27 +++---
> drivers/gpu/drm/i915/i915_drv.c | 17 ++--
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 19 +++--
> drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
> drivers/gpu/drm/i915/i915_perf.c | 5 +-
> drivers/gpu/drm/i915/i915_query.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 82 +++++++++++--------
> drivers/gpu/drm/i915/intel_device_info.h | 42 ++++++----
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_display.h | 6 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 14 ++--
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +-
> drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +-
> drivers/gpu/drm/i915/intel_workarounds.c | 6 +-
> .../gpu/drm/i915/selftests/i915_gem_context.c | 6 +-
> drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +-
> 19 files changed, 144 insertions(+), 106 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 670db5073d70..1b8a3f203b92 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -48,7 +48,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
> seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
>
> intel_device_info_dump_flags(info, &p);
> - intel_device_info_dump_runtime(info, &p);
> + intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
> intel_driver_caps_print(&dev_priv->caps, &p);
>
> kernel_param_lock(THIS_MODULE);
> @@ -3289,7 +3289,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
> seq_printf(m, "Global active requests: %d\n",
> dev_priv->gt.active_requests);
> seq_printf(m, "CS timestamp frequency: %u kHz\n",
> - dev_priv->info.cs_timestamp_frequency_khz);
> + dev_priv->runtime_info.cs_timestamp_frequency_khz);
>
> p = drm_seq_file_printer(m);
> for_each_engine(engine, dev_priv, id)
> @@ -3305,7 +3305,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
>
> - intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
> + intel_device_info_dump_topology(&dev_priv->runtime_info.sseu, &p);
>
> return 0;
> }
> @@ -4341,7 +4341,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> #define SS_MAX 6
> - const struct intel_device_info *info = INTEL_INFO(dev_priv);
> + const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
> u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
> int s, ss;
>
> @@ -4397,7 +4397,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> #define SS_MAX 3
> - const struct intel_device_info *info = INTEL_INFO(dev_priv);
> + const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
> u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
> int s, ss;
>
> @@ -4424,8 +4424,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> sseu->slice_mask |= BIT(s);
>
> if (IS_GEN9_BC(dev_priv))
> - sseu->subslice_mask[s] =
> - INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
> + sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> @@ -4459,10 +4458,10 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
>
> if (sseu->slice_mask) {
> sseu->eu_per_subslice =
> - INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
> + dev_priv->runtime_info.sseu.eu_per_subslice;
> for (s = 0; s < fls(sseu->slice_mask); s++) {
> sseu->subslice_mask[s] =
> - INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
> + dev_priv->runtime_info.sseu.subslice_mask[s];
> }
> sseu->eu_total = sseu->eu_per_subslice *
> sseu_subslice_total(sseu);
> @@ -4470,7 +4469,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
> /* subtract fused off EU(s) from enabled slice(s) */
> for (s = 0; s < fls(sseu->slice_mask); s++) {
> u8 subslice_7eu =
> - INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
> + dev_priv->runtime_info.sseu.subslice_7eu[s];
>
> sseu->eu_total -= hweight8(subslice_7eu);
> }
> @@ -4523,14 +4522,14 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> return -ENODEV;
>
> seq_puts(m, "SSEU Device Info\n");
> - i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
> + i915_print_sseu_info(m, true, &dev_priv->runtime_info.sseu);
>
> seq_puts(m, "SSEU Device Status\n");
> memset(&sseu, 0, sizeof(sseu));
> - sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
> - sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
> + sseu.max_slices = dev_priv->runtime_info.sseu.max_slices;
> + sseu.max_subslices = dev_priv->runtime_info.sseu.max_subslices;
> sseu.max_eus_per_subslice =
> - INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
> + dev_priv->runtime_info.sseu.max_eus_per_subslice;
>
> intel_runtime_pm_get(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b1d23c73c147..9cfd5b145248 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -357,12 +357,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = i915_cmd_parser_get_version(dev_priv);
> break;
> case I915_PARAM_SUBSLICE_TOTAL:
> - value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
> + value = sseu_subslice_total(&dev_priv->runtime_info.sseu);
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_EU_TOTAL:
> - value = INTEL_INFO(dev_priv)->sseu.eu_total;
> + value = dev_priv->runtime_info.sseu.eu_total;
> if (!value)
> return -ENODEV;
> break;
> @@ -379,7 +379,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = HAS_POOLED_EU(dev_priv);
> break;
> case I915_PARAM_MIN_EU_IN_POOL:
> - value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> + value = dev_priv->runtime_info.sseu.min_eu_in_pool;
> break;
> case I915_PARAM_HUC_STATUS:
> value = intel_huc_check_status(&dev_priv->huc);
> @@ -429,17 +429,18 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = intel_engines_has_context_isolation(dev_priv);
> break;
> case I915_PARAM_SLICE_MASK:
> - value = INTEL_INFO(dev_priv)->sseu.slice_mask;
> + value = dev_priv->runtime_info.sseu.slice_mask;
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_SUBSLICE_MASK:
> - value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
> + value = dev_priv->runtime_info.sseu.subslice_mask[0];
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
> - value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
> + value = 1000 *
> + dev_priv->runtime_info.cs_timestamp_frequency_khz;
> break;
> case I915_PARAM_MMAP_GTT_COHERENT:
> value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
> @@ -1372,7 +1373,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
> if (i915_inject_load_failure())
> return -ENODEV;
>
> - intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
> + intel_device_info_runtime_init(dev_priv);
>
> if (HAS_PPGTT(dev_priv)) {
> if (intel_vgpu_active(dev_priv) &&
> @@ -1620,7 +1621,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
> struct drm_printer p = drm_debug_printer("i915 device info:");
>
> intel_device_info_dump(&dev_priv->info, &p);
> - intel_device_info_dump_runtime(&dev_priv->info, &p);
> + intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
> }
>
> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 08d25aa480f7..f677a9936d33 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1589,6 +1589,7 @@ struct drm_i915_private {
> struct kmem_cache *priorities;
>
> const struct intel_device_info info;
> + struct intel_runtime_device_info runtime_info;
> struct intel_driver_caps caps;
>
> /**
> @@ -2663,7 +2664,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
> #define USES_HUC(dev_priv) intel_uc_is_using_huc()
>
> -#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
> +#define HAS_POOLED_EU(dev_priv) ((dev_priv)->runtime_info.has_pooled_eu)
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index c8d8f79688a8..3e872bb1f00a 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -589,15 +589,18 @@ static void print_error_obj(struct drm_i915_error_state_buf *m,
> err_puts(m, "\n");
> }
>
> -static void err_print_capabilities(struct drm_i915_error_state_buf *m,
> - const struct intel_device_info *info,
> - const struct intel_driver_caps *caps)
> +static void
> +err_print_capabilities(struct drm_i915_error_state_buf *m,
> + const struct intel_device_info *info,
> + const struct intel_runtime_device_info *runtime_info,
> + const struct intel_driver_caps *caps)
> {
> struct drm_printer p = i915_error_printer(m);
>
> intel_device_info_dump_flags(info, &p);
> + intel_device_info_dump_runtime(runtime_info, &p);
> intel_driver_caps_print(caps, &p);
> - intel_device_info_dump_topology(&info->sseu, &p);
> + intel_device_info_dump_topology(&runtime_info->sseu, &p);
> }
>
> static void err_print_params(struct drm_i915_error_state_buf *m,
> @@ -829,7 +832,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> if (error->display)
> intel_display_print_error_state(m, error->display);
>
> - err_print_capabilities(m, &error->device_info, &error->driver_caps);
> + err_print_capabilities(m,
> + &error->device_info,
> + &error->runtime_device_info,
> + &error->driver_caps);
> err_print_params(m, &error->params);
> err_print_uc(m, &error->uc);
>
> @@ -1751,6 +1757,9 @@ static void capture_gen_state(struct i915_gpu_state *error)
> memcpy(&error->device_info,
> INTEL_INFO(i915),
> sizeof(error->device_info));
> + memcpy(&error->runtime_device_info,
> + &i915->runtime_info,
> + sizeof(error->runtime_device_info));
> error->driver_caps = i915->caps;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
> index 8710fb18ed74..ede9aa5ae1a2 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
> @@ -45,6 +45,7 @@ struct i915_gpu_state {
> u32 reset_count;
> u32 suspend_count;
> struct intel_device_info device_info;
> + struct intel_runtime_device_info runtime_device_info;
> struct intel_driver_caps driver_caps;
> struct i915_params params;
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2c2b63be7a6c..9054237251c3 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2646,7 +2646,8 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
> static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
> {
> return div64_u64(1000000000ULL * (2ULL << exponent),
> - 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);
> + 1000ULL *
> + dev_priv->runtime_info.cs_timestamp_frequency_khz);
> }
>
> static int
> @@ -3505,7 +3506,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
> spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
>
> oa_sample_rate_hard_limit = 1000 *
> - (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
> + (dev_priv->runtime_info.cs_timestamp_frequency_khz / 2);
> dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
>
> mutex_init(&dev_priv->perf.metrics_lock);
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 6fc4b8eeab42..6b2c6e6873d3 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -13,7 +13,7 @@
> static int query_topology_info(struct drm_i915_private *dev_priv,
> struct drm_i915_query_item *query_item)
> {
> - const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
> + const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 89ed3a84a4fa..8385767aaf08 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -79,6 +79,15 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
> #undef PRINT_FLAG
> }
>
> +void
> +intel_runtime_device_info_dump_flags(const struct intel_runtime_device_info *info,
> + struct drm_printer *p)
> +{
> +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
> + DEV_RUNTIME_INFO_FOR_EACH_FLAG(PRINT_FLAG);
> +#undef PRINT_FLAG
> +}
> +
> static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> {
> int s;
> @@ -100,13 +109,16 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
> }
>
> -void intel_device_info_dump_runtime(const struct intel_device_info *info,
> - struct drm_printer *p)
> +void
> +intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
> + struct drm_printer *p)
> {
> sseu_dump(&info->sseu, p);
>
> drm_printf(p, "CS timestamp frequency: %u kHz\n",
> info->cs_timestamp_frequency_khz);
> +
> + intel_runtime_device_info_dump_flags(info, p);
> }
>
> void intel_device_info_dump(const struct intel_device_info *info,
> @@ -160,7 +172,7 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
>
> static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> + struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> u8 s_en;
> u32 ss_en, ss_en_mask;
> u8 eu_en;
> @@ -199,7 +211,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>
> static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> + struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> const u32 fuse2 = I915_READ(GEN8_FUSE2);
> int s, ss;
> const int eu_mask = 0xff;
> @@ -276,7 +288,7 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
>
> static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> + struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> u32 fuse;
>
> fuse = I915_READ(CHV_FUSE_GT);
> @@ -329,7 +341,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>
> static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> - struct intel_device_info *info = mkwrite_device_info(dev_priv);
> + struct intel_runtime_device_info *info = &dev_priv->runtime_info;
> struct sseu_dev_info *sseu = &info->sseu;
> int s, ss;
> u32 fuse2, eu_disable, subslice_mask;
> @@ -433,7 +445,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>
> static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> + struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> int s, ss;
> u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
>
> @@ -515,8 +527,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
>
> static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> - struct intel_device_info *info = mkwrite_device_info(dev_priv);
> - struct sseu_dev_info *sseu = &info->sseu;
> + struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> u32 fuse1;
> int s, ss;
>
> @@ -524,9 +535,9 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> * There isn't a register to tell us how many slices/subslices. We
> * work off the PCI-ids here.
> */
> - switch (info->gt) {
> + switch (INTEL_INFO(dev_priv)->gt) {
> default:
> - MISSING_CASE(info->gt);
> + MISSING_CASE(INTEL_INFO(dev_priv)->gt);
> /* fall through */
> case 1:
> sseu->slice_mask = BIT(0);
> @@ -735,29 +746,30 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> * - after the PCH has been detected,
> * - before the first usage of the fields it can tweak.
> */
> -void intel_device_info_runtime_init(struct intel_device_info *info)
> +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv =
> - container_of(info, struct drm_i915_private, info);
> + struct intel_device_info *info = mkwrite_device_info(dev_priv);
> + struct intel_runtime_device_info *runtime_info =
> + &dev_priv->runtime_info;
> enum pipe pipe;
>
> if (INTEL_GEN(dev_priv) >= 10) {
> for_each_pipe(dev_priv, pipe)
> - info->num_scalers[pipe] = 2;
> + runtime_info->num_scalers[pipe] = 2;
> } else if (IS_GEN9(dev_priv)) {
> - info->num_scalers[PIPE_A] = 2;
> - info->num_scalers[PIPE_B] = 2;
> - info->num_scalers[PIPE_C] = 1;
> + runtime_info->num_scalers[PIPE_A] = 2;
> + runtime_info->num_scalers[PIPE_B] = 2;
> + runtime_info->num_scalers[PIPE_C] = 1;
> }
>
> BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
>
> if (IS_GEN11(dev_priv))
> for_each_pipe(dev_priv, pipe)
> - info->num_sprites[pipe] = 6;
> + runtime_info->num_sprites[pipe] = 6;
> else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
> for_each_pipe(dev_priv, pipe)
> - info->num_sprites[pipe] = 3;
> + runtime_info->num_sprites[pipe] = 3;
> else if (IS_BROXTON(dev_priv)) {
> /*
> * Skylake and Broxton currently don't expose the topmost plane as its
> @@ -768,15 +780,15 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> * down the line.
> */
>
> - info->num_sprites[PIPE_A] = 2;
> - info->num_sprites[PIPE_B] = 2;
> - info->num_sprites[PIPE_C] = 1;
> + runtime_info->num_sprites[PIPE_A] = 2;
> + runtime_info->num_sprites[PIPE_B] = 2;
> + runtime_info->num_sprites[PIPE_C] = 1;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> - info->num_sprites[pipe] = 2;
> + runtime_info->num_sprites[pipe] = 2;
> } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> - info->num_sprites[pipe] = 1;
> + runtime_info->num_sprites[pipe] = 1;
> }
>
> if (i915_modparams.disable_display) {
> @@ -860,7 +872,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> }
>
> /* Initialize command stream timestamp frequency */
> - info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
> + runtime_info->cs_timestamp_frequency_khz =
> + read_timestamp_frequency(dev_priv);
> }
>
> void intel_driver_caps_print(const struct intel_driver_caps *caps,
> @@ -880,6 +893,8 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
> void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> {
> struct intel_device_info *info = mkwrite_device_info(dev_priv);
> + struct intel_runtime_device_info *runtime_info =
> + &dev_priv->runtime_info;
> u32 media_fuse;
> unsigned int i;
>
> @@ -888,27 +903,28 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
>
> media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
>
> - info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> - info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> - GEN11_GT_VEBOX_DISABLE_SHIFT;
> + runtime_info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> + runtime_info->vebox_enable =
> + (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> + GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> - DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable);
> + DRM_DEBUG_DRIVER("vdbox enable: %04x\n", runtime_info->vdbox_enable);
> for (i = 0; i < I915_MAX_VCS; i++) {
> if (!HAS_ENGINE(dev_priv, _VCS(i)))
> continue;
>
> - if (!(BIT(i) & info->vdbox_enable)) {
> + if (!(BIT(i) & runtime_info->vdbox_enable)) {
> info->ring_mask &= ~ENGINE_MASK(_VCS(i));
> DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
> }
> }
>
> - DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable);
> + DRM_DEBUG_DRIVER("vebox enable: %04x\n", runtime_info->vebox_enable);
> for (i = 0; i < I915_MAX_VECS; i++) {
> if (!HAS_ENGINE(dev_priv, _VECS(i)))
> continue;
>
> - if (!(BIT(i) & info->vebox_enable)) {
> + if (!(BIT(i) & runtime_info->vebox_enable)) {
> info->ring_mask &= ~ENGINE_MASK(_VECS(i));
> DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
> }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 88f97210dc49..83e19ac8e401 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -105,7 +105,6 @@ enum intel_ppgtt {
> func(has_logical_ring_elsq); \
> func(has_logical_ring_preemption); \
> func(has_overlay); \
> - func(has_pooled_eu); \
> func(has_psr); \
> func(has_rc6); \
> func(has_rc6p); \
> @@ -154,8 +153,8 @@ struct intel_device_info {
>
> u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> - u8 num_rings;
> intel_ring_mask_t ring_mask; /* Rings supported by the HW */
> + u8 num_pipes;
>
> enum intel_platform platform;
> u32 platform_mask;
> @@ -165,10 +164,6 @@ struct intel_device_info {
>
> u32 display_mmio_offset;
>
> - u8 num_pipes;
> - u8 num_sprites[I915_MAX_PIPES];
> - u8 num_scalers[I915_MAX_PIPES];
> -
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
> @@ -179,19 +174,33 @@ struct intel_device_info {
> int trans_offsets[I915_MAX_TRANSCODERS];
> int cursor_offsets[I915_MAX_PIPES];
>
> - /* Slice/subslice/EU info */
> - struct sseu_dev_info sseu;
> + struct color_luts {
> + u16 degamma_lut_size;
> + u16 gamma_lut_size;
> + } color;
> +};
>
> - u32 cs_timestamp_frequency_khz;
> +#define DEV_RUNTIME_INFO_FOR_EACH_FLAG(func) \
> + func(has_pooled_eu); \
> +
> +struct intel_runtime_device_info {
> + unsigned int num_rings;
> +
> + u8 num_sprites[I915_MAX_PIPES];
> + u8 num_scalers[I915_MAX_PIPES];
>
> /* Enabled (not fused off) media engine bitmasks. */
> u8 vdbox_enable;
> u8 vebox_enable;
>
> - struct color_luts {
> - u16 degamma_lut_size;
> - u16 gamma_lut_size;
> - } color;
> + u32 cs_timestamp_frequency_khz;
> +
> + /* Slice/subslice/EU info */
> + struct sseu_dev_info sseu;
> +
> +#define DEFINE_FLAG(name) u8 name:1
> + DEV_RUNTIME_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> +#undef DEFINE_FLAG
> };
>
> struct intel_driver_caps {
> @@ -248,13 +257,14 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
>
> const char *intel_platform_name(enum intel_platform platform);
>
> -void intel_device_info_runtime_init(struct intel_device_info *info);
> +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
> void intel_device_info_dump(const struct intel_device_info *info,
> struct drm_printer *p);
> void intel_device_info_dump_flags(const struct intel_device_info *info,
> struct drm_printer *p);
> -void intel_device_info_dump_runtime(const struct intel_device_info *info,
> - struct drm_printer *p);
> +void
> +intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
> + struct drm_printer *p);
> void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a7fa032310ae..cc30bf1172ad 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13892,7 +13892,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int i;
>
> - crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
> + crtc->num_scalers = dev_priv->runtime_info.num_scalers[crtc->pipe];
> if (!crtc->num_scalers)
> return;
>
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..607ddc4a0b11 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -105,7 +105,7 @@ enum i9xx_plane_id {
> };
>
> #define plane_name(p) ((p) + 'A')
> -#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
> +#define sprite_name(p, s) ((p) * dev_priv->runtime_info.num_sprites[(p)] + (s) + 'A')
>
> /*
> * Per-pipe plane identifier.
> @@ -294,12 +294,12 @@ struct intel_link_m_n {
>
> #define for_each_universal_plane(__dev_priv, __pipe, __p) \
> for ((__p) = 0; \
> - (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
> + (__p) < (__dev_priv)->runtime_info.num_sprites[(__pipe)] + 1;\
> (__p)++)
>
> #define for_each_sprite(__dev_priv, __p, __s) \
> for ((__s) = 0; \
> - (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
> + (__s) < (__dev_priv)->runtime_info.num_sprites[(__p)]; \
> (__s)++)
>
> #define for_each_port_masked(__port, __ports_mask) \
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bc147d9e6c92..b464ee0afb85 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -365,7 +365,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
> goto cleanup;
> }
>
> - device_info->num_rings = hweight32(mask);
> + dev_priv->runtime_info.num_rings = hweight32(mask);
>
> i915_check_and_clear_faults(dev_priv);
>
> @@ -807,7 +807,7 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>
> u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> {
> - const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> + const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> u32 mcr_s_ss_select;
> u32 slice = fls(sseu->slice_mask);
> u32 subslice = fls(sseu->subslice_mask[slice]);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 08fd9b12e4d7..cc897f429635 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2343,9 +2343,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
> static u32
> make_rpcs(struct drm_i915_private *dev_priv)
> {
> - bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
> - u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
> - u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
> + bool subslice_pg = dev_priv->runtime_info.sseu.has_subslice_pg;
> + u8 slices = hweight8(dev_priv->runtime_info.sseu.slice_mask);
> + u8 subslices = hweight8(dev_priv->runtime_info.sseu.subslice_mask[0]);
> u32 rpcs = 0;
>
> /*
> @@ -2393,7 +2393,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
> * must make an explicit request through RPCS for full
> * enablement.
> */
> - if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
> + if (dev_priv->runtime_info.sseu.has_slice_pg) {
> u32 mask, val = slices;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> @@ -2421,17 +2421,17 @@ make_rpcs(struct drm_i915_private *dev_priv)
> rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
> }
>
> - if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
> + if (dev_priv->runtime_info.sseu.has_eu_pg) {
> u32 val;
>
> - val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
> + val = dev_priv->runtime_info.sseu.eu_per_subslice <<
> GEN8_RPCS_EU_MIN_SHIFT;
> GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
> val &= GEN8_RPCS_EU_MIN_MASK;
>
> rpcs |= val;
>
> - val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
> + val = dev_priv->runtime_info.sseu.eu_per_subslice <<
> GEN8_RPCS_EU_MAX_SHIFT;
> GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
> val &= GEN8_RPCS_EU_MAX_MASK;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5df7f6e1ab5e..17270d8f1880 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7341,7 +7341,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>
> val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
>
> - switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
> + switch (dev_priv->runtime_info.sseu.eu_total) {
> case 8:
> /* (2 * 4) config */
> rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 87eebc13c0d8..fccebf773461 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1566,7 +1566,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
> const int num_rings =
> /* Use an extended w/a on gen7 if signalling from other rings */
> (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
> - INTEL_INFO(i915)->num_rings - 1 :
> + i915->runtime_info.num_rings - 1 :
> 0;
> bool force_restore = false;
> int len;
> @@ -2231,7 +2231,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>
> engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
>
> - num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
> + num_rings = dev_priv->runtime_info.num_rings - 1;
> engine->emit_breadcrumb_sz += num_rings * 3;
> if (num_rings & 1)
> engine->emit_breadcrumb_sz++;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 8a2270b209b0..db2933d287b8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -94,11 +94,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
>
> #define instdone_slice_mask(dev_priv__) \
> (IS_GEN7(dev_priv__) ? \
> - 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
> + 1 : (dev_priv__)->runtime_info.sseu.slice_mask)
>
> #define instdone_subslice_mask(dev_priv__) \
> (IS_GEN7(dev_priv__) ? \
> - 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
> + 1 : (dev_priv__)->runtime_info.sseu.subslice_mask[0])
>
> #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> for ((slice__) = 0, (subslice__) = 0; \
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index d7176213e3ce..110556d0934f 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -318,7 +318,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
> * Only consider slices where one, and only one, subslice has 7
> * EUs
> */
> - if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
> + if (!is_power_of_2(dev_priv->runtime_info.sseu.subslice_7eu[i]))
> continue;
>
> /*
> @@ -327,7 +327,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
> *
> * -> 0 <= ss <= 3;
> */
> - ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
> + ss = ffs(dev_priv->runtime_info.sseu.subslice_7eu[i]) - 1;
> vals[i] = 3 - ss;
> }
>
> @@ -732,7 +732,7 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>
> static void wa_init_mcr(struct drm_i915_private *dev_priv)
> {
> - const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> + const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
> u32 mcr;
> u32 mcr_slice_subslice_mask;
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 7d82043aff10..4ee3fcff815a 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -627,7 +627,7 @@ static int igt_ctx_exec(void *arg)
> ncontexts++;
> }
> pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n",
> - ncontexts, INTEL_INFO(i915)->num_rings, ndwords);
> + ncontexts, i915->runtime_info.num_rings, ndwords);
>
> dw = 0;
> list_for_each_entry(obj, &objects, st_link) {
> @@ -732,7 +732,7 @@ static int igt_ctx_readonly(void *arg)
> }
> }
> pr_info("Submitted %lu dwords (across %u engines)\n",
> - ndwords, INTEL_INFO(i915)->num_rings);
> + ndwords, i915->runtime_info.num_rings);
>
> dw = 0;
> list_for_each_entry(obj, &objects, st_link) {
> @@ -1064,7 +1064,7 @@ static int igt_vm_isolation(void *arg)
> count += this;
> }
> pr_info("Checked %lu scratch offsets across %d engines\n",
> - count, INTEL_INFO(i915)->num_rings);
> + count, i915->runtime_info.num_rings);
>
> out_rpm:
> intel_runtime_pm_put(i915);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c
> index 94fc0e5c8766..7237a2474805 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
> @@ -719,7 +719,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
>
> pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
> count, flags,
> - INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
> + smoke->i915->runtime_info.num_rings, smoke->ncontext);
> return 0;
> }
>
> @@ -747,7 +747,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
>
> pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
> count, flags,
> - INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
> + smoke->i915->runtime_info.num_rings, smoke->ncontext);
> return 0;
> }
>
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* ✗ Fi.CI.SPARSE: warning for mkwrite_device_info removal
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
` (7 preceding siblings ...)
2018-11-12 17:34 ` ✗ Fi.CI.CHECKPATCH: warning for mkwrite_device_info removal Patchwork
@ 2018-11-12 17:37 ` Patchwork
2018-11-12 17:50 ` ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2018-11-12 17:37 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: mkwrite_device_info removal
URL : https://patchwork.freedesktop.org/series/52381/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Remove has_pooled_eu static initializer
Okay!
Commit: drm/i915: Introduce runtime device info
+drivers/gpu/drm/i915/intel_device_info.c:83:1: warning: symbol 'intel_runtime_device_info_dump_flags' was not declared. Should it be static?
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3714:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3715:16: warning: expression using sizeof(void)
Commit: drm/i915: Move all runtime modified device info fields into runtime info
Okay!
Commit: drm/i915: Remove mkwrite_device_info
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3715:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3702:16: warning: expression using sizeof(void)
Commit: drm/i915: Move gen and platform mask to runtime device info
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3702:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void)
Commit: drm/i915: Introduce subplatform concept
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3693:16: warning: expression using sizeof(void)
Commit: drm/i915: Remove double underscore from static device info member names
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* ✗ Fi.CI.BAT: failure for mkwrite_device_info removal
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
` (8 preceding siblings ...)
2018-11-12 17:37 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-11-12 17:50 ` Patchwork
9 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2018-11-12 17:50 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: mkwrite_device_info removal
URL : https://patchwork.freedesktop.org/series/52381/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5126 -> Patchwork_10807 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10807 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10807, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52381/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10807:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_hangcheck:
fi-bwr-2160: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10807 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
fi-icl-u: PASS -> INCOMPLETE (fdo#107713)
igt@kms_chamelium@common-hpd-after-suspend:
fi-skl-6700k2: PASS -> WARN (fdo#108680)
==== Possible fixes ====
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108680 https://bugs.freedesktop.org/show_bug.cgi?id=108680
== Participating hosts (51 -> 46) ==
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5126 -> Patchwork_10807
CI_DRM_5126: 1465b00c43e237ca0064d75283ef305eea5549a4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10807: a5943656b1ec6860caeb895d33ec25a8ae44b583 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a5943656b1ec drm/i915: Remove double underscore from static device info member names
f2178767efa7 drm/i915: Introduce subplatform concept
5df06a41ec00 drm/i915: Move gen and platform mask to runtime device info
0f083e1ac103 drm/i915: Remove mkwrite_device_info
4048ffe0db39 drm/i915: Move all runtime modified device info fields into runtime info
fb31d94b767b drm/i915: Introduce runtime device info
5d13c3c4a414 drm/i915: Remove has_pooled_eu static initializer
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10807/issues.html
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info
2018-11-12 17:12 ` [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info Tvrtko Ursulin
2018-11-12 17:24 ` Chris Wilson
@ 2018-11-12 21:22 ` Lucas De Marchi
2018-11-13 9:19 ` Tvrtko Ursulin
1 sibling, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2018-11-12 21:22 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx
On Mon, Nov 12, 2018 at 05:12:38PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> After the previous change which cleared the static tables from effectively
> unused storage, we now replicate entries which have defaults set from
> there, but can be overriden at runtime.
>
> For this class of variables all accessor macros and call sites are changed
> to use the runtime version. Therefore at driver load we need to copy over
> these variables from static to the runtime table.
>
> We add double prefixes to the affected device info members to signify they
> are special and to catch all current and future users.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
[...]
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 43ed8b28aeaa..b6849ca11e01 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -174,12 +174,11 @@ struct drm_i915_private *mock_gem_device(void)
> /* Using the global GTT may ask questions about KMS users, so prepare */
> drm_mode_config_init(&i915->drm);
>
> - mkwrite_device_info(i915)->gen = -1;
> + i915->runtime_info.gen = -1;
this seems the only place that is setting gen to something not statically
defined. And it also misses that it'd need to set gen_mask, too.
Could we rather define a device_info for the mock device with the
proper values rather than doing this?
Lucas De Marchi
>
> - mkwrite_device_info(i915)->page_sizes =
> - I915_GTT_PAGE_SIZE_4K |
> - I915_GTT_PAGE_SIZE_64K |
> - I915_GTT_PAGE_SIZE_2M;
> + i915->runtime_info.page_sizes = I915_GTT_PAGE_SIZE_4K |
> + I915_GTT_PAGE_SIZE_64K |
> + I915_GTT_PAGE_SIZE_2M;
>
> mock_uncore_init(i915);
> i915_gem_init__mm(i915);
> @@ -231,7 +230,7 @@ struct drm_i915_private *mock_gem_device(void)
>
> mock_init_ggtt(i915);
>
> - mkwrite_device_info(i915)->ring_mask = BIT(0);
> + i915->runtime_info.ring_mask = BIT(0);
> i915->kernel_context = mock_context(i915, NULL);
> if (!i915->kernel_context)
> goto err_unlock;
> --
> 2.19.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 2/7] drm/i915: Introduce runtime device info
2018-11-12 17:36 ` Ville Syrjälä
@ 2018-11-13 9:11 ` Tvrtko Ursulin
0 siblings, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 9:11 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, Intel-gfx
On 12/11/2018 17:36, Ville Syrjälä wrote:
> On Mon, Nov 12, 2018 at 05:12:37PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Idea of runtime device info is to contain all fields from the existing
>> device info which are modified at runtime.
>>
>> Initially we move there fields which are never set from the static
>> tables ie.: num_rings, num_sprites, num_scalers,
>
> If we accept that num_sprites[fused_off_pipe] can be non-zero
> we could keep num_sprites and num_scalers in the static info.
> I don't *think* we have any code that would rely on those being
> zero.
Works for me, that is, I don't have a strong opinion on this one. If
display folks agree on this direction you can either implement this
ahead, or I can incorporate the move in this series.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info
2018-11-12 17:24 ` Chris Wilson
@ 2018-11-13 9:13 ` Tvrtko Ursulin
2018-11-13 9:42 ` Chris Wilson
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 9:13 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx; +Cc: Jani Nikula
On 12/11/2018 17:24, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-11-12 17:12:38)
>> struct intel_device_info {
>> - u16 device_id;
>> u16 gen_mask;
>>
>> - u8 gen;
>> + u8 __gen;
>> u8 gt; /* GT number, 0 if undefined */
>> - intel_ring_mask_t ring_mask; /* Rings supported by the HW */
>> - u8 num_pipes;
>> + intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
>> + u8 __num_pipes;
>>
>> enum intel_platform platform;
>> u32 platform_mask;
>>
>> - enum intel_ppgtt ppgtt;
>> - unsigned int page_sizes; /* page sizes supported by the HW */
>> + enum intel_ppgtt __ppgtt;
>
> ppgtt mode is static.
What about:
@@ -868,7 +867,7 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
if (IS_GEN6(dev_priv) && intel_vtd_active()) {
DRM_INFO("Disabling ppGTT for VT-d support\n");
- info->ppgtt = INTEL_PPGTT_NONE;
+ runtime_info->ppgtt = INTEL_PPGTT_NONE;
}
/* Initialize command stream timestamp frequency */
And:
@@ -1711,7 +1711,7 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+ dev_priv->runtime_info.ppgtt = INTEL_PPGTT_FULL_4LVL;
pdev = dev_priv->drm.pdev;
dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
?
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-12 17:25 ` Chris Wilson
@ 2018-11-13 9:16 ` Tvrtko Ursulin
2018-11-13 11:28 ` Jani Nikula
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 9:16 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx; +Cc: Jani Nikula
On 12/11/2018 17:25, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-11-12 17:12:39)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Now that we are down to one caller, which does not even modify copied
>> device info, we can remove the mkwrite_device_info helper and convert the
>> device info pointer itself to be a pointer to static table instead of a
>> copy.
>
> The copy was deliberate to avoid the extra pointer. How does the change
> in code size now compare?
AFAIR grows a bit, but overall series still ends up overall smaller. I
need to re-run the numbers for more concrete info.
However, if we keep having a copy, ie. do not make device info properly
read-only, are we still interested in splitting the two? Benefit would
be diminished, but presumably people still think it would be worth it?
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-12 17:29 ` Chris Wilson
@ 2018-11-13 9:17 ` Tvrtko Ursulin
0 siblings, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 9:17 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx; +Cc: Jani Nikula
On 12/11/2018 17:29, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-11-12 17:12:41)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 00758d11047b..b9d08428f35b 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -118,6 +118,8 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
>> drm_printf(p, "CS timestamp frequency: %u kHz\n",
>> info->cs_timestamp_frequency_khz);
>>
>> + drm_printf(p, "Subplatform mask: %x\n", info->subplatform_mask);
>
> Any chance for a magic decoder ring? Quick identification of ult/ulx I
> think would be very nice.
Yes I wasn't happy with not doing that myself. So I think it is
definitely needed.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info
2018-11-12 21:22 ` Lucas De Marchi
@ 2018-11-13 9:19 ` Tvrtko Ursulin
0 siblings, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 9:19 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Jani Nikula, Intel-gfx
On 12/11/2018 21:22, Lucas De Marchi wrote:
> On Mon, Nov 12, 2018 at 05:12:38PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> After the previous change which cleared the static tables from effectively
>> unused storage, we now replicate entries which have defaults set from
>> there, but can be overriden at runtime.
>>
>> For this class of variables all accessor macros and call sites are changed
>> to use the runtime version. Therefore at driver load we need to copy over
>> these variables from static to the runtime table.
>>
>> We add double prefixes to the affected device info members to signify they
>> are special and to catch all current and future users.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> ---
>
> [...]
>
>> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> index 43ed8b28aeaa..b6849ca11e01 100644
>> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> @@ -174,12 +174,11 @@ struct drm_i915_private *mock_gem_device(void)
>> /* Using the global GTT may ask questions about KMS users, so prepare */
>> drm_mode_config_init(&i915->drm);
>>
>> - mkwrite_device_info(i915)->gen = -1;
>> + i915->runtime_info.gen = -1;
>
> this seems the only place that is setting gen to something not statically
> defined. And it also misses that it'd need to set gen_mask, too.
>
> Could we rather define a device_info for the mock device with the
> proper values rather than doing this?
That would be indeed preferable and I hated the runtime edit of the gen
myself. For the RFC I just did not spend the time to investigate why the
mock device needs this etc. Marking as TODO.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info
2018-11-13 9:13 ` Tvrtko Ursulin
@ 2018-11-13 9:42 ` Chris Wilson
0 siblings, 0 replies; 39+ messages in thread
From: Chris Wilson @ 2018-11-13 9:42 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin; +Cc: Jani Nikula
Quoting Tvrtko Ursulin (2018-11-13 09:13:47)
>
> On 12/11/2018 17:24, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-12 17:12:38)
> >> struct intel_device_info {
> >> - u16 device_id;
> >> u16 gen_mask;
> >>
> >> - u8 gen;
> >> + u8 __gen;
> >> u8 gt; /* GT number, 0 if undefined */
> >> - intel_ring_mask_t ring_mask; /* Rings supported by the HW */
> >> - u8 num_pipes;
> >> + intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
> >> + u8 __num_pipes;
> >>
> >> enum intel_platform platform;
> >> u32 platform_mask;
> >>
> >> - enum intel_ppgtt ppgtt;
> >> - unsigned int page_sizes; /* page sizes supported by the HW */
> >> + enum intel_ppgtt __ppgtt;
> >
> > ppgtt mode is static.
>
> What about:
>
> @@ -868,7 +867,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> DRM_INFO("Disabling ppGTT for VT-d support\n");
> - info->ppgtt = INTEL_PPGTT_NONE;
> + runtime_info->ppgtt = INTEL_PPGTT_NONE;
Cunning, you see I grepped the patch for the wrong thing (thinking it
was just the markup). We could make it static, but that would devalue the
information stored by ppgtt.
The alternative plan:
- move the disabling ppgtt into aliasing setup
- tag the PD offsets in the error state with [none, aliasing, full]
Advantage: we don't need to worry about runtime_info.pggtt
Disadvantage: extra code to generate equiv of runtime_info.ppgtt for
debugging.
> }
>
> /* Initialize command stream timestamp frequency */
>
> And:
>
> @@ -1711,7 +1711,7 @@ int i915_gem_huge_page_mock_selftests(void)
> return -ENOMEM;
>
> /* Pretend to be a device which supports the 48b PPGTT */
> - mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
> + dev_priv->runtime_info.ppgtt = INTEL_PPGTT_FULL_4LVL;
That can be made static, but drops out later anyway. And when we have
separate ppgtt mode and size, I think it should be static (certainly we
are unlikely to change the ppgtt_size at runtime).
-Chris
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-13 9:16 ` Tvrtko Ursulin
@ 2018-11-13 11:28 ` Jani Nikula
2018-11-13 11:34 ` Chris Wilson
0 siblings, 1 reply; 39+ messages in thread
From: Jani Nikula @ 2018-11-13 11:28 UTC (permalink / raw)
To: Tvrtko Ursulin, Chris Wilson, Intel-gfx
On Tue, 13 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 12/11/2018 17:25, Chris Wilson wrote:
>> Quoting Tvrtko Ursulin (2018-11-12 17:12:39)
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> Now that we are down to one caller, which does not even modify copied
>>> device info, we can remove the mkwrite_device_info helper and convert the
>>> device info pointer itself to be a pointer to static table instead of a
>>> copy.
>>
>> The copy was deliberate to avoid the extra pointer. How does the change
>> in code size now compare?
>
> AFAIR grows a bit, but overall series still ends up overall smaller. I
> need to re-run the numbers for more concrete info.
>
> However, if we keep having a copy, ie. do not make device info properly
> read-only, are we still interested in splitting the two? Benefit would
> be diminished, but presumably people still think it would be worth it?
If we don't turn device info into a pointer to the static const structs,
IMO there's simply no point in any of this. Then we might just as well
drop the const and mkwrite_device_info, and use the mutable thing all
over the place.
Modifying the device info copy was supposed to be an exception at the
time of the copy, but with mkwrite_device_info it has proliferated. It's
silly and ugly and wrong with no benefits. The const was put in place to
hint that it's not supposed to be modified, but that didn't work out.
So which is it, runtime/static split with an extra pointer chase to the
const data in rodata (I'm in favor), or just drop the const from the
dev_priv copy and remove mkwrite_device_info?
The latter makes future attempts at utilizing DCE/LTO with a reduced
number of device infos much harder I think.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info
2018-11-12 17:12 ` [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info Tvrtko Ursulin
@ 2018-11-13 11:30 ` Jani Nikula
2018-11-13 11:48 ` Tvrtko Ursulin
0 siblings, 1 reply; 39+ messages in thread
From: Jani Nikula @ 2018-11-13 11:30 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx
On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> It is more space efficient to store these two at the runtime copy since
> both are trivially derived from the static data.
Any consideration for potential future config option for reduced number
of supported device infos, and compiler optimization on const gen?
BR,
Jani.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 15 +++++++++----
> drivers/gpu/drm/i915/i915_drv.h | 28 ++++++++++++++----------
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> drivers/gpu/drm/i915/intel_device_info.h | 6 ++---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 5 files changed, 33 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 77dd7763b334..4f5ddc3d2f4d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1657,10 +1657,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
> i915->info = device_info = match_info;
> pci_set_drvdata(pdev, &i915->drm);
>
> - BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> - BITS_PER_TYPE(device_info->platform_mask));
> - BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
> -
> /*
> * Early setup of the runtime device info.
> */
> @@ -1681,6 +1677,17 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
> runtime_info->ring_mask = device_info->__ring_mask;
> runtime_info->num_pipes = device_info->__num_pipes;
>
> + /*
> + * Initialize GEN and platform masks.
> + */
> + BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> + BITS_PER_TYPE(runtime_info->platform_mask));
> +
> + BUG_ON(INTEL_GEN(i915) > BITS_PER_TYPE(runtime_info->gen_mask));
> +
> + runtime_info->gen_mask = BIT(INTEL_GEN(i915) - 1);
> + runtime_info->platform_mask = BIT(device_info->platform);
> +
> return i915;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 77ef41d53558..283592dd7023 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2365,7 +2365,7 @@ static inline unsigned int i915_sg_segment_size(void)
>
> /* Returns true if Gen is in inclusive range [Start, End] */
> #define IS_GEN(dev_priv, s, e) \
> - (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
> + (!!((dev_priv)->runtime_info.gen_mask & INTEL_GEN_MASK((s), (e))))
>
> /*
> * Return true if revision is in range [since,until] inclusive.
> @@ -2375,7 +2375,8 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_REVID(p, since, until) \
> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>
> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
> +#define IS_PLATFORM(dev_priv, p) \
> + ((dev_priv)->runtime_info.platform_mask & BIT(p))
>
> #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
> #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
> @@ -2524,16 +2525,19 @@ static inline unsigned int i915_sg_segment_size(void)
> * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
> * chips, etc.).
> */
> -#define IS_GEN2(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1)))
> -#define IS_GEN3(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2)))
> -#define IS_GEN4(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3)))
> -#define IS_GEN5(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4)))
> -#define IS_GEN6(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5)))
> -#define IS_GEN7(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6)))
> -#define IS_GEN8(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7)))
> -#define IS_GEN9(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8)))
> -#define IS_GEN10(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9)))
> -#define IS_GEN11(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10)))
> +#define __IS_GEN(dev_priv, g) \
> + (!!((dev_priv)->runtime_info.gen_mask & BIT((g) - 1)))
> +
> +#define IS_GEN2(dev_priv) __IS_GEN(dev_priv, 2)
> +#define IS_GEN3(dev_priv) __IS_GEN(dev_priv, 3)
> +#define IS_GEN4(dev_priv) __IS_GEN(dev_priv, 4)
> +#define IS_GEN5(dev_priv) __IS_GEN(dev_priv, 5)
> +#define IS_GEN6(dev_priv) __IS_GEN(dev_priv, 6)
> +#define IS_GEN7(dev_priv) __IS_GEN(dev_priv, 7)
> +#define IS_GEN8(dev_priv) __IS_GEN(dev_priv, 8)
> +#define IS_GEN9(dev_priv) __IS_GEN(dev_priv, 9)
> +#define IS_GEN10(dev_priv) __IS_GEN(dev_priv, 10)
> +#define IS_GEN11(dev_priv) __IS_GEN(dev_priv, 11)
>
> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 8eb16c54648f..4fff59249932 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -29,8 +29,8 @@
> #include "i915_drv.h"
> #include "i915_selftest.h"
>
> -#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
> -#define GEN(x) .__gen = (x), .gen_mask = BIT((x) - 1)
> +#define PLATFORM(x) .platform = (x)
> +#define GEN(x) .__gen = (x)
>
> #define GEN_DEFAULT_PIPEOFFSETS \
> .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 9bacd466f4a2..f9e577ccf775 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -148,15 +148,12 @@ struct sseu_dev_info {
> typedef u8 intel_ring_mask_t;
>
> struct intel_device_info {
> - u16 gen_mask;
> -
> u8 __gen;
> u8 gt; /* GT number, 0 if undefined */
> intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
> u8 __num_pipes;
>
> enum intel_platform platform;
> - u32 platform_mask;
>
> enum intel_ppgtt __ppgtt;
> unsigned int __page_sizes; /* page sizes supported by the HW */
> @@ -188,11 +185,14 @@ struct intel_device_info {
> struct intel_runtime_device_info {
> int gen;
>
> + u32 platform_mask;
> +
> unsigned int num_rings;
>
> enum intel_ppgtt ppgtt;
> unsigned int page_sizes; /* page sizes supported by the HW */
>
> + u16 gen_mask;
> u16 device_id;
>
> intel_ring_mask_t ring_mask; /* Rings supported by the HW */
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index def498402bbb..b226aae22a03 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1683,7 +1683,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
> GEM_BUG_ON(entry->size > 8);
> GEM_BUG_ON(entry_offset & (entry->size - 1));
>
> - if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
> + if (dev_priv->runtime_info.gen_mask & entry->gen_mask &&
> entry_offset == (reg->offset & -entry->size))
> break;
> entry++;
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-13 11:28 ` Jani Nikula
@ 2018-11-13 11:34 ` Chris Wilson
0 siblings, 0 replies; 39+ messages in thread
From: Chris Wilson @ 2018-11-13 11:34 UTC (permalink / raw)
To: Intel-gfx, Jani Nikula, Tvrtko Ursulin
Quoting Jani Nikula (2018-11-13 11:28:11)
> On Tue, 13 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> > On 12/11/2018 17:25, Chris Wilson wrote:
> >> Quoting Tvrtko Ursulin (2018-11-12 17:12:39)
> >>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>
> >>> Now that we are down to one caller, which does not even modify copied
> >>> device info, we can remove the mkwrite_device_info helper and convert the
> >>> device info pointer itself to be a pointer to static table instead of a
> >>> copy.
> >>
> >> The copy was deliberate to avoid the extra pointer. How does the change
> >> in code size now compare?
> >
> > AFAIR grows a bit, but overall series still ends up overall smaller. I
> > need to re-run the numbers for more concrete info.
> >
> > However, if we keep having a copy, ie. do not make device info properly
> > read-only, are we still interested in splitting the two? Benefit would
> > be diminished, but presumably people still think it would be worth it?
>
> If we don't turn device info into a pointer to the static const structs,
> IMO there's simply no point in any of this. Then we might just as well
> drop the const and mkwrite_device_info, and use the mutable thing all
> over the place.
>
> Modifying the device info copy was supposed to be an exception at the
> time of the copy, but with mkwrite_device_info it has proliferated. It's
> silly and ugly and wrong with no benefits. The const was put in place to
> hint that it's not supposed to be modified, but that didn't work out.
>
> So which is it, runtime/static split with an extra pointer chase to the
> const data in rodata (I'm in favor), or just drop the const from the
> dev_priv copy and remove mkwrite_device_info?
>
> The latter makes future attempts at utilizing DCE/LTO with a reduced
> number of device infos much harder I think.
The DCE goal is still worthwhile, as is making our constants truly
immutable.
It's just a digression as I remembered one benefit of the copy, and
tracking how much of that benefit remains and could maybe recovered in
other ways is something we can measure.
-Chris
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-12 17:12 ` [RFC 6/7] drm/i915: Introduce subplatform concept Tvrtko Ursulin
2018-11-12 17:29 ` Chris Wilson
@ 2018-11-13 11:40 ` Jani Nikula
2018-11-13 17:11 ` Tvrtko Ursulin
1 sibling, 1 reply; 39+ messages in thread
From: Jani Nikula @ 2018-11-13 11:40 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx
On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Introduce subplatform mask to eliminate throughout the code devid checking
> sprinkle, mostly courtesy of IS_*_UL[TX] macros.
>
> Subplatform mask initialization is done at runtime device info init.
I kind of like the concept, and I like the centralization of devid
checks in one function, but I've always wanted to take this to one step
further: only specify device ids in i915_pciids.h, and *nowhere* else.
It's perhaps too much duplication to create a device info for all these
variants, but I think it would be possible to make the subplatform info
table driven using macros defined in i915_pciids.h.
I think Rodrigo had patches to define CNL port F in terms of num_ports,
but perhaps the subplatform approach works better for that.
BR,
Jani.
>
> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
> v3: Chris was right, there is an ordering problem.
> v4: Drop mask sharing, rename title, rebase.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +
> drivers/gpu/drm/i915/i915_drv.h | 59 +++++++++------------
> drivers/gpu/drm/i915/intel_device_info.c | 65 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_device_info.h | 18 +++++++
> 4 files changed, 108 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4f5ddc3d2f4d..14c199438978 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1688,6 +1688,8 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
> runtime_info->gen_mask = BIT(INTEL_GEN(i915) - 1);
> runtime_info->platform_mask = BIT(device_info->platform);
>
> + intel_device_info_subplatform_init(i915);
> +
> return i915;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 283592dd7023..4ec4a6308fe4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2377,6 +2377,10 @@ static inline unsigned int i915_sg_segment_size(void)
>
> #define IS_PLATFORM(dev_priv, p) \
> ((dev_priv)->runtime_info.platform_mask & BIT(p))
> +#define IS_SUBPLATFORM(dev_priv, p, s) \
> + (IS_PLATFORM(dev_priv, p) && \
> + ((dev_priv)->runtime_info.subplatform_mask & \
> + BIT(INTEL_SUBPLATFORM_##s)))
>
> #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
> #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
> @@ -2391,11 +2395,15 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
> #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
> #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
> -#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
> -#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
> +#define IS_PINEVIEW_G(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_PINEVIEW, PINEVIEW_G)
> +#define IS_PINEVIEW_M(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_PINEVIEW, PINEVIEW_M)
> #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
> #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
> -#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
> +#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
> +#define IS_IRONLAKE_M(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_IRONLAKE, IRONLAKE_M)
> #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
> #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
> INTEL_INFO(dev_priv)->gt == 1)
> @@ -2413,40 +2421,20 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> -#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
> - ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
> - (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
> - (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
> -/* ULX machines are also considered ULT. */
> -#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
> - (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> +#define IS_BDW_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, ULT)
> +#define IS_BDW_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, ULX)
> #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
> INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
> - (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> +#define IS_HSW_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, ULT)
> #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
> INTEL_INFO(dev_priv)->gt == 3)
> /* ULX machines are also considered ULT. */
> -#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
> - INTEL_DEVID(dev_priv) == 0x0A1E)
> -#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
> - INTEL_DEVID(dev_priv) == 0x1913 || \
> - INTEL_DEVID(dev_priv) == 0x1916 || \
> - INTEL_DEVID(dev_priv) == 0x1921 || \
> - INTEL_DEVID(dev_priv) == 0x1926)
> -#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
> - INTEL_DEVID(dev_priv) == 0x1915 || \
> - INTEL_DEVID(dev_priv) == 0x191E)
> -#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
> - INTEL_DEVID(dev_priv) == 0x5913 || \
> - INTEL_DEVID(dev_priv) == 0x5916 || \
> - INTEL_DEVID(dev_priv) == 0x5921 || \
> - INTEL_DEVID(dev_priv) == 0x5926)
> -#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
> - INTEL_DEVID(dev_priv) == 0x5915 || \
> - INTEL_DEVID(dev_priv) == 0x591E)
> -#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
> - INTEL_DEVID(dev_priv) == 0x87C0)
> +#define IS_HSW_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, ULX)
> +#define IS_SKL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, ULT)
> +#define IS_SKL_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, ULX)
> +#define IS_KBL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, ULT)
> +#define IS_KBL_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, ULX)
> +#define IS_AML_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, AML)
> #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
> INTEL_INFO(dev_priv)->gt == 2)
> #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
> @@ -2457,14 +2445,13 @@ static inline unsigned int i915_sg_segment_size(void)
> INTEL_INFO(dev_priv)->gt == 2)
> #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
> INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> +#define IS_CFL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, ULT)
> #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> INTEL_INFO(dev_priv)->gt == 2)
> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> - (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
> +#define IS_CNL_WITH_PORT_F(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, PORTF)
>
> #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 00758d11047b..b9d08428f35b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -118,6 +118,8 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
> drm_printf(p, "CS timestamp frequency: %u kHz\n",
> info->cs_timestamp_frequency_khz);
>
> + drm_printf(p, "Subplatform mask: %x\n", info->subplatform_mask);
> +
> intel_runtime_device_info_dump_flags(info, p);
> }
>
> @@ -727,6 +729,69 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> +void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> +{
> + struct intel_runtime_device_info *info = &i915->runtime_info;
> + u16 devid = INTEL_DEVID(i915);
> +
> + if (IS_PINEVIEW(i915)) {
> + if (devid == 0xa001)
> + info->subplatform_mask =
> + BIT(INTEL_SUBPLATFORM_PINEVIEW_G);
> + else if (devid == 0xa011)
> + info->subplatform_mask =
> + BIT(INTEL_SUBPLATFORM_PINEVIEW_M);
> + } else if (IS_IRONLAKE(i915) && devid == 0x0046) {
> + info->subplatform_mask =
> + BIT(INTEL_SUBPLATFORM_IRONLAKE_M);
> + } else if (IS_HASWELL(i915)) {
> + if ((devid & 0xFF00) == 0x0A00)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
> + /* ULX machines are also considered ULT. */
> + if (devid == 0x0A0E || devid == 0x0A1E)
> + info->subplatform_mask |= BIT(INTEL_SUBPLATFORM_ULX);
> + } else if (IS_BROADWELL(i915)) {
> + if ((devid & 0xf) == 0x6 ||
> + (devid & 0xf) == 0xb ||
> + (devid & 0xf) == 0xe)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
> + /* ULX machines are also considered ULT. */
> + if ((devid & 0xf) == 0xe)
> + info->subplatform_mask |= BIT(INTEL_SUBPLATFORM_ULX);
> + } else if (IS_SKYLAKE(i915)) {
> + if (devid == 0x1906 ||
> + devid == 0x1913 ||
> + devid == 0x1916 ||
> + devid == 0x1921 ||
> + devid == 0x1926)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
> + else if (devid == 0x190E ||
> + devid == 0x1915 ||
> + devid == 0x191E)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULX);
> + } else if (IS_KABYLAKE(i915)) {
> + if (devid == 0x591c ||
> + devid == 0x87c0)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_AML);
> + else if (devid == 0x5906 ||
> + devid == 0x5913 ||
> + devid == 0x5916 ||
> + devid == 0x5921 ||
> + devid == 0x5926)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
> + else if (devid == 0x590E ||
> + devid == 0x5915 ||
> + devid == 0x591E)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULX);
> + } else if (IS_COFFEELAKE(i915)) {
> + if ((devid & 0x00F0) == 0x00A0)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_ULT);
> + } else if (IS_CANNONLAKE(i915)) {
> + if ((devid & 0x0004) == 0x0004)
> + info->subplatform_mask = BIT(INTEL_SUBPLATFORM_PORTF);
> + }
> +}
> +
> /**
> * intel_device_info_runtime_init - initialize runtime info
> * @info: intel device info struct
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index f9e577ccf775..91f163039949 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -182,10 +182,27 @@ struct intel_device_info {
> func(has_rc6); \
> func(has_rc6p); \
>
> +/*
> + * Subplatform bits share the same namespace per parent platform. In other words
> + * it is fine for the same bit to be used on multiple parent platform.
> + */
> +#define INTEL_SUBPLATFORM_IRONLAKE_M (0)
> +
> +#define INTEL_SUBPLATFORM_PINEVIEW_G (0)
> +#define INTEL_SUBPLATFORM_PINEVIEW_M (1)
> +
> +/* SKL/KBL */
> +#define INTEL_SUBPLATFORM_ULT (0)
> +#define INTEL_SUBPLATFORM_ULX (1)
> +#define INTEL_SUBPLATFORM_AML (2)
> +
> +#define INTEL_SUBPLATFORM_PORTF (0)
> +
> struct intel_runtime_device_info {
> int gen;
>
> u32 platform_mask;
> + u32 subplatform_mask;
>
> unsigned int num_rings;
>
> @@ -270,6 +287,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> const char *intel_platform_name(enum intel_platform platform);
>
> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
> +void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
> void intel_device_info_dump(struct drm_i915_private *dev_priv,
> struct drm_printer *p);
> void intel_device_info_dump_flags(const struct intel_device_info *info,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-12 17:12 ` [RFC 4/7] drm/i915: Remove mkwrite_device_info Tvrtko Ursulin
2018-11-12 17:25 ` Chris Wilson
@ 2018-11-13 11:45 ` Jani Nikula
2018-11-13 11:50 ` Jani Nikula
` (2 more replies)
1 sibling, 3 replies; 39+ messages in thread
From: Jani Nikula @ 2018-11-13 11:45 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx
On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Now that we are down to one caller, which does not even modify copied
> device info, we can remove the mkwrite_device_info helper and convert the
> device info pointer itself to be a pointer to static table instead of a
> copy.
>
> Only unfortnate thing is that we need to convert all callsites which were
> referencing the device info directly to using the INTEL_INFO helper.
I'm not sure if that's all that bad. When I was toying around with
mkwrite_device_info removal, I actually started off with changing all
device info references to INTEL_INFO. It's a big patch, but it nicely
centralizes many of the other changes instead of splattering all over
the place.
I'd actually like to see RUNTIME_INFO or similar macro as well, just to
be able to change the way it's handled later on.
BR,
Jani.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 9 +-
> drivers/gpu/drm/i915/i915_drv.h | 107 ++++++-------
> drivers/gpu/drm/i915/i915_reg.h | 190 +++++++++++------------
> drivers/gpu/drm/i915/intel_device_info.c | 11 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 6 files changed, 151 insertions(+), 170 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index bbdd36119eae..77dd7763b334 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1620,7 +1620,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
> if (drm_debug & DRM_UT_DRIVER) {
> struct drm_printer p = drm_debug_printer("i915 device info:");
>
> - intel_device_info_dump(&dev_priv->info, &p);
> + intel_device_info_dump(dev_priv, &p);
> intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
> }
>
> @@ -1638,7 +1638,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
> const struct intel_device_info *match_info =
> (struct intel_device_info *)ent->driver_data;
> struct intel_runtime_device_info *runtime_info;
> - struct intel_device_info *device_info;
> + const struct intel_device_info *device_info;
> struct drm_i915_private *i915;
> int err;
>
> @@ -1654,12 +1654,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>
> i915->drm.pdev = pdev;
> i915->drm.dev_private = i915;
> + i915->info = device_info = match_info;
> pci_set_drvdata(pdev, &i915->drm);
>
> - /* Setup the write-once "constant" device info */
> - device_info = mkwrite_device_info(i915);
> - memcpy(device_info, match_info, sizeof(*device_info));
> -
> BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> BITS_PER_TYPE(device_info->platform_mask));
> BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4fabbcd6cfb2..77ef41d53558 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1588,7 +1588,7 @@ struct drm_i915_private {
> struct kmem_cache *dependencies;
> struct kmem_cache *priorities;
>
> - const struct intel_device_info info;
> + const struct intel_device_info *info;
> struct intel_runtime_device_info runtime_info;
> struct intel_driver_caps caps;
>
> @@ -2349,13 +2349,7 @@ static inline unsigned int i915_sg_segment_size(void)
> return size;
> }
>
> -static inline const struct intel_device_info *
> -intel_info(const struct drm_i915_private *dev_priv)
> -{
> - return &dev_priv->info;
> -}
> -
> -#define INTEL_INFO(dev_priv) intel_info((dev_priv))
> +#define INTEL_INFO(dev_priv) ((dev_priv)->info)
> #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
>
> #define INTEL_GEN(dev_priv) ((dev_priv)->runtime_info.gen)
> @@ -2371,7 +2365,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> /* Returns true if Gen is in inclusive range [Start, End] */
> #define IS_GEN(dev_priv, s, e) \
> - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
> + (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
>
> /*
> * Return true if revision is in range [since,until] inclusive.
> @@ -2381,7 +2375,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_REVID(p, since, until) \
> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>
> -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
> +#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
>
> #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
> #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
> @@ -2403,7 +2397,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
> #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
> #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
> - (dev_priv)->info.gt == 1)
> + INTEL_INFO(dev_priv)->gt == 1)
> #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
> #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
> #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
> @@ -2415,7 +2409,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
> +#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
> @@ -2426,11 +2420,11 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> /* ULX machines are also considered ULT. */
> #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
> INTEL_DEVID(dev_priv) == 0x0A1E)
> @@ -2453,21 +2447,21 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
> INTEL_DEVID(dev_priv) == 0x87C0)
> #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 2)
> + INTEL_INFO(dev_priv)->gt == 2)
> #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 4)
> + INTEL_INFO(dev_priv)->gt == 4)
> #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 2)
> + INTEL_INFO(dev_priv)->gt == 2)
> #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> - (dev_priv)->info.gt == 2)
> + INTEL_INFO(dev_priv)->gt == 2)
> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>
> @@ -2530,16 +2524,16 @@ intel_info(const struct drm_i915_private *dev_priv)
> * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
> * chips, etc.).
> */
> -#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
> -#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
> -#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
> -#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
> -#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
> -#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
> -#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
> -#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
> -#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
> -#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
> +#define IS_GEN2(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1)))
> +#define IS_GEN3(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2)))
> +#define IS_GEN4(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3)))
> +#define IS_GEN5(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4)))
> +#define IS_GEN6(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5)))
> +#define IS_GEN7(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6)))
> +#define IS_GEN8(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7)))
> +#define IS_GEN9(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8)))
> +#define IS_GEN10(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9)))
> +#define IS_GEN11(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10)))
>
> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
> @@ -2566,20 +2560,20 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
>
> -#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
> -#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
> +#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
> #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
> IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
>
> -#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
> +#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
>
> #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
> - ((dev_priv)->info.has_logical_ring_contexts)
> + (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
> #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
> - ((dev_priv)->info.has_logical_ring_elsq)
> + (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
> #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
> - ((dev_priv)->info.has_logical_ring_preemption)
> + (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
>
> #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>
> @@ -2596,9 +2590,9 @@ intel_info(const struct drm_i915_private *dev_priv)
> ((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \
> })
>
> -#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
> +#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->has_overlay)
> #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
> - ((dev_priv)->info.overlay_needs_physical)
> + (INTEL_INFO(dev_priv)->overlay_needs_physical)
>
> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
> @@ -2619,8 +2613,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
> !(IS_I915G(dev_priv) || \
> IS_I915GM(dev_priv)))
> -#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
> -#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
> +#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->supports_tv)
> +#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->has_hotplug)
>
> #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> #define HAS_FBC(dev_priv) ((dev_priv)->runtime_info.has_fbc)
> @@ -2628,30 +2622,30 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> -#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
> +#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->has_dp_mst)
>
> -#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
> -#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
> +#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->has_ddi)
> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
> +#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->has_psr)
>
> #define HAS_RC6(dev_priv) ((dev_priv)->runtime_info.has_rc6)
> #define HAS_RC6p(dev_priv) ((dev_priv)->runtime_info.has_rc6p)
> #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
>
> -#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
> +#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->has_csr)
>
> -#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
> -#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
> +#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
> +#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
>
> -#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
> +#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->has_ipc)
>
> /*
> * For now, anything with a GuC requires uCode loading, and then supports
> * command submission once loaded. But these are logically independent
> * properties, so we have separate macros to test them.
> */
> -#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
> -#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
> +#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
> +#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
>
> @@ -2704,12 +2698,12 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>
> -#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
> +#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->has_gmch_display)
>
> #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
>
> /* DPF == dynamic parity feature */
> -#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
> +#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
> #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
> 2 : HAS_L3_DPF(dev_priv))
>
> @@ -3465,13 +3459,6 @@ static inline void intel_register_dsm_handler(void) { return; }
> static inline void intel_unregister_dsm_handler(void) { return; }
> #endif /* CONFIG_ACPI */
>
> -/* intel_device_info.c */
> -static inline struct intel_device_info *
> -mkwrite_device_info(struct drm_i915_private *dev_priv)
> -{
> - return (struct intel_device_info *)&dev_priv->info;
> -}
> -
> /* modesetting */
> extern void intel_modeset_init_hw(struct drm_device *dev);
> extern int intel_modeset_init(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fe4b913e46ac..4c0e5b62e7fa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -179,15 +179,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> * Device info offset array based helpers for groups of registers with unevenly
> * spaced base offsets.
> */
> -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
> - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
> - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
> - dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
> + INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
> + INTEL_INFO(dev_priv)->display_mmio_offset)
> +#define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
> + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
> + INTEL_INFO(dev_priv)->display_mmio_offset)
> +#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
> + INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
> + INTEL_INFO(dev_priv)->display_mmio_offset)
>
> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
> #define _MASKED_FIELD(mask, value) ({ \
> @@ -3153,9 +3153,9 @@ enum i915_power_well_id {
> /*
> * Clock control & power management
> */
> -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
> -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
> -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
> +#define _DPLL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6014)
> +#define _DPLL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6018)
> +#define _CHV_DPLL_C (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6030)
> #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
>
> #define VGA0 _MMIO(0x6000)
> @@ -3252,9 +3252,9 @@ enum i915_power_well_id {
> #define SDVO_MULTIPLIER_SHIFT_HIRES 4
> #define SDVO_MULTIPLIER_SHIFT_VGA 0
>
> -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
> -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
> -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
> +#define _DPLL_A_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x601c)
> +#define _DPLL_B_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6020)
> +#define _CHV_DPLL_C_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x603c)
> #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
>
> /*
> @@ -3326,7 +3326,7 @@ enum i915_power_well_id {
> #define DSTATE_PLL_D3_OFF (1 << 3)
> #define DSTATE_GFX_CLOCK_GATING (1 << 1)
> #define DSTATE_DOT_CLOCK_GATING (1 << 0)
> -#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
> +#define DSPCLK_GATE_D _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6200)
> # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
> # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
> # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
> @@ -3466,7 +3466,7 @@ enum i915_power_well_id {
> #define _PALETTE_A 0xa000
> #define _PALETTE_B 0xa800
> #define _CHV_PALETTE_C 0xc000
> -#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \
> +#define PALETTE(pipe, i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + \
> _PICK((pipe), _PALETTE_A, \
> _PALETTE_B, _CHV_PALETTE_C) + \
> (i) * 4)
> @@ -4295,7 +4295,7 @@ enum {
>
>
> /* Hotplug control (945+ only) */
> -#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
> +#define PORT_HOTPLUG_EN _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61110)
> #define PORTB_HOTPLUG_INT_EN (1 << 29)
> #define PORTC_HOTPLUG_INT_EN (1 << 28)
> #define PORTD_HOTPLUG_INT_EN (1 << 27)
> @@ -4325,7 +4325,7 @@ enum {
> #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
> #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
>
> -#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
> +#define PORT_HOTPLUG_STAT _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61114)
> /*
> * HDMI/DP bits are g4x+
> *
> @@ -4407,7 +4407,7 @@ enum {
>
> #define PORT_DFT_I9XX _MMIO(0x61150)
> #define DC_BALANCE_RESET (1 << 25)
> -#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
> +#define PORT_DFT2_G4X _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61154)
> #define DC_BALANCE_RESET_VLV (1 << 31)
> #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
> #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
> @@ -4680,7 +4680,7 @@ enum {
> #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
>
> /* Panel fitting */
> -#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
> +#define PFIT_CONTROL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61230)
> #define PFIT_ENABLE (1 << 31)
> #define PFIT_PIPE_MASK (3 << 29)
> #define PFIT_PIPE_SHIFT 29
> @@ -4698,7 +4698,7 @@ enum {
> #define PFIT_SCALING_PROGRAMMED (1 << 26)
> #define PFIT_SCALING_PILLAR (2 << 26)
> #define PFIT_SCALING_LETTER (3 << 26)
> -#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
> +#define PFIT_PGM_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61234)
> /* Pre-965 */
> #define PFIT_VERT_SCALE_SHIFT 20
> #define PFIT_VERT_SCALE_MASK 0xfff00000
> @@ -4710,25 +4710,25 @@ enum {
> #define PFIT_HORIZ_SCALE_SHIFT_965 0
> #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
>
> -#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
> +#define PFIT_AUTO_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61238)
>
> -#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
> -#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
> +#define _VLV_BLC_PWM_CTL2_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250)
> +#define _VLV_BLC_PWM_CTL2_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61350)
> #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
> _VLV_BLC_PWM_CTL2_B)
>
> -#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
> -#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
> +#define _VLV_BLC_PWM_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
> +#define _VLV_BLC_PWM_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61354)
> #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
> _VLV_BLC_PWM_CTL_B)
>
> -#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
> -#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
> +#define _VLV_BLC_HIST_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
> +#define _VLV_BLC_HIST_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61360)
> #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
> _VLV_BLC_HIST_CTL_B)
>
> /* Backlight control */
> -#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
> +#define BLC_PWM_CTL2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250) /* 965+ only */
> #define BLM_PWM_ENABLE (1 << 31)
> #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
> #define BLM_PIPE_SELECT (1 << 29)
> @@ -4751,7 +4751,7 @@ enum {
> #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
> #define BLM_PHASE_IN_INCR_SHIFT (0)
> #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
> -#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
> +#define BLC_PWM_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
> /*
> * This is the most significant 15 bits of the number of backlight cycles in a
> * complete cycle of the modulated backlight control.
> @@ -4773,7 +4773,7 @@ enum {
> #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
>
> -#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
> +#define BLC_HIST_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
> #define BLM_HISTOGRAM_ENABLE (1 << 31)
>
> /* New registers for PCH-split platforms. Safe where new bits show up, the
> @@ -5397,47 +5397,47 @@ enum {
> * is 20 bytes in each direction, hence the 5 fixed
> * data registers
> */
> -#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
> -#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
> -#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
> -#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
> -#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
> -#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
> -
> -#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
> -#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
> -#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
> -#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
> -#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
> -#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
> -
> -#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
> -#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
> -#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
> -#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
> -#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
> -#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
> -
> -#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
> -#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
> -#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
> -#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
> -#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
> -#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
> -
> -#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
> -#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
> -#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
> -#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
> -#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
> -#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
> -
> -#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
> -#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
> -#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
> -#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
> -#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
> -#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
> +#define _DPA_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64010)
> +#define _DPA_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64014)
> +#define _DPA_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64018)
> +#define _DPA_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6401c)
> +#define _DPA_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64020)
> +#define _DPA_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64024)
> +
> +#define _DPB_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64110)
> +#define _DPB_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64114)
> +#define _DPB_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64118)
> +#define _DPB_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6411c)
> +#define _DPB_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64120)
> +#define _DPB_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64124)
> +
> +#define _DPC_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64210)
> +#define _DPC_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64214)
> +#define _DPC_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64218)
> +#define _DPC_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6421c)
> +#define _DPC_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64220)
> +#define _DPC_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64224)
> +
> +#define _DPD_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64310)
> +#define _DPD_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64314)
> +#define _DPD_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64318)
> +#define _DPD_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6431c)
> +#define _DPD_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64320)
> +#define _DPD_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64324)
> +
> +#define _DPE_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64410)
> +#define _DPE_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64414)
> +#define _DPE_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64418)
> +#define _DPE_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6441c)
> +#define _DPE_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64420)
> +#define _DPE_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64424)
> +
> +#define _DPF_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64510)
> +#define _DPF_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64514)
> +#define _DPF_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64518)
> +#define _DPF_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6451c)
> +#define _DPF_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64520)
> +#define _DPF_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64524)
>
> #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> @@ -5713,7 +5713,7 @@ enum {
> #define DPINVGTT_STATUS_MASK 0xff
> #define DPINVGTT_STATUS_MASK_CHV 0xfff
>
> -#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
> +#define DSPARB _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70030)
> #define DSPARB_CSTART_MASK (0x7f << 7)
> #define DSPARB_CSTART_SHIFT 7
> #define DSPARB_BSTART_MASK (0x7f)
> @@ -5748,7 +5748,7 @@ enum {
> #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
>
> /* pnv/gen4/g4x/vlv/chv */
> -#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
> +#define DSPFW1 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70034)
> #define DSPFW_SR_SHIFT 23
> #define DSPFW_SR_MASK (0x1ff << 23)
> #define DSPFW_CURSORB_SHIFT 16
> @@ -5759,7 +5759,7 @@ enum {
> #define DSPFW_PLANEA_SHIFT 0
> #define DSPFW_PLANEA_MASK (0x7f << 0)
> #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
> -#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
> +#define DSPFW2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70038)
> #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
> #define DSPFW_FBC_SR_SHIFT 28
> #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
> @@ -5775,7 +5775,7 @@ enum {
> #define DSPFW_SPRITEA_SHIFT 0
> #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
> #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
> -#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
> +#define DSPFW3 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7003c)
> #define DSPFW_HPLL_SR_EN (1 << 31)
> #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
> #define DSPFW_CURSOR_SR_SHIFT 24
> @@ -6191,35 +6191,35 @@ enum {
> * [10:1f] all
> * [30:32] all
> */
> -#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
> -#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
> -#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
> +#define SWF0(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70410 + (i) * 4)
> +#define SWF1(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71410 + (i) * 4)
> +#define SWF3(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x72414 + (i) * 4)
> #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
>
> /* Pipe B */
> -#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
> -#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
> -#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
> +#define _PIPEBDSL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71000)
> +#define _PIPEBCONF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71008)
> +#define _PIPEBSTAT (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71024)
> #define _PIPEBFRAMEHIGH 0x71040
> #define _PIPEBFRAMEPIXEL 0x71044
> -#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
> -#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
> +#define _PIPEB_FRMCOUNT_G4X (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71040)
> +#define _PIPEB_FLIPCOUNT_G4X (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71044)
>
>
> /* Display B control */
> -#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
> +#define _DSPBCNTR (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71180)
> #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
> #define DISPPLANE_ALPHA_TRANS_DISABLE 0
> #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
> #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
> -#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
> -#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
> -#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
> -#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
> -#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
> -#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
> -#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
> -#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
> +#define _DSPBADDR (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71184)
> +#define _DSPBSTRIDE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71188)
> +#define _DSPBPOS (INTEL_INFO(dev_priv)->display_mmio_offset + 0x7118C)
> +#define _DSPBSIZE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71190)
> +#define _DSPBSURF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x7119C)
> +#define _DSPBTILEOFF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
> +#define _DSPBOFFSET (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
> +#define _DSPBSURFLIVE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711AC)
>
> /* ICL DSI 0 and 1 */
> #define _PIPEDSI0CONF 0x7b008
> @@ -8773,7 +8773,7 @@ enum {
> #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
>
> /* Audio */
> -#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
> +#define G4X_AUD_VID_DID _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x62020)
> #define INTEL_AUDIO_DEVCL 0x808629FB
> #define INTEL_AUDIO_DEVBLC 0x80862801
> #define INTEL_AUDIO_DEVCTG 0x80862802
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index aeb7b9225b18..00758d11047b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -121,19 +121,16 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
> intel_runtime_device_info_dump_flags(info, p);
> }
>
> -void intel_device_info_dump(const struct intel_device_info *info,
> +void intel_device_info_dump(struct drm_i915_private *dev_priv,
> struct drm_printer *p)
> {
> - struct drm_i915_private *dev_priv =
> - container_of(info, struct drm_i915_private, info);
> -
> drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
> INTEL_DEVID(dev_priv),
> INTEL_REVID(dev_priv),
> - intel_platform_name(info->platform),
> - info->__gen);
> + intel_platform_name(INTEL_INFO(dev_priv)->platform),
> + INTEL_INFO(dev_priv)->__gen);
>
> - intel_device_info_dump_flags(info, p);
> + intel_device_info_dump_flags(INTEL_INFO(dev_priv), p);
> }
>
> void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 50c8fda20bdd..9bacd466f4a2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -270,7 +270,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> const char *intel_platform_name(enum intel_platform platform);
>
> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
> -void intel_device_info_dump(const struct intel_device_info *info,
> +void intel_device_info_dump(struct drm_i915_private *dev_priv,
> struct drm_printer *p);
> void intel_device_info_dump_flags(const struct intel_device_info *info,
> struct drm_printer *p);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 9289515108c3..def498402bbb 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2256,7 +2256,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
>
> bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
> {
> - return (dev_priv->info.has_reset_engine &&
> + return (INTEL_INFO(dev_priv)->has_reset_engine &&
> i915_modparams.reset >= 2);
> }
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info
2018-11-13 11:30 ` Jani Nikula
@ 2018-11-13 11:48 ` Tvrtko Ursulin
2018-11-13 11:58 ` Tvrtko Ursulin
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 11:48 UTC (permalink / raw)
To: Jani Nikula, Intel-gfx
On 13/11/2018 11:30, Jani Nikula wrote:
> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> It is more space efficient to store these two at the runtime copy since
>> both are trivially derived from the static data.
>
> Any consideration for potential future config option for reduced number
> of supported device infos, and compiler optimization on const gen?
I of all people should have remember that detail!
Thanks,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-13 11:45 ` Jani Nikula
@ 2018-11-13 11:50 ` Jani Nikula
2018-11-13 11:51 ` Chris Wilson
2018-11-13 17:15 ` Tvrtko Ursulin
2 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2018-11-13 11:50 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx
On Tue, 13 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Now that we are down to one caller, which does not even modify copied
>> device info, we can remove the mkwrite_device_info helper and convert the
>> device info pointer itself to be a pointer to static table instead of a
>> copy.
>>
>> Only unfortnate thing is that we need to convert all callsites which were
>> referencing the device info directly to using the INTEL_INFO helper.
>
> I'm not sure if that's all that bad. When I was toying around with
> mkwrite_device_info removal, I actually started off with changing all
> device info references to INTEL_INFO. It's a big patch, but it nicely
> centralizes many of the other changes instead of splattering all over
> the place.
>
> I'd actually like to see RUNTIME_INFO or similar macro as well, just to
> be able to change the way it's handled later on.
Oh, and it would actually be possible to start off with a RUNTIME_INFO
macro that's just INTEL_INFO, and change all use sites of runtime info
first. Everything still pointing at the same place. Could then proceed
with a runtime copy, and then with actual splitting off of the structs.
Just food for thought, and definitely not a request to restructure the
series. But it might simplify some of the steps.
BR,
Jani.
>
> BR,
> Jani.
>
>
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 9 +-
>> drivers/gpu/drm/i915/i915_drv.h | 107 ++++++-------
>> drivers/gpu/drm/i915/i915_reg.h | 190 +++++++++++------------
>> drivers/gpu/drm/i915/intel_device_info.c | 11 +-
>> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
>> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
>> 6 files changed, 151 insertions(+), 170 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index bbdd36119eae..77dd7763b334 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1620,7 +1620,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>> if (drm_debug & DRM_UT_DRIVER) {
>> struct drm_printer p = drm_debug_printer("i915 device info:");
>>
>> - intel_device_info_dump(&dev_priv->info, &p);
>> + intel_device_info_dump(dev_priv, &p);
>> intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
>> }
>>
>> @@ -1638,7 +1638,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>> const struct intel_device_info *match_info =
>> (struct intel_device_info *)ent->driver_data;
>> struct intel_runtime_device_info *runtime_info;
>> - struct intel_device_info *device_info;
>> + const struct intel_device_info *device_info;
>> struct drm_i915_private *i915;
>> int err;
>>
>> @@ -1654,12 +1654,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>>
>> i915->drm.pdev = pdev;
>> i915->drm.dev_private = i915;
>> + i915->info = device_info = match_info;
>> pci_set_drvdata(pdev, &i915->drm);
>>
>> - /* Setup the write-once "constant" device info */
>> - device_info = mkwrite_device_info(i915);
>> - memcpy(device_info, match_info, sizeof(*device_info));
>> -
>> BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>> BITS_PER_TYPE(device_info->platform_mask));
>> BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 4fabbcd6cfb2..77ef41d53558 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1588,7 +1588,7 @@ struct drm_i915_private {
>> struct kmem_cache *dependencies;
>> struct kmem_cache *priorities;
>>
>> - const struct intel_device_info info;
>> + const struct intel_device_info *info;
>> struct intel_runtime_device_info runtime_info;
>> struct intel_driver_caps caps;
>>
>> @@ -2349,13 +2349,7 @@ static inline unsigned int i915_sg_segment_size(void)
>> return size;
>> }
>>
>> -static inline const struct intel_device_info *
>> -intel_info(const struct drm_i915_private *dev_priv)
>> -{
>> - return &dev_priv->info;
>> -}
>> -
>> -#define INTEL_INFO(dev_priv) intel_info((dev_priv))
>> +#define INTEL_INFO(dev_priv) ((dev_priv)->info)
>> #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
>>
>> #define INTEL_GEN(dev_priv) ((dev_priv)->runtime_info.gen)
>> @@ -2371,7 +2365,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>>
>> /* Returns true if Gen is in inclusive range [Start, End] */
>> #define IS_GEN(dev_priv, s, e) \
>> - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
>> + (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
>>
>> /*
>> * Return true if revision is in range [since,until] inclusive.
>> @@ -2381,7 +2375,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define IS_REVID(p, since, until) \
>> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>>
>> -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
>> +#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
>>
>> #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
>> #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
>> @@ -2403,7 +2397,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
>> #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
>> #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
>> - (dev_priv)->info.gt == 1)
>> + INTEL_INFO(dev_priv)->gt == 1)
>> #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
>> #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
>> #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
>> @@ -2415,7 +2409,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
>> #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>> -#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
>> +#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
>> @@ -2426,11 +2420,11 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
>> #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
>> - (dev_priv)->info.gt == 3)
>> + INTEL_INFO(dev_priv)->gt == 3)
>> #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
>> #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
>> - (dev_priv)->info.gt == 3)
>> + INTEL_INFO(dev_priv)->gt == 3)
>> /* ULX machines are also considered ULT. */
>> #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
>> INTEL_DEVID(dev_priv) == 0x0A1E)
>> @@ -2453,21 +2447,21 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
>> INTEL_DEVID(dev_priv) == 0x87C0)
>> #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
>> - (dev_priv)->info.gt == 2)
>> + INTEL_INFO(dev_priv)->gt == 2)
>> #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
>> - (dev_priv)->info.gt == 3)
>> + INTEL_INFO(dev_priv)->gt == 3)
>> #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
>> - (dev_priv)->info.gt == 4)
>> + INTEL_INFO(dev_priv)->gt == 4)
>> #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
>> - (dev_priv)->info.gt == 2)
>> + INTEL_INFO(dev_priv)->gt == 2)
>> #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
>> - (dev_priv)->info.gt == 3)
>> + INTEL_INFO(dev_priv)->gt == 3)
>> #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
>> #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
>> - (dev_priv)->info.gt == 2)
>> + INTEL_INFO(dev_priv)->gt == 2)
>> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
>> - (dev_priv)->info.gt == 3)
>> + INTEL_INFO(dev_priv)->gt == 3)
>> #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>>
>> @@ -2530,16 +2524,16 @@ intel_info(const struct drm_i915_private *dev_priv)
>> * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
>> * chips, etc.).
>> */
>> -#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
>> -#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
>> -#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
>> -#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
>> -#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
>> -#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
>> -#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
>> -#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
>> -#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
>> -#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
>> +#define IS_GEN2(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1)))
>> +#define IS_GEN3(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2)))
>> +#define IS_GEN4(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3)))
>> +#define IS_GEN5(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4)))
>> +#define IS_GEN6(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5)))
>> +#define IS_GEN7(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6)))
>> +#define IS_GEN8(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7)))
>> +#define IS_GEN9(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8)))
>> +#define IS_GEN10(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9)))
>> +#define IS_GEN11(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10)))
>>
>> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
>> #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
>> @@ -2566,20 +2560,20 @@ intel_info(const struct drm_i915_private *dev_priv)
>>
>> #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
>>
>> -#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
>> -#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
>> +#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
>> +#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
>> #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
>> #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
>> IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
>>
>> -#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
>> +#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
>>
>> #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
>> - ((dev_priv)->info.has_logical_ring_contexts)
>> + (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
>> #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
>> - ((dev_priv)->info.has_logical_ring_elsq)
>> + (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
>> #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
>> - ((dev_priv)->info.has_logical_ring_preemption)
>> + (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
>>
>> #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>>
>> @@ -2596,9 +2590,9 @@ intel_info(const struct drm_i915_private *dev_priv)
>> ((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \
>> })
>>
>> -#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
>> +#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->has_overlay)
>> #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
>> - ((dev_priv)->info.overlay_needs_physical)
>> + (INTEL_INFO(dev_priv)->overlay_needs_physical)
>>
>> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
>> #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
>> @@ -2619,8 +2613,8 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
>> !(IS_I915G(dev_priv) || \
>> IS_I915GM(dev_priv)))
>> -#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
>> -#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
>> +#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->supports_tv)
>> +#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->has_hotplug)
>>
>> #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
>> #define HAS_FBC(dev_priv) ((dev_priv)->runtime_info.has_fbc)
>> @@ -2628,30 +2622,30 @@ intel_info(const struct drm_i915_private *dev_priv)
>>
>> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>>
>> -#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
>> +#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->has_dp_mst)
>>
>> -#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
>> -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
>> -#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
>> +#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->has_ddi)
>> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
>> +#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->has_psr)
>>
>> #define HAS_RC6(dev_priv) ((dev_priv)->runtime_info.has_rc6)
>> #define HAS_RC6p(dev_priv) ((dev_priv)->runtime_info.has_rc6p)
>> #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
>>
>> -#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
>> +#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->has_csr)
>>
>> -#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
>> -#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
>> +#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
>> +#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
>>
>> -#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
>> +#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->has_ipc)
>>
>> /*
>> * For now, anything with a GuC requires uCode loading, and then supports
>> * command submission once loaded. But these are logically independent
>> * properties, so we have separate macros to test them.
>> */
>> -#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
>> -#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
>> +#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
>> +#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
>> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
>> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
>>
>> @@ -2704,12 +2698,12 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
>> #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>>
>> -#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>> +#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->has_gmch_display)
>>
>> #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
>>
>> /* DPF == dynamic parity feature */
>> -#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
>> +#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
>> #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
>> 2 : HAS_L3_DPF(dev_priv))
>>
>> @@ -3465,13 +3459,6 @@ static inline void intel_register_dsm_handler(void) { return; }
>> static inline void intel_unregister_dsm_handler(void) { return; }
>> #endif /* CONFIG_ACPI */
>>
>> -/* intel_device_info.c */
>> -static inline struct intel_device_info *
>> -mkwrite_device_info(struct drm_i915_private *dev_priv)
>> -{
>> - return (struct intel_device_info *)&dev_priv->info;
>> -}
>> -
>> /* modesetting */
>> extern void intel_modeset_init_hw(struct drm_device *dev);
>> extern int intel_modeset_init(struct drm_device *dev);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index fe4b913e46ac..4c0e5b62e7fa 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -179,15 +179,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> * Device info offset array based helpers for groups of registers with unevenly
>> * spaced base offsets.
>> */
>> -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
>> - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
>> - dev_priv->info.display_mmio_offset)
>> -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
>> - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
>> - dev_priv->info.display_mmio_offset)
>> -#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
>> - dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
>> - dev_priv->info.display_mmio_offset)
>> +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
>> + INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
>> + INTEL_INFO(dev_priv)->display_mmio_offset)
>> +#define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
>> + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
>> + INTEL_INFO(dev_priv)->display_mmio_offset)
>> +#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
>> + INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
>> + INTEL_INFO(dev_priv)->display_mmio_offset)
>>
>> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
>> #define _MASKED_FIELD(mask, value) ({ \
>> @@ -3153,9 +3153,9 @@ enum i915_power_well_id {
>> /*
>> * Clock control & power management
>> */
>> -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
>> -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
>> -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
>> +#define _DPLL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6014)
>> +#define _DPLL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6018)
>> +#define _CHV_DPLL_C (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6030)
>> #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
>>
>> #define VGA0 _MMIO(0x6000)
>> @@ -3252,9 +3252,9 @@ enum i915_power_well_id {
>> #define SDVO_MULTIPLIER_SHIFT_HIRES 4
>> #define SDVO_MULTIPLIER_SHIFT_VGA 0
>>
>> -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
>> -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
>> -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
>> +#define _DPLL_A_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x601c)
>> +#define _DPLL_B_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6020)
>> +#define _CHV_DPLL_C_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x603c)
>> #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
>>
>> /*
>> @@ -3326,7 +3326,7 @@ enum i915_power_well_id {
>> #define DSTATE_PLL_D3_OFF (1 << 3)
>> #define DSTATE_GFX_CLOCK_GATING (1 << 1)
>> #define DSTATE_DOT_CLOCK_GATING (1 << 0)
>> -#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
>> +#define DSPCLK_GATE_D _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6200)
>> # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
>> # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
>> # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
>> @@ -3466,7 +3466,7 @@ enum i915_power_well_id {
>> #define _PALETTE_A 0xa000
>> #define _PALETTE_B 0xa800
>> #define _CHV_PALETTE_C 0xc000
>> -#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \
>> +#define PALETTE(pipe, i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + \
>> _PICK((pipe), _PALETTE_A, \
>> _PALETTE_B, _CHV_PALETTE_C) + \
>> (i) * 4)
>> @@ -4295,7 +4295,7 @@ enum {
>>
>>
>> /* Hotplug control (945+ only) */
>> -#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
>> +#define PORT_HOTPLUG_EN _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61110)
>> #define PORTB_HOTPLUG_INT_EN (1 << 29)
>> #define PORTC_HOTPLUG_INT_EN (1 << 28)
>> #define PORTD_HOTPLUG_INT_EN (1 << 27)
>> @@ -4325,7 +4325,7 @@ enum {
>> #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
>> #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
>>
>> -#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
>> +#define PORT_HOTPLUG_STAT _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61114)
>> /*
>> * HDMI/DP bits are g4x+
>> *
>> @@ -4407,7 +4407,7 @@ enum {
>>
>> #define PORT_DFT_I9XX _MMIO(0x61150)
>> #define DC_BALANCE_RESET (1 << 25)
>> -#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
>> +#define PORT_DFT2_G4X _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61154)
>> #define DC_BALANCE_RESET_VLV (1 << 31)
>> #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
>> #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
>> @@ -4680,7 +4680,7 @@ enum {
>> #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
>>
>> /* Panel fitting */
>> -#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
>> +#define PFIT_CONTROL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61230)
>> #define PFIT_ENABLE (1 << 31)
>> #define PFIT_PIPE_MASK (3 << 29)
>> #define PFIT_PIPE_SHIFT 29
>> @@ -4698,7 +4698,7 @@ enum {
>> #define PFIT_SCALING_PROGRAMMED (1 << 26)
>> #define PFIT_SCALING_PILLAR (2 << 26)
>> #define PFIT_SCALING_LETTER (3 << 26)
>> -#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
>> +#define PFIT_PGM_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61234)
>> /* Pre-965 */
>> #define PFIT_VERT_SCALE_SHIFT 20
>> #define PFIT_VERT_SCALE_MASK 0xfff00000
>> @@ -4710,25 +4710,25 @@ enum {
>> #define PFIT_HORIZ_SCALE_SHIFT_965 0
>> #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
>>
>> -#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
>> +#define PFIT_AUTO_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61238)
>>
>> -#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
>> -#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
>> +#define _VLV_BLC_PWM_CTL2_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250)
>> +#define _VLV_BLC_PWM_CTL2_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61350)
>> #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
>> _VLV_BLC_PWM_CTL2_B)
>>
>> -#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
>> -#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
>> +#define _VLV_BLC_PWM_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
>> +#define _VLV_BLC_PWM_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61354)
>> #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
>> _VLV_BLC_PWM_CTL_B)
>>
>> -#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
>> -#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
>> +#define _VLV_BLC_HIST_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
>> +#define _VLV_BLC_HIST_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61360)
>> #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
>> _VLV_BLC_HIST_CTL_B)
>>
>> /* Backlight control */
>> -#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
>> +#define BLC_PWM_CTL2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250) /* 965+ only */
>> #define BLM_PWM_ENABLE (1 << 31)
>> #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
>> #define BLM_PIPE_SELECT (1 << 29)
>> @@ -4751,7 +4751,7 @@ enum {
>> #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
>> #define BLM_PHASE_IN_INCR_SHIFT (0)
>> #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
>> -#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
>> +#define BLC_PWM_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
>> /*
>> * This is the most significant 15 bits of the number of backlight cycles in a
>> * complete cycle of the modulated backlight control.
>> @@ -4773,7 +4773,7 @@ enum {
>> #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
>> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
>>
>> -#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
>> +#define BLC_HIST_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
>> #define BLM_HISTOGRAM_ENABLE (1 << 31)
>>
>> /* New registers for PCH-split platforms. Safe where new bits show up, the
>> @@ -5397,47 +5397,47 @@ enum {
>> * is 20 bytes in each direction, hence the 5 fixed
>> * data registers
>> */
>> -#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
>> -#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
>> -#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
>> -#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
>> -#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
>> -#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
>> -
>> -#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
>> -#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
>> -#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
>> -#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
>> -#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
>> -#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
>> -
>> -#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
>> -#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
>> -#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
>> -#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
>> -#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
>> -#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
>> -
>> -#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
>> -#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
>> -#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
>> -#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
>> -#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
>> -#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
>> -
>> -#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
>> -#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
>> -#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
>> -#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
>> -#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
>> -#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
>> -
>> -#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
>> -#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
>> -#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
>> -#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
>> -#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
>> -#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
>> +#define _DPA_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64010)
>> +#define _DPA_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64014)
>> +#define _DPA_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64018)
>> +#define _DPA_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6401c)
>> +#define _DPA_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64020)
>> +#define _DPA_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64024)
>> +
>> +#define _DPB_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64110)
>> +#define _DPB_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64114)
>> +#define _DPB_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64118)
>> +#define _DPB_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6411c)
>> +#define _DPB_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64120)
>> +#define _DPB_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64124)
>> +
>> +#define _DPC_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64210)
>> +#define _DPC_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64214)
>> +#define _DPC_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64218)
>> +#define _DPC_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6421c)
>> +#define _DPC_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64220)
>> +#define _DPC_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64224)
>> +
>> +#define _DPD_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64310)
>> +#define _DPD_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64314)
>> +#define _DPD_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64318)
>> +#define _DPD_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6431c)
>> +#define _DPD_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64320)
>> +#define _DPD_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64324)
>> +
>> +#define _DPE_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64410)
>> +#define _DPE_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64414)
>> +#define _DPE_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64418)
>> +#define _DPE_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6441c)
>> +#define _DPE_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64420)
>> +#define _DPE_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64424)
>> +
>> +#define _DPF_AUX_CH_CTL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64510)
>> +#define _DPF_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64514)
>> +#define _DPF_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64518)
>> +#define _DPF_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6451c)
>> +#define _DPF_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64520)
>> +#define _DPF_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64524)
>>
>> #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
>> #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>> @@ -5713,7 +5713,7 @@ enum {
>> #define DPINVGTT_STATUS_MASK 0xff
>> #define DPINVGTT_STATUS_MASK_CHV 0xfff
>>
>> -#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
>> +#define DSPARB _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70030)
>> #define DSPARB_CSTART_MASK (0x7f << 7)
>> #define DSPARB_CSTART_SHIFT 7
>> #define DSPARB_BSTART_MASK (0x7f)
>> @@ -5748,7 +5748,7 @@ enum {
>> #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
>>
>> /* pnv/gen4/g4x/vlv/chv */
>> -#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
>> +#define DSPFW1 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70034)
>> #define DSPFW_SR_SHIFT 23
>> #define DSPFW_SR_MASK (0x1ff << 23)
>> #define DSPFW_CURSORB_SHIFT 16
>> @@ -5759,7 +5759,7 @@ enum {
>> #define DSPFW_PLANEA_SHIFT 0
>> #define DSPFW_PLANEA_MASK (0x7f << 0)
>> #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
>> -#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
>> +#define DSPFW2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70038)
>> #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
>> #define DSPFW_FBC_SR_SHIFT 28
>> #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
>> @@ -5775,7 +5775,7 @@ enum {
>> #define DSPFW_SPRITEA_SHIFT 0
>> #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
>> #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
>> -#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
>> +#define DSPFW3 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7003c)
>> #define DSPFW_HPLL_SR_EN (1 << 31)
>> #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
>> #define DSPFW_CURSOR_SR_SHIFT 24
>> @@ -6191,35 +6191,35 @@ enum {
>> * [10:1f] all
>> * [30:32] all
>> */
>> -#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
>> -#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
>> -#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
>> +#define SWF0(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70410 + (i) * 4)
>> +#define SWF1(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71410 + (i) * 4)
>> +#define SWF3(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x72414 + (i) * 4)
>> #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
>>
>> /* Pipe B */
>> -#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
>> -#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
>> -#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
>> +#define _PIPEBDSL (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71000)
>> +#define _PIPEBCONF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71008)
>> +#define _PIPEBSTAT (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71024)
>> #define _PIPEBFRAMEHIGH 0x71040
>> #define _PIPEBFRAMEPIXEL 0x71044
>> -#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
>> -#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
>> +#define _PIPEB_FRMCOUNT_G4X (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71040)
>> +#define _PIPEB_FLIPCOUNT_G4X (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71044)
>>
>>
>> /* Display B control */
>> -#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
>> +#define _DSPBCNTR (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71180)
>> #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
>> #define DISPPLANE_ALPHA_TRANS_DISABLE 0
>> #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
>> #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
>> -#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
>> -#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
>> -#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
>> -#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
>> -#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
>> -#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
>> -#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
>> -#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
>> +#define _DSPBADDR (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71184)
>> +#define _DSPBSTRIDE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71188)
>> +#define _DSPBPOS (INTEL_INFO(dev_priv)->display_mmio_offset + 0x7118C)
>> +#define _DSPBSIZE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71190)
>> +#define _DSPBSURF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x7119C)
>> +#define _DSPBTILEOFF (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
>> +#define _DSPBOFFSET (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
>> +#define _DSPBSURFLIVE (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711AC)
>>
>> /* ICL DSI 0 and 1 */
>> #define _PIPEDSI0CONF 0x7b008
>> @@ -8773,7 +8773,7 @@ enum {
>> #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
>>
>> /* Audio */
>> -#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
>> +#define G4X_AUD_VID_DID _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x62020)
>> #define INTEL_AUDIO_DEVCL 0x808629FB
>> #define INTEL_AUDIO_DEVBLC 0x80862801
>> #define INTEL_AUDIO_DEVCTG 0x80862802
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index aeb7b9225b18..00758d11047b 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -121,19 +121,16 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
>> intel_runtime_device_info_dump_flags(info, p);
>> }
>>
>> -void intel_device_info_dump(const struct intel_device_info *info,
>> +void intel_device_info_dump(struct drm_i915_private *dev_priv,
>> struct drm_printer *p)
>> {
>> - struct drm_i915_private *dev_priv =
>> - container_of(info, struct drm_i915_private, info);
>> -
>> drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
>> INTEL_DEVID(dev_priv),
>> INTEL_REVID(dev_priv),
>> - intel_platform_name(info->platform),
>> - info->__gen);
>> + intel_platform_name(INTEL_INFO(dev_priv)->platform),
>> + INTEL_INFO(dev_priv)->__gen);
>>
>> - intel_device_info_dump_flags(info, p);
>> + intel_device_info_dump_flags(INTEL_INFO(dev_priv), p);
>> }
>>
>> void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 50c8fda20bdd..9bacd466f4a2 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -270,7 +270,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
>> const char *intel_platform_name(enum intel_platform platform);
>>
>> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>> -void intel_device_info_dump(const struct intel_device_info *info,
>> +void intel_device_info_dump(struct drm_i915_private *dev_priv,
>> struct drm_printer *p);
>> void intel_device_info_dump_flags(const struct intel_device_info *info,
>> struct drm_printer *p);
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 9289515108c3..def498402bbb 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -2256,7 +2256,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
>>
>> bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
>> {
>> - return (dev_priv->info.has_reset_engine &&
>> + return (INTEL_INFO(dev_priv)->has_reset_engine &&
>> i915_modparams.reset >= 2);
>> }
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-13 11:45 ` Jani Nikula
2018-11-13 11:50 ` Jani Nikula
@ 2018-11-13 11:51 ` Chris Wilson
2018-11-13 17:33 ` Tvrtko Ursulin
2018-11-13 17:15 ` Tvrtko Ursulin
2 siblings, 1 reply; 39+ messages in thread
From: Chris Wilson @ 2018-11-13 11:51 UTC (permalink / raw)
To: Intel-gfx, Jani Nikula, Tvrtko Ursulin
Quoting Jani Nikula (2018-11-13 11:45:02)
> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >
> > Now that we are down to one caller, which does not even modify copied
> > device info, we can remove the mkwrite_device_info helper and convert the
> > device info pointer itself to be a pointer to static table instead of a
> > copy.
> >
> > Only unfortnate thing is that we need to convert all callsites which were
> > referencing the device info directly to using the INTEL_INFO helper.
>
> I'm not sure if that's all that bad. When I was toying around with
> mkwrite_device_info removal, I actually started off with changing all
> device info references to INTEL_INFO. It's a big patch, but it nicely
> centralizes many of the other changes instead of splattering all over
> the place.
Fwiw, replacing all the static i915->info accesses with INTEL_INFO (or
DEVICE_INFO since STATIC_INFO I think is too confusing with C, and
INTEL_INFO is not distinct enough from RUNTIME_INFO) is perhaps a
pre-requisite for single platform DCE. Along the lines of
#define INTEL_INFO(i915) (&skylake_gt3_info)
-Chris
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info
2018-11-13 11:48 ` Tvrtko Ursulin
@ 2018-11-13 11:58 ` Tvrtko Ursulin
0 siblings, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 11:58 UTC (permalink / raw)
To: Jani Nikula, Intel-gfx
On 13/11/2018 11:48, Tvrtko Ursulin wrote:
>
> On 13/11/2018 11:30, Jani Nikula wrote:
>> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> It is more space efficient to store these two at the runtime copy since
>>> both are trivially derived from the static data.
>>
>> Any consideration for potential future config option for reduced number
>> of supported device infos, and compiler optimization on const gen?
>
> I of all people should have remember that detail!
Remembered... but actually.. AFAIR the Kconfig platform/gen selection
worked on the IS_xxx macro level so that would still work. It wasn't
able to compile time optimize against the runtime device info copy
anyway. So I think this does not interfere. Will keep it in mind.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-13 11:40 ` Jani Nikula
@ 2018-11-13 17:11 ` Tvrtko Ursulin
2018-11-13 22:28 ` Jani Nikula
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 17:11 UTC (permalink / raw)
To: Jani Nikula, Intel-gfx
On 13/11/2018 11:40, Jani Nikula wrote:
> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Introduce subplatform mask to eliminate throughout the code devid checking
>> sprinkle, mostly courtesy of IS_*_UL[TX] macros.
>>
>> Subplatform mask initialization is done at runtime device info init.
>
> I kind of like the concept, and I like the centralization of devid
> checks in one function, but I've always wanted to take this to one step
> further: only specify device ids in i915_pciids.h, and *nowhere* else.
>
> It's perhaps too much duplication to create a device info for all these
> variants, but I think it would be possible to make the subplatform info
> table driven using macros defined in i915_pciids.h.
It would be much nicer, but how would you do it? Perhaps my imagination
is just strong enough today.
Simply by splitting the id's into subplatform parts, for instance where
we have today:
#define INTEL_BDW_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
We'd split to:
#define INTEL_BDW_GT1_ULT_IDS(info) \
INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
#define INTEL_BDW_GT1_ULX_IDS(info) \
INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
#define INTEL_BDW_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
Then in i915_pci.c, instead of:
...
INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
...
We'd have:
...
INTEL_BDW_GT1_ULT_IDS(&intel_broadwell_gt1_info),
INTEL_BDW_GT1_ULX_IDS(&intel_broadwell_gt1_info),
INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
...
And a separate table to map the id's to subplatform values.
Hmm, but we would probably need to extrac the id's from the
INTEL_BDW1_GT_IDS like macros so they can be used in this second site
without the info parameter. Something like the trick for device info
flags, but can it be made to generate a macro? I think not..
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-13 11:45 ` Jani Nikula
2018-11-13 11:50 ` Jani Nikula
2018-11-13 11:51 ` Chris Wilson
@ 2018-11-13 17:15 ` Tvrtko Ursulin
2 siblings, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 17:15 UTC (permalink / raw)
To: Jani Nikula, Intel-gfx
On 13/11/2018 11:45, Jani Nikula wrote:
> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Now that we are down to one caller, which does not even modify copied
>> device info, we can remove the mkwrite_device_info helper and convert the
>> device info pointer itself to be a pointer to static table instead of a
>> copy.
>>
>> Only unfortnate thing is that we need to convert all callsites which were
>> referencing the device info directly to using the INTEL_INFO helper.
>
> I'm not sure if that's all that bad. When I was toying around with
> mkwrite_device_info removal, I actually started off with changing all
> device info references to INTEL_INFO. It's a big patch, but it nicely
> centralizes many of the other changes instead of splattering all over
> the place.
Yes, but then you still need to splat all over the place to change the
same use sites to RUNTIME_INFO or equivalent.
> I'd actually like to see RUNTIME_INFO or similar macro as well, just to
> be able to change the way it's handled later on.
I actually started of with introducing INTEL_RUNTIME_INFO but ended up
backing off with that idea since it looked to "uppercasey". Not saying
that the sprinkle of dev_priv->runtime_info.something is that much
better, but at least it did not hurt my eyes so much. Don't know.. I am
happy to go with popular vote here.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-13 11:51 ` Chris Wilson
@ 2018-11-13 17:33 ` Tvrtko Ursulin
2018-11-13 17:40 ` Chris Wilson
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 17:33 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx, Jani Nikula
On 13/11/2018 11:51, Chris Wilson wrote:
> Quoting Jani Nikula (2018-11-13 11:45:02)
>> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> Now that we are down to one caller, which does not even modify copied
>>> device info, we can remove the mkwrite_device_info helper and convert the
>>> device info pointer itself to be a pointer to static table instead of a
>>> copy.
>>>
>>> Only unfortnate thing is that we need to convert all callsites which were
>>> referencing the device info directly to using the INTEL_INFO helper.
>>
>> I'm not sure if that's all that bad. When I was toying around with
>> mkwrite_device_info removal, I actually started off with changing all
>> device info references to INTEL_INFO. It's a big patch, but it nicely
>> centralizes many of the other changes instead of splattering all over
>> the place.
>
> Fwiw, replacing all the static i915->info accesses with INTEL_INFO (or
> DEVICE_INFO since STATIC_INFO I think is too confusing with C, and
> INTEL_INFO is not distinct enough from RUNTIME_INFO) is perhaps a
You propose DEVICE_INFO for the static part and RUNTIME_INFO for
dynamic, all with INTEL_ prefix?
> pre-requisite for single platform DCE. Along the lines of
> #define INTEL_INFO(i915) (&skylake_gt3_info)
Definitely, and I think this patch changed them all. There weren't that
many.
We also need to minimize the runtime portion for best DCE results. But
AFAIR it was quite good already with just IS_GEN and IS_PLATFORM changes
and not even LTO.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 4/7] drm/i915: Remove mkwrite_device_info
2018-11-13 17:33 ` Tvrtko Ursulin
@ 2018-11-13 17:40 ` Chris Wilson
0 siblings, 0 replies; 39+ messages in thread
From: Chris Wilson @ 2018-11-13 17:40 UTC (permalink / raw)
To: Intel-gfx, Jani Nikula, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2018-11-13 17:33:38)
>
> On 13/11/2018 11:51, Chris Wilson wrote:
> > Quoting Jani Nikula (2018-11-13 11:45:02)
> >> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> >>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>
> >>> Now that we are down to one caller, which does not even modify copied
> >>> device info, we can remove the mkwrite_device_info helper and convert the
> >>> device info pointer itself to be a pointer to static table instead of a
> >>> copy.
> >>>
> >>> Only unfortnate thing is that we need to convert all callsites which were
> >>> referencing the device info directly to using the INTEL_INFO helper.
> >>
> >> I'm not sure if that's all that bad. When I was toying around with
> >> mkwrite_device_info removal, I actually started off with changing all
> >> device info references to INTEL_INFO. It's a big patch, but it nicely
> >> centralizes many of the other changes instead of splattering all over
> >> the place.
> >
> > Fwiw, replacing all the static i915->info accesses with INTEL_INFO (or
> > DEVICE_INFO since STATIC_INFO I think is too confusing with C, and
> > INTEL_INFO is not distinct enough from RUNTIME_INFO) is perhaps a
>
> You propose DEVICE_INFO for the static part and RUNTIME_INFO for
> dynamic, all with INTEL_ prefix?
INTEL_DEVICE_INFO()
INTEL_RUNTIME_INFO()
is getting unwieldy?
I just used DEVICE_INFO() and RUNTIME_INFO(). Although, there aren't
that many direct users of INTEL_*_INFO() so I guess it's not that bad,
and any that are, merit a shorter helper.
-Chris
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-13 17:11 ` Tvrtko Ursulin
@ 2018-11-13 22:28 ` Jani Nikula
2018-11-15 11:03 ` Tvrtko Ursulin
2019-03-25 18:00 ` Tvrtko Ursulin
0 siblings, 2 replies; 39+ messages in thread
From: Jani Nikula @ 2018-11-13 22:28 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx
On Tue, 13 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 13/11/2018 11:40, Jani Nikula wrote:
>> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> Introduce subplatform mask to eliminate throughout the code devid checking
>>> sprinkle, mostly courtesy of IS_*_UL[TX] macros.
>>>
>>> Subplatform mask initialization is done at runtime device info init.
>>
>> I kind of like the concept, and I like the centralization of devid
>> checks in one function, but I've always wanted to take this to one step
>> further: only specify device ids in i915_pciids.h, and *nowhere* else.
>>
>> It's perhaps too much duplication to create a device info for all these
>> variants, but I think it would be possible to make the subplatform info
>> table driven using macros defined in i915_pciids.h.
>
> It would be much nicer, but how would you do it? Perhaps my imagination
> is just strong enough today.
So here's an idea.
>
> Simply by splitting the id's into subplatform parts, for instance where
> we have today:
>
> #define INTEL_BDW_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
>
> We'd split to:
>
> #define INTEL_BDW_GT1_ULT_IDS(info) \
> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>
> #define INTEL_BDW_GT1_ULX_IDS(info) \
> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
So far so good.
>
> #define INTEL_BDW_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
Now include INTEL_BDW_GT1_ULT_IDS(info) and INTEL_BDW_GT1_ULX_IDS(info)
to the above...
>
> Then in i915_pci.c, instead of:
>
> ...
> INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
> ...
>
> We'd have:
>
> ...
> INTEL_BDW_GT1_ULT_IDS(&intel_broadwell_gt1_info),
> INTEL_BDW_GT1_ULX_IDS(&intel_broadwell_gt1_info),
> INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
> ...
...so you don't need to make this change at all. But that's a minor
detail.
> And a separate table to map the id's to subplatform values.
>
> Hmm, but we would probably need to extrac the id's from the
> INTEL_BDW1_GT_IDS like macros so they can be used in this second site
> without the info parameter. Something like the trick for device info
> flags, but can it be made to generate a macro? I think not..
Are we shy of macro magic? Pfft.
#undef INTEL_VGA_DEVICE
#define INTEL_VGA_DEVICE(id, info) (id)
static const u32 bdw_ult_ids[] = {
INTEL_BDW_GT1_ULT_IDS(0),
};
static const u32 bdw_ulx_ids[] = {
INTEL_BDW_GT1_ULX_IDS(0),
};
#undef INTEL_VGA_DEVICE
Now you can add another mapping on top with pointers to similar arrays
as above and corresponding subplatform bits. Just need to order the code
to not clobber the real INTEL_VGA_DEVICE needs.
We don't need to split the ult/ulx tables by platform either if we only
care about the subplatform ult/ulx here, just need to remember add all
ult/ulx in corresponding arrays.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-13 22:28 ` Jani Nikula
@ 2018-11-15 11:03 ` Tvrtko Ursulin
2019-03-25 18:00 ` Tvrtko Ursulin
1 sibling, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2018-11-15 11:03 UTC (permalink / raw)
To: Jani Nikula, Intel-gfx
On 13/11/2018 22:28, Jani Nikula wrote:
> On Tue, 13 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> On 13/11/2018 11:40, Jani Nikula wrote:
>>> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Introduce subplatform mask to eliminate throughout the code devid checking
>>>> sprinkle, mostly courtesy of IS_*_UL[TX] macros.
>>>>
>>>> Subplatform mask initialization is done at runtime device info init.
>>>
>>> I kind of like the concept, and I like the centralization of devid
>>> checks in one function, but I've always wanted to take this to one step
>>> further: only specify device ids in i915_pciids.h, and *nowhere* else.
>>>
>>> It's perhaps too much duplication to create a device info for all these
>>> variants, but I think it would be possible to make the subplatform info
>>> table driven using macros defined in i915_pciids.h.
>>
>> It would be much nicer, but how would you do it? Perhaps my imagination
>> is just strong enough today.
>
> So here's an idea.
>
>>
>> Simply by splitting the id's into subplatform parts, for instance where
>> we have today:
>>
>> #define INTEL_BDW_GT1_IDS(info) \
>> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
>> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
>> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
>> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
>> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
>>
>> We'd split to:
>>
>> #define INTEL_BDW_GT1_ULT_IDS(info) \
>> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
>> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>>
>> #define INTEL_BDW_GT1_ULX_IDS(info) \
>> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
>
> So far so good.
>
>>
>> #define INTEL_BDW_GT1_IDS(info) \
>> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
>> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
>> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
>
> Now include INTEL_BDW_GT1_ULT_IDS(info) and INTEL_BDW_GT1_ULX_IDS(info)
> to the above...
>
>>
>> Then in i915_pci.c, instead of:
>>
>> ...
>> INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
>> ...
>>
>> We'd have:
>>
>> ...
>> INTEL_BDW_GT1_ULT_IDS(&intel_broadwell_gt1_info),
>> INTEL_BDW_GT1_ULX_IDS(&intel_broadwell_gt1_info),
>> INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
>> ...
>
> ...so you don't need to make this change at all. But that's a minor
> detail.
Indeed, makes the change less intrusive.
>> And a separate table to map the id's to subplatform values.
>>
>> Hmm, but we would probably need to extrac the id's from the
>> INTEL_BDW1_GT_IDS like macros so they can be used in this second site
>> without the info parameter. Something like the trick for device info
>> flags, but can it be made to generate a macro? I think not..
>
> Are we shy of macro magic? Pfft.
>
> #undef INTEL_VGA_DEVICE
> #define INTEL_VGA_DEVICE(id, info) (id)
>
> static const u32 bdw_ult_ids[] = {
> INTEL_BDW_GT1_ULT_IDS(0),
> };
>
> static const u32 bdw_ulx_ids[] = {
> INTEL_BDW_GT1_ULX_IDS(0),
> };
>
> #undef INTEL_VGA_DEVICE
>
> Now you can add another mapping on top with pointers to similar arrays
> as above and corresponding subplatform bits. Just need to order the code
> to not clobber the real INTEL_VGA_DEVICE needs.
>
> We don't need to split the ult/ulx tables by platform either if we only
> care about the subplatform ult/ulx here, just need to remember add all
> ult/ulx in corresponding arrays.
Nice and simple, thank you!
I am marking this for when I get round updating the series.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC 6/7] drm/i915: Introduce subplatform concept
2018-11-13 22:28 ` Jani Nikula
2018-11-15 11:03 ` Tvrtko Ursulin
@ 2019-03-25 18:00 ` Tvrtko Ursulin
1 sibling, 0 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2019-03-25 18:00 UTC (permalink / raw)
To: Jani Nikula, Intel-gfx
On 13/11/2018 22:28, Jani Nikula wrote:
> On Tue, 13 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> On 13/11/2018 11:40, Jani Nikula wrote:
>>> On Mon, 12 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Introduce subplatform mask to eliminate throughout the code devid checking
>>>> sprinkle, mostly courtesy of IS_*_UL[TX] macros.
>>>>
>>>> Subplatform mask initialization is done at runtime device info init.
>>>
>>> I kind of like the concept, and I like the centralization of devid
>>> checks in one function, but I've always wanted to take this to one step
>>> further: only specify device ids in i915_pciids.h, and *nowhere* else.
>>>
>>> It's perhaps too much duplication to create a device info for all these
>>> variants, but I think it would be possible to make the subplatform info
>>> table driven using macros defined in i915_pciids.h.
>>
>> It would be much nicer, but how would you do it? Perhaps my imagination
>> is just strong enough today.
>
> So here's an idea.
>
>>
>> Simply by splitting the id's into subplatform parts, for instance where
>> we have today:
>>
>> #define INTEL_BDW_GT1_IDS(info) \
>> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
>> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
>> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
>> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
>> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
>>
>> We'd split to:
>>
>> #define INTEL_BDW_GT1_ULT_IDS(info) \
>> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
>> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>>
>> #define INTEL_BDW_GT1_ULX_IDS(info) \
>> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
>
> So far so good.
>
>>
>> #define INTEL_BDW_GT1_IDS(info) \
>> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
>> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
>> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
>
> Now include INTEL_BDW_GT1_ULT_IDS(info) and INTEL_BDW_GT1_ULX_IDS(info)
> to the above...
>
>>
>> Then in i915_pci.c, instead of:
>>
>> ...
>> INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
>> ...
>>
>> We'd have:
>>
>> ...
>> INTEL_BDW_GT1_ULT_IDS(&intel_broadwell_gt1_info),
>> INTEL_BDW_GT1_ULX_IDS(&intel_broadwell_gt1_info),
>> INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
>> ...
>
> ...so you don't need to make this change at all. But that's a minor
> detail.
>
>> And a separate table to map the id's to subplatform values.
>>
>> Hmm, but we would probably need to extrac the id's from the
>> INTEL_BDW1_GT_IDS like macros so they can be used in this second site
>> without the info parameter. Something like the trick for device info
>> flags, but can it be made to generate a macro? I think not..
>
> Are we shy of macro magic? Pfft.
>
> #undef INTEL_VGA_DEVICE
> #define INTEL_VGA_DEVICE(id, info) (id)
>
> static const u32 bdw_ult_ids[] = {
> INTEL_BDW_GT1_ULT_IDS(0),
> };
>
> static const u32 bdw_ulx_ids[] = {
> INTEL_BDW_GT1_ULX_IDS(0),
> };
>
> #undef INTEL_VGA_DEVICE
>
> Now you can add another mapping on top with pointers to similar arrays
> as above and corresponding subplatform bits. Just need to order the code
> to not clobber the real INTEL_VGA_DEVICE needs.
>
> We don't need to split the ult/ulx tables by platform either if we only
> care about the subplatform ult/ulx here, just need to remember add all
> ult/ulx in corresponding arrays.
I eventually remember this thread/idea and have incorporated it into the
latest series. Only on trybot for now, but you can have a peek if you
want to see if it matches your expectations.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2019-03-25 18:00 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-12 17:12 [RFC 0/7] mkwrite_device_info removal Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 1/7] drm/i915: Remove has_pooled_eu static initializer Tvrtko Ursulin
2018-11-12 17:29 ` Ville Syrjälä
2018-11-12 17:12 ` [RFC 2/7] drm/i915: Introduce runtime device info Tvrtko Ursulin
2018-11-12 17:36 ` Ville Syrjälä
2018-11-13 9:11 ` Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 3/7] drm/i915: Move all runtime modified device info fields into runtime info Tvrtko Ursulin
2018-11-12 17:24 ` Chris Wilson
2018-11-13 9:13 ` Tvrtko Ursulin
2018-11-13 9:42 ` Chris Wilson
2018-11-12 21:22 ` Lucas De Marchi
2018-11-13 9:19 ` Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 4/7] drm/i915: Remove mkwrite_device_info Tvrtko Ursulin
2018-11-12 17:25 ` Chris Wilson
2018-11-13 9:16 ` Tvrtko Ursulin
2018-11-13 11:28 ` Jani Nikula
2018-11-13 11:34 ` Chris Wilson
2018-11-13 11:45 ` Jani Nikula
2018-11-13 11:50 ` Jani Nikula
2018-11-13 11:51 ` Chris Wilson
2018-11-13 17:33 ` Tvrtko Ursulin
2018-11-13 17:40 ` Chris Wilson
2018-11-13 17:15 ` Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 5/7] drm/i915: Move gen and platform mask to runtime device info Tvrtko Ursulin
2018-11-13 11:30 ` Jani Nikula
2018-11-13 11:48 ` Tvrtko Ursulin
2018-11-13 11:58 ` Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 6/7] drm/i915: Introduce subplatform concept Tvrtko Ursulin
2018-11-12 17:29 ` Chris Wilson
2018-11-13 9:17 ` Tvrtko Ursulin
2018-11-13 11:40 ` Jani Nikula
2018-11-13 17:11 ` Tvrtko Ursulin
2018-11-13 22:28 ` Jani Nikula
2018-11-15 11:03 ` Tvrtko Ursulin
2019-03-25 18:00 ` Tvrtko Ursulin
2018-11-12 17:12 ` [RFC 7/7] drm/i915: Remove double underscore from static device info member names Tvrtko Ursulin
2018-11-12 17:34 ` ✗ Fi.CI.CHECKPATCH: warning for mkwrite_device_info removal Patchwork
2018-11-12 17:37 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-12 17:50 ` ✗ Fi.CI.BAT: failure " Patchwork
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