* A question on Linux SMP and cache coherency
@ 2003-01-23 23:21 Adam Kiepul
2003-01-23 23:32 ` Keith Owens
0 siblings, 1 reply; 4+ messages in thread
From: Adam Kiepul @ 2003-01-23 23:21 UTC (permalink / raw)
To: 'linux-mips@linux-mips.org'
Hi,
I would really appreciate if anyone could tell me whether Hardware-maintained cache coherency between processors is required for Linux SMP operation.
Thank you very much,
Adam Kiepul
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: A question on Linux SMP and cache coherency
2003-01-23 23:21 A question on Linux SMP and cache coherency Adam Kiepul
@ 2003-01-23 23:32 ` Keith Owens
0 siblings, 0 replies; 4+ messages in thread
From: Keith Owens @ 2003-01-23 23:32 UTC (permalink / raw)
To: Adam Kiepul; +Cc: 'linux-mips@linux-mips.org'
On Thu, 23 Jan 2003 15:21:01 -0800,
Adam Kiepul <Adam_Kiepul@pmc-sierra.com> wrote:
> I would really appreciate if anyone could tell me whether Hardware-maintained cache coherency between processors is required for Linux SMP operation.
http://www.uwsg.iu.edu/hypermail/linux/kernel/0007.3/1220.html
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: A question on Linux SMP and cache coherency
2003-01-23 23:17 Adam Kiepul
@ 2003-01-24 14:31 ` Ralf Baechle
0 siblings, 0 replies; 4+ messages in thread
From: Ralf Baechle @ 2003-01-24 14:31 UTC (permalink / raw)
To: Adam Kiepul; +Cc: 'linux-mips@linux-mips.org'
On Thu, Jan 23, 2003 at 03:17:25PM -0800, Adam Kiepul wrote:
> I would really appreciate if anyone could tell me whether
> Hardware-maintained cache coherency between processors is required for
> Linux SMP operation.
(Sending just one copy of a posting is sufficient ...)
There have been imho fairly ridiculous attempts at constructing dual-core
SMPs for the use with Linux/MIPS by changing the kernel to 16kB page
size [1] and using write through-caches plus some extra hacks. Needless
to say the solution is about as stupid as something can be and is probably
going to perform worse than a uniprocessor ...
Ralf
[1] good idea for other reasons but completly stupid in this context
^ permalink raw reply [flat|nested] 4+ messages in thread
* A question on Linux SMP and cache coherency
@ 2003-01-23 23:17 Adam Kiepul
2003-01-24 14:31 ` Ralf Baechle
0 siblings, 1 reply; 4+ messages in thread
From: Adam Kiepul @ 2003-01-23 23:17 UTC (permalink / raw)
To: 'linux-mips@linux-mips.org'
Hi,
I would really appreciate if anyone could tell me whether Hardware-maintained cache coherency between processors is required for Linux SMP operation.
Thank you very much,
Adam Kiepul
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2003-01-24 14:31 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2003-01-23 23:21 A question on Linux SMP and cache coherency Adam Kiepul
2003-01-23 23:32 ` Keith Owens
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2003-01-23 23:17 Adam Kiepul
2003-01-24 14:31 ` Ralf Baechle
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