* [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU
@ 2022-02-14 18:31 Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 01/14] meson: Display libfdt as disabled when system emulation is disabled Philippe Mathieu-Daudé via
` (15 more replies)
0 siblings, 16 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
Missing review: 10, 13, 14
Since v1:
- Include Hexagon OBJECT_DECLARE_TYPE() patch
- Add missing includes to Hexagon
- Introduce OBJECT_DECLARE_CPU_TYPE() macro
- Use OBJECT_DECLARE_CPU_TYPE()
Kind of respin of the "exec: Move translation declarations to
'translate-all.h'" series, but without modifying translate-all.h :)
(same same but different).
Based-on: <20220207082756.82600-1-f4bug@amsat.org>
"exec: Remove 'qemu/log.h' from 'exec-all.h'"
Philippe Mathieu-Daudé (13):
meson: Display libfdt as disabled when system emulation is disabled
hw/m68k/mcf: Add missing 'exec/hwaddr.h' header
hw/tricore: Remove unused and incorrect header
exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition
cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers
target/i386/cpu: Ensure accelerators set CPU addressble physical bits
target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header
target: Include missing 'cpu.h'
target/hexagon: Add missing 'hw/core/cpu.h' include
target: Use forward declared type instead of structure type
target: Use CPUArchState as interface to target-specific CPU state
target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
target: Use ArchCPU as interface to target CPU
Taylor Simpson (1):
Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE
cpu.c | 2 ++
include/exec/cpu_ldst.h | 1 +
include/exec/poison.h | 2 --
include/hw/core/cpu.h | 20 +++++++++++++++++++-
include/hw/m68k/mcf.h | 1 +
include/hw/tricore/triboard.h | 1 -
include/qemu/typedefs.h | 2 ++
meson.build | 4 +++-
target/alpha/cpu-qom.h | 3 +--
target/alpha/cpu.h | 11 +++--------
target/arm/cpu-qom.h | 3 +--
target/arm/cpu.h | 7 ++-----
target/arm/hvf_arm.h | 2 +-
target/avr/cpu-qom.h | 3 +--
target/avr/cpu.h | 13 ++++---------
target/cris/cpu-qom.h | 3 +--
target/cris/cpu.h | 7 ++-----
target/hexagon/cpu.h | 23 ++++++++---------------
target/hppa/cpu-qom.h | 3 +--
target/hppa/cpu.h | 12 +++---------
target/i386/cpu-qom.h | 3 +--
target/i386/cpu.c | 1 +
target/i386/cpu.h | 7 ++-----
target/i386/tcg/sysemu/excp_helper.c | 1 +
target/i386/tcg/sysemu/misc_helper.c | 1 +
target/m68k/cpu-qom.h | 3 +--
target/m68k/cpu.h | 7 ++-----
target/microblaze/cpu-qom.h | 3 +--
target/microblaze/cpu.h | 9 +++------
target/microblaze/mmu.h | 2 ++
target/mips/cpu-qom.h | 3 +--
target/mips/cpu.h | 10 +++-------
target/mips/internal.h | 15 ++++++++-------
target/nios2/cpu.h | 9 ++++-----
target/nios2/mmu.h | 2 ++
target/openrisc/cpu.h | 17 +++++------------
target/ppc/cpu-qom.h | 5 ++---
target/ppc/cpu.h | 7 ++-----
target/riscv/cpu.h | 11 ++++-------
target/riscv/pmp.h | 2 ++
target/rx/cpu-qom.h | 5 +----
target/rx/cpu.h | 6 ++----
target/s390x/cpu-qom.h | 7 +++----
target/s390x/cpu.h | 7 ++-----
target/sh4/cpu-qom.h | 3 +--
target/sh4/cpu.h | 7 ++-----
target/sparc/cpu-qom.h | 3 +--
target/sparc/cpu.h | 9 +++------
target/tricore/cpu-qom.h | 3 +--
target/tricore/cpu.h | 10 +++-------
target/xtensa/cpu-qom.h | 3 +--
target/xtensa/cpu.h | 13 +++++--------
52 files changed, 129 insertions(+), 188 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 01/14] meson: Display libfdt as disabled when system emulation is disabled
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 02/14] hw/m68k/mcf: Add missing 'exec/hwaddr.h' header Philippe Mathieu-Daudé via
` (14 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
When configuring QEMU with --disable-system, meson keeps showing
libfdt as "auto". Mark it as disabled instead.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
meson.build | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index df25e7a5e7..9460875693 100644
--- a/meson.build
+++ b/meson.build
@@ -2266,8 +2266,8 @@ if get_option('cfi') and slirp_opt == 'system'
endif
fdt = not_found
-fdt_opt = get_option('fdt')
if have_system
+ fdt_opt = get_option('fdt')
if fdt_opt in ['enabled', 'auto', 'system']
have_internal = fs.exists(meson.current_source_dir() / 'dtc/libfdt/Makefile.libfdt')
fdt = cc.find_library('fdt', kwargs: static_kwargs,
@@ -2310,6 +2310,8 @@ if have_system
fdt = declare_dependency(link_with: libfdt,
include_directories: fdt_inc)
endif
+else
+ fdt_opt = 'disabled'
endif
if not fdt.found() and fdt_required.length() > 0
error('fdt not available but required by targets ' + ', '.join(fdt_required))
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 02/14] hw/m68k/mcf: Add missing 'exec/hwaddr.h' header
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 01/14] meson: Display libfdt as disabled when system emulation is disabled Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 03/14] hw/tricore: Remove unused and incorrect header Philippe Mathieu-Daudé via
` (13 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
hwaddr type is defined in "exec/hwaddr.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/m68k/mcf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
index decf17ce42..8cbd587bbf 100644
--- a/include/hw/m68k/mcf.h
+++ b/include/hw/m68k/mcf.h
@@ -2,6 +2,7 @@
#define HW_MCF_H
/* Motorola ColdFire device prototypes. */
+#include "exec/hwaddr.h"
#include "target/m68k/cpu-qom.h"
/* mcf_uart.c */
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 03/14] hw/tricore: Remove unused and incorrect header
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 01/14] meson: Display libfdt as disabled when system emulation is disabled Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 02/14] hw/m68k/mcf: Add missing 'exec/hwaddr.h' header Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 04/14] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition Philippe Mathieu-Daudé via
` (12 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
TriCore boards certainly don't need the ARM loader API :)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/tricore/triboard.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h
index f3844be447..094c8bd563 100644
--- a/include/hw/tricore/triboard.h
+++ b/include/hw/tricore/triboard.h
@@ -21,7 +21,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/boards.h"
-#include "hw/arm/boot.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 04/14] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (2 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 03/14] hw/tricore: Remove unused and incorrect header Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 05/14] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers Philippe Mathieu-Daudé via
` (11 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/exec/cpu_ldst.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index da987fe8ad..6adacf8928 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -64,6 +64,7 @@
#include "exec/memopidx.h"
#include "qemu/int128.h"
+#include "cpu.h"
#if defined(CONFIG_USER_ONLY)
/* sparc32plus has 64bit long but 32bit space address
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 05/14] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (3 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 04/14] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 06/14] target/i386/cpu: Ensure accelerators set CPU addressble physical bits Philippe Mathieu-Daudé via
` (10 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
cpu.c requires "exec/exec-all.h" to call tlb_flush() and
"qemu/accel.h" to call accel_cpu_realizefn().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/cpu.c b/cpu.c
index d5d4cbf8cb..d564886149 100644
--- a/cpu.c
+++ b/cpu.c
@@ -35,10 +35,12 @@
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
#include "sysemu/replay.h"
+#include "exec/exec-all.h"
#include "exec/translate-all.h"
#include "exec/log.h"
#include "hw/core/accel-cpu.h"
#include "trace/trace-root.h"
+#include "qemu/accel.h"
uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 06/14] target/i386/cpu: Ensure accelerators set CPU addressble physical bits
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (4 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 05/14] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 07/14] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header Philippe Mathieu-Daudé via
` (9 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
The only accelerator allowed to use zero as default value is TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aa9e636800..16523a78d9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6384,6 +6384,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
* In this case, the default is the value used by TCG (40).
*/
if (cpu->phys_bits == 0) {
+ assert(tcg_enabled());
cpu->phys_bits = TCG_PHYS_ADDR_BITS;
}
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 07/14] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (5 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 06/14] target/i386/cpu: Ensure accelerators set CPU addressble physical bits Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 08/14] Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE Philippe Mathieu-Daudé via
` (8 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
excp_helper.c requires "exec/exec-all.h" for tlb_set_page_with_attrs()
and misc_helper.c for tlb_flush().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/tcg/sysemu/excp_helper.c | 1 +
target/i386/tcg/sysemu/misc_helper.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index 5ba739fbed..5627772e7c 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
int get_pg_mode(CPUX86State *env)
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 9ccaa054c4..3715c1e262 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -23,6 +23,7 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
+#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 08/14] Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (6 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 07/14] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 09/14] target: Include missing 'cpu.h' Philippe Mathieu-Daudé via
` (7 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
From: Taylor Simpson <tsimpson@quicinc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220211033034.21107-1-tsimpson@quicinc.com>
[PMD: Add missing "qom/object.h" include]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/hexagon/cpu.h | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 58a0d3870b..096aa2deb6 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -26,6 +26,7 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "exec/cpu-defs.h"
#include "hex_regs.h"
#include "mmvec/mmvec.h"
+#include "qom/object.h"
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
@@ -131,12 +132,7 @@ struct CPUHexagonState {
VTCMStoreLog vtcm_log;
};
-#define HEXAGON_CPU_CLASS(klass) \
- OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU)
-#define HEXAGON_CPU(obj) \
- OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU)
-#define HEXAGON_CPU_GET_CLASS(obj) \
- OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU)
+OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
typedef struct HexagonCPUClass {
/*< private >*/
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 09/14] target: Include missing 'cpu.h'
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (7 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 08/14] Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include Philippe Mathieu-Daudé via
` (6 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
These target-specific files use the target-specific CPU state
but lack to include "cpu.h"; i.e.:
../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState'
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
^
../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State'
void mmu_flip_um(CPUNios2State *env, unsigned int um);
^
../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'; did you mean 'CPUState'?
uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
^~~~~~~~~~
CPUState
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/microblaze/mmu.h | 2 ++
target/mips/internal.h | 1 +
target/nios2/mmu.h | 2 ++
target/riscv/pmp.h | 2 ++
4 files changed, 7 insertions(+)
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index b6b4b9ad60..1068bd2d52 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -20,6 +20,8 @@
#ifndef TARGET_MICROBLAZE_MMU_H
#define TARGET_MICROBLAZE_MMU_H
+#include "cpu.h"
+
#define MMU_R_PID 0
#define MMU_R_ZPR 1
#define MMU_R_TLBX 2
diff --git a/target/mips/internal.h b/target/mips/internal.h
index daddb05fd4..f705d6bfa6 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -12,6 +12,7 @@
#ifdef CONFIG_TCG
#include "tcg/tcg-internal.h"
#endif
+#include "cpu.h"
/*
* MMU types, the first four entries have the same layout as the
diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h
index 4f46fbb82e..d36b8cc86a 100644
--- a/target/nios2/mmu.h
+++ b/target/nios2/mmu.h
@@ -21,6 +21,8 @@
#ifndef NIOS2_MMU_H
#define NIOS2_MMU_H
+#include "cpu.h"
+
typedef struct Nios2TLBEntry {
target_ulong tag;
target_ulong data;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index a9a0b363a7..fcb6b7c467 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -22,6 +22,8 @@
#ifndef RISCV_PMP_H
#define RISCV_PMP_H
+#include "cpu.h"
+
typedef enum {
PMP_READ = 1 << 0,
PMP_WRITE = 1 << 1,
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (8 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 09/14] target: Include missing 'cpu.h' Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-15 8:47 ` Damien Hedde
2022-02-25 0:04 ` Richard Henderson
2022-02-14 18:31 ` [PATCH v2 11/14] target: Use forward declared type instead of structure type Philippe Mathieu-Daudé via
` (5 subsequent siblings)
15 siblings, 2 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
HexagonCPU field parent_class is of type CPUClass, which
is declared in "hw/core/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/hexagon/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 096aa2deb6..76cd1d5021 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -27,6 +27,7 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "hex_regs.h"
#include "mmvec/mmvec.h"
#include "qom/object.h"
+#include "hw/core/cpu.h"
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 11/14] target: Use forward declared type instead of structure type
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (9 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 12/14] target: Use CPUArchState as interface to target-specific CPU state Philippe Mathieu-Daudé via
` (4 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
The CPU / CPU state are forward declared.
$ git grep -E 'struct [A-Za-z]+CPU\ \*'
target/arm/hvf_arm.h:16:void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);
target/openrisc/cpu.h:234: int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
target/openrisc/cpu.h:238: int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
$ git grep -E 'struct CPU[A-Za-z]+State\ \*'
target/mips/internal.h:137: int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
target/mips/internal.h:139: void (*helper_tlbwi)(struct CPUMIPSState *env);
target/mips/internal.h:140: void (*helper_tlbwr)(struct CPUMIPSState *env);
target/mips/internal.h:141: void (*helper_tlbp)(struct CPUMIPSState *env);
target/mips/internal.h:142: void (*helper_tlbr)(struct CPUMIPSState *env);
target/mips/internal.h:143: void (*helper_tlbinv)(struct CPUMIPSState *env);
target/mips/internal.h:144: void (*helper_tlbinvf)(struct CPUMIPSState *env);
target/xtensa/cpu.h:347: struct CPUXtensaState *env;
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/hvf_arm.h | 2 +-
target/mips/internal.h | 14 +++++++-------
target/openrisc/cpu.h | 4 ++--
target/xtensa/cpu.h | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h
index ea238cff83..9a9d1a0bf5 100644
--- a/target/arm/hvf_arm.h
+++ b/target/arm/hvf_arm.h
@@ -13,6 +13,6 @@
#include "cpu.h"
-void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);
+void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu);
#endif
diff --git a/target/mips/internal.h b/target/mips/internal.h
index f705d6bfa6..ac6e03e2f2 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -134,14 +134,14 @@ struct r4k_tlb_t {
struct CPUMIPSTLBContext {
uint32_t nb_tlb;
uint32_t tlb_in_use;
- int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
+ int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, MMUAccessType access_type);
- void (*helper_tlbwi)(struct CPUMIPSState *env);
- void (*helper_tlbwr)(struct CPUMIPSState *env);
- void (*helper_tlbp)(struct CPUMIPSState *env);
- void (*helper_tlbr)(struct CPUMIPSState *env);
- void (*helper_tlbinv)(struct CPUMIPSState *env);
- void (*helper_tlbinvf)(struct CPUMIPSState *env);
+ void (*helper_tlbwi)(CPUMIPSState *env);
+ void (*helper_tlbwr)(CPUMIPSState *env);
+ void (*helper_tlbp)(CPUMIPSState *env);
+ void (*helper_tlbr)(CPUMIPSState *env);
+ void (*helper_tlbinv)(CPUMIPSState *env);
+ void (*helper_tlbinvf)(CPUMIPSState *env);
union {
struct {
r4k_tlb_t tlb[MIPS_TLB_MAX];
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index ee069b080c..5711591520 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -231,11 +231,11 @@ typedef struct CPUOpenRISCTLBContext {
OpenRISCTLBEntry itlb[TLB_SIZE];
OpenRISCTLBEntry dtlb[TLB_SIZE];
- int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
+ int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu,
hwaddr *physical,
int *prot,
target_ulong address, int rw);
- int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
+ int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu,
hwaddr *physical,
int *prot,
target_ulong address, int rw);
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 02143f2f77..f2165b17e2 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -344,7 +344,7 @@ typedef struct XtensaGdbRegmap {
} XtensaGdbRegmap;
typedef struct XtensaCcompareTimer {
- struct CPUXtensaState *env;
+ CPUXtensaState *env;
QEMUTimer *timer;
} XtensaCcompareTimer;
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 12/14] target: Use CPUArchState as interface to target-specific CPU state
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (10 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 11/14] target: Use forward declared type instead of structure type Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 13/14] target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro Philippe Mathieu-Daudé via
` (3 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/exec/poison.h | 2 --
include/hw/core/cpu.h | 2 +-
include/qemu/typedefs.h | 1 +
target/alpha/cpu.h | 7 ++-----
target/arm/cpu.h | 3 +--
target/avr/cpu.h | 7 ++-----
target/cris/cpu.h | 3 +--
target/hexagon/cpu.h | 8 ++------
target/hppa/cpu.h | 8 ++------
target/i386/cpu.h | 3 +--
target/m68k/cpu.h | 3 +--
target/microblaze/cpu.h | 5 ++---
target/mips/cpu.h | 6 ++----
target/nios2/cpu.h | 4 ++--
target/openrisc/cpu.h | 3 +--
target/ppc/cpu-qom.h | 2 +-
target/ppc/cpu.h | 3 +--
target/riscv/cpu.h | 5 ++---
target/rx/cpu-qom.h | 2 --
target/rx/cpu.h | 2 +-
target/s390x/cpu-qom.h | 4 ++--
target/s390x/cpu.h | 3 +--
target/sh4/cpu.h | 3 +--
target/sparc/cpu.h | 5 ++---
target/tricore/cpu.h | 6 ++----
target/xtensa/cpu.h | 7 +++----
26 files changed, 37 insertions(+), 70 deletions(-)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 7ad4ad18e8..7c5c02f03f 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -51,8 +51,6 @@
#pragma GCC poison TARGET_PAGE_BITS
#pragma GCC poison TARGET_PAGE_ALIGN
-#pragma GCC poison CPUArchState
-
#pragma GCC poison CPU_INTERRUPT_HARD
#pragma GCC poison CPU_INTERRUPT_EXITTB
#pragma GCC poison CPU_INTERRUPT_HALT
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3f2b681281..c9d41e4ece 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -340,7 +340,7 @@ struct CPUState {
AddressSpace *as;
MemoryRegion *memory;
- void *env_ptr; /* CPUArchState */
+ CPUArchState *env_ptr;
IcountDecr *icount_decr_ptr;
/* Accessed in parallel; all accesses must be atomic */
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index ee60eb3de4..c6f692b0dd 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -39,6 +39,7 @@ typedef struct CompatProperty CompatProperty;
typedef struct CoMutex CoMutex;
typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
typedef struct CPUAddressSpace CPUAddressSpace;
+typedef struct CPUArchState CPUArchState;
typedef struct CPUState CPUState;
typedef struct DeviceListener DeviceListener;
typedef struct DeviceState DeviceState;
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e819211503..cfd17fd265 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -197,9 +197,7 @@ enum {
#define MMU_USER_IDX 1
#define MMU_PHYS_IDX 2
-typedef struct CPUAlphaState CPUAlphaState;
-
-struct CPUAlphaState {
+typedef struct CPUArchState {
uint64_t ir[31];
float64 fir[31];
uint64_t pc;
@@ -251,7 +249,7 @@ struct CPUAlphaState {
uint32_t features;
uint32_t amask;
int implver;
-};
+} CPUAlphaState;
/**
* AlphaCPU:
@@ -285,7 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#define cpu_list alpha_cpu_list
-typedef CPUAlphaState CPUArchState;
typedef AlphaCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c6a4d50e82..a95a070647 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -232,7 +232,7 @@ typedef struct CPUARMTBFlags {
target_ulong flags2;
} CPUARMTBFlags;
-typedef struct CPUARMState {
+typedef struct CPUArchState {
/* Regs for current mode. */
uint32_t regs[16];
@@ -3410,7 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
}
-typedef CPUARMState CPUArchState;
typedef ARMCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index dceacf3cd7..e4a990556b 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -108,9 +108,7 @@ typedef enum AVRFeature {
AVR_FEATURE_RAMPZ,
} AVRFeature;
-typedef struct CPUAVRState CPUAVRState;
-
-struct CPUAVRState {
+typedef struct CPUArchState {
uint32_t pc_w; /* 0x003fffff up to 22 bits */
uint32_t sregC; /* 0x00000001 1 bit */
@@ -137,7 +135,7 @@ struct CPUAVRState {
bool fullacc; /* CPU/MEM if true MEM only otherwise */
uint64_t features;
-};
+} CPUAVRState;
/**
* AVRCPU:
@@ -247,7 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-typedef CPUAVRState CPUArchState;
typedef AVRCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index b445b194ea..763d4f882e 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -105,7 +105,7 @@ typedef struct {
uint32_t lo;
} TLBSet;
-typedef struct CPUCRISState {
+typedef struct CPUArchState {
uint32_t regs[16];
/* P0 - P15 are referred to as special registers in the docs. */
uint32_t pregs[16];
@@ -265,7 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
-typedef CPUCRISState CPUArchState;
typedef CRISCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 76cd1d5021..a65bd935c3 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -18,9 +18,6 @@
#ifndef HEXAGON_CPU_H
#define HEXAGON_CPU_H
-/* Forward declaration needed by some of the header files */
-typedef struct CPUHexagonState CPUHexagonState;
-
#include "fpu/softfloat-types.h"
#include "exec/cpu-defs.h"
@@ -77,7 +74,7 @@ typedef struct {
/* Maximum number of vector temps in a packet */
#define VECTOR_TEMPS_MAX 4
-struct CPUHexagonState {
+typedef struct CPUArchState {
target_ulong gpr[TOTAL_PER_THREAD_REGS];
target_ulong pred[NUM_PREGS];
target_ulong branch_taken;
@@ -131,7 +128,7 @@ struct CPUHexagonState {
target_ulong vstore_pending[VSTORES_MAX];
bool vtcm_pending;
VTCMStoreLog vtcm_log;
-};
+} CPUHexagonState;
OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
@@ -177,7 +174,6 @@ static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
#endif
}
-typedef struct CPUHexagonState CPUArchState;
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 93c119532a..d36e5c170c 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -138,8 +138,6 @@
#define CR_IPSW 22
#define CR_EIRR 23
-typedef struct CPUHPPAState CPUHPPAState;
-
#if TARGET_REGISTER_BITS == 32
typedef uint32_t target_ureg;
typedef int32_t target_sreg;
@@ -168,7 +166,7 @@ typedef struct {
unsigned access_id : 16;
} hppa_tlb_entry;
-struct CPUHPPAState {
+typedef struct CPUArchState {
target_ureg gr[32];
uint64_t fr[32];
uint64_t sr[8]; /* stored shifted into place for gva */
@@ -207,7 +205,7 @@ struct CPUHPPAState {
/* ??? We should use a more intelligent data structure. */
hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
uint32_t tlb_last;
-};
+} CPUHPPAState;
/**
* HPPACPU:
@@ -225,8 +223,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer;
};
-
-typedef CPUHPPAState CPUArchState;
typedef HPPACPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 9911d7c871..31ae748570 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1429,7 +1429,7 @@ typedef struct HVFX86LazyFlags {
target_ulong auxbits;
} HVFX86LazyFlags;
-typedef struct CPUX86State {
+typedef struct CPUArchState {
/* standard registers */
target_ulong regs[CPU_NB_REGS];
target_ulong eip;
@@ -2072,7 +2072,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#define CC_SRC2 (env->cc_src2)
#define CC_OP (env->cc_op)
-typedef CPUX86State CPUArchState;
typedef X86CPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index a3423729ef..0245398230 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -79,7 +79,7 @@
typedef CPU_LDoubleU FPReg;
-typedef struct CPUM68KState {
+typedef struct CPUArchState {
uint32_t dregs[8];
uint32_t aregs[8];
uint32_t pc;
@@ -574,7 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
-typedef CPUM68KState CPUArchState;
typedef M68kCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e9cd0b88de..acfd35d3f7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -24,7 +24,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
-typedef struct CPUMBState CPUMBState;
+typedef struct CPUArchState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
@@ -239,7 +239,7 @@ typedef struct CPUMBState CPUMBState;
#define USE_NON_SECURE_M_AXI_DC_MASK 0x4
#define USE_NON_SECURE_M_AXI_IC_MASK 0x8
-struct CPUMBState {
+struct CPUArchState {
uint32_t bvalue; /* TCG temporary, only valid during a TB */
uint32_t btarget; /* Full resolved branch destination */
@@ -394,7 +394,6 @@ void mb_tcg_init(void);
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-typedef CPUMBState CPUArchState;
typedef MicroBlazeCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 56b1cbd091..d4f5d7099a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -524,8 +524,7 @@ struct TCState {
};
struct MIPSITUState;
-typedef struct CPUMIPSState CPUMIPSState;
-struct CPUMIPSState {
+typedef struct CPUArchState {
TCState active_tc;
CPUMIPSFPUContext active_fpu;
@@ -1161,7 +1160,7 @@ struct CPUMIPSState {
QEMUTimer *timer; /* Internal timer */
target_ulong exception_base; /* ExceptionBase input to the core */
uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
-};
+} CPUMIPSState;
/**
* MIPSCPU:
@@ -1218,7 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
-typedef CPUMIPSState CPUArchState;
typedef MIPSCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index d2ba0c5bbd..629b9e2301 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -25,7 +25,7 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
-typedef struct CPUNios2State CPUNios2State;
+typedef struct CPUArchState CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
@@ -155,7 +155,7 @@ struct Nios2CPUClass {
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
-struct CPUNios2State {
+struct CPUArchState {
uint32_t regs[NUM_CORE_REGS];
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 5711591520..a218e49f0e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -242,7 +242,7 @@ typedef struct CPUOpenRISCTLBContext {
} CPUOpenRISCTLBContext;
#endif
-typedef struct CPUOpenRISCState {
+typedef struct CPUArchState {
target_ulong shadow_gpr[16][32]; /* Shadow registers */
target_ulong pc; /* Program counter */
@@ -348,7 +348,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
-typedef CPUOpenRISCState CPUArchState;
typedef OpenRISCCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 98facee9fa..78b19a5cdb 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -32,7 +32,7 @@
OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
POWERPC_CPU)
-typedef struct CPUPPCState CPUPPCState;
+typedef struct CPUArchState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_dcr_t ppc_dcr_t;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 555c6b9245..4c3ab4fa9c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1075,7 +1075,7 @@ struct ppc_radix_page_info {
#define PPC_CPU_OPCODES_LEN 0x40
#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
-struct CPUPPCState {
+struct CPUArchState {
/* Most commonly used resources during translated code execution first */
target_ulong gpr[32]; /* general purpose registers */
target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
@@ -1467,7 +1467,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
uint32_t *compat_pvr, const char *basedesc);
#endif /* defined(TARGET_PPC64) */
-typedef CPUPPCState CPUArchState;
typedef PowerPCCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 55635d68d5..79144ddc24 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -97,7 +97,7 @@ enum {
#define MAX_RISCV_PMPS (16)
-typedef struct CPURISCVState CPURISCVState;
+typedef struct CPUArchState CPURISCVState;
#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
@@ -112,7 +112,7 @@ FIELD(VTYPE, VMA, 7, 1)
FIELD(VTYPE, VEDIV, 8, 2)
FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
-struct CPURISCVState {
+struct CPUArchState {
target_ulong gpr[32];
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
uint64_t fpr[32]; /* assume both F and D extensions */
@@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
-typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 7310558e0c..f918c46b00 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -45,6 +45,4 @@ struct RXCPUClass {
DeviceReset parent_reset;
};
-#define CPUArchState struct CPURXState
-
#endif
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 58adf9edf6..0f3d9d5bd9 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -65,7 +65,7 @@ enum {
NUM_REGS = 16,
};
-typedef struct CPURXState {
+typedef struct CPUArchState {
/* CPU registers */
uint32_t regs[NUM_REGS]; /* general registers */
uint32_t psw_o; /* O bit of status register */
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 9f3a0d86c5..04d5b3012c 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -31,6 +31,8 @@ OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
typedef struct S390CPUModel S390CPUModel;
typedef struct S390CPUDef S390CPUDef;
+typedef struct CPUArchState CPUS390XState;
+
typedef enum cpu_reset_type {
S390_CPU_RESET_NORMAL,
S390_CPU_RESET_INITIAL,
@@ -63,6 +65,4 @@ struct S390CPUClass {
void (*reset)(CPUState *cpu, cpu_reset_type type);
};
-typedef struct CPUS390XState CPUS390XState;
-
#endif
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index a75e559134..b668c1b0c7 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -51,7 +51,7 @@ typedef struct PSW {
uint64_t addr;
} PSW;
-struct CPUS390XState {
+struct CPUArchState {
uint64_t regs[16]; /* GP registers */
/*
* The floating point registers are part of the vector registers.
@@ -840,7 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
/* outside of target/s390x/ */
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
-typedef CPUS390XState CPUArchState;
typedef S390CPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index fb9dd9db2f..9a89d2d038 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -130,7 +130,7 @@ typedef struct memory_content {
struct memory_content *next;
} memory_content;
-typedef struct CPUSH4State {
+typedef struct CPUArchState {
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */
@@ -264,7 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
}
}
-typedef CPUSH4State CPUArchState;
typedef SuperHCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5a7f1ed5d6..938efb72bf 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -420,7 +420,7 @@ struct CPUTimer
typedef struct CPUTimer CPUTimer;
-typedef struct CPUSPARCState CPUSPARCState;
+typedef struct CPUArchState CPUSPARCState;
#if defined(TARGET_SPARC64)
typedef union {
uint64_t mmuregs[16];
@@ -439,7 +439,7 @@ typedef union {
};
} SparcV9MMU;
#endif
-struct CPUSPARCState {
+struct CPUArchState {
target_ulong gregs[8]; /* general registers */
target_ulong *regwptr; /* pointer to current register window */
target_ulong pc; /* program counter */
@@ -743,7 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
#endif
}
-typedef CPUSPARCState CPUArchState;
typedef SPARCCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index c461387e71..398d5076be 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -28,8 +28,7 @@ struct tricore_boot_info;
typedef struct tricore_def_t tricore_def_t;
-typedef struct CPUTriCoreState CPUTriCoreState;
-struct CPUTriCoreState {
+typedef struct CPUArchState {
/* GPR Register */
uint32_t gpr_a[16];
uint32_t gpr_d[16];
@@ -189,7 +188,7 @@ struct CPUTriCoreState {
const tricore_def_t *cpu_model;
void *irq[8];
struct QEMUTimer *timer; /* Internal timer */
-};
+} CPUTriCoreState;
/**
* TriCoreCPU:
@@ -369,7 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
return 0;
}
-typedef CPUTriCoreState CPUArchState;
typedef TriCoreCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index f2165b17e2..4496325970 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -306,7 +306,7 @@ typedef enum {
INTTYPE_MAX
} interrupt_type;
-struct CPUXtensaState;
+typedef struct CPUArchState CPUXtensaState;
typedef struct xtensa_tlb_entry {
uint32_t vaddr;
@@ -506,7 +506,7 @@ enum {
};
#endif
-typedef struct CPUXtensaState {
+struct CPUArchState {
const XtensaConfig *config;
uint32_t regs[16];
uint32_t pc;
@@ -545,7 +545,7 @@ typedef struct CPUXtensaState {
/* Watchpoints for DBREAK registers */
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
-} CPUXtensaState;
+};
/**
* XtensaCPU:
@@ -722,7 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
-typedef CPUXtensaState CPUArchState;
typedef XtensaCPU ArchCPU;
#include "exec/cpu-all.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 13/14] target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (11 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 12/14] target: Use CPUArchState as interface to target-specific CPU state Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-25 0:08 ` Richard Henderson
2022-02-14 18:31 ` [PATCH v2 14/14] target: Use ArchCPU as interface to target CPU Philippe Mathieu-Daudé via
` (2 subsequent siblings)
15 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
Replace the boilerplate code to declare CPU QOM types
and macros, and forward-declare the CPU instance type.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 18 ++++++++++++++++++
target/alpha/cpu-qom.h | 3 +--
target/alpha/cpu.h | 2 --
target/arm/cpu-qom.h | 3 +--
target/arm/cpu.h | 2 --
target/avr/cpu-qom.h | 3 +--
target/avr/cpu.h | 6 ++----
target/cris/cpu-qom.h | 3 +--
target/cris/cpu.h | 2 --
target/hexagon/cpu.h | 6 +++---
target/hppa/cpu-qom.h | 3 +--
target/hppa/cpu.h | 2 --
target/i386/cpu-qom.h | 3 +--
target/i386/cpu.h | 2 --
target/m68k/cpu-qom.h | 3 +--
target/m68k/cpu.h | 2 --
target/microblaze/cpu-qom.h | 3 +--
target/microblaze/cpu.h | 2 --
target/mips/cpu-qom.h | 3 +--
target/mips/cpu.h | 2 --
target/nios2/cpu.h | 3 +--
target/openrisc/cpu.h | 8 +-------
target/ppc/cpu-qom.h | 3 +--
target/ppc/cpu.h | 2 --
target/riscv/cpu.h | 4 +---
target/rx/cpu-qom.h | 3 +--
target/rx/cpu.h | 2 --
target/s390x/cpu-qom.h | 3 +--
target/s390x/cpu.h | 2 --
target/sh4/cpu-qom.h | 3 +--
target/sh4/cpu.h | 2 --
target/sparc/cpu-qom.h | 3 +--
target/sparc/cpu.h | 2 --
target/tricore/cpu-qom.h | 3 +--
target/tricore/cpu.h | 2 --
target/xtensa/cpu-qom.h | 3 +--
target/xtensa/cpu.h | 2 --
37 files changed, 42 insertions(+), 81 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c9d41e4ece..2a0893b1dc 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -55,6 +55,24 @@ typedef struct CPUClass CPUClass;
DECLARE_CLASS_CHECKERS(CPUClass, CPU,
TYPE_CPU)
+/**
+ * OBJECT_DECLARE_CPU_TYPE:
+ * @CpuInstanceType: instance struct name
+ * @CpuClassType: class struct name
+ * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
+ *
+ * This macro is typically used in "cpu-qom.h" header file, and will:
+ *
+ * - create the typedefs for the CPU object and class structs
+ * - register the type for use with g_autoptr
+ * - provide three standard type cast functions
+ *
+ * The object struct and class struct need to be declared manually.
+ */
+#define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
+ OBJECT_DECLARE_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME); \
+ typedef CpuInstanceType ArchCPU;
+
typedef enum MMUAccessType {
MMU_DATA_LOAD = 0,
MMU_DATA_STORE = 1,
diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index 7bb9173c57..1f200724b6 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -25,8 +25,7 @@
#define TYPE_ALPHA_CPU "alpha-cpu"
-OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass,
- ALPHA_CPU)
+OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
/**
* AlphaCPUClass:
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index cfd17fd265..84430aff42 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -283,8 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#define cpu_list alpha_cpu_list
-typedef AlphaCPU ArchCPU;
-
#include "exec/cpu-all.h"
enum {
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index a22bd506d0..64c44cef2d 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -27,8 +27,7 @@ struct arm_boot_info;
#define TYPE_ARM_CPU "arm-cpu"
-OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
- ARM_CPU)
+OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a95a070647..a137c564c4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
}
-typedef ARMCPU ArchCPU;
-
#include "exec/cpu-all.h"
/*
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index 14e5b3ce72..32a1c762e6 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -26,8 +26,7 @@
#define TYPE_AVR_CPU "avr-cpu"
-OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
- AVR_CPU)
+OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
/**
* AVRCPUClass:
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index e4a990556b..a833799fc1 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -143,14 +143,14 @@ typedef struct CPUArchState {
*
* A AVR CPU.
*/
-typedef struct AVRCPU {
+struct AVRCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUAVRState env;
-} AVRCPU;
+};
extern const struct VMStateDescription vms_avr_cpu;
@@ -245,8 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-typedef AVRCPU ArchCPU;
-
#include "exec/cpu-all.h"
#endif /* !defined (QEMU_AVR_CPU_H) */
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index 2596edc7e3..71e8af0e70 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -25,8 +25,7 @@
#define TYPE_CRIS_CPU "cris-cpu"
-OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass,
- CRIS_CPU)
+OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
/**
* CRISCPUClass:
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 763d4f882e..af7121bba0 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -265,8 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
-typedef CRISCPU ArchCPU;
-
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index a65bd935c3..8db0aa542d 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -130,7 +130,7 @@ typedef struct CPUArchState {
VTCMStoreLog vtcm_log;
} CPUHexagonState;
-OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
+OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
typedef struct HexagonCPUClass {
/*< private >*/
@@ -140,7 +140,7 @@ typedef struct HexagonCPUClass {
DeviceReset parent_reset;
} HexagonCPUClass;
-typedef struct HexagonCPU {
+struct HexagonCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@@ -149,7 +149,7 @@ typedef struct HexagonCPU {
bool lldb_compat;
target_ulong lldb_stack_adjust;
-} HexagonCPU;
+};
#include "cpu_bits.h"
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index d424f88370..b96e0318c7 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -25,8 +25,7 @@
#define TYPE_HPPA_CPU "hppa-cpu"
-OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass,
- HPPA_CPU)
+OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
/**
* HPPACPUClass:
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index d36e5c170c..73a3f32389 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -223,8 +223,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer;
};
-typedef HPPACPU ArchCPU;
-
#include "exec/cpu-all.h"
static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index f9923cee04..c557a522e1 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -30,8 +30,7 @@
#define TYPE_X86_CPU "i386-cpu"
#endif
-OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass,
- X86_CPU)
+OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
typedef struct X86CPUModel X86CPUModel;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 31ae748570..f3b951df0d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2072,8 +2072,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#define CC_SRC2 (env->cc_src2)
#define CC_OP (env->cc_op)
-typedef X86CPU ArchCPU;
-
#include "exec/cpu-all.h"
#include "svm.h"
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 1ceb160ecb..cd9687192c 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -25,8 +25,7 @@
#define TYPE_M68K_CPU "m68k-cpu"
-OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass,
- M68K_CPU)
+OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
/*
* M68kCPUClass:
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 0245398230..76a7cc70b4 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -574,8 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
-typedef M68kCPU ArchCPU;
-
#include "exec/cpu-all.h"
/* TB flags */
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index e520eefb12..255b39a45d 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -25,8 +25,7 @@
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
-OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
- MICROBLAZE_CPU)
+OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index acfd35d3f7..6e4e90a41e 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -394,8 +394,6 @@ void mb_tcg_init(void);
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-typedef MicroBlazeCPU ArchCPU;
-
#include "exec/cpu-all.h"
/* Ensure there is no overlap between the two masks. */
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index dda0c911fa..e28b529607 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -29,8 +29,7 @@
#define TYPE_MIPS_CPU "mips-cpu"
#endif
-OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass,
- MIPS_CPU)
+OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/**
* MIPSCPUClass:
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d4f5d7099a..c361408cc8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1217,8 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
-typedef MIPSCPU ArchCPU;
-
#include "exec/cpu-all.h"
/* Exceptions */
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 629b9e2301..94c581a98f 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -32,8 +32,7 @@ typedef struct CPUArchState CPUNios2State;
#define TYPE_NIOS2_CPU "nios2-cpu"
-OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
- NIOS2_CPU)
+OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
/**
* Nios2CPUClass:
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index a218e49f0e..bcd28802e4 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -24,13 +24,9 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
-/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
-struct OpenRISCCPU;
-
#define TYPE_OPENRISC_CPU "or1k-cpu"
-OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass,
- OPENRISC_CPU)
+OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
/**
* OpenRISCCPUClass:
@@ -348,8 +344,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
-typedef OpenRISCCPU ArchCPU;
-
#include "exec/cpu-all.h"
#define TB_FLAGS_SM SR_SM
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 78b19a5cdb..ad7e3c3db9 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -29,8 +29,7 @@
#define TYPE_POWERPC_CPU "powerpc-cpu"
#endif
-OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
- POWERPC_CPU)
+OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
typedef struct CPUArchState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4c3ab4fa9c..8a879f0e5e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1467,8 +1467,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
uint32_t *compat_pvr, const char *basedesc);
#endif /* defined(TARGET_PPC64) */
-typedef PowerPCCPU ArchCPU;
-
#include "exec/cpu-all.h"
/*****************************************************************************/
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 79144ddc24..421d18ad0b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -285,8 +285,7 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
-OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
- RISCV_CPU)
+OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
@@ -430,7 +429,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
-typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index f918c46b00..4533759d96 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -26,8 +26,7 @@
#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
-OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass,
- RX_CPU)
+OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
/*
* RXCPUClass:
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0f3d9d5bd9..f81bf5b592 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -114,8 +114,6 @@ struct RXCPU {
CPURXState env;
};
-typedef RXCPU ArchCPU;
-
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 04d5b3012c..00cae2b131 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -25,8 +25,7 @@
#define TYPE_S390_CPU "s390x-cpu"
-OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
- S390_CPU)
+OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
typedef struct S390CPUModel S390CPUModel;
typedef struct S390CPUDef S390CPUDef;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index b668c1b0c7..bdf3f7d4fe 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -840,8 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
/* outside of target/s390x/ */
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
-typedef S390CPU ArchCPU;
-
#include "exec/cpu-all.h"
#endif
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 8903b4b9c7..d4192d1090 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -29,8 +29,7 @@
#define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
#define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785")
-OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass,
- SUPERH_CPU)
+OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
/**
* SuperHCPUClass:
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9a89d2d038..dd477ba577 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -264,8 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
}
}
-typedef SuperHCPU ArchCPU;
-
#include "exec/cpu-all.h"
/* MMU control register */
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index f33949aaee..86ed37d933 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -29,8 +29,7 @@
#define TYPE_SPARC_CPU "sparc-cpu"
#endif
-OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass,
- SPARC_CPU)
+OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
typedef struct sparc_def_t sparc_def_t;
/**
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 938efb72bf..2a7fd47da3 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -743,8 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
#endif
}
-typedef SPARCCPU ArchCPU;
-
#include "exec/cpu-all.h"
#ifdef TARGET_SPARC64
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index 59bfd01bbc..ee24e9fa76 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -24,8 +24,7 @@
#define TYPE_TRICORE_CPU "tricore-cpu"
-OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass,
- TRICORE_CPU)
+OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
struct TriCoreCPUClass {
/*< private >*/
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 398d5076be..cd1954aa9e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -368,8 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
return 0;
}
-typedef TriCoreCPU ArchCPU;
-
#include "exec/cpu-all.h"
void cpu_state_reset(CPUTriCoreState *s);
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 41d9859673..4fc35ee49b 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -34,8 +34,7 @@
#define TYPE_XTENSA_CPU "xtensa-cpu"
-OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass,
- XTENSA_CPU)
+OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
typedef struct XtensaConfig XtensaConfig;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 4496325970..a361ab8785 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -722,8 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
-typedef XtensaCPU ArchCPU;
-
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 14/14] target: Use ArchCPU as interface to target CPU
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (12 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 13/14] target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro Philippe Mathieu-Daudé via
@ 2022-02-14 18:31 ` Philippe Mathieu-Daudé via
2022-02-25 0:10 ` Richard Henderson
2022-02-15 17:45 ` [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract " Damien Hedde
2022-03-06 11:12 ` Philippe Mathieu-Daudé
15 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-02-14 18:31 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Taylor Simpson, Paolo Bonzini, Eduardo Habkost,
Richard Henderson, Philippe Mathieu-Daudé
ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 4 ++--
include/qemu/typedefs.h | 1 +
target/alpha/cpu.h | 2 +-
target/arm/cpu.h | 2 +-
target/avr/cpu.h | 2 +-
target/cris/cpu.h | 2 +-
target/hexagon/cpu.h | 2 +-
target/hppa/cpu.h | 2 +-
target/i386/cpu.h | 2 +-
target/m68k/cpu.h | 2 +-
target/microblaze/cpu.h | 2 +-
target/mips/cpu.h | 2 +-
target/nios2/cpu.h | 2 +-
target/openrisc/cpu.h | 2 +-
target/ppc/cpu.h | 2 +-
target/riscv/cpu.h | 2 +-
target/rx/cpu.h | 2 +-
target/s390x/cpu.h | 2 +-
target/sh4/cpu.h | 2 +-
target/sparc/cpu.h | 2 +-
target/tricore/cpu.h | 2 +-
target/xtensa/cpu.h | 2 +-
22 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2a0893b1dc..0efc6153ed 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -70,8 +70,8 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU,
* The object struct and class struct need to be declared manually.
*/
#define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
- OBJECT_DECLARE_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME); \
- typedef CpuInstanceType ArchCPU;
+ typedef struct ArchCPU CpuInstanceType; \
+ OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
typedef enum MMUAccessType {
MMU_DATA_LOAD = 0,
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index c6f692b0dd..c564f54c11 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -26,6 +26,7 @@ typedef struct AddressSpace AddressSpace;
typedef struct AioContext AioContext;
typedef struct Aml Aml;
typedef struct AnnounceTimer AnnounceTimer;
+typedef struct ArchCPU ArchCPU;
typedef struct BdrvDirtyBitmap BdrvDirtyBitmap;
typedef struct BdrvDirtyBitmapIter BdrvDirtyBitmapIter;
typedef struct BlockBackend BlockBackend;
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 84430aff42..58f00b7814 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -257,7 +257,7 @@ typedef struct CPUArchState {
*
* An Alpha CPU.
*/
-struct AlphaCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a137c564c4..a4bbca1812 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -774,7 +774,7 @@ typedef struct ARMISARegisters ARMISARegisters;
*
* An ARM CPU core.
*/
-struct ARMCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index a833799fc1..55497f851d 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -143,7 +143,7 @@ typedef struct CPUArchState {
*
* A AVR CPU.
*/
-struct AVRCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index af7121bba0..e6776f25b1 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -173,7 +173,7 @@ typedef struct CPUArchState {
*
* A CRIS CPU.
*/
-struct CRISCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 8db0aa542d..2a65a57bab 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -140,7 +140,7 @@ typedef struct HexagonCPUClass {
DeviceReset parent_reset;
} HexagonCPUClass;
-struct HexagonCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 73a3f32389..4cc936b6bf 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -213,7 +213,7 @@ typedef struct CPUArchState {
*
* An HPPA CPU.
*/
-struct HPPACPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f3b951df0d..b5d1ff5956 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1705,7 +1705,7 @@ struct kvm_msrs;
*
* An x86 CPU.
*/
-struct X86CPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 76a7cc70b4..872e8ce637 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -156,7 +156,7 @@ typedef struct CPUArchState {
*
* A Motorola 68k CPU.
*/
-struct M68kCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 6e4e90a41e..0a0ce71b6a 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -339,7 +339,7 @@ typedef struct {
*
* A MicroBlaze CPU.
*/
-struct MicroBlazeCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index c361408cc8..09e98f64de 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1171,7 +1171,7 @@ typedef struct CPUArchState {
*
* A MIPS CPU.
*/
-struct MIPSCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 94c581a98f..eedcf3c27d 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -170,7 +170,7 @@ struct CPUArchState {
*
* A Nios2 CPU.
*/
-struct Nios2CPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index bcd28802e4..bdf29d2dc4 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -297,7 +297,7 @@ typedef struct CPUArchState {
*
* A OpenRISC CPU.
*/
-struct OpenRISCCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 8a879f0e5e..04c9c6113b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1273,7 +1273,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
*
* A PowerPC CPU.
*/
-struct PowerPCCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 421d18ad0b..dffc01ee6d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -308,7 +308,7 @@ struct RISCVCPUClass {
*
* A RISCV CPU.
*/
-struct RISCVCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index f81bf5b592..b4abd90ccd 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -105,7 +105,7 @@ typedef struct CPUArchState {
*
* A RX CPU
*/
-struct RXCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index bdf3f7d4fe..c49c8466e7 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -163,7 +163,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
*
* An S/390 CPU.
*/
-struct S390CPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dd477ba577..c72a30edfd 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -195,7 +195,7 @@ typedef struct CPUArchState {
*
* A SuperH CPU.
*/
-struct SuperHCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 2a7fd47da3..abb38db674 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -556,7 +556,7 @@ struct CPUArchState {
*
* A SPARC CPU.
*/
-struct SPARCCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index cd1954aa9e..108d6b8288 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -196,7 +196,7 @@ typedef struct CPUArchState {
*
* A TriCore CPU.
*/
-struct TriCoreCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index a361ab8785..4515f682aa 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -553,7 +553,7 @@ struct CPUArchState {
*
* An Xtensa CPU.
*/
-struct XtensaCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include
2022-02-14 18:31 ` [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include Philippe Mathieu-Daudé via
@ 2022-02-15 8:47 ` Damien Hedde
2022-02-25 0:04 ` Richard Henderson
1 sibling, 0 replies; 21+ messages in thread
From: Damien Hedde @ 2022-02-15 8:47 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Eduardo Habkost, Paolo Bonzini, Thomas Huth, Richard Henderson,
Taylor Simpson
On 2/14/22 19:31, Philippe Mathieu-Daudé via wrote:
> HexagonCPU field parent_class is of type CPUClass, which
> is declared in "hw/core/cpu.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
> ---
> target/hexagon/cpu.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 096aa2deb6..76cd1d5021 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -27,6 +27,7 @@ typedef struct CPUHexagonState CPUHexagonState;
> #include "hex_regs.h"
> #include "mmvec/mmvec.h"
> #include "qom/object.h"
> +#include "hw/core/cpu.h"
>
> #define NUM_PREGS 4
> #define TOTAL_PER_THREAD_REGS 64
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (13 preceding siblings ...)
2022-02-14 18:31 ` [PATCH v2 14/14] target: Use ArchCPU as interface to target CPU Philippe Mathieu-Daudé via
@ 2022-02-15 17:45 ` Damien Hedde
2022-03-06 11:12 ` Philippe Mathieu-Daudé
15 siblings, 0 replies; 21+ messages in thread
From: Damien Hedde @ 2022-02-15 17:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Eduardo Habkost, Paolo Bonzini, Thomas Huth, Richard Henderson,
Taylor Simpson
Hi Philippe,
What's the idea behind these 2 types: ArchCPU and CPUArchState ?
I don't understand why we'll need them.
Thanks,
Damien
On 2/14/22 19:31, Philippe Mathieu-Daudé via wrote:
> Missing review: 10, 13, 14
>
> Since v1:
> - Include Hexagon OBJECT_DECLARE_TYPE() patch
> - Add missing includes to Hexagon
> - Introduce OBJECT_DECLARE_CPU_TYPE() macro
> - Use OBJECT_DECLARE_CPU_TYPE()
>
> Kind of respin of the "exec: Move translation declarations to
> 'translate-all.h'" series, but without modifying translate-all.h :)
> (same same but different).
>
> Based-on: <20220207082756.82600-1-f4bug@amsat.org>
> "exec: Remove 'qemu/log.h' from 'exec-all.h'"
>
> Philippe Mathieu-Daudé (13):
> meson: Display libfdt as disabled when system emulation is disabled
> hw/m68k/mcf: Add missing 'exec/hwaddr.h' header
> hw/tricore: Remove unused and incorrect header
> exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition
> cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers
> target/i386/cpu: Ensure accelerators set CPU addressble physical bits
> target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header
> target: Include missing 'cpu.h'
> target/hexagon: Add missing 'hw/core/cpu.h' include
> target: Use forward declared type instead of structure type
> target: Use CPUArchState as interface to target-specific CPU state
> target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
> target: Use ArchCPU as interface to target CPU
>
> Taylor Simpson (1):
> Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE
>
> cpu.c | 2 ++
> include/exec/cpu_ldst.h | 1 +
> include/exec/poison.h | 2 --
> include/hw/core/cpu.h | 20 +++++++++++++++++++-
> include/hw/m68k/mcf.h | 1 +
> include/hw/tricore/triboard.h | 1 -
> include/qemu/typedefs.h | 2 ++
> meson.build | 4 +++-
> target/alpha/cpu-qom.h | 3 +--
> target/alpha/cpu.h | 11 +++--------
> target/arm/cpu-qom.h | 3 +--
> target/arm/cpu.h | 7 ++-----
> target/arm/hvf_arm.h | 2 +-
> target/avr/cpu-qom.h | 3 +--
> target/avr/cpu.h | 13 ++++---------
> target/cris/cpu-qom.h | 3 +--
> target/cris/cpu.h | 7 ++-----
> target/hexagon/cpu.h | 23 ++++++++---------------
> target/hppa/cpu-qom.h | 3 +--
> target/hppa/cpu.h | 12 +++---------
> target/i386/cpu-qom.h | 3 +--
> target/i386/cpu.c | 1 +
> target/i386/cpu.h | 7 ++-----
> target/i386/tcg/sysemu/excp_helper.c | 1 +
> target/i386/tcg/sysemu/misc_helper.c | 1 +
> target/m68k/cpu-qom.h | 3 +--
> target/m68k/cpu.h | 7 ++-----
> target/microblaze/cpu-qom.h | 3 +--
> target/microblaze/cpu.h | 9 +++------
> target/microblaze/mmu.h | 2 ++
> target/mips/cpu-qom.h | 3 +--
> target/mips/cpu.h | 10 +++-------
> target/mips/internal.h | 15 ++++++++-------
> target/nios2/cpu.h | 9 ++++-----
> target/nios2/mmu.h | 2 ++
> target/openrisc/cpu.h | 17 +++++------------
> target/ppc/cpu-qom.h | 5 ++---
> target/ppc/cpu.h | 7 ++-----
> target/riscv/cpu.h | 11 ++++-------
> target/riscv/pmp.h | 2 ++
> target/rx/cpu-qom.h | 5 +----
> target/rx/cpu.h | 6 ++----
> target/s390x/cpu-qom.h | 7 +++----
> target/s390x/cpu.h | 7 ++-----
> target/sh4/cpu-qom.h | 3 +--
> target/sh4/cpu.h | 7 ++-----
> target/sparc/cpu-qom.h | 3 +--
> target/sparc/cpu.h | 9 +++------
> target/tricore/cpu-qom.h | 3 +--
> target/tricore/cpu.h | 10 +++-------
> target/xtensa/cpu-qom.h | 3 +--
> target/xtensa/cpu.h | 13 +++++--------
> 52 files changed, 129 insertions(+), 188 deletions(-)
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include
2022-02-14 18:31 ` [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include Philippe Mathieu-Daudé via
2022-02-15 8:47 ` Damien Hedde
@ 2022-02-25 0:04 ` Richard Henderson
1 sibling, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2022-02-25 0:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Eduardo Habkost, Paolo Bonzini, Thomas Huth, Taylor Simpson
On 2/14/22 08:31, Philippe Mathieu-Daudé wrote:
> HexagonCPU field parent_class is of type CPUClass, which
> is declared in "hw/core/cpu.h".
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/hexagon/cpu.h | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 13/14] target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
2022-02-14 18:31 ` [PATCH v2 13/14] target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro Philippe Mathieu-Daudé via
@ 2022-02-25 0:08 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2022-02-25 0:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Eduardo Habkost, Paolo Bonzini, Thomas Huth, Taylor Simpson
On 2/14/22 08:31, Philippe Mathieu-Daudé wrote:
> Replace the boilerplate code to declare CPU QOM types
> and macros, and forward-declare the CPU instance type.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 14/14] target: Use ArchCPU as interface to target CPU
2022-02-14 18:31 ` [PATCH v2 14/14] target: Use ArchCPU as interface to target CPU Philippe Mathieu-Daudé via
@ 2022-02-25 0:10 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2022-02-25 0:10 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Eduardo Habkost, Paolo Bonzini, Thomas Huth, Taylor Simpson
On 2/14/22 08:31, Philippe Mathieu-Daudé wrote:
> ArchCPU is our interface with target-specific code. Use it as
> a forward-declared opaque pointer (abstract type), having its
> structure defined by each target.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> include/hw/core/cpu.h | 4 ++--
> include/qemu/typedefs.h | 1 +
> target/alpha/cpu.h | 2 +-
> target/arm/cpu.h | 2 +-
> target/avr/cpu.h | 2 +-
> target/cris/cpu.h | 2 +-
> target/hexagon/cpu.h | 2 +-
> target/hppa/cpu.h | 2 +-
> target/i386/cpu.h | 2 +-
> target/m68k/cpu.h | 2 +-
> target/microblaze/cpu.h | 2 +-
> target/mips/cpu.h | 2 +-
> target/nios2/cpu.h | 2 +-
> target/openrisc/cpu.h | 2 +-
> target/ppc/cpu.h | 2 +-
> target/riscv/cpu.h | 2 +-
> target/rx/cpu.h | 2 +-
> target/s390x/cpu.h | 2 +-
> target/sh4/cpu.h | 2 +-
> target/sparc/cpu.h | 2 +-
> target/tricore/cpu.h | 2 +-
> target/xtensa/cpu.h | 2 +-
> 22 files changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 2a0893b1dc..0efc6153ed 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -70,8 +70,8 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU,
> * The object struct and class struct need to be declared manually.
> */
> #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
> - OBJECT_DECLARE_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME); \
> - typedef CpuInstanceType ArchCPU;
> + typedef struct ArchCPU CpuInstanceType; \
> + OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
>
Nice.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
` (14 preceding siblings ...)
2022-02-15 17:45 ` [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract " Damien Hedde
@ 2022-03-06 11:12 ` Philippe Mathieu-Daudé
15 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-06 11:12 UTC (permalink / raw)
To: qemu-devel
Cc: Eduardo Habkost, Thomas Huth, Richard Henderson,
Philippe Mathieu-Daudé,
Taylor Simpson, Paolo Bonzini
On 14/2/22 19:31, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (13):
> meson: Display libfdt as disabled when system emulation is disabled
> hw/m68k/mcf: Add missing 'exec/hwaddr.h' header
> hw/tricore: Remove unused and incorrect header
> exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition
> cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers
> target/i386/cpu: Ensure accelerators set CPU addressble physical bits
> target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header
> target: Include missing 'cpu.h'
> target/hexagon: Add missing 'hw/core/cpu.h' include
> target: Use forward declared type instead of structure type
> target: Use CPUArchState as interface to target-specific CPU state
> target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
> target: Use ArchCPU as interface to target CPU
>
> Taylor Simpson (1):
> Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE
Since this series is fully reviewed and soft-freeze is soon,
I'm going to send a pull request for this cleanup.
Queuing as 'abstract-arch-cpu'.
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-03-06 11:17 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-14 18:31 [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract interface to target CPU Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 01/14] meson: Display libfdt as disabled when system emulation is disabled Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 02/14] hw/m68k/mcf: Add missing 'exec/hwaddr.h' header Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 03/14] hw/tricore: Remove unused and incorrect header Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 04/14] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 05/14] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 06/14] target/i386/cpu: Ensure accelerators set CPU addressble physical bits Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 07/14] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 08/14] Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 09/14] target: Include missing 'cpu.h' Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 10/14] target/hexagon: Add missing 'hw/core/cpu.h' include Philippe Mathieu-Daudé via
2022-02-15 8:47 ` Damien Hedde
2022-02-25 0:04 ` Richard Henderson
2022-02-14 18:31 ` [PATCH v2 11/14] target: Use forward declared type instead of structure type Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 12/14] target: Use CPUArchState as interface to target-specific CPU state Philippe Mathieu-Daudé via
2022-02-14 18:31 ` [PATCH v2 13/14] target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro Philippe Mathieu-Daudé via
2022-02-25 0:08 ` Richard Henderson
2022-02-14 18:31 ` [PATCH v2 14/14] target: Use ArchCPU as interface to target CPU Philippe Mathieu-Daudé via
2022-02-25 0:10 ` Richard Henderson
2022-02-15 17:45 ` [PATCH v2 00/14] target: Use ArchCPU & CPUArchState as abstract " Damien Hedde
2022-03-06 11:12 ` Philippe Mathieu-Daudé
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