* [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C
@ 2020-10-28 22:54 Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 1/6] i2c: mlxbf: Add CONFIG_ACPI to guard ACPI function call Khalil Blaiech
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-10-28 22:54 UTC (permalink / raw)
To: linux-i2c; +Cc: kblaiech, wsa+renesas
This set of fixes tends to complement the upstream effort of the
driver code and aims to address the following issues:
- Convert the DT file to a YAML schema to be consistent with the
latest kernel releases.
- Fix build issues reproted by the kernel test robot.
- Apply a couple of changes to the driver code to include bug fixes.
- Keep the MAINTAINER info up-to-date.
Khalil Blaiech (6):
i2c: mlxbf: Add CONFIG_ACPI to guard ACPI function call
i2c: mlxbf: Fix resrticted cast warning of sparse
i2c: mlxbf: Remove unecessary wrapper functions
i2c: mlxbf: Update reference clock frequency
i2c: mlxbf: Update author and maintainer email info
dt-bindings: i2c: Convert DT file to YAML schema
.../bindings/i2c/mellanox,i2c-mlxbf.txt | 42 ----
.../bindings/i2c/mellanox,i2c-mlxbf.yaml | 78 +++++++
MAINTAINERS | 3 +-
drivers/i2c/busses/i2c-mlxbf.c | 204 ++++++++----------
4 files changed, 166 insertions(+), 161 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
create mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
--
2.24.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH i2c-next v1 1/6] i2c: mlxbf: Add CONFIG_ACPI to guard ACPI function call
2020-10-28 22:54 [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C Khalil Blaiech
@ 2020-10-28 22:54 ` Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 2/6] i2c: mlxbf: Fix resrticted cast warning of sparse Khalil Blaiech
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-10-28 22:54 UTC (permalink / raw)
To: linux-i2c
Cc: kblaiech, wsa+renesas, kernel test robot, Leon Romanovsky,
Vadim Pasternak
The build fails with "implicit declaration of function
'acpi_device_uid'" error. Thus, protect ACPI function calls
from being called when CONFIG_ACPI is disabled.
Fixes: b5b5b32081cd206b ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
---
drivers/i2c/busses/i2c-mlxbf.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index ee59e0da082d..e18f595b37a7 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -2264,6 +2264,7 @@ static const struct of_device_id mlxbf_i2c_dt_ids[] = {
MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids);
+#ifdef CONFIG_ACPI
static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = {
{ "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] },
{ "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] },
@@ -2305,6 +2306,12 @@ static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
return ret;
}
+#else
+static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
+{
+ return -ENOENT;
+}
+#endif /* CONFIG_ACPI */
static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
{
@@ -2473,7 +2480,9 @@ static struct platform_driver mlxbf_i2c_driver = {
.driver = {
.name = "i2c-mlxbf",
.of_match_table = mlxbf_i2c_dt_ids,
+#ifdef CONFIG_ACPI
.acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids),
+#endif /* CONFIG_ACPI */
},
};
--
2.24.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH i2c-next v1 2/6] i2c: mlxbf: Fix resrticted cast warning of sparse
2020-10-28 22:54 [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 1/6] i2c: mlxbf: Add CONFIG_ACPI to guard ACPI function call Khalil Blaiech
@ 2020-10-28 22:54 ` Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 3/6] i2c: mlxbf: Remove unecessary wrapper functions Khalil Blaiech
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-10-28 22:54 UTC (permalink / raw)
To: linux-i2c
Cc: kblaiech, wsa+renesas, kernel test robot, Leon Romanovsky,
Vadim Pasternak
Address warnings "warning: cast to restricted __be32" reported
by sparse.
Fixes: b5b5b32081cd206b ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
---
drivers/i2c/busses/i2c-mlxbf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index e18f595b37a7..4bd80b1b6a29 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -510,7 +510,7 @@ static u32 mlxbf_i2c_read(void __iomem *io, int reg)
*/
static u32 mlxbf_i2c_read_data(void __iomem *io, int reg)
{
- return (u32)be32_to_cpu(mlxbf_i2c_read(io, reg));
+ return ioread32be(io + reg);
}
/*
@@ -524,7 +524,7 @@ static u32 mlxbf_i2c_read_data(void __iomem *io, int reg)
*/
static void mlxbf_i2c_write_data(void __iomem *io, int reg, u32 val)
{
- mlxbf_i2c_write(io, reg, (u32)cpu_to_be32(val));
+ iowrite32be(val, io + reg);
}
/*
--
2.24.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH i2c-next v1 3/6] i2c: mlxbf: Remove unecessary wrapper functions
2020-10-28 22:54 [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 1/6] i2c: mlxbf: Add CONFIG_ACPI to guard ACPI function call Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 2/6] i2c: mlxbf: Fix resrticted cast warning of sparse Khalil Blaiech
@ 2020-10-28 22:54 ` Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 4/6] i2c: mlxbf: Update reference clock frequency Khalil Blaiech
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-10-28 22:54 UTC (permalink / raw)
To: linux-i2c; +Cc: kblaiech, wsa+renesas, Leon Romanovsky, Vadim Pasternak
Few wrapper functions are useless and can be inlined. So
delete mlxbf_i2c_read() and mlxbf_i2c_write() and replace
them with readl() and writel(), respectively. Also delete
mlxbf_i2c_read_data() and mlxbf_i2c_write() and replace
them with ioread32be() and iowrite32be(), respectively.
Fixes: b5b5b32081cd206b ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
---
drivers/i2c/busses/i2c-mlxbf.c | 183 +++++++++++++--------------------
1 file changed, 72 insertions(+), 111 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index 4bd80b1b6a29..fca8a3bddcb1 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -489,44 +489,6 @@ static struct mutex mlxbf_i2c_bus_lock;
#define MLXBF_I2C_FREQUENCY_1GHZ 1000000000
-static void mlxbf_i2c_write(void __iomem *io, int reg, u32 val)
-{
- writel(val, io + reg);
-}
-
-static u32 mlxbf_i2c_read(void __iomem *io, int reg)
-{
- return readl(io + reg);
-}
-
-/*
- * This function is used to read data from Master GW Data Descriptor.
- * Data bytes in the Master GW Data Descriptor are shifted left so the
- * data starts at the MSB of the descriptor registers as set by the
- * underlying hardware. TYU_READ_DATA enables byte swapping while
- * reading data bytes, and MUST be called by the SMBus read routines
- * to copy data from the 32 * 32-bit HW Data registers a.k.a Master GW
- * Data Descriptor.
- */
-static u32 mlxbf_i2c_read_data(void __iomem *io, int reg)
-{
- return ioread32be(io + reg);
-}
-
-/*
- * This function is used to write data to the Master GW Data Descriptor.
- * Data copied to the Master GW Data Descriptor MUST be shifted left so
- * the data starts at the MSB of the descriptor registers as required by
- * the underlying hardware. TYU_WRITE_DATA enables byte swapping when
- * writing data bytes, and MUST be called by the SMBus write routines to
- * copy data to the 32 * 32-bit HW Data registers a.k.a Master GW Data
- * Descriptor.
- */
-static void mlxbf_i2c_write_data(void __iomem *io, int reg, u32 val)
-{
- iowrite32be(val, io + reg);
-}
-
/*
* Function to poll a set of bits at a specific address; it checks whether
* the bits are equal to zero when eq_zero is set to 'true', and not equal
@@ -541,7 +503,7 @@ static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask,
timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;
do {
- bits = mlxbf_i2c_read(io, addr) & mask;
+ bits = readl(io + addr) & mask;
if (eq_zero ? bits == 0 : bits != 0)
return eq_zero ? 1 : bits;
udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);
@@ -609,16 +571,16 @@ static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)
MLXBF_I2C_SMBUS_TIMEOUT);
/* Read cause status bits. */
- cause_status_bits = mlxbf_i2c_read(priv->mst_cause->io,
- MLXBF_I2C_CAUSE_ARBITER);
+ cause_status_bits = readl(priv->mst_cause->io +
+ MLXBF_I2C_CAUSE_ARBITER);
cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;
/*
* Parse both Cause and Master GW bits, then return transaction status.
*/
- master_status_bits = mlxbf_i2c_read(priv->smbus->io,
- MLXBF_I2C_SMBUS_MASTER_STATUS);
+ master_status_bits = readl(priv->smbus->io +
+ MLXBF_I2C_SMBUS_MASTER_STATUS);
master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;
if (mlxbf_i2c_smbus_transaction_success(master_status_bits,
@@ -649,10 +611,17 @@ static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,
aligned_length = round_up(length, 4);
- /* Copy data bytes from 4-byte aligned source buffer. */
+ /*
+ * Copy data bytes from 4-byte aligned source buffer.
+ * Data copied to the Master GW Data Descriptor MUST be shifted
+ * left so the data starts at the MSB of the descriptor registers
+ * as required by the underlying hardware. Enable byte swapping
+ * when writing data bytes to the 32 * 32-bit HW Data registers
+ * a.k.a Master GW Data Descriptor.
+ */
for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {
data32 = *((u32 *)(data + offset));
- mlxbf_i2c_write_data(priv->smbus->io, addr + offset, data32);
+ iowrite32be(data32, priv->smbus->io + addr + offset);
}
}
@@ -664,15 +633,23 @@ static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,
mask = sizeof(u32) - 1;
+ /*
+ * Data bytes in the Master GW Data Descriptor are shifted left
+ * so the data starts at the MSB of the descriptor registers as
+ * set by the underlying hardware. Enable byte swapping while
+ * reading data bytes from the 32 * 32-bit HW Data registers
+ * a.k.a Master GW Data Descriptor.
+ */
+
for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {
- data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset);
+ data32 = ioread32be(priv->smbus->io + addr + offset);
*((u32 *)(data + offset)) = data32;
}
if (!(length & mask))
return;
- data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset);
+ data32 = ioread32be(priv->smbus->io + addr + offset);
for (byte = 0; byte < (length & mask); byte++) {
data[offset + byte] = data32 & GENMASK(7, 0);
@@ -698,16 +675,16 @@ static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
/* Clear status bits. */
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_STATUS, 0x0);
+ writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
/* Set the cause data. */
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0);
+ writel(~0x0, priv->smbus->io + MLXBF_I2C_CAUSE_OR_CLEAR);
/* Zero PEC byte. */
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_PEC, 0x0);
+ writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC);
/* Zero byte count. */
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_RS_BYTES, 0x0);
+ writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES);
/* GW activation. */
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, command);
+ writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
/*
* Poll master status and check status bits. An ACK is sent when
@@ -823,8 +800,8 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
* needs to be 'manually' reset. This should be removed in
* next tag integration.
*/
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_FSM,
- MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK);
+ writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
+ priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM);
}
return ret;
@@ -1113,8 +1090,8 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,
false, MLXBF_I2C_MASK_16,
MLXBF_I2C_SHIFT_16);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH,
- timer);
+ writel(timer, priv->smbus->io +
+ MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);
timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,
MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);
@@ -1124,37 +1101,34 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);
timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,
MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE,
- timer);
+ writel(timer, priv->smbus->io +
+ MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);
timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,
MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,
MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_THOLD, timer);
+ writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,
MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,
MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
- mlxbf_i2c_write(priv->smbus->io,
- MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP, timer);
+ writel(timer, priv->smbus->io +
+ MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);
timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,
MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA,
- timer);
+ writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
timer = mlxbf_i2c_set_timer(priv, timings->buf, false,
MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,
MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_THIGH_MAX_TBUF,
- timer);
+ writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
timer = timings->timeout;
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT,
- timer);
+ writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
}
enum mlxbf_i2c_timings_config {
@@ -1426,19 +1400,15 @@ static int mlxbf_i2c_init_master(struct platform_device *pdev,
* platform firmware; disabling the bus might compromise the system
* functionality.
*/
- config_reg = mlxbf_i2c_read(gpio_res->io,
- MLXBF_I2C_GPIO_0_FUNC_EN_0);
+ config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,
config_reg);
- mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FUNC_EN_0,
- config_reg);
+ writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
- config_reg = mlxbf_i2c_read(gpio_res->io,
- MLXBF_I2C_GPIO_0_FORCE_OE_EN);
+ config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,
config_reg);
- mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FORCE_OE_EN,
- config_reg);
+ writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
mutex_unlock(gpio_res->lock);
@@ -1454,8 +1424,7 @@ static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ;
- corepll_val = mlxbf_i2c_read(corepll_res->io,
- MLXBF_I2C_CORE_PLL_REG1);
+ corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
/* Get Core PLL configuration bits. */
core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) &
@@ -1490,10 +1459,8 @@ static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ;
- corepll_reg1_val = mlxbf_i2c_read(corepll_res->io,
- MLXBF_I2C_CORE_PLL_REG1);
- corepll_reg2_val = mlxbf_i2c_read(corepll_res->io,
- MLXBF_I2C_CORE_PLL_REG2);
+ corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
+ corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
/* Get Core PLL configuration bits */
core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) &
@@ -1585,7 +1552,7 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
* (7-bit address, 1 status bit (1 if enabled, 0 if not)).
*/
for (reg = 0; reg < reg_cnt; reg++) {
- slave_reg = mlxbf_i2c_read(priv->smbus->io,
+ slave_reg = readl(priv->smbus->io +
MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
/*
* Each register holds 4 slave addresses. So, we have to keep
@@ -1643,8 +1610,8 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
/* Enable the slave address and update the register. */
slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8);
- mlxbf_i2c_write(priv->smbus->io,
- MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg);
+ writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
+ reg * 0x4);
return 0;
}
@@ -1668,7 +1635,7 @@ static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
* (7-bit address, 1 status bit (1 if enabled, 0 if not)).
*/
for (reg = 0; reg < reg_cnt; reg++) {
- slave_reg = mlxbf_i2c_read(priv->smbus->io,
+ slave_reg = readl(priv->smbus->io +
MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
/* Check whether the address slots are empty. */
@@ -1708,8 +1675,8 @@ static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
/* Cleanup the slave address slot. */
slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8));
- mlxbf_i2c_write(priv->smbus->io,
- MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg);
+ writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
+ reg * 0x4);
return 0;
}
@@ -1801,7 +1768,7 @@ static int mlxbf_i2c_init_slave(struct platform_device *pdev,
int ret;
/* Reset FSM. */
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_FSM, 0);
+ writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
/*
* Enable slave cause interrupt bits. Drive
@@ -1810,15 +1777,13 @@ static int mlxbf_i2c_init_slave(struct platform_device *pdev,
* masters issue a Read and Write, respectively. But, clear all
* interrupts first.
*/
- mlxbf_i2c_write(priv->slv_cause->io,
- MLXBF_I2C_CAUSE_OR_CLEAR, ~0);
+ writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;
int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;
- mlxbf_i2c_write(priv->slv_cause->io,
- MLXBF_I2C_CAUSE_OR_EVTEN0, int_reg);
+ writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
/* Finally, set the 'ready' bit to start handling transactions. */
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
+ writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
/* Initialize the cause coalesce resource. */
ret = mlxbf_i2c_init_coalesce(pdev, priv);
@@ -1844,23 +1809,21 @@ static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,
MLXBF_I2C_CAUSE_YU_SLAVE_BIT :
priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;
- coalesce0_reg = mlxbf_i2c_read(priv->coalesce->io,
- MLXBF_I2C_CAUSE_COALESCE_0);
+ coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);
is_set = coalesce0_reg & (1 << slave_shift);
if (!is_set)
return false;
/* Check the source of the interrupt, i.e. whether a Read or Write. */
- cause_reg = mlxbf_i2c_read(priv->slv_cause->io,
- MLXBF_I2C_CAUSE_ARBITER);
+ cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);
if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)
*read = true;
else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)
*write = true;
/* Clear cause bits. */
- mlxbf_i2c_write(priv->slv_cause->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0);
+ writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
return true;
}
@@ -1900,8 +1863,8 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
* address, if supplied.
*/
if (recv_bytes > 0) {
- data32 = mlxbf_i2c_read_data(priv->smbus->io,
- MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
+ data32 = ioread32be(priv->smbus->io +
+ MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
/* Parse the received bytes. */
switch (recv_bytes) {
@@ -1966,7 +1929,7 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_GW, control32);
+ writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW);
/*
* Wait until the transfer is completed; the driver will wait
@@ -1975,10 +1938,9 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
/* Release the Slave GW. */
- mlxbf_i2c_write(priv->smbus->io,
- MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
+ writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
+ writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
+ writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
return 0;
}
@@ -2023,10 +1985,9 @@ static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
/* Release the Slave GW. */
- mlxbf_i2c_write(priv->smbus->io,
- MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0);
- mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
+ writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
+ writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
+ writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
return ret;
}
@@ -2061,8 +2022,8 @@ static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr)
* slave, if the higher 8 bits are sent then the slave expect N bytes
* from the master.
*/
- rw_bytes_reg = mlxbf_i2c_read(priv->smbus->io,
- MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
+ rw_bytes_reg = readl(priv->smbus->io +
+ MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);
/*
--
2.24.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH i2c-next v1 4/6] i2c: mlxbf: Update reference clock frequency
2020-10-28 22:54 [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C Khalil Blaiech
` (2 preceding siblings ...)
2020-10-28 22:54 ` [PATCH i2c-next v1 3/6] i2c: mlxbf: Remove unecessary wrapper functions Khalil Blaiech
@ 2020-10-28 22:54 ` Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 5/6] i2c: mlxbf: Update author and maintainer email info Khalil Blaiech
2020-10-28 22:55 ` [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema Khalil Blaiech
5 siblings, 0 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-10-28 22:54 UTC (permalink / raw)
To: linux-i2c; +Cc: kblaiech, wsa+renesas, Leon Romanovsky
The reference clock frequency remains the same across Bluefield
products. Thus, update the frequency and rename the macro.
Fixes: b5b5b32081cd206b ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
---
drivers/i2c/busses/i2c-mlxbf.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index fca8a3bddcb1..afc996d07504 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -62,10 +62,8 @@
* Master. Default value is set to 400MHz.
*/
#define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)
-/* Reference clock for Bluefield 1 - 156 MHz. */
-#define MLXBF_I2C_TYU_PLL_IN_FREQ (156 * 1000 * 1000)
-/* Reference clock for BlueField 2 - 200 MHz. */
-#define MLXBF_I2C_YU_PLL_IN_FREQ (200 * 1000 * 1000)
+/* Reference clock for Bluefield - 156 MHz. */
+#define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000)
/* Constant used to determine the PLL frequency. */
#define MLNXBF_I2C_COREPLL_CONST 16384
@@ -1422,7 +1420,7 @@ static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
u32 corepll_val;
u16 core_f;
- pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ;
+ pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
@@ -1457,7 +1455,7 @@ static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
u8 core_od, core_r;
u32 core_f;
- pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ;
+ pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
--
2.24.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH i2c-next v1 5/6] i2c: mlxbf: Update author and maintainer email info
2020-10-28 22:54 [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C Khalil Blaiech
` (3 preceding siblings ...)
2020-10-28 22:54 ` [PATCH i2c-next v1 4/6] i2c: mlxbf: Update reference clock frequency Khalil Blaiech
@ 2020-10-28 22:54 ` Khalil Blaiech
2020-10-28 22:55 ` [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema Khalil Blaiech
5 siblings, 0 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-10-28 22:54 UTC (permalink / raw)
To: linux-i2c; +Cc: kblaiech, wsa+renesas, Leon Romanovsky
Correct the email addresses of the author and the maintainer
of the Mellanox BlueField I2C driver.
Fixes: b5b5b32081cd206b ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
---
MAINTAINERS | 2 +-
drivers/i2c/busses/i2c-mlxbf.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8580de35179f..9128200af1d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11072,7 +11072,7 @@ F: Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt
F: drivers/input/touchscreen/melfas_mip4.c
MELLANOX BLUEFIELD I2C DRIVER
-M: Khalil Blaiech <kblaiech@mellanox.com>
+M: Khalil Blaiech <kblaiech@nvidia.com>
L: linux-i2c@vger.kernel.org
S: Supported
F: drivers/i2c/busses/i2c-mlxbf.c
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index afc996d07504..33574d40ea9c 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -2470,5 +2470,5 @@ static void __exit mlxbf_i2c_exit(void)
module_exit(mlxbf_i2c_exit);
MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");
-MODULE_AUTHOR("Khalil Blaiech <kblaiech@mellanox.com>");
+MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");
MODULE_LICENSE("GPL v2");
--
2.24.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema
2020-10-28 22:54 [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C Khalil Blaiech
` (4 preceding siblings ...)
2020-10-28 22:54 ` [PATCH i2c-next v1 5/6] i2c: mlxbf: Update author and maintainer email info Khalil Blaiech
@ 2020-10-28 22:55 ` Khalil Blaiech
2020-10-29 15:33 ` Rob Herring
2020-10-29 15:33 ` Rob Herring
5 siblings, 2 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-10-28 22:55 UTC (permalink / raw)
To: linux-i2c, devicetree; +Cc: kblaiech, wsa+renesas, Leon Romanovsky
Write the devicetree binding text file in schema file, JSON
compatible subset of YAML.
Besides, add an entry within MAINTAINERS file.
Fixes: d9becc53b3ade81e ("dt-bindings: i2c: I2C binding for Mellanox BlueField SoC")
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
---
.../bindings/i2c/mellanox,i2c-mlxbf.txt | 42 ----------
.../bindings/i2c/mellanox,i2c-mlxbf.yaml | 78 +++++++++++++++++++
MAINTAINERS | 1 +
3 files changed, 79 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
create mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
deleted file mode 100644
index 566ea861aa00..000000000000
--- a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs
-
-Required Properties:
-
-- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2".
-
-- reg : address offset and length of the device registers. The
- registers consist of the following set of resources:
- 1) Smbus block registers.
- 2) Cause master registers.
- 3) Cause slave registers.
- 4) Cause coalesce registers (if compatible isn't set
- to "mellanox,i2c-mlxbf1").
-
-- interrupts : interrupt number.
-
-Optional Properties:
-
-- clock-frequency : bus frequency used to configure timing registers;
- allowed values are 100000, 400000 and 1000000;
- those are expressed in Hz. Default is 100000.
-
-Example:
-
-i2c@2804000 {
- compatible = "mellanox,i2c-mlxbf1";
- reg = <0x02804000 0x800>,
- <0x02801200 0x020>,
- <0x02801260 0x020>;
- interrupts = <57>;
- clock-frequency = <100000>;
-};
-
-i2c@2808800 {
- compatible = "mellanox,i2c-mlxbf2";
- reg = <0x02808800 0x600>,
- <0x02808e00 0x020>,
- <0x02808e20 0x020>,
- <0x02808e40 0x010>;
- interrupts = <57>;
- clock-frequency = <400000>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
new file mode 100644
index 000000000000..b9f6b07c503f
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mellanox I2C SMBus on BlueField SoCs
+
+maintainers:
+ - Khalil Blaiech <kblaiech@nvidia.com>
+
+properties:
+ compatible:
+ enum:
+ - mellanox,i2c-mlxbf1
+ - mellanox,i2c-mlxbf2
+
+ reg:
+ minItems: 3
+ maxItems: 4
+ items:
+ - description: Smbus block registers
+ - description: Cause master registers
+ - description: Cause slave registers
+ - description: Cause coalesce registers
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency:
+ enum: [ 100000, 400000, 1000000 ]
+
+ description:
+ bus frequency used to configure timing registers;
+ The frequency is expressed in Hz. Default is 100000.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mellanox,i2c-mlxbf1
+
+then:
+ properties:
+ reg:
+ maxItems: 3
+
+examples:
+ - |
+ i2c@2804000 {
+ compatible = "mellanox,i2c-mlxbf1";
+ reg = <0x02804000 0x800>,
+ <0x02801200 0x020>,
+ <0x02801260 0x020>;
+ interrupts = <57>;
+ clock-frequency = <100000>;
+ };
+
+ - |
+ i2c@2808800 {
+ compatible = "mellanox,i2c-mlxbf2";
+ reg = <0x02808800 0x600>,
+ <0x02808e00 0x020>,
+ <0x02808e20 0x020>,
+ <0x02808e40 0x010>;
+ interrupts = <57>;
+ clock-frequency = <400000>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9128200af1d0..8dba7ace4a40 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11075,6 +11075,7 @@ MELLANOX BLUEFIELD I2C DRIVER
M: Khalil Blaiech <kblaiech@nvidia.com>
L: linux-i2c@vger.kernel.org
S: Supported
+F: Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
F: drivers/i2c/busses/i2c-mlxbf.c
MELLANOX ETHERNET DRIVER (mlx4_en)
--
2.24.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema
2020-10-28 22:55 ` [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema Khalil Blaiech
@ 2020-10-29 15:33 ` Rob Herring
2020-11-03 14:08 ` Khalil Blaiech
2020-10-29 15:33 ` Rob Herring
1 sibling, 1 reply; 11+ messages in thread
From: Rob Herring @ 2020-10-29 15:33 UTC (permalink / raw)
To: Khalil Blaiech; +Cc: linux-i2c, devicetree, wsa+renesas, Leon Romanovsky
On Wed, Oct 28, 2020 at 06:55:54PM -0400, Khalil Blaiech wrote:
> Write the devicetree binding text file in schema file, JSON
> compatible subset of YAML.
> Besides, add an entry within MAINTAINERS file.
The subject should contain something about Mellanox BlueField.
>
> Fixes: d9becc53b3ade81e ("dt-bindings: i2c: I2C binding for Mellanox BlueField SoC")
Fixes is not appropriate for this.
> Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
> Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
> ---
> .../bindings/i2c/mellanox,i2c-mlxbf.txt | 42 ----------
> .../bindings/i2c/mellanox,i2c-mlxbf.yaml | 78 +++++++++++++++++++
> MAINTAINERS | 1 +
> 3 files changed, 79 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> create mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
>
> diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> deleted file mode 100644
> index 566ea861aa00..000000000000
> --- a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs
> -
> -Required Properties:
> -
> -- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2".
> -
> -- reg : address offset and length of the device registers. The
> - registers consist of the following set of resources:
> - 1) Smbus block registers.
> - 2) Cause master registers.
> - 3) Cause slave registers.
> - 4) Cause coalesce registers (if compatible isn't set
> - to "mellanox,i2c-mlxbf1").
> -
> -- interrupts : interrupt number.
> -
> -Optional Properties:
> -
> -- clock-frequency : bus frequency used to configure timing registers;
> - allowed values are 100000, 400000 and 1000000;
> - those are expressed in Hz. Default is 100000.
> -
> -Example:
> -
> -i2c@2804000 {
> - compatible = "mellanox,i2c-mlxbf1";
> - reg = <0x02804000 0x800>,
> - <0x02801200 0x020>,
> - <0x02801260 0x020>;
> - interrupts = <57>;
> - clock-frequency = <100000>;
> -};
> -
> -i2c@2808800 {
> - compatible = "mellanox,i2c-mlxbf2";
> - reg = <0x02808800 0x600>,
> - <0x02808e00 0x020>,
> - <0x02808e20 0x020>,
> - <0x02808e40 0x010>;
> - interrupts = <57>;
> - clock-frequency = <400000>;
> -};
> diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
> new file mode 100644
> index 000000000000..b9f6b07c503f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: GPL-2.0
If you have rights, please dual license adding BSD-2-Clause.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mellanox I2C SMBus on BlueField SoCs
> +
> +maintainers:
> + - Khalil Blaiech <kblaiech@nvidia.com>
allOf:
- $ref: i2c-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - mellanox,i2c-mlxbf1
> + - mellanox,i2c-mlxbf2
> +
> + reg:
> + minItems: 3
> + maxItems: 4
> + items:
> + - description: Smbus block registers
> + - description: Cause master registers
> + - description: Cause slave registers
> + - description: Cause coalesce registers
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-frequency:
> + enum: [ 100000, 400000, 1000000 ]
> +
Drop the blank line.
> + description:
> + bus frequency used to configure timing registers;
> + The frequency is expressed in Hz. Default is 100000.
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +unevaluatedProperties: false
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mellanox,i2c-mlxbf1
> +
> +then:
> + properties:
> + reg:
> + maxItems: 3
> +
> +examples:
> + - |
> + i2c@2804000 {
> + compatible = "mellanox,i2c-mlxbf1";
> + reg = <0x02804000 0x800>,
> + <0x02801200 0x020>,
> + <0x02801260 0x020>;
> + interrupts = <57>;
> + clock-frequency = <100000>;
> + };
> +
> + - |
> + i2c@2808800 {
> + compatible = "mellanox,i2c-mlxbf2";
> + reg = <0x02808800 0x600>,
> + <0x02808e00 0x020>,
> + <0x02808e20 0x020>,
> + <0x02808e40 0x010>;
> + interrupts = <57>;
> + clock-frequency = <400000>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9128200af1d0..8dba7ace4a40 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11075,6 +11075,7 @@ MELLANOX BLUEFIELD I2C DRIVER
> M: Khalil Blaiech <kblaiech@nvidia.com>
> L: linux-i2c@vger.kernel.org
> S: Supported
> +F: Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
> F: drivers/i2c/busses/i2c-mlxbf.c
>
> MELLANOX ETHERNET DRIVER (mlx4_en)
> --
> 2.24.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema
2020-10-28 22:55 ` [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema Khalil Blaiech
2020-10-29 15:33 ` Rob Herring
@ 2020-10-29 15:33 ` Rob Herring
2020-11-03 14:06 ` Khalil Blaiech
1 sibling, 1 reply; 11+ messages in thread
From: Rob Herring @ 2020-10-29 15:33 UTC (permalink / raw)
To: Khalil Blaiech; +Cc: linux-i2c, Leon Romanovsky, devicetree, wsa+renesas
On Wed, 28 Oct 2020 18:55:54 -0400, Khalil Blaiech wrote:
> Write the devicetree binding text file in schema file, JSON
> compatible subset of YAML.
> Besides, add an entry within MAINTAINERS file.
>
> Fixes: d9becc53b3ade81e ("dt-bindings: i2c: I2C binding for Mellanox BlueField SoC")
> Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
> Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
> ---
> .../bindings/i2c/mellanox,i2c-mlxbf.txt | 42 ----------
> .../bindings/i2c/mellanox,i2c-mlxbf.yaml | 78 +++++++++++++++++++
> MAINTAINERS | 1 +
> 3 files changed, 79 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> create mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml:28:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml:31:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
dtschema/dtc warnings/errors:
See https://patchwork.ozlabs.org/patch/1389582
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema
2020-10-29 15:33 ` Rob Herring
@ 2020-11-03 14:06 ` Khalil Blaiech
0 siblings, 0 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-11-03 14:06 UTC (permalink / raw)
To: Rob Herring; +Cc: linux-i2c, Leon Romanovsky, devicetree, wsa+renesas
> On Wed, 28 Oct 2020 18:55:54 -0400, Khalil Blaiech wrote:
> > Write the devicetree binding text file in schema file, JSON
> > compatible subset of YAML.
> > Besides, add an entry within MAINTAINERS file.
> >
> > Fixes: d9becc53b3ade81e ("dt-bindings: i2c: I2C binding for Mellanox
> BlueField SoC")
> > Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
> > Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
> > ---
> > .../bindings/i2c/mellanox,i2c-mlxbf.txt | 42 ----------
> > .../bindings/i2c/mellanox,i2c-mlxbf.yaml | 78 +++++++++++++++++++
> > MAINTAINERS | 1 +
> > 3 files changed, 79 insertions(+), 42 deletions(-)
> > delete mode 100644
> Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> > create mode 100644
> Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
> >
>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml:28:7:
> [warning] wrong indentation: expected 4 but found 6 (indentation)
> ./Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml:31:7:
> [warning] wrong indentation: expected 4 but found 6 (indentation)
>
> dtschema/dtc warnings/errors:
>
>
> See https://patchwork.ozlabs.org/patch/1389582
>
> The base for the patch is generally the last rc1. Any dependencies
> should be noted.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
Thank you, Rob. Will do.
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema
2020-10-29 15:33 ` Rob Herring
@ 2020-11-03 14:08 ` Khalil Blaiech
0 siblings, 0 replies; 11+ messages in thread
From: Khalil Blaiech @ 2020-11-03 14:08 UTC (permalink / raw)
To: Rob Herring; +Cc: linux-i2c, devicetree, wsa+renesas, Leon Romanovsky
> On Wed, Oct 28, 2020 at 06:55:54PM -0400, Khalil Blaiech wrote:
> > Write the devicetree binding text file in schema file, JSON
> > compatible subset of YAML.
> > Besides, add an entry within MAINTAINERS file.
>
> The subject should contain something about Mellanox BlueField.
Got it.
> >
> > Fixes: d9becc53b3ade81e ("dt-bindings: i2c: I2C binding for Mellanox
> BlueField SoC")
>
> Fixes is not appropriate for this.
Should I remove?
>
> > Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
> > Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
> > ---
> > .../bindings/i2c/mellanox,i2c-mlxbf.txt | 42 ----------
> > .../bindings/i2c/mellanox,i2c-mlxbf.yaml | 78 +++++++++++++++++++
> > MAINTAINERS | 1 +
> > 3 files changed, 79 insertions(+), 42 deletions(-)
> > delete mode 100644
> Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> > create mode 100644
> Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> > deleted file mode 100644
> > index 566ea861aa00..000000000000
> > --- a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
> > +++ /dev/null
> > @@ -1,42 +0,0 @@
> > -Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs
> > -
> > -Required Properties:
> > -
> > -- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2".
> > -
> > -- reg : address offset and length of the device registers. The
> > - registers consist of the following set of resources:
> > - 1) Smbus block registers.
> > - 2) Cause master registers.
> > - 3) Cause slave registers.
> > - 4) Cause coalesce registers (if compatible isn't set
> > - to "mellanox,i2c-mlxbf1").
> > -
> > -- interrupts : interrupt number.
> > -
> > -Optional Properties:
> > -
> > -- clock-frequency : bus frequency used to configure timing registers;
> > - allowed values are 100000, 400000 and 1000000;
> > - those are expressed in Hz. Default is 100000.
> > -
> > -Example:
> > -
> > -i2c@2804000 {
> > - compatible = "mellanox,i2c-mlxbf1";
> > - reg = <0x02804000 0x800>,
> > - <0x02801200 0x020>,
> > - <0x02801260 0x020>;
> > - interrupts = <57>;
> > - clock-frequency = <100000>;
> > -};
> > -
> > -i2c@2808800 {
> > - compatible = "mellanox,i2c-mlxbf2";
> > - reg = <0x02808800 0x600>,
> > - <0x02808e00 0x020>,
> > - <0x02808e20 0x020>,
> > - <0x02808e40 0x010>;
> > - interrupts = <57>;
> > - clock-frequency = <400000>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-
> mlxbf.yaml b/Documentation/devicetree/bindings/i2c/mellanox,i2c-
> mlxbf.yaml
> > new file mode 100644
> > index 000000000000..b9f6b07c503f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
> > @@ -0,0 +1,78 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> If you have rights, please dual license adding BSD-2-Clause.
Sure.
>
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mellanox I2C SMBus on BlueField SoCs
> > +
> > +maintainers:
> > + - Khalil Blaiech <kblaiech@nvidia.com>
>
> allOf:
> - $ref: i2c-controller.yaml#
>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mellanox,i2c-mlxbf1
> > + - mellanox,i2c-mlxbf2
> > +
> > + reg:
> > + minItems: 3
> > + maxItems: 4
> > + items:
> > + - description: Smbus block registers
> > + - description: Cause master registers
> > + - description: Cause slave registers
> > + - description: Cause coalesce registers
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clock-frequency:
> > + enum: [ 100000, 400000, 1000000 ]
> > +
>
> Drop the blank line.
>
> > + description:
> > + bus frequency used to configure timing registers;
> > + The frequency is expressed in Hz. Default is 100000.
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > +
> > +unevaluatedProperties: false
> > +
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - mellanox,i2c-mlxbf1
> > +
> > +then:
> > + properties:
> > + reg:
> > + maxItems: 3
> > +
> > +examples:
> > + - |
> > + i2c@2804000 {
> > + compatible = "mellanox,i2c-mlxbf1";
> > + reg = <0x02804000 0x800>,
> > + <0x02801200 0x020>,
> > + <0x02801260 0x020>;
> > + interrupts = <57>;
> > + clock-frequency = <100000>;
> > + };
> > +
> > + - |
> > + i2c@2808800 {
> > + compatible = "mellanox,i2c-mlxbf2";
> > + reg = <0x02808800 0x600>,
> > + <0x02808e00 0x020>,
> > + <0x02808e20 0x020>,
> > + <0x02808e40 0x010>;
> > + interrupts = <57>;
> > + clock-frequency = <400000>;
> > + };
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 9128200af1d0..8dba7ace4a40 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -11075,6 +11075,7 @@ MELLANOX BLUEFIELD I2C DRIVER
> > M: Khalil Blaiech <kblaiech@nvidia.com>
> > L: linux-i2c@vger.kernel.org
> > S: Supported
> > +F: Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
> > F: drivers/i2c/busses/i2c-mlxbf.c
> >
> > MELLANOX ETHERNET DRIVER (mlx4_en)
> > --
> > 2.24.1
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-11-03 14:10 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-28 22:54 [PATCH i2c-next v1 0/6] i2c: Incremental fixes for Mellanox BlueField I2C Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 1/6] i2c: mlxbf: Add CONFIG_ACPI to guard ACPI function call Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 2/6] i2c: mlxbf: Fix resrticted cast warning of sparse Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 3/6] i2c: mlxbf: Remove unecessary wrapper functions Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 4/6] i2c: mlxbf: Update reference clock frequency Khalil Blaiech
2020-10-28 22:54 ` [PATCH i2c-next v1 5/6] i2c: mlxbf: Update author and maintainer email info Khalil Blaiech
2020-10-28 22:55 ` [PATCH i2c-next v1 6/6] dt-bindings: i2c: Convert DT file to YAML schema Khalil Blaiech
2020-10-29 15:33 ` Rob Herring
2020-11-03 14:08 ` Khalil Blaiech
2020-10-29 15:33 ` Rob Herring
2020-11-03 14:06 ` Khalil Blaiech
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.