Re: [PATCH 2/4] drm/bridge: tc358767: Move hardware init to enable callback

[Marek Vasut <marex@denx.de>]

On 12/6/21 19:01, Dave Stevenson wrote:
> Hi Marek

Hi,

>> The TC358767/TC358867/TC9595 are all capable of operating either from
>> attached Xtal or from DSI clock lane clock. In case the later is used,
>> all I2C accesses will fail until the DSI clock lane is running and
>> supplying clock to the chip.
>>
>> Move all hardware initialization to enable callback to guarantee the
>> DSI clock lane is running before accessing the hardware. In case Xtal
>> is attached to the chip, this change has no effect.
> 
> This puzzles me as there seem to be a couple of ambiguities over how
> it would be used.
> 
> Firstly the DT binding lists the clock as a required property, but
> there isn't one present if deriving the clock from the DSI clock lane.

That's correct, the clock for the internal PLLs are derived from the DSI 
clock lane.

> Secondly the datasheet states that the DSI Reference Clock Source
> Division Selection is done by the MODE1 pin, and switches between
> HSCKBY2 divided by 7 and HSCKBY2 divided by 9. There is a stated
> assumption that HSCK is either 364MHz or 468MHz, thereby ending up
> with 26MHz. To do this we have to be running DSI in burst mode, but
> the support for that in DRM is near zero.

Yes, you have to run the DSI clock lane at either of the two clock 
frequencies, that is rather limiting. The DSI has to be running in 
continuous clock mode, this has nothing to do with burst mode, the burst 
mode is a DSI host setting which is supported by most DSI hosts.

> Can I ask how the chip has actually been configured and run in this mode?

REFCLK Xtal disconnected and HSCKBY2/7 MODE0=H MODE1=L , that should be 
all you need. Do you plan to develop a board with this bridge ?