* [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU
@ 2017-06-11 23:16 Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 1/7] softfloat: define 680x0 specific values Laurent Vivier
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
This series modifies the original ColdFire FPU implementation
to use floatx80 instead of float64 internally as this
is the native datatype for 680x0. I didn't keep the float64
type for ColdFire, but if someone thinks it's required I
can update this series in this way.
The series also adds the FPU status and control registers.
The floatx80 datatype used here is not exactly the same as the
one used by 680x0 for its extended precision data type, because
normally the signaling bit of 680x0 NAN is the MSB of the mantissa
minus one and in floatx80 it is the MSB.
We also add the gdb server parts to read the new FPU registers.
A strange thing happens here: while the gdb client running remotely
from a debian etch-m68k has no issue working with 96bit FPU registers
(the 680x0 extended precision data type), new gdbs (from a debian unstable
and gdb for cross-compiled environment) don't expect this FPU registers
size. But it seems like a bug in gdb, not in this implementation.
v4:
this is only a subset of v3
add a patch to move fmove CR to a function
use "FPReg *" instead of FP0/FP1 temporaries
fcmp/ftst take old FPSR register from parameters
and return the new one
add R-b from Richard
v3:
fix fsave opcode
Add comment to define "unnormalized" number
Correctly define pickNaN()
v2:
complete rework of the series
force single precision in ColdFire mode
add "forced" precision instructions (fsmove, fdmove, fsadd, ...)
fixed Fcc.
Laurent Vivier (7):
softfloat: define 680x0 specific values
target-m68k: move FPU helpers to fpu_helper.c
target-m68k: define ext_opsize
target-m68k: move fmove CR to a function
target-m68k: use floatx80 internally
target-m68k: define 96bit FP registers for gdb on 680x0
target-m68k: add FPCR and FPSR
configure | 2 +-
fpu/softfloat-specialize.h | 34 +-
gdb-xml/m68k-fp.xml | 21 ++
target/m68k/Makefile.objs | 2 +-
target/m68k/cpu.c | 9 +-
target/m68k/cpu.h | 42 ++-
target/m68k/fpu_helper.c | 207 ++++++++++
target/m68k/helper.c | 165 ++++----
target/m68k/helper.h | 38 +-
target/m68k/qregs.def | 2 +-
target/m68k/translate.c | 918 +++++++++++++++++++++++++++++++--------------
11 files changed, 1031 insertions(+), 409 deletions(-)
create mode 100644 gdb-xml/m68k-fp.xml
create mode 100644 target/m68k/fpu_helper.c
--
2.9.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v4 1/7] softfloat: define 680x0 specific values
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
@ 2017-06-11 23:16 ` Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 2/7] target-m68k: move FPU helpers to fpu_helper.c Laurent Vivier
` (5 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
fpu/softfloat-specialize.h | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 100c8a9..de2c5d5 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -111,7 +111,7 @@ float16 float16_default_nan(float_status *status)
*----------------------------------------------------------------------------*/
float32 float32_default_nan(float_status *status)
{
-#if defined(TARGET_SPARC)
+#if defined(TARGET_SPARC) || defined(TARGET_M68K)
return const_float32(0x7FFFFFFF);
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE)
@@ -136,7 +136,7 @@ float32 float32_default_nan(float_status *status)
*----------------------------------------------------------------------------*/
float64 float64_default_nan(float_status *status)
{
-#if defined(TARGET_SPARC)
+#if defined(TARGET_SPARC) || defined(TARGET_M68K)
return const_float64(LIT64(0x7FFFFFFFFFFFFFFF));
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_S390X)
@@ -162,7 +162,10 @@ float64 float64_default_nan(float_status *status)
floatx80 floatx80_default_nan(float_status *status)
{
floatx80 r;
-
+#if defined(TARGET_M68K)
+ r.low = LIT64(0xFFFFFFFFFFFFFFFF);
+ r.high = 0x7FFF;
+#else
if (status->snan_bit_is_one) {
r.low = LIT64(0xBFFFFFFFFFFFFFFF);
r.high = 0x7FFF;
@@ -170,6 +173,7 @@ floatx80 floatx80_default_nan(float_status *status)
r.low = LIT64(0xC000000000000000);
r.high = 0xFFFF;
}
+#endif
return r;
}
@@ -502,6 +506,30 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
return 1;
}
}
+#elif defined(TARGET_M68K)
+static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
+ flag aIsLargerSignificand)
+{
+ /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
+ * 3.4 FLOATING-POINT INSTRUCTION DETAILS
+ * If either operand, but not both operands, of an operation is a
+ * nonsignaling NaN, then that NaN is returned as the result. If both
+ * operands are nonsignaling NaNs, then the destination operand
+ * nonsignaling NaN is returned as the result.
+ * If either operand to an operation is a signaling NaN (SNaN), then the
+ * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
+ * is set in the FPCR ENABLE byte, then the exception is taken and the
+ * destination is not modified. If the SNaN exception enable bit is not
+ * set, setting the SNaN bit in the operand to a one converts the SNaN to
+ * a nonsignaling NaN. The operation then continues as described in the
+ * preceding paragraph for nonsignaling NaNs.
+ */
+ if (aIsQNaN || aIsSNaN) { /* a is the destination operand */
+ return 0; /* return the destination operand */
+ } else {
+ return 1; /* return b */
+ }
+}
#else
static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag aIsLargerSignificand)
--
2.9.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v4 2/7] target-m68k: move FPU helpers to fpu_helper.c
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 1/7] softfloat: define 680x0 specific values Laurent Vivier
@ 2017-06-11 23:16 ` Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 3/7] target-m68k: define ext_opsize Laurent Vivier
` (4 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target/m68k/Makefile.objs | 2 +-
target/m68k/fpu_helper.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++
target/m68k/helper.c | 88 ------------------------------------
3 files changed, 113 insertions(+), 89 deletions(-)
create mode 100644 target/m68k/fpu_helper.c
diff --git a/target/m68k/Makefile.objs b/target/m68k/Makefile.objs
index 02cf616..39141ab 100644
--- a/target/m68k/Makefile.objs
+++ b/target/m68k/Makefile.objs
@@ -1,3 +1,3 @@
obj-y += m68k-semi.o
-obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o
obj-y += gdbstub.o
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
new file mode 100644
index 0000000..5bf2576
--- /dev/null
+++ b/target/m68k/fpu_helper.c
@@ -0,0 +1,112 @@
+/*
+ * m68k FPU helpers
+ *
+ * Copyright (c) 2006-2007 CodeSourcery
+ * Written by Paul Brook
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+
+uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val)
+{
+ return float64_to_int32(val, &env->fp_status);
+}
+
+float32 HELPER(f64_to_f32)(CPUM68KState *env, float64 val)
+{
+ return float64_to_float32(val, &env->fp_status);
+}
+
+float64 HELPER(i32_to_f64)(CPUM68KState *env, uint32_t val)
+{
+ return int32_to_float64(val, &env->fp_status);
+}
+
+float64 HELPER(f32_to_f64)(CPUM68KState *env, float32 val)
+{
+ return float32_to_float64(val, &env->fp_status);
+}
+
+float64 HELPER(iround_f64)(CPUM68KState *env, float64 val)
+{
+ return float64_round_to_int(val, &env->fp_status);
+}
+
+float64 HELPER(itrunc_f64)(CPUM68KState *env, float64 val)
+{
+ return float64_trunc_to_int(val, &env->fp_status);
+}
+
+float64 HELPER(sqrt_f64)(CPUM68KState *env, float64 val)
+{
+ return float64_sqrt(val, &env->fp_status);
+}
+
+float64 HELPER(abs_f64)(float64 val)
+{
+ return float64_abs(val);
+}
+
+float64 HELPER(chs_f64)(float64 val)
+{
+ return float64_chs(val);
+}
+
+float64 HELPER(add_f64)(CPUM68KState *env, float64 a, float64 b)
+{
+ return float64_add(a, b, &env->fp_status);
+}
+
+float64 HELPER(sub_f64)(CPUM68KState *env, float64 a, float64 b)
+{
+ return float64_sub(a, b, &env->fp_status);
+}
+
+float64 HELPER(mul_f64)(CPUM68KState *env, float64 a, float64 b)
+{
+ return float64_mul(a, b, &env->fp_status);
+}
+
+float64 HELPER(div_f64)(CPUM68KState *env, float64 a, float64 b)
+{
+ return float64_div(a, b, &env->fp_status);
+}
+
+float64 HELPER(sub_cmp_f64)(CPUM68KState *env, float64 a, float64 b)
+{
+ /* ??? This may incorrectly raise exceptions. */
+ /* ??? Should flush denormals to zero. */
+ float64 res;
+ res = float64_sub(a, b, &env->fp_status);
+ if (float64_is_quiet_nan(res, &env->fp_status)) {
+ /* +/-inf compares equal against itself, but sub returns nan. */
+ if (!float64_is_quiet_nan(a, &env->fp_status)
+ && !float64_is_quiet_nan(b, &env->fp_status)) {
+ res = float64_zero;
+ if (float64_lt_quiet(a, res, &env->fp_status)) {
+ res = float64_chs(res);
+ }
+ }
+ }
+ return res;
+}
+
+uint32_t HELPER(compare_f64)(CPUM68KState *env, float64 val)
+{
+ return float64_compare_quiet(val, float64_zero, &env->fp_status);
+}
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index f750d3d..5ca9911 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -284,94 +284,6 @@ void HELPER(set_sr)(CPUM68KState *env, uint32_t val)
m68k_switch_sp(env);
}
-/* FPU helpers. */
-uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val)
-{
- return float64_to_int32(val, &env->fp_status);
-}
-
-float32 HELPER(f64_to_f32)(CPUM68KState *env, float64 val)
-{
- return float64_to_float32(val, &env->fp_status);
-}
-
-float64 HELPER(i32_to_f64)(CPUM68KState *env, uint32_t val)
-{
- return int32_to_float64(val, &env->fp_status);
-}
-
-float64 HELPER(f32_to_f64)(CPUM68KState *env, float32 val)
-{
- return float32_to_float64(val, &env->fp_status);
-}
-
-float64 HELPER(iround_f64)(CPUM68KState *env, float64 val)
-{
- return float64_round_to_int(val, &env->fp_status);
-}
-
-float64 HELPER(itrunc_f64)(CPUM68KState *env, float64 val)
-{
- return float64_trunc_to_int(val, &env->fp_status);
-}
-
-float64 HELPER(sqrt_f64)(CPUM68KState *env, float64 val)
-{
- return float64_sqrt(val, &env->fp_status);
-}
-
-float64 HELPER(abs_f64)(float64 val)
-{
- return float64_abs(val);
-}
-
-float64 HELPER(chs_f64)(float64 val)
-{
- return float64_chs(val);
-}
-
-float64 HELPER(add_f64)(CPUM68KState *env, float64 a, float64 b)
-{
- return float64_add(a, b, &env->fp_status);
-}
-
-float64 HELPER(sub_f64)(CPUM68KState *env, float64 a, float64 b)
-{
- return float64_sub(a, b, &env->fp_status);
-}
-
-float64 HELPER(mul_f64)(CPUM68KState *env, float64 a, float64 b)
-{
- return float64_mul(a, b, &env->fp_status);
-}
-
-float64 HELPER(div_f64)(CPUM68KState *env, float64 a, float64 b)
-{
- return float64_div(a, b, &env->fp_status);
-}
-
-float64 HELPER(sub_cmp_f64)(CPUM68KState *env, float64 a, float64 b)
-{
- /* ??? This may incorrectly raise exceptions. */
- /* ??? Should flush denormals to zero. */
- float64 res;
- res = float64_sub(a, b, &env->fp_status);
- if (float64_is_quiet_nan(res, &env->fp_status)) {
- /* +/-inf compares equal against itself, but sub returns nan. */
- if (!float64_is_quiet_nan(a, &env->fp_status)
- && !float64_is_quiet_nan(b, &env->fp_status)) {
- res = float64_zero;
- if (float64_lt_quiet(a, res, &env->fp_status))
- res = float64_chs(res);
- }
- }
- return res;
-}
-
-uint32_t HELPER(compare_f64)(CPUM68KState *env, float64 val)
-{
- return float64_compare_quiet(val, float64_zero, &env->fp_status);
-}
/* MAC unit. */
/* FIXME: The MAC unit implementation is a bit of a mess. Some helpers
--
2.9.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v4 3/7] target-m68k: define ext_opsize
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 1/7] softfloat: define 680x0 specific values Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 2/7] target-m68k: move FPU helpers to fpu_helper.c Laurent Vivier
@ 2017-06-11 23:16 ` Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function Laurent Vivier
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target/m68k/translate.c | 43 ++++++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ad4d4ef..049d837 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -669,6 +669,21 @@ static inline int insn_opsize(int insn)
}
}
+static inline int ext_opsize(int ext, int pos)
+{
+ switch ((ext >> pos) & 7) {
+ case 0: return OS_LONG;
+ case 1: return OS_SINGLE;
+ case 2: return OS_EXTENDED;
+ case 3: return OS_PACKED;
+ case 4: return OS_WORD;
+ case 5: return OS_DOUBLE;
+ case 6: return OS_BYTE;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/* Assign value to a register. If the width is less than the register width
only the low part of the register is set. */
static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
@@ -4111,20 +4126,19 @@ DISAS_INSN(fpu)
tmp32 = tcg_temp_new_i32();
/* fmove */
/* ??? TODO: Proper behavior on overflow. */
- switch ((ext >> 10) & 7) {
- case 0:
- opsize = OS_LONG;
+
+ opsize = ext_opsize(ext, 10);
+ switch (opsize) {
+ case OS_LONG:
gen_helper_f64_to_i32(tmp32, cpu_env, src);
break;
- case 1:
- opsize = OS_SINGLE;
+ case OS_SINGLE:
gen_helper_f64_to_f32(tmp32, cpu_env, src);
break;
- case 4:
- opsize = OS_WORD;
+ case OS_WORD:
gen_helper_f64_to_i32(tmp32, cpu_env, src);
break;
- case 5: /* OS_DOUBLE */
+ case OS_DOUBLE:
tcg_gen_mov_i32(tmp32, AREG(insn, 0));
switch ((insn >> 3) & 7) {
case 2:
@@ -4153,8 +4167,7 @@ DISAS_INSN(fpu)
}
tcg_temp_free_i32(tmp32);
return;
- case 6:
- opsize = OS_BYTE;
+ case OS_BYTE:
gen_helper_f64_to_i32(tmp32, cpu_env, src);
break;
default:
@@ -4227,15 +4240,7 @@ DISAS_INSN(fpu)
}
if (ext & (1 << 14)) {
/* Source effective address. */
- switch ((ext >> 10) & 7) {
- case 0: opsize = OS_LONG; break;
- case 1: opsize = OS_SINGLE; break;
- case 4: opsize = OS_WORD; break;
- case 5: opsize = OS_DOUBLE; break;
- case 6: opsize = OS_BYTE; break;
- default:
- goto undef;
- }
+ opsize = ext_opsize(ext, 10);
if (opsize == OS_DOUBLE) {
tmp32 = tcg_temp_new_i32();
tcg_gen_mov_i32(tmp32, AREG(insn, 0));
--
2.9.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
` (2 preceding siblings ...)
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 3/7] target-m68k: define ext_opsize Laurent Vivier
@ 2017-06-11 23:16 ` Laurent Vivier
2017-06-12 16:13 ` Richard Henderson
2017-06-12 19:12 ` Philippe Mathieu-Daudé
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally Laurent Vivier
` (2 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
Move code of fmove to/from control register to a function
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 66 ++++++++++++++++++++++++++++++-------------------
1 file changed, 41 insertions(+), 25 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 049d837..45733ce 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4099,6 +4099,45 @@ DISAS_INSN(trap)
gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
}
+static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
+ uint32_t insn, uint32_t ext)
+{
+ int mask = (ext >> 10) & 7;
+ int is_write = (ext >> 13) & 1;
+ TCGv val;
+
+ if (is_write) {
+ switch (mask) {
+ case 1: /* FPIAR */
+ case 2: /* FPSR */
+ default:
+ cpu_abort(NULL, "Unimplemented: fmove from control %d", mask);
+ goto undef;
+ case 4: /* FPCR */
+ val = tcg_const_i32(0);
+ DEST_EA(env, insn, OS_LONG, val, NULL);
+ tcg_temp_free(val);
+ break;
+ }
+ return;
+ }
+ switch (mask) {
+ case 1: /* FPIAR */
+ case 2: /* FPSR */
+ default:
+ cpu_abort(NULL, "Unimplemented: fmove to control %d",
+ mask);
+ break;
+ case 4: /* FPCR */
+ /* Not implemented. Ignore writes. */
+ break;
+ }
+ return;
+undef:
+ s->pc -= 2;
+ disas_undef_fpu(env, s, insn);
+}
+
/* ??? FP exceptions are not implemented. Most exceptions are deferred until
immediately before the next FP instruction is executed. */
DISAS_INSN(fpu)
@@ -4177,32 +4216,9 @@ DISAS_INSN(fpu)
tcg_temp_free_i32(tmp32);
return;
case 4: /* fmove to control register. */
- switch ((ext >> 10) & 7) {
- case 4: /* FPCR */
- /* Not implemented. Ignore writes. */
- break;
- case 1: /* FPIAR */
- case 2: /* FPSR */
- default:
- cpu_abort(NULL, "Unimplemented: fmove to control %d",
- (ext >> 10) & 7);
- }
- break;
case 5: /* fmove from control register. */
- switch ((ext >> 10) & 7) {
- case 4: /* FPCR */
- /* Not implemented. Always return zero. */
- tmp32 = tcg_const_i32(0);
- break;
- case 1: /* FPIAR */
- case 2: /* FPSR */
- default:
- cpu_abort(NULL, "Unimplemented: fmove from control %d",
- (ext >> 10) & 7);
- goto undef;
- }
- DEST_EA(env, insn, OS_LONG, tmp32, NULL);
- break;
+ gen_op_fmove_fcr(env, s, insn, ext);
+ return;
case 6: /* fmovem */
case 7:
{
--
2.9.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
` (3 preceding siblings ...)
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function Laurent Vivier
@ 2017-06-11 23:16 ` Laurent Vivier
2017-06-13 4:48 ` Thomas Huth
2017-06-19 20:53 ` Richard Henderson
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 6/7] target-m68k: define 96bit FP registers for gdb on 680x0 Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 7/7] target-m68k: add FPCR and FPSR Laurent Vivier
6 siblings, 2 replies; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
Coldfire uses float64, but 680x0 use floatx80.
This patch introduces the use of floatx80 internally
and enables 680x0 80bits FPU.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/cpu.c | 9 +-
target/m68k/cpu.h | 6 +-
target/m68k/fpu_helper.c | 85 +++----
target/m68k/helper.c | 12 +-
target/m68k/helper.h | 37 +--
target/m68k/qregs.def | 1 -
target/m68k/translate.c | 568 +++++++++++++++++++++++++++++++----------------
7 files changed, 464 insertions(+), 254 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index f068922..435456f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -49,6 +49,8 @@ static void m68k_cpu_reset(CPUState *s)
M68kCPU *cpu = M68K_CPU(s);
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);
CPUM68KState *env = &cpu->env;
+ floatx80 nan = floatx80_default_nan(NULL);
+ int i;
mcc->parent_reset(s);
@@ -57,7 +59,12 @@ static void m68k_cpu_reset(CPUState *s)
env->sr = 0x2700;
#endif
m68k_switch_sp(env);
- /* ??? FP regs should be initialized to NaN. */
+ for (i = 0; i < 8; i++) {
+ env->fregs[i].d = nan;
+ }
+ env->fpcr = 0;
+ env->fpsr = 0;
+
cpu_m68k_set_ccr(env, 0);
/* TODO: We should set PC from the interrupt vector. */
env->pc = 0;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 384ec5d..dcdf3d2 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -64,6 +64,8 @@
#define NB_MMU_MODES 2
#define TARGET_INSN_START_EXTRA_WORDS 1
+typedef CPU_LDoubleU FPReg;
+
typedef struct CPUM68KState {
uint32_t dregs[8];
uint32_t aregs[8];
@@ -82,8 +84,8 @@ typedef struct CPUM68KState {
uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
uint32_t cc_z; /* == 0 or unused */
- float64 fregs[8];
- float64 fp_result;
+ FPReg fregs[8];
+ FPReg fp_result;
uint32_t fpcr;
uint32_t fpsr;
float_status fp_status;
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index 5bf2576..f4d3821 100644
--- a/target/m68k/fpu_helper.c
+++ b/target/m68k/fpu_helper.c
@@ -21,92 +21,101 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
-uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val)
+int32_t HELPER(reds32)(CPUM68KState *env, FPReg *val)
{
- return float64_to_int32(val, &env->fp_status);
+ return floatx80_to_int32(val->d, &env->fp_status);
}
-float32 HELPER(f64_to_f32)(CPUM68KState *env, float64 val)
+float32 HELPER(redf32)(CPUM68KState *env, FPReg *val)
{
- return float64_to_float32(val, &env->fp_status);
+ return floatx80_to_float32(val->d, &env->fp_status);
}
-float64 HELPER(i32_to_f64)(CPUM68KState *env, uint32_t val)
+void HELPER(exts32)(CPUM68KState *env, FPReg *res, int32_t val)
{
- return int32_to_float64(val, &env->fp_status);
+ res->d = int32_to_floatx80(val, &env->fp_status);
}
-float64 HELPER(f32_to_f64)(CPUM68KState *env, float32 val)
+void HELPER(extf32)(CPUM68KState *env, FPReg *res, float32 val)
{
- return float32_to_float64(val, &env->fp_status);
+ res->d = float32_to_floatx80(val, &env->fp_status);
}
-float64 HELPER(iround_f64)(CPUM68KState *env, float64 val)
+void HELPER(extf64)(CPUM68KState *env, FPReg *res, float64 val)
{
- return float64_round_to_int(val, &env->fp_status);
+ res->d = float64_to_floatx80(val, &env->fp_status);
}
-float64 HELPER(itrunc_f64)(CPUM68KState *env, float64 val)
+float64 HELPER(redf64)(CPUM68KState *env, FPReg *val)
{
- return float64_trunc_to_int(val, &env->fp_status);
+ return floatx80_to_float64(val->d, &env->fp_status);
}
-float64 HELPER(sqrt_f64)(CPUM68KState *env, float64 val)
+void HELPER(firound)(CPUM68KState *env, FPReg *res, FPReg *val)
{
- return float64_sqrt(val, &env->fp_status);
+ res->d = floatx80_round_to_int(val->d, &env->fp_status);
}
-float64 HELPER(abs_f64)(float64 val)
+void HELPER(fitrunc)(CPUM68KState *env, FPReg *res, FPReg *val)
{
- return float64_abs(val);
+ res->d = floatx80_round_to_int(val->d, &env->fp_status);
}
-float64 HELPER(chs_f64)(float64 val)
+void HELPER(fsqrt)(CPUM68KState *env, FPReg *res, FPReg *val)
{
- return float64_chs(val);
+ res->d = floatx80_sqrt(val->d, &env->fp_status);
}
-float64 HELPER(add_f64)(CPUM68KState *env, float64 a, float64 b)
+void HELPER(fabs)(CPUM68KState *env, FPReg *res, FPReg *val)
{
- return float64_add(a, b, &env->fp_status);
+ res->d = floatx80_abs(val->d);
}
-float64 HELPER(sub_f64)(CPUM68KState *env, float64 a, float64 b)
+void HELPER(fchs)(CPUM68KState *env, FPReg *res, FPReg *val)
{
- return float64_sub(a, b, &env->fp_status);
+ res->d = floatx80_chs(val->d);
}
-float64 HELPER(mul_f64)(CPUM68KState *env, float64 a, float64 b)
+void HELPER(fadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
{
- return float64_mul(a, b, &env->fp_status);
+ res->d = floatx80_add(val0->d, val1->d, &env->fp_status);
}
-float64 HELPER(div_f64)(CPUM68KState *env, float64 a, float64 b)
+void HELPER(fsub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
{
- return float64_div(a, b, &env->fp_status);
+ res->d = floatx80_sub(val1->d, val0->d, &env->fp_status);
}
-float64 HELPER(sub_cmp_f64)(CPUM68KState *env, float64 a, float64 b)
+void HELPER(fmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
+{
+ res->d = floatx80_mul(val0->d, val1->d, &env->fp_status);
+}
+
+void HELPER(fdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
+{
+ res->d = floatx80_div(val1->d, val0->d, &env->fp_status);
+}
+
+void HELPER(fsub_cmp)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
{
/* ??? This may incorrectly raise exceptions. */
/* ??? Should flush denormals to zero. */
- float64 res;
- res = float64_sub(a, b, &env->fp_status);
- if (float64_is_quiet_nan(res, &env->fp_status)) {
+ res->d = floatx80_sub(val0->d, val1->d, &env->fp_status);
+ if (floatx80_is_quiet_nan(res->d, &env->fp_status)) {
/* +/-inf compares equal against itself, but sub returns nan. */
- if (!float64_is_quiet_nan(a, &env->fp_status)
- && !float64_is_quiet_nan(b, &env->fp_status)) {
- res = float64_zero;
- if (float64_lt_quiet(a, res, &env->fp_status)) {
- res = float64_chs(res);
+ if (!floatx80_is_quiet_nan(val0->d, &env->fp_status)
+ && !floatx80_is_quiet_nan(val1->d, &env->fp_status)) {
+ res->d = floatx80_zero;
+ if (floatx80_lt_quiet(val0->d, res->d, &env->fp_status)) {
+ res->d = floatx80_chs(res->d);
}
}
}
- return res;
}
-uint32_t HELPER(compare_f64)(CPUM68KState *env, float64 val)
+uint32_t HELPER(fcompare)(CPUM68KState *env, FPReg *val)
{
- return float64_compare_quiet(val, float64_zero, &env->fp_status);
+ return floatx80_compare_quiet(val->d, floatx80_zero, &env->fp_status);
}
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 5ca9911..8bfc881 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -73,10 +73,11 @@ void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf)
g_slist_free(list);
}
-static int fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+static int cf_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
- stfq_p(mem_buf, env->fregs[n]);
+ float_status s;
+ stfq_p(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
return 8;
}
if (n < 11) {
@@ -87,10 +88,11 @@ static int fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
- env->fregs[n] = ldfq_p(mem_buf);
+ float_status s;
+ env->fregs[n].d = float64_to_floatx80(ldfq_p(mem_buf), &s);
return 8;
}
if (n < 11) {
@@ -126,7 +128,7 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
CPUM68KState *env = &cpu->env;
if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
- gdb_register_coprocessor(cs, fpu_gdb_get_reg, fpu_gdb_set_reg,
+ gdb_register_coprocessor(cs, cf_fpu_gdb_get_reg, cf_fpu_gdb_set_reg,
11, "cf-fp.xml", 18);
}
/* TODO: Add [E]MAC registers. */
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index d7a4bf1..d871be6 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -12,21 +12,28 @@ DEF_HELPER_3(movec, void, env, i32, i32)
DEF_HELPER_4(cas2w, void, env, i32, i32, i32)
DEF_HELPER_4(cas2l, void, env, i32, i32, i32)
-DEF_HELPER_2(f64_to_i32, f32, env, f64)
-DEF_HELPER_2(f64_to_f32, f32, env, f64)
-DEF_HELPER_2(i32_to_f64, f64, env, i32)
-DEF_HELPER_2(f32_to_f64, f64, env, f32)
-DEF_HELPER_2(iround_f64, f64, env, f64)
-DEF_HELPER_2(itrunc_f64, f64, env, f64)
-DEF_HELPER_2(sqrt_f64, f64, env, f64)
-DEF_HELPER_1(abs_f64, f64, f64)
-DEF_HELPER_1(chs_f64, f64, f64)
-DEF_HELPER_3(add_f64, f64, env, f64, f64)
-DEF_HELPER_3(sub_f64, f64, env, f64, f64)
-DEF_HELPER_3(mul_f64, f64, env, f64, f64)
-DEF_HELPER_3(div_f64, f64, env, f64, f64)
-DEF_HELPER_3(sub_cmp_f64, f64, env, f64, f64)
-DEF_HELPER_2(compare_f64, i32, env, f64)
+#define dh_alias_fp ptr
+#define dh_ctype_fp FPReg *
+#define dh_is_signed_fp dh_is_signed_ptr
+
+DEF_HELPER_3(exts32, void, env, fp, s32)
+DEF_HELPER_3(extf32, void, env, fp, f32)
+DEF_HELPER_3(extf64, void, env, fp, f64)
+DEF_HELPER_2(redf32, f32, env, fp)
+DEF_HELPER_2(redf64, f64, env, fp)
+DEF_HELPER_2(reds32, s32, env, fp)
+
+DEF_HELPER_3(firound, void, env, fp, fp)
+DEF_HELPER_3(fitrunc, void, env, fp, fp)
+DEF_HELPER_3(fsqrt, void, env, fp, fp)
+DEF_HELPER_3(fabs, void, env, fp, fp)
+DEF_HELPER_3(fchs, void, env, fp, fp)
+DEF_HELPER_4(fadd, void, env, fp, fp, fp)
+DEF_HELPER_4(fsub, void, env, fp, fp, fp)
+DEF_HELPER_4(fmul, void, env, fp, fp, fp)
+DEF_HELPER_4(fdiv, void, env, fp, fp, fp)
+DEF_HELPER_4(fsub_cmp, void, env, fp, fp, fp)
+DEF_HELPER_2(fcompare, i32, env, fp)
DEF_HELPER_3(mac_move, void, env, i32, i32)
DEF_HELPER_3(macmulf, i64, env, i32, i32)
diff --git a/target/m68k/qregs.def b/target/m68k/qregs.def
index 51ff43b..1aadc62 100644
--- a/target/m68k/qregs.def
+++ b/target/m68k/qregs.def
@@ -1,4 +1,3 @@
-DEFF64(FP_RESULT, fp_result)
DEFO32(PC, pc)
DEFO32(SR, sr)
DEFO32(CC_OP, cc_op)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 45733ce..5847c6f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -32,37 +32,27 @@
#include "trace-tcg.h"
#include "exec/log.h"
-
//#define DEBUG_DISPATCH 1
-/* Fake floating point. */
-#define tcg_gen_mov_f64 tcg_gen_mov_i64
-#define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
-#define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
-
#define DEFO32(name, offset) static TCGv QREG_##name;
#define DEFO64(name, offset) static TCGv_i64 QREG_##name;
-#define DEFF64(name, offset) static TCGv_i64 QREG_##name;
#include "qregs.def"
#undef DEFO32
#undef DEFO64
-#undef DEFF64
static TCGv_i32 cpu_halted;
static TCGv_i32 cpu_exception_index;
static TCGv_env cpu_env;
-static char cpu_reg_names[3*8*3 + 5*4];
+static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
static TCGv cpu_dregs[8];
static TCGv cpu_aregs[8];
-static TCGv_i64 cpu_fregs[8];
static TCGv_i64 cpu_macc[4];
#define REG(insn, pos) (((insn) >> (pos)) & 7)
#define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
#define AREG(insn, pos) get_areg(s, REG(insn, pos))
-#define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
#define MACREG(acc) cpu_macc[acc]
#define QREG_SP get_areg(s, 7)
@@ -87,11 +77,9 @@ void m68k_tcg_init(void)
#define DEFO64(name, offset) \
QREG_##name = tcg_global_mem_new_i64(cpu_env, \
offsetof(CPUM68KState, offset), #name);
-#define DEFF64(name, offset) DEFO64(name, offset)
#include "qregs.def"
#undef DEFO32
#undef DEFO64
-#undef DEFF64
cpu_halted = tcg_global_mem_new_i32(cpu_env,
-offsetof(M68kCPU, env) +
@@ -111,10 +99,6 @@ void m68k_tcg_init(void)
cpu_aregs[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUM68KState, aregs[i]), p);
p += 3;
- sprintf(p, "F%d", i);
- cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env,
- offsetof(CPUM68KState, fregs[i]), p);
- p += 3;
}
for (i = 0; i < 4; i++) {
sprintf(p, "ACC%d", i);
@@ -286,7 +270,6 @@ static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
tcg_gen_qemu_ld16u(tmp, addr, index);
break;
case OS_LONG:
- case OS_SINGLE:
tcg_gen_qemu_ld32u(tmp, addr, index);
break;
default:
@@ -296,16 +279,6 @@ static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
return tmp;
}
-static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
-{
- TCGv_i64 tmp;
- int index = IS_USER(s);
- tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ldf64(tmp, addr, index);
- gen_throws_exception = gen_last_qop;
- return tmp;
-}
-
/* Generate a store. */
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
{
@@ -318,7 +291,6 @@ static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
tcg_gen_qemu_st16(val, addr, index);
break;
case OS_LONG:
- case OS_SINGLE:
tcg_gen_qemu_st32(val, addr, index);
break;
default:
@@ -327,13 +299,6 @@ static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
gen_throws_exception = gen_last_qop;
}
-static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
-{
- int index = IS_USER(s);
- tcg_gen_qemu_stf64(val, addr, index);
- gen_throws_exception = gen_last_qop;
-}
-
typedef enum {
EA_STORE,
EA_LOADU,
@@ -377,6 +342,15 @@ static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
return im;
}
+/* Read a 64-bit immediate constant. */
+static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
+{
+ uint64_t im;
+ im = (uint64_t)read_im32(env, s) << 32;
+ im |= (uint64_t)read_im32(env, s);
+ return im;
+}
+
/* Calculate and address index. */
static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
{
@@ -909,6 +883,296 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what);
}
+static TCGv_ptr gen_fp_ptr(int freg)
+{
+ TCGv_ptr fp = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
+ return fp;
+}
+
+static TCGv_ptr gen_fp_result_ptr(void)
+{
+ TCGv_ptr fp = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
+ return fp;
+}
+
+static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
+{
+ TCGv t32;
+ TCGv_i64 t64;
+
+ t32 = tcg_temp_new();
+ tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
+ tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
+ tcg_temp_free(t32);
+
+ t64 = tcg_temp_new_i64();
+ tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
+ tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
+ tcg_temp_free_i64(t64);
+}
+
+static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
+{
+ TCGv tmp;
+ TCGv_i64 t64;
+ int index = IS_USER(s);
+
+ t64 = tcg_temp_new_i64();
+ tmp = tcg_temp_new();
+ switch (opsize) {
+ case OS_BYTE:
+ tcg_gen_qemu_ld8s(tmp, addr, index);
+ gen_helper_exts32(cpu_env, fp, tmp);
+ break;
+ case OS_WORD:
+ tcg_gen_qemu_ld16s(tmp, addr, index);
+ gen_helper_exts32(cpu_env, fp, tmp);
+ break;
+ case OS_LONG:
+ tcg_gen_qemu_ld32u(tmp, addr, index);
+ gen_helper_exts32(cpu_env, fp, tmp);
+ break;
+ case OS_SINGLE:
+ tcg_gen_qemu_ld32u(tmp, addr, index);
+ gen_helper_extf32(cpu_env, fp, tmp);
+ break;
+ case OS_DOUBLE:
+ tcg_gen_qemu_ld64(t64, addr, index);
+ gen_helper_extf64(cpu_env, fp, t64);
+ tcg_temp_free_i64(t64);
+ break;
+ case OS_EXTENDED:
+ tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_shri_i32(tmp, tmp, 16);
+ tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
+ tcg_gen_addi_i32(tmp, addr, 4);
+ tcg_gen_qemu_ld64(t64, tmp, index);
+ tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
+ break;
+ case OS_PACKED:
+ tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
+ tcg_gen_addi_i32(tmp, addr, 4);
+ tcg_gen_qemu_ld64(t64, tmp, index);
+ tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free(tmp);
+ tcg_temp_free_i64(t64);
+ gen_throws_exception = gen_last_qop;
+}
+
+static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
+{
+ TCGv tmp;
+ TCGv_i64 t64;
+ int index = IS_USER(s);
+
+ t64 = tcg_temp_new_i64();
+ tmp = tcg_temp_new();
+ switch (opsize) {
+ case OS_BYTE:
+ gen_helper_reds32(tmp, cpu_env, fp);
+ tcg_gen_qemu_st8(tmp, addr, index);
+ break;
+ case OS_WORD:
+ gen_helper_reds32(tmp, cpu_env, fp);
+ tcg_gen_qemu_st16(tmp, addr, index);
+ break;
+ case OS_LONG:
+ gen_helper_reds32(tmp, cpu_env, fp);
+ tcg_gen_qemu_st32(tmp, addr, index);
+ break;
+ case OS_SINGLE:
+ gen_helper_redf32(tmp, cpu_env, fp);
+ tcg_gen_qemu_st32(tmp, addr, index);
+ break;
+ case OS_DOUBLE:
+ gen_helper_redf64(t64, cpu_env, fp);
+ tcg_gen_qemu_st64(t64, addr, index);
+ break;
+ case OS_EXTENDED:
+ tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
+ tcg_gen_shli_i32(tmp, tmp, 16);
+ tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_addi_i32(tmp, addr, 4);
+ tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
+ tcg_gen_qemu_st64(t64, tmp, index);
+ break;
+ case OS_PACKED:
+ tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
+ tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_addi_i32(tmp, addr, 4);
+ tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
+ tcg_gen_qemu_st64(t64, tmp, index);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free(tmp);
+ tcg_temp_free_i64(t64);
+ gen_throws_exception = gen_last_qop;
+}
+
+static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
+ TCGv_ptr fp, ea_what what)
+{
+ if (what == EA_STORE) {
+ gen_store_fp(s, opsize, addr, fp);
+ } else {
+ gen_load_fp(s, opsize, addr, fp);
+ }
+}
+
+static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
+ int reg0, int opsize, TCGv_ptr fp, ea_what what)
+{
+ TCGv reg, addr, tmp;
+ TCGv_i64 t64;
+
+ switch (mode) {
+ case 0: /* Data register direct. */
+ reg = cpu_dregs[reg0];
+ if (what == EA_STORE) {
+ switch (opsize) {
+ case OS_BYTE:
+ case OS_WORD:
+ case OS_LONG:
+ gen_helper_reds32(reg, cpu_env, fp);
+ break;
+ case OS_SINGLE:
+ gen_helper_redf32(reg, cpu_env, fp);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ tmp = tcg_temp_new();
+ switch (opsize) {
+ case OS_BYTE:
+ tcg_gen_ext8s_i32(tmp, reg);
+ gen_helper_exts32(cpu_env, fp, tmp);
+ break;
+ case OS_WORD:
+ tcg_gen_ext16s_i32(tmp, reg);
+ gen_helper_exts32(cpu_env, fp, tmp);
+ break;
+ case OS_LONG:
+ gen_helper_exts32(cpu_env, fp, reg);
+ break;
+ case OS_SINGLE:
+ gen_helper_extf32(cpu_env, fp, reg);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free(tmp);
+ }
+ return 0;
+ case 1: /* Address register direct. */
+ return -1;
+ case 2: /* Indirect register */
+ addr = get_areg(s, reg0);
+ gen_ldst_fp(s, opsize, addr, fp, what);
+ return 0;
+ case 3: /* Indirect postincrement. */
+ addr = cpu_aregs[reg0];
+ gen_ldst_fp(s, opsize, addr, fp, what);
+ tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
+ return 0;
+ case 4: /* Indirect predecrememnt. */
+ addr = gen_lea_mode(env, s, mode, reg0, opsize);
+ if (IS_NULL_QREG(addr)) {
+ return -1;
+ }
+ gen_ldst_fp(s, opsize, addr, fp, what);
+ tcg_gen_mov_i32(cpu_aregs[reg0], addr);
+ return 0;
+ case 5: /* Indirect displacement. */
+ case 6: /* Indirect index + displacement. */
+ do_indirect:
+ addr = gen_lea_mode(env, s, mode, reg0, opsize);
+ if (IS_NULL_QREG(addr)) {
+ return -1;
+ }
+ gen_ldst_fp(s, opsize, addr, fp, what);
+ return 0;
+ case 7: /* Other */
+ switch (reg0) {
+ case 0: /* Absolute short. */
+ case 1: /* Absolute long. */
+ case 2: /* pc displacement */
+ case 3: /* pc index+displacement. */
+ goto do_indirect;
+ case 4: /* Immediate. */
+ if (what == EA_STORE) {
+ return -1;
+ }
+ switch (opsize) {
+ case OS_BYTE:
+ tmp = tcg_const_i32((int8_t)read_im8(env, s));
+ gen_helper_exts32(cpu_env, fp, tmp);
+ tcg_temp_free(tmp);
+ break;
+ case OS_WORD:
+ tmp = tcg_const_i32((int16_t)read_im16(env, s));
+ gen_helper_exts32(cpu_env, fp, tmp);
+ tcg_temp_free(tmp);
+ break;
+ case OS_LONG:
+ tmp = tcg_const_i32(read_im32(env, s));
+ gen_helper_exts32(cpu_env, fp, tmp);
+ tcg_temp_free(tmp);
+ break;
+ case OS_SINGLE:
+ tmp = tcg_const_i32(read_im32(env, s));
+ gen_helper_extf32(cpu_env, fp, tmp);
+ tcg_temp_free(tmp);
+ break;
+ case OS_DOUBLE:
+ t64 = tcg_const_i64(read_im64(env, s));
+ gen_helper_extf64(cpu_env, fp, t64);
+ tcg_temp_free_i64(t64);
+ break;
+ case OS_EXTENDED:
+ tmp = tcg_const_i32(read_im32(env, s) >> 16);
+ tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
+ tcg_temp_free(tmp);
+ t64 = tcg_const_i64(read_im64(env, s));
+ tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
+ tcg_temp_free_i64(t64);
+ break;
+ case OS_PACKED:
+ tmp = tcg_const_i32(read_im32(env, s));
+ tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
+ tcg_temp_free(tmp);
+ t64 = tcg_const_i64(read_im64(env, s));
+ tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
+ tcg_temp_free_i64(t64);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return 0;
+ default:
+ return -1;
+ }
+ }
+ return -1;
+}
+
+static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
+ int opsize, TCGv_ptr fp, ea_what what)
+{
+ int mode = extract32(insn, 3, 3);
+ int reg0 = REG(insn, 0);
+ return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what);
+}
+
typedef struct {
TCGCond tcond;
bool g1;
@@ -4143,15 +4407,11 @@ undef:
DISAS_INSN(fpu)
{
uint16_t ext;
- int32_t offset;
int opmode;
- TCGv_i64 src;
- TCGv_i64 dest;
- TCGv_i64 res;
TCGv tmp32;
int round;
- int set_dest;
int opsize;
+ TCGv_ptr cpu_src, cpu_dest;
ext = read_im16(env, s);
opmode = ext & 0x7f;
@@ -4161,59 +4421,12 @@ DISAS_INSN(fpu)
case 1:
goto undef;
case 3: /* fmove out */
- src = FREG(ext, 7);
- tmp32 = tcg_temp_new_i32();
- /* fmove */
- /* ??? TODO: Proper behavior on overflow. */
-
+ cpu_src = gen_fp_ptr(REG(ext, 7));
opsize = ext_opsize(ext, 10);
- switch (opsize) {
- case OS_LONG:
- gen_helper_f64_to_i32(tmp32, cpu_env, src);
- break;
- case OS_SINGLE:
- gen_helper_f64_to_f32(tmp32, cpu_env, src);
- break;
- case OS_WORD:
- gen_helper_f64_to_i32(tmp32, cpu_env, src);
- break;
- case OS_DOUBLE:
- tcg_gen_mov_i32(tmp32, AREG(insn, 0));
- switch ((insn >> 3) & 7) {
- case 2:
- case 3:
- break;
- case 4:
- tcg_gen_addi_i32(tmp32, tmp32, -8);
- break;
- case 5:
- offset = cpu_ldsw_code(env, s->pc);
- s->pc += 2;
- tcg_gen_addi_i32(tmp32, tmp32, offset);
- break;
- default:
- goto undef;
- }
- gen_store64(s, tmp32, src);
- switch ((insn >> 3) & 7) {
- case 3:
- tcg_gen_addi_i32(tmp32, tmp32, 8);
- tcg_gen_mov_i32(AREG(insn, 0), tmp32);
- break;
- case 4:
- tcg_gen_mov_i32(AREG(insn, 0), tmp32);
- break;
- }
- tcg_temp_free_i32(tmp32);
- return;
- case OS_BYTE:
- gen_helper_f64_to_i32(tmp32, cpu_env, src);
- break;
- default:
- goto undef;
+ if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) == -1) {
+ gen_addr_fault(s);
}
- DEST_EA(env, insn, opsize, tmp32, NULL);
- tcg_temp_free_i32(tmp32);
+ tcg_temp_free_ptr(cpu_src);
return;
case 4: /* fmove to control register. */
case 5: /* fmove from control register. */
@@ -4223,6 +4436,7 @@ DISAS_INSN(fpu)
case 7:
{
TCGv addr;
+ TCGv_ptr fp;
uint16_t mask;
int i;
if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
@@ -4235,136 +4449,86 @@ DISAS_INSN(fpu)
addr = tcg_temp_new_i32();
tcg_gen_mov_i32(addr, tmp32);
mask = 0x80;
+ fp = tcg_temp_new_ptr();
for (i = 0; i < 8; i++) {
if (ext & mask) {
- dest = FREG(i, 0);
- if (ext & (1 << 13)) {
- /* store */
- tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
- } else {
- /* load */
- tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
- }
+ tcg_gen_addi_ptr(fp, cpu_env,
+ offsetof(CPUM68KState, fregs[i]));
+ gen_ldst_fp(s, OS_DOUBLE, addr, fp,
+ (ext & (1 << 13)) ? EA_STORE : EA_LOADS);
if (ext & (mask - 1))
tcg_gen_addi_i32(addr, addr, 8);
}
mask >>= 1;
}
tcg_temp_free_i32(addr);
+ tcg_temp_free_ptr(fp);
}
return;
}
if (ext & (1 << 14)) {
/* Source effective address. */
opsize = ext_opsize(ext, 10);
- if (opsize == OS_DOUBLE) {
- tmp32 = tcg_temp_new_i32();
- tcg_gen_mov_i32(tmp32, AREG(insn, 0));
- switch ((insn >> 3) & 7) {
- case 2:
- case 3:
- break;
- case 4:
- tcg_gen_addi_i32(tmp32, tmp32, -8);
- break;
- case 5:
- offset = cpu_ldsw_code(env, s->pc);
- s->pc += 2;
- tcg_gen_addi_i32(tmp32, tmp32, offset);
- break;
- case 7:
- offset = cpu_ldsw_code(env, s->pc);
- offset += s->pc - 2;
- s->pc += 2;
- tcg_gen_addi_i32(tmp32, tmp32, offset);
- break;
- default:
- goto undef;
- }
- src = gen_load64(s, tmp32);
- switch ((insn >> 3) & 7) {
- case 3:
- tcg_gen_addi_i32(tmp32, tmp32, 8);
- tcg_gen_mov_i32(AREG(insn, 0), tmp32);
- break;
- case 4:
- tcg_gen_mov_i32(AREG(insn, 0), tmp32);
- break;
- }
- tcg_temp_free_i32(tmp32);
- } else {
- SRC_EA(env, tmp32, opsize, 1, NULL);
- src = tcg_temp_new_i64();
- switch (opsize) {
- case OS_LONG:
- case OS_WORD:
- case OS_BYTE:
- gen_helper_i32_to_f64(src, cpu_env, tmp32);
- break;
- case OS_SINGLE:
- gen_helper_f32_to_f64(src, cpu_env, tmp32);
- break;
- }
+ cpu_src = gen_fp_result_ptr();
+ if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_LOADS) == -1) {
+ gen_addr_fault(s);
+ return;
}
} else {
/* Source register. */
- src = FREG(ext, 10);
+ opsize = OS_EXTENDED;
+ cpu_src = gen_fp_ptr(REG(ext, 10));
}
- dest = FREG(ext, 7);
- res = tcg_temp_new_i64();
- if (opmode != 0x3a)
- tcg_gen_mov_f64(res, dest);
round = 1;
- set_dest = 1;
+ cpu_dest = gen_fp_ptr(REG(ext, 7));
switch (opmode) {
case 0: case 0x40: case 0x44: /* fmove */
- tcg_gen_mov_f64(res, src);
+ gen_fp_move(cpu_dest, cpu_src);
break;
case 1: /* fint */
- gen_helper_iround_f64(res, cpu_env, src);
+ gen_helper_firound(cpu_env, cpu_dest, cpu_src);
round = 0;
break;
case 3: /* fintrz */
- gen_helper_itrunc_f64(res, cpu_env, src);
+ gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
round = 0;
break;
case 4: case 0x41: case 0x45: /* fsqrt */
- gen_helper_sqrt_f64(res, cpu_env, src);
+ gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
break;
case 0x18: case 0x58: case 0x5c: /* fabs */
- gen_helper_abs_f64(res, src);
+ gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
break;
case 0x1a: case 0x5a: case 0x5e: /* fneg */
- gen_helper_chs_f64(res, src);
+ gen_helper_fchs(cpu_env, cpu_dest, cpu_src);
break;
case 0x20: case 0x60: case 0x64: /* fdiv */
- gen_helper_div_f64(res, cpu_env, res, src);
+ gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x22: case 0x62: case 0x66: /* fadd */
- gen_helper_add_f64(res, cpu_env, res, src);
+ gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x23: case 0x63: case 0x67: /* fmul */
- gen_helper_mul_f64(res, cpu_env, res, src);
+ gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x28: case 0x68: case 0x6c: /* fsub */
- gen_helper_sub_f64(res, cpu_env, res, src);
+ gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x38: /* fcmp */
- gen_helper_sub_cmp_f64(res, cpu_env, res, src);
- set_dest = 0;
+ tcg_temp_free_ptr(cpu_dest);
+ cpu_dest = gen_fp_result_ptr();
+ gen_helper_fsub_cmp(cpu_env, cpu_dest, cpu_src, cpu_dest);
round = 0;
break;
case 0x3a: /* ftst */
- tcg_gen_mov_f64(res, src);
- set_dest = 0;
+ tcg_temp_free_ptr(cpu_dest);
+ cpu_dest = gen_fp_result_ptr();
+ gen_fp_move(cpu_dest, cpu_src);
round = 0;
break;
default:
goto undef;
}
- if (ext & (1 << 14)) {
- tcg_temp_free_i64(src);
- }
if (round) {
if (opmode & 0x40) {
if ((opmode & 0x4) != 0)
@@ -4374,16 +4538,18 @@ DISAS_INSN(fpu)
}
}
if (round) {
- TCGv tmp = tcg_temp_new_i32();
- gen_helper_f64_to_f32(tmp, cpu_env, res);
- gen_helper_f32_to_f64(res, cpu_env, tmp);
- tcg_temp_free_i32(tmp);
- }
- tcg_gen_mov_f64(QREG_FP_RESULT, res);
- if (set_dest) {
- tcg_gen_mov_f64(dest, res);
+ TCGv tmp = tcg_temp_new();
+ gen_helper_redf32(tmp, cpu_env, cpu_dest);
+ gen_helper_extf32(cpu_env, cpu_dest, tmp);
+ tcg_temp_free(tmp);
+ } else {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ gen_helper_redf64(t64, cpu_env, cpu_dest);
+ gen_helper_extf64(cpu_env, cpu_dest, t64);
+ tcg_temp_free_i64(t64);
}
- tcg_temp_free_i64(res);
+ tcg_temp_free_ptr(cpu_src);
+ tcg_temp_free_ptr(cpu_dest);
return;
undef:
/* FIXME: Is this right for offset addressing modes? */
@@ -4397,6 +4563,7 @@ DISAS_INSN(fbcc)
uint32_t addr;
TCGv flag;
TCGLabel *l1;
+ TCGv_ptr fp_result;
addr = s->pc;
offset = cpu_ldsw_code(env, s->pc);
@@ -4408,10 +4575,12 @@ DISAS_INSN(fbcc)
l1 = gen_new_label();
/* TODO: Raise BSUN exception. */
flag = tcg_temp_new();
- gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
+ fp_result = gen_fp_result_ptr();
+ gen_helper_fcompare(flag, cpu_env, fp_result);
+ tcg_temp_free_ptr(fp_result);
/* Jump to l1 if condition is true. */
switch (insn & 0xf) {
- case 0: /* f */
+ case 0: /* False */
break;
case 1: /* eq (=0) */
tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
@@ -5038,11 +5207,15 @@ void register_m68k_insns (CPUM68KState *env)
INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
- INSN(undef_fpu, f000, f000, CF_ISA_A);
+ BASE(undef_fpu, f000, f000);
INSN(fpu, f200, ffc0, CF_FPU);
INSN(fbcc, f280, ffc0, CF_FPU);
INSN(frestore, f340, ffc0, CF_FPU);
- INSN(fsave, f340, ffc0, CF_FPU);
+ INSN(fsave, f300, ffc0, CF_FPU);
+ INSN(fpu, f200, ffc0, FPU);
+ INSN(fbcc, f280, ff80, FPU);
+ INSN(frestore, f340, ffc0, FPU);
+ INSN(fsave, f300, ffc0, FPU);
INSN(intouch, f340, ffc0, CF_ISA_A);
INSN(cpushl, f428, ff38, CF_ISA_A);
INSN(wddata, fb00, ff00, CF_ISA_A);
@@ -5168,6 +5341,18 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
tb->icount = num_insns;
}
+static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
+{
+ floatx80 a = { .high = high, .low = low };
+ union {
+ float64 f64;
+ double d;
+ } u;
+
+ u.f64 = floatx80_to_float64(a, &env->fp_status);
+ return u.d;
+}
+
void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
@@ -5175,20 +5360,19 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
CPUM68KState *env = &cpu->env;
int i;
uint16_t sr;
- CPU_DoubleU u;
- for (i = 0; i < 8; i++)
- {
- u.d = env->fregs[i];
- cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
+ for (i = 0; i < 8; i++) {
+ cpu_fprintf(f, "D%d = %08x A%d = %08x "
+ "F%d = %04x %016"PRIx64" (%12g)\n",
i, env->dregs[i], i, env->aregs[i],
- i, u.l.upper, u.l.lower, *(double *)&u.d);
- }
+ i, env->fregs[i].l.upper, env->fregs[i].l.lower,
+ floatx80_to_double(env, env->fregs[i].l.upper,
+ env->fregs[i].l.lower));
+ }
cpu_fprintf (f, "PC = %08x ", env->pc);
sr = env->sr | cpu_m68k_get_ccr(env);
cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
(sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
(sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
- cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
}
void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
--
2.9.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v4 6/7] target-m68k: define 96bit FP registers for gdb on 680x0
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
` (4 preceding siblings ...)
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally Laurent Vivier
@ 2017-06-11 23:16 ` Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 7/7] target-m68k: add FPCR and FPSR Laurent Vivier
6 siblings, 0 replies; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
configure | 2 +-
gdb-xml/m68k-fp.xml | 21 +++++++++++++++++++++
target/m68k/helper.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 67 insertions(+), 1 deletion(-)
create mode 100644 gdb-xml/m68k-fp.xml
diff --git a/configure b/configure
index 13e040d..37af69b 100755
--- a/configure
+++ b/configure
@@ -6056,7 +6056,7 @@ case "$target_name" in
;;
m68k)
bflt="yes"
- gdb_xml_files="cf-core.xml cf-fp.xml"
+ gdb_xml_files="cf-core.xml cf-fp.xml m68k-fp.xml"
;;
microblaze|microblazeel)
TARGET_ARCH=microblaze
diff --git a/gdb-xml/m68k-fp.xml b/gdb-xml/m68k-fp.xml
new file mode 100644
index 0000000..64290d1
--- /dev/null
+++ b/gdb-xml/m68k-fp.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.coldfire.fp">
+ <reg name="fp0" bitsize="96" type="float" group="float"/>
+ <reg name="fp1" bitsize="96" type="float" group="float"/>
+ <reg name="fp2" bitsize="96" type="float" group="float"/>
+ <reg name="fp3" bitsize="96" type="float" group="float"/>
+ <reg name="fp4" bitsize="96" type="float" group="float"/>
+ <reg name="fp5" bitsize="96" type="float" group="float"/>
+ <reg name="fp6" bitsize="96" type="float" group="float"/>
+ <reg name="fp7" bitsize="96" type="float" group="float"/>
+
+ <reg name="fpcontrol" bitsize="32" group="float"/>
+ <reg name="fpstatus" bitsize="32" group="float"/>,
+ <reg name="fpiaddr" bitsize="32" type="code_ptr" group="float"/>
+</feature>
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 8bfc881..f2de6b5 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -102,6 +102,48 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
return 0;
}
+static int m68k_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 8) {
+ stw_be_p(mem_buf, env->fregs[n].l.upper);
+ memset(mem_buf + 2, 0, 2);
+ stq_be_p(mem_buf + 4, env->fregs[n].l.lower);
+ return 12;
+ }
+ switch (n) {
+ case 8: /* fpcontrol */
+ stl_be_p(mem_buf, env->fpcr);
+ return 4;
+ case 9: /* fpstatus */
+ stl_be_p(mem_buf, env->fpsr);
+ return 4;
+ case 10: /* fpiar, not implemented */
+ memset(mem_buf, 0, 4);
+ return 4;
+ }
+ return 0;
+}
+
+static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 8) {
+ env->fregs[n].l.upper = lduw_be_p(mem_buf);
+ env->fregs[n].l.lower = ldq_be_p(mem_buf + 4);
+ return 12;
+ }
+ switch (n) {
+ case 8: /* fpcontrol */
+ env->fpcr = ldl_p(mem_buf);
+ return 4;
+ case 9: /* fpstatus */
+ env->fpsr = ldl_p(mem_buf);
+ return 4;
+ case 10: /* fpiar, not implemented */
+ return 4;
+ }
+ return 0;
+}
+
M68kCPU *cpu_m68k_init(const char *cpu_model)
{
M68kCPU *cpu;
@@ -130,6 +172,9 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
gdb_register_coprocessor(cs, cf_fpu_gdb_get_reg, cf_fpu_gdb_set_reg,
11, "cf-fp.xml", 18);
+ } else if (m68k_feature(env, M68K_FEATURE_FPU)) {
+ gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg,
+ m68k_fpu_gdb_set_reg, 11, "m68k-fp.xml", 18);
}
/* TODO: Add [E]MAC registers. */
}
--
2.9.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v4 7/7] target-m68k: add FPCR and FPSR
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
` (5 preceding siblings ...)
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 6/7] target-m68k: define 96bit FP registers for gdb on 680x0 Laurent Vivier
@ 2017-06-11 23:16 ` Laurent Vivier
2017-06-19 21:16 ` Richard Henderson
6 siblings, 1 reply; 18+ messages in thread
From: Laurent Vivier @ 2017-06-11 23:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno, Richard Henderson, Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/cpu.c | 2 +-
target/m68k/cpu.h | 36 ++++-
target/m68k/fpu_helper.c | 118 ++++++++++++++---
target/m68k/helper.c | 20 ++-
target/m68k/helper.h | 5 +-
target/m68k/qregs.def | 1 +
target/m68k/translate.c | 335 +++++++++++++++++++++++++++++++++--------------
7 files changed, 395 insertions(+), 122 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 435456f..a14b6dd 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -62,7 +62,7 @@ static void m68k_cpu_reset(CPUState *s)
for (i = 0; i < 8; i++) {
env->fregs[i].d = nan;
}
- env->fpcr = 0;
+ cpu_m68k_set_fpcr(env, 0);
env->fpsr = 0;
cpu_m68k_set_ccr(env, 0);
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index dcdf3d2..748d11f 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -164,6 +164,7 @@ int cpu_m68k_signal_handler(int host_signum, void *pinfo,
void *puc);
uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
+void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
/* Instead of computing the condition codes after each m68k instruction,
@@ -208,6 +209,36 @@ typedef enum {
#define M68K_SSP 0
#define M68K_USP 1
+/* Floating-Point Status Register */
+
+/* Condition Code */
+#define FPSR_CC_MASK 0x0f000000
+#define FPSR_CC_A 0x01000000 /* Not-A-Number */
+#define FPSR_CC_I 0x02000000 /* Infinity */
+#define FPSR_CC_Z 0x04000000 /* Zero */
+#define FPSR_CC_N 0x08000000 /* Negative */
+
+/* Quotient */
+
+#define FPSR_QT_MASK 0x00ff0000
+
+/* Floating-Point Control Register */
+/* Rounding mode */
+#define FPCR_RND_MASK 0x0030
+#define FPCR_RND_N 0x0000
+#define FPCR_RND_Z 0x0010
+#define FPCR_RND_M 0x0020
+#define FPCR_RND_P 0x0030
+
+/* Rounding precision */
+#define FPCR_PREC_MASK 0x00c0
+#define FPCR_PREC_X 0x0000
+#define FPCR_PREC_S 0x0040
+#define FPCR_PREC_D 0x0080
+#define FPCR_PREC_U 0x00c0
+
+#define FPCR_EXCP_MASK 0xff00
+
/* CACR fields are implementation defined, but some bits are common. */
#define M68K_CACR_EUSP 0x10
@@ -224,8 +255,6 @@ typedef enum {
void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
void m68k_switch_sp(CPUM68KState *env);
-#define M68K_FPCR_PREC (1 << 6)
-
void do_m68k_semihosting(CPUM68KState *env, int nr);
/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
@@ -303,8 +332,7 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
{
*pc = env->pc;
*cs_base = 0;
- *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
- | (env->sr & SR_S) /* Bit 13 */
+ *flags = (env->sr & SR_S) /* Bit 13 */
| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
}
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index f4d3821..d8cd4cd 100644
--- a/target/m68k/fpu_helper.c
+++ b/target/m68k/fpu_helper.c
@@ -58,9 +58,74 @@ void HELPER(firound)(CPUM68KState *env, FPReg *res, FPReg *val)
res->d = floatx80_round_to_int(val->d, &env->fp_status);
}
+static void m68k_restore_precision_mode(CPUM68KState *env)
+{
+ switch (env->fpcr & FPCR_PREC_MASK) {
+ case FPCR_PREC_X: /* extended */
+ set_floatx80_rounding_precision(80, &env->fp_status);
+ break;
+ case FPCR_PREC_S: /* single */
+ set_floatx80_rounding_precision(32, &env->fp_status);
+ break;
+ case FPCR_PREC_D: /* double */
+ set_floatx80_rounding_precision(64, &env->fp_status);
+ break;
+ case FPCR_PREC_U: /* undefined */
+ default:
+ break;
+ }
+}
+
+static void cf_restore_precision_mode(CPUM68KState *env)
+{
+ if (env->fpcr & FPCR_PREC_S) { /* single */
+ set_floatx80_rounding_precision(32, &env->fp_status);
+ } else { /* double */
+ set_floatx80_rounding_precision(64, &env->fp_status);
+ }
+}
+
+static void restore_rounding_mode(CPUM68KState *env)
+{
+ switch (env->fpcr & FPCR_RND_MASK) {
+ case FPCR_RND_N: /* round to nearest */
+ set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+ break;
+ case FPCR_RND_Z: /* round to zero */
+ set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+ break;
+ case FPCR_RND_M: /* round toward minus infinity */
+ set_float_rounding_mode(float_round_down, &env->fp_status);
+ break;
+ case FPCR_RND_P: /* round toward positive infinity */
+ set_float_rounding_mode(float_round_up, &env->fp_status);
+ break;
+ }
+}
+
+void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val)
+{
+ env->fpcr = val & 0xffff;
+
+ if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
+ cf_restore_precision_mode(env);
+ } else {
+ m68k_restore_precision_mode(env);
+ }
+ restore_rounding_mode(env);
+}
+
void HELPER(fitrunc)(CPUM68KState *env, FPReg *res, FPReg *val)
{
+ int rounding_mode = get_float_rounding_mode(&env->fp_status);
+ set_float_rounding_mode(float_round_to_zero, &env->fp_status);
res->d = floatx80_round_to_int(val->d, &env->fp_status);
+ set_float_rounding_mode(rounding_mode, &env->fp_status);
+}
+
+void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val)
+{
+ cpu_m68k_set_fpcr(env, val);
}
void HELPER(fsqrt)(CPUM68KState *env, FPReg *res, FPReg *val)
@@ -98,24 +163,45 @@ void HELPER(fdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
res->d = floatx80_div(val1->d, val0->d, &env->fp_status);
}
-void HELPER(fsub_cmp)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
-{
- /* ??? This may incorrectly raise exceptions. */
- /* ??? Should flush denormals to zero. */
- res->d = floatx80_sub(val0->d, val1->d, &env->fp_status);
- if (floatx80_is_quiet_nan(res->d, &env->fp_status)) {
- /* +/-inf compares equal against itself, but sub returns nan. */
- if (!floatx80_is_quiet_nan(val0->d, &env->fp_status)
- && !floatx80_is_quiet_nan(val1->d, &env->fp_status)) {
- res->d = floatx80_zero;
- if (floatx80_lt_quiet(val0->d, res->d, &env->fp_status)) {
- res->d = floatx80_chs(res->d);
- }
- }
+static int float_comp_to_cc(int float_compare)
+{
+ switch (float_compare) {
+ case float_relation_equal:
+ return FPSR_CC_Z;
+ case float_relation_less:
+ return FPSR_CC_N;
+ case float_relation_unordered:
+ return FPSR_CC_A;
+ case float_relation_greater:
+ return 0;
+ default:
+ g_assert_not_reached();
}
}
-uint32_t HELPER(fcompare)(CPUM68KState *env, FPReg *val)
+uint32_t HELPER(fcmp)(CPUM68KState *env, uint32_t fpsr,
+ FPReg *val0, FPReg *val1)
{
- return floatx80_compare_quiet(val->d, floatx80_zero, &env->fp_status);
+ int float_compare;
+
+ float_compare = floatx80_compare(val1->d, val0->d, &env->fp_status);
+ return (fpsr & ~FPSR_CC_MASK) | float_comp_to_cc(float_compare);
+}
+
+uint32_t HELPER(ftst)(CPUM68KState *env, uint32_t fpsr, FPReg *val)
+{
+ uint32_t cc = 0;
+
+ if (floatx80_is_neg(val->d)) {
+ cc |= FPSR_CC_N;
+ }
+
+ if (floatx80_is_any_nan(val->d)) {
+ cc |= FPSR_CC_A;
+ } else if (floatx80_is_infinity(val->d)) {
+ cc |= FPSR_CC_I;
+ } else if (floatx80_is_zero(val->d)) {
+ cc |= FPSR_CC_Z;
+ }
+ return (fpsr & ~FPSR_CC_MASK) | cc;
}
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index f2de6b5..d93fad9 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -80,8 +80,14 @@ static int cf_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
stfq_p(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
return 8;
}
- if (n < 11) {
- /* FP control registers (not implemented) */
+ switch (n) {
+ case 8: /* fpcontrol */
+ stl_be_p(mem_buf, env->fpcr);
+ return 4;
+ case 9: /* fpstatus */
+ stl_be_p(mem_buf, env->fpsr);
+ return 4;
+ case 10: /* fpiar, not implemented */
memset(mem_buf, 0, 4);
return 4;
}
@@ -95,8 +101,14 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
env->fregs[n].d = float64_to_floatx80(ldfq_p(mem_buf), &s);
return 8;
}
- if (n < 11) {
- /* FP control registers (not implemented) */
+ switch (n) {
+ case 8: /* fpcontrol */
+ env->fpcr = ldl_p(mem_buf);
+ return 4;
+ case 9: /* fpstatus */
+ env->fpsr = ldl_p(mem_buf);
+ return 4;
+ case 10: /* fpiar, not implemented */
return 4;
}
return 0;
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index d871be6..1c6b5c2 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -32,8 +32,9 @@ DEF_HELPER_4(fadd, void, env, fp, fp, fp)
DEF_HELPER_4(fsub, void, env, fp, fp, fp)
DEF_HELPER_4(fmul, void, env, fp, fp, fp)
DEF_HELPER_4(fdiv, void, env, fp, fp, fp)
-DEF_HELPER_4(fsub_cmp, void, env, fp, fp, fp)
-DEF_HELPER_2(fcompare, i32, env, fp)
+DEF_HELPER_FLAGS_4(fcmp, TCG_CALL_NO_RWG, i32, env, i32, fp, fp)
+DEF_HELPER_2(set_fpcr, void, env, i32)
+DEF_HELPER_FLAGS_3(ftst, TCG_CALL_NO_RWG, i32, env, i32, fp)
DEF_HELPER_3(mac_move, void, env, i32, i32)
DEF_HELPER_3(macmulf, i64, env, i32, i32)
diff --git a/target/m68k/qregs.def b/target/m68k/qregs.def
index 1aadc62..a3d79e9 100644
--- a/target/m68k/qregs.def
+++ b/target/m68k/qregs.def
@@ -8,3 +8,4 @@ DEFO32(CC_V, cc_v)
DEFO32(CC_Z, cc_z)
DEFO32(MACSR, macsr)
DEFO32(MAC_MASK, mac_mask)
+DEFO32(FPSR, fpsr)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 5847c6f..b9f3bce 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -49,6 +49,8 @@ static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
static TCGv cpu_dregs[8];
static TCGv cpu_aregs[8];
static TCGv_i64 cpu_macc[4];
+static TCGv QEMU_FPSR;
+static TCGv QEMU_FPCR;
#define REG(insn, pos) (((insn) >> (pos)) & 7)
#define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
@@ -107,6 +109,11 @@ void m68k_tcg_init(void)
p += 5;
}
+ QEMU_FPSR = tcg_global_mem_new(cpu_env, offsetof(CPUM68KState, fpsr),
+ "FPSR");
+ QEMU_FPCR = tcg_global_mem_new(cpu_env, offsetof(CPUM68KState, fpcr),
+ "FPCR");
+
NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
}
@@ -120,7 +127,6 @@ typedef struct DisasContext {
CCOp cc_op; /* Current CC operation */
int cc_op_synced;
int user;
- uint32_t fpcr;
struct TranslationBlock *tb;
int singlestep_enabled;
TCGv_i64 mactmp;
@@ -4363,43 +4369,121 @@ DISAS_INSN(trap)
gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
}
+static void gen_store_fcr(DisasContext *s, TCGv addr, int reg)
+{
+ int index = IS_USER(s);
+
+ switch (reg) {
+ case 0: /* FPSR */
+ tcg_gen_qemu_st32(QEMU_FPSR, addr, index);
+ break;
+ case 1: /* FPIAR */
+ break;
+ case 2: /* FPCR */
+ tcg_gen_qemu_st32(QEMU_FPCR, addr, index);
+ break;
+ }
+}
+
+static void gen_load_fcr(DisasContext *s, TCGv addr, int reg)
+{
+ int index = IS_USER(s);
+ TCGv val;
+
+ switch (reg) {
+ case 0: /* FPSR */
+ tcg_gen_qemu_ld32u(QEMU_FPSR, addr, index);
+ break;
+ case 1: /* FPIAR */
+ break;
+ case 2: /* FPCR */
+ val = tcg_temp_new();
+ tcg_gen_qemu_ld32u(val, addr, index);
+ gen_helper_set_fpcr(cpu_env, val);
+ tcg_temp_free(val);
+ break;
+ }
+}
+
static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
uint32_t insn, uint32_t ext)
{
int mask = (ext >> 10) & 7;
int is_write = (ext >> 13) & 1;
- TCGv val;
+ int i;
+ TCGv addr, tmp;
- if (is_write) {
+ tmp = gen_lea(env, s, insn, OS_LONG);
+ if (IS_NULL_QREG(tmp)) {
+ TCGv val;
+
+ if (is_write) {
+ switch (mask) {
+ case 1: /* FPIAR */
+ break;
+ case 2: /* FPSR */
+ DEST_EA(env, insn, OS_LONG, QEMU_FPSR, NULL);
+ break;
+ case 4: /* FPCR */
+ DEST_EA(env, insn, OS_LONG, QEMU_FPCR, NULL);
+ break;
+ }
+ return;
+ }
switch (mask) {
case 1: /* FPIAR */
+ break;
case 2: /* FPSR */
- default:
- cpu_abort(NULL, "Unimplemented: fmove from control %d", mask);
- goto undef;
+ SRC_EA(env, val, OS_LONG, 0, NULL);
+ tcg_gen_mov_i32(QEMU_FPSR, val);
+ break;
case 4: /* FPCR */
- val = tcg_const_i32(0);
- DEST_EA(env, insn, OS_LONG, val, NULL);
- tcg_temp_free(val);
+ SRC_EA(env, val, OS_LONG, 0, NULL);
+ gen_helper_set_fpcr(cpu_env, val);
break;
}
return;
}
- switch (mask) {
- case 1: /* FPIAR */
- case 2: /* FPSR */
- default:
- cpu_abort(NULL, "Unimplemented: fmove to control %d",
- mask);
- break;
- case 4: /* FPCR */
- /* Not implemented. Ignore writes. */
- break;
+
+ addr = tcg_temp_new();
+ tcg_gen_mov_i32(addr, tmp);
+
+ /* mask:
+ *
+ * 0b100 Floating-Point Control Register
+ * 0b010 Floating-Point Status Register
+ * 0b001 Floating-Point Instruction Address Register
+ *
+ */
+
+ if (is_write && (insn & 070) == 040) {
+ for (i = 2; i >= 0; i--, mask >>= 1) {
+ if (mask & 1) {
+ gen_store_fcr(s, addr, i);
+ if (mask != 1) {
+ tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
+ }
+ }
+ }
+ tcg_gen_mov_i32(AREG(insn, 0), addr);
+ } else {
+ for (i = 0; i < 3; i++, mask >>= 1) {
+ if (mask & 1) {
+ if (is_write) {
+ gen_store_fcr(s, addr, i);
+ } else {
+ gen_load_fcr(s, addr, i);
+ }
+ if (mask != 1 || (insn & 070) == 030) {
+ tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
+ }
+ }
+ }
+ if ((insn & 070) == 030) {
+ tcg_gen_mov_i32(AREG(insn, 0), addr);
+ }
}
- return;
-undef:
- s->pc -= 2;
- disas_undef_fpu(env, s, insn);
+ tcg_temp_free_i32(addr);
}
/* ??? FP exceptions are not implemented. Most exceptions are deferred until
@@ -4409,7 +4493,6 @@ DISAS_INSN(fpu)
uint16_t ext;
int opmode;
TCGv tmp32;
- int round;
int opsize;
TCGv_ptr cpu_src, cpu_dest;
@@ -4426,6 +4509,7 @@ DISAS_INSN(fpu)
if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) == -1) {
gen_addr_fault(s);
}
+ gen_helper_ftst(QREG_FPSR, cpu_env, QREG_FPSR, cpu_src);
tcg_temp_free_ptr(cpu_src);
return;
case 4: /* fmove to control register. */
@@ -4479,7 +4563,6 @@ DISAS_INSN(fpu)
opsize = OS_EXTENDED;
cpu_src = gen_fp_ptr(REG(ext, 10));
}
- round = 1;
cpu_dest = gen_fp_ptr(REG(ext, 7));
switch (opmode) {
case 0: case 0x40: case 0x44: /* fmove */
@@ -4487,11 +4570,9 @@ DISAS_INSN(fpu)
break;
case 1: /* fint */
gen_helper_firound(cpu_env, cpu_dest, cpu_src);
- round = 0;
break;
case 3: /* fintrz */
gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
- round = 0;
break;
case 4: case 0x41: case 0x45: /* fsqrt */
gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
@@ -4515,40 +4596,16 @@ DISAS_INSN(fpu)
gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x38: /* fcmp */
- tcg_temp_free_ptr(cpu_dest);
- cpu_dest = gen_fp_result_ptr();
- gen_helper_fsub_cmp(cpu_env, cpu_dest, cpu_src, cpu_dest);
- round = 0;
- break;
+ gen_helper_fcmp(QREG_FPSR, cpu_env, QREG_FPSR, cpu_src, cpu_dest);
+ return;
case 0x3a: /* ftst */
- tcg_temp_free_ptr(cpu_dest);
- cpu_dest = gen_fp_result_ptr();
- gen_fp_move(cpu_dest, cpu_src);
- round = 0;
- break;
+ gen_helper_ftst(QREG_FPSR, cpu_env, QREG_FPSR, cpu_src);
+ return;
default:
goto undef;
}
- if (round) {
- if (opmode & 0x40) {
- if ((opmode & 0x4) != 0)
- round = 0;
- } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
- round = 0;
- }
- }
- if (round) {
- TCGv tmp = tcg_temp_new();
- gen_helper_redf32(tmp, cpu_env, cpu_dest);
- gen_helper_extf32(cpu_env, cpu_dest, tmp);
- tcg_temp_free(tmp);
- } else {
- TCGv_i64 t64 = tcg_temp_new_i64();
- gen_helper_redf64(t64, cpu_env, cpu_dest);
- gen_helper_extf64(cpu_env, cpu_dest, t64);
- tcg_temp_free_i64(t64);
- }
tcg_temp_free_ptr(cpu_src);
+ gen_helper_ftst(QREG_FPSR, cpu_env, QREG_FPSR, cpu_dest);
tcg_temp_free_ptr(cpu_dest);
return;
undef:
@@ -4561,9 +4618,8 @@ DISAS_INSN(fbcc)
{
uint32_t offset;
uint32_t addr;
- TCGv flag;
TCGLabel *l1;
- TCGv_ptr fp_result;
+ TCGv tmp;
addr = s->pc;
offset = cpu_ldsw_code(env, s->pc);
@@ -4574,59 +4630,117 @@ DISAS_INSN(fbcc)
l1 = gen_new_label();
/* TODO: Raise BSUN exception. */
- flag = tcg_temp_new();
- fp_result = gen_fp_result_ptr();
- gen_helper_fcompare(flag, cpu_env, fp_result);
- tcg_temp_free_ptr(fp_result);
/* Jump to l1 if condition is true. */
- switch (insn & 0xf) {
+ switch (insn & 0x3f) {
case 0: /* False */
+ case 16: /* Signaling False */
break;
- case 1: /* eq (=0) */
- tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
+ case 1: /* EQual Z */
+ case 17: /* Signaling EQual Z */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_Z);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 2: /* ogt (=1) */
- tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
+ case 2: /* Ordered Greater Than !(A || Z || N) */
+ case 18: /* Greater Than !(A || Z || N) */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR,
+ FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
- case 3: /* oge (=0 or =1) */
- tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
+ case 3: /* Ordered Greater than or Equal Z || !(A || N) */
+ case 19: /* Greater than or Equal Z || !(A || N) */
+ assert(FPSR_CC_A == (FPSR_CC_N >> 3));
+ tmp = tcg_temp_new();
+ tcg_gen_shli_i32(tmp, QREG_FPSR, 3);
+ tcg_gen_or_i32(tmp, tmp, QREG_FPSR);
+ tcg_gen_xori_i32(tmp, tmp, FPSR_CC_N);
+ tcg_gen_andi_i32(tmp, tmp, FPSR_CC_N | FPSR_CC_Z);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 4: /* olt (=-1) */
- tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
+ case 4: /* Ordered Less Than !(!N || A || Z); */
+ case 20: /* Less Than !(!N || A || Z); */
+ tmp = tcg_temp_new();
+ tcg_gen_xori_i32(tmp, QREG_FPSR, FPSR_CC_N);
+ tcg_gen_andi_i32(tmp, tmp, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
- case 5: /* ole (=-1 or =0) */
- tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
+ case 5: /* Ordered Less than or Equal Z || (N && !A) */
+ case 21: /* Less than or Equal Z || (N && !A) */
+ assert(FPSR_CC_A == (FPSR_CC_N >> 3));
+ tmp = tcg_temp_new();
+ tcg_gen_xori_i32(tmp, QREG_FPSR, FPSR_CC_A);
+ tcg_gen_shli_i32(tmp, tmp, 3);
+ tcg_gen_ori_i32(tmp, tmp, FPSR_CC_Z);
+ tcg_gen_and_i32(tmp, tmp, QREG_FPSR);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 6: /* ogl (=-1 or =1) */
- tcg_gen_andi_i32(flag, flag, 1);
- tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
+ case 6: /* Ordered Greater or Less than !(A || Z) */
+ case 22: /* Greater or Less than !(A || Z) */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_A | FPSR_CC_Z);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
- case 7: /* or (=2) */
- tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
+ case 7: /* Ordered !A */
+ case 23: /* Greater, Less or Equal !A */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_A);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
- case 8: /* un (<2) */
- tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
+ case 8: /* Unordered A */
+ case 24: /* Not Greater, Less or Equal A */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_A);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 9: /* ueq (=0 or =2) */
- tcg_gen_andi_i32(flag, flag, 1);
- tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
+ case 9: /* Unordered or Equal A || Z */
+ case 25: /* Not Greater or Less then A || Z */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_A | FPSR_CC_Z);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 10: /* ugt (>0) */
- tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
+ case 10: /* Unordered or Greater Than A || !(N || Z)) */
+ case 26: /* Not Less or Equal A || !(N || Z)) */
+ assert(FPSR_CC_Z == (FPSR_CC_N >> 1));
+ tmp = tcg_temp_new();
+ tcg_gen_shli_i32(tmp, QREG_FPSR, 1);
+ tcg_gen_or_i32(tmp, tmp, QREG_FPSR);
+ tcg_gen_xori_i32(tmp, tmp, FPSR_CC_N);
+ tcg_gen_andi_i32(tmp, tmp, FPSR_CC_N | FPSR_CC_A);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 11: /* uge (>=0) */
- tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
+ case 11: /* Unordered or Greater or Equal A || Z || !N */
+ case 27: /* Not Less Than A || Z || !N */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
+ tcg_gen_xori_i32(tmp, tmp, FPSR_CC_N);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 12: /* ult (=-1 or =2) */
- tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
+ case 12: /* Unordered or Less Than A || (N && !Z) */
+ case 28: /* Not Greater than or Equal A || (N && !Z) */
+ assert(FPSR_CC_Z == (FPSR_CC_N >> 1));
+ tmp = tcg_temp_new();
+ tcg_gen_xori_i32(tmp, QREG_FPSR, FPSR_CC_Z);
+ tcg_gen_shli_i32(tmp, tmp, 1);
+ tcg_gen_ori_i32(tmp, tmp, FPSR_CC_A);
+ tcg_gen_and_i32(tmp, tmp, QREG_FPSR);
+ tcg_gen_andi_i32(tmp, tmp, FPSR_CC_A | FPSR_CC_N);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 13: /* ule (!=1) */
- tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
+ case 13: /* Unordered or Less or Equal A || Z || N */
+ case 29: /* Not Greater Than A || Z || N */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
- case 14: /* ne (!=0) */
- tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
+ case 14: /* Not Equal !Z */
+ case 30: /* Signaling Not Equal !Z */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(tmp, QREG_FPSR, FPSR_CC_Z);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
- case 15: /* t */
+ case 15: /* True */
+ case 31: /* Signaling True */
tcg_gen_br(l1);
break;
}
@@ -5254,7 +5368,6 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_synced = 1;
dc->singlestep_enabled = cs->singlestep_enabled;
- dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
dc->done_mac = 0;
dc->writeback_mask = 0;
@@ -5373,6 +5486,38 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
(sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
(sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
+ cpu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
+ (env->fpsr & FPSR_CC_A) ? 'A' : '-',
+ (env->fpsr & FPSR_CC_I) ? 'I' : '-',
+ (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
+ (env->fpsr & FPSR_CC_N) ? 'N' : '-');
+ cpu_fprintf(f, "\n "
+ "FPCR = %04x ", env->fpcr);
+ switch (env->fpcr & FPCR_PREC_MASK) {
+ case FPCR_PREC_X:
+ cpu_fprintf(f, "X ");
+ break;
+ case FPCR_PREC_S:
+ cpu_fprintf(f, "S ");
+ break;
+ case FPCR_PREC_D:
+ cpu_fprintf(f, "D ");
+ break;
+ }
+ switch (env->fpcr & FPCR_RND_MASK) {
+ case FPCR_RND_N:
+ cpu_fprintf(f, "RN ");
+ break;
+ case FPCR_RND_Z:
+ cpu_fprintf(f, "RZ ");
+ break;
+ case FPCR_RND_M:
+ cpu_fprintf(f, "RM ");
+ break;
+ case FPCR_RND_P:
+ cpu_fprintf(f, "RP ");
+ break;
+ }
}
void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
--
2.9.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function Laurent Vivier
@ 2017-06-12 16:13 ` Richard Henderson
2017-06-12 17:56 ` Laurent Vivier
2017-06-12 19:12 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2017-06-12 16:13 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Aurelien Jarno
On 06/11/2017 04:16 PM, Laurent Vivier wrote:
> Move code of fmove to/from control register to a function
>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> target/m68k/translate.c | 66 ++++++++++++++++++++++++++++++-------------------
> 1 file changed, 41 insertions(+), 25 deletions(-)
In that this is 100% code movement,
Reviewed-by: Richard Henderson <rth@twiddle.net>
> + cpu_abort(NULL, "Unimplemented: fmove from control %d", mask);
> + goto undef;
But cpu_abort doesn't return, and will exit qemu.
This should be qemu_log_mask(LOG_UNIMP, ...).
r~
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function
2017-06-12 16:13 ` Richard Henderson
@ 2017-06-12 17:56 ` Laurent Vivier
2017-06-12 18:37 ` Richard Henderson
0 siblings, 1 reply; 18+ messages in thread
From: Laurent Vivier @ 2017-06-12 17:56 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aurelien Jarno
Le 12/06/2017 à 18:13, Richard Henderson a écrit :
> On 06/11/2017 04:16 PM, Laurent Vivier wrote:
>> Move code of fmove to/from control register to a function
>>
>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>> ---
>> target/m68k/translate.c | 66
>> ++++++++++++++++++++++++++++++-------------------
>> 1 file changed, 41 insertions(+), 25 deletions(-)
>
> In that this is 100% code movement,
>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
>
>
>> + cpu_abort(NULL, "Unimplemented: fmove from control %d",
>> mask);
>> + goto undef;
>
> But cpu_abort doesn't return, and will exit qemu.
> This should be qemu_log_mask(LOG_UNIMP, ...).
Do you want I update the patch to fix that?
Thanks,
Laurent
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function
2017-06-12 17:56 ` Laurent Vivier
@ 2017-06-12 18:37 ` Richard Henderson
0 siblings, 0 replies; 18+ messages in thread
From: Richard Henderson @ 2017-06-12 18:37 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Aurelien Jarno
On 06/12/2017 10:56 AM, Laurent Vivier wrote:
> Le 12/06/2017 à 18:13, Richard Henderson a écrit :
>> On 06/11/2017 04:16 PM, Laurent Vivier wrote:
>>> Move code of fmove to/from control register to a function
>>>
>>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>>> ---
>>> target/m68k/translate.c | 66
>>> ++++++++++++++++++++++++++++++-------------------
>>> 1 file changed, 41 insertions(+), 25 deletions(-)
>>
>> In that this is 100% code movement,
>>
>> Reviewed-by: Richard Henderson <rth@twiddle.net>
>>
>>
>>> + cpu_abort(NULL, "Unimplemented: fmove from control %d",
>>> mask);
>>> + goto undef;
>>
>> But cpu_abort doesn't return, and will exit qemu.
>> This should be qemu_log_mask(LOG_UNIMP, ...).
>
> Do you want I update the patch to fix that?
Yes please.
r~
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function Laurent Vivier
2017-06-12 16:13 ` Richard Henderson
@ 2017-06-12 19:12 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-06-12 19:12 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Aurelien Jarno, Richard Henderson
Hi Laurent,
On 06/11/2017 08:16 PM, Laurent Vivier wrote:
> Move code of fmove to/from control register to a function
>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> target/m68k/translate.c | 66 ++++++++++++++++++++++++++++++-------------------
> 1 file changed, 41 insertions(+), 25 deletions(-)
>
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index 049d837..45733ce 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -4099,6 +4099,45 @@ DISAS_INSN(trap)
> gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
> }
>
> +static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
> + uint32_t insn, uint32_t ext)
> +{
> + int mask = (ext >> 10) & 7;
> + int is_write = (ext >> 13) & 1;
> + TCGv val;
> +
> + if (is_write) {
> + switch (mask) {
> + case 1: /* FPIAR */
> + case 2: /* FPSR */
> + default:
> + cpu_abort(NULL, "Unimplemented: fmove from control %d", mask);
> + goto undef;
> + case 4: /* FPCR */
It seems easier to move the 'if (is_write) {' check here
> + val = tcg_const_i32(0);
> + DEST_EA(env, insn, OS_LONG, val, NULL);
> + tcg_temp_free(val);
then '}'
> + break;
> + }
> + return;
> + }
> + switch (mask) {
> + case 1: /* FPIAR */
> + case 2: /* FPSR */
> + default:
> + cpu_abort(NULL, "Unimplemented: fmove to control %d",
> + mask);
> + break;
> + case 4: /* FPCR */
> + /* Not implemented. Ignore writes. */
> + break;
> + }
> + return;
> +undef:
> + s->pc -= 2;
> + disas_undef_fpu(env, s, insn);
> +}
> +
> /* ??? FP exceptions are not implemented. Most exceptions are deferred until
> immediately before the next FP instruction is executed. */
> DISAS_INSN(fpu)
> @@ -4177,32 +4216,9 @@ DISAS_INSN(fpu)
> tcg_temp_free_i32(tmp32);
> return;
> case 4: /* fmove to control register. */
> - switch ((ext >> 10) & 7) {
> - case 4: /* FPCR */
> - /* Not implemented. Ignore writes. */
> - break;
> - case 1: /* FPIAR */
> - case 2: /* FPSR */
> - default:
> - cpu_abort(NULL, "Unimplemented: fmove to control %d",
> - (ext >> 10) & 7);
> - }
> - break;
> case 5: /* fmove from control register. */
> - switch ((ext >> 10) & 7) {
> - case 4: /* FPCR */
> - /* Not implemented. Always return zero. */
> - tmp32 = tcg_const_i32(0);
> - break;
> - case 1: /* FPIAR */
> - case 2: /* FPSR */
> - default:
> - cpu_abort(NULL, "Unimplemented: fmove from control %d",
> - (ext >> 10) & 7);
> - goto undef;
> - }
> - DEST_EA(env, insn, OS_LONG, tmp32, NULL);
> - break;
> + gen_op_fmove_fcr(env, s, insn, ext);
> + return;
> case 6: /* fmovem */
> case 7:
> {
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally Laurent Vivier
@ 2017-06-13 4:48 ` Thomas Huth
2017-06-19 20:53 ` Richard Henderson
1 sibling, 0 replies; 18+ messages in thread
From: Thomas Huth @ 2017-06-13 4:48 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Aurelien Jarno, Richard Henderson
On 12.06.2017 01:16, Laurent Vivier wrote:
> Coldfire uses float64, but 680x0 use floatx80.
> This patch introduces the use of floatx80 internally
> and enables 680x0 80bits FPU.
>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> target/m68k/cpu.c | 9 +-
> target/m68k/cpu.h | 6 +-
> target/m68k/fpu_helper.c | 85 +++----
> target/m68k/helper.c | 12 +-
> target/m68k/helper.h | 37 +--
> target/m68k/qregs.def | 1 -
> target/m68k/translate.c | 568 +++++++++++++++++++++++++++++++----------------
> 7 files changed, 464 insertions(+), 254 deletions(-)
>
> diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
> index f068922..435456f 100644
> --- a/target/m68k/cpu.c
> +++ b/target/m68k/cpu.c
> @@ -49,6 +49,8 @@ static void m68k_cpu_reset(CPUState *s)
> M68kCPU *cpu = M68K_CPU(s);
> M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);
> CPUM68KState *env = &cpu->env;
> + floatx80 nan = floatx80_default_nan(NULL);
> + int i;
>
> mcc->parent_reset(s);
>
> @@ -57,7 +59,12 @@ static void m68k_cpu_reset(CPUState *s)
> env->sr = 0x2700;
> #endif
> m68k_switch_sp(env);
> - /* ??? FP regs should be initialized to NaN. */
> + for (i = 0; i < 8; i++) {
> + env->fregs[i].d = nan;
> + }
> + env->fpcr = 0;
> + env->fpsr = 0;
> +
Maybe move such non-related hunks to a separate patch? This patch here
is already big enough...
Thomas
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally Laurent Vivier
2017-06-13 4:48 ` Thomas Huth
@ 2017-06-19 20:53 ` Richard Henderson
2017-06-19 21:03 ` Laurent Vivier
1 sibling, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2017-06-19 20:53 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Aurelien Jarno
On 06/11/2017 04:16 PM, Laurent Vivier wrote:
> +static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
> +{
> + TCGv tmp;
> + TCGv_i64 t64;
> + int index = IS_USER(s);
> +
> + t64 = tcg_temp_new_i64();
> + tmp = tcg_temp_new();
> + switch (opsize) {
> + case OS_BYTE:
> + tcg_gen_qemu_ld8s(tmp, addr, index);
> + gen_helper_exts32(cpu_env, fp, tmp);
> + break;
> + case OS_WORD:
> + tcg_gen_qemu_ld16s(tmp, addr, index);
> + gen_helper_exts32(cpu_env, fp, tmp);
> + break;
> + case OS_LONG:
> + tcg_gen_qemu_ld32u(tmp, addr, index);
> + gen_helper_exts32(cpu_env, fp, tmp);
> + break;
> + case OS_SINGLE:
> + tcg_gen_qemu_ld32u(tmp, addr, index);
> + gen_helper_extf32(cpu_env, fp, tmp);
> + break;
> + case OS_DOUBLE:
> + tcg_gen_qemu_ld64(t64, addr, index);
> + gen_helper_extf64(cpu_env, fp, t64);
> + tcg_temp_free_i64(t64);
> + break;
> + case OS_EXTENDED:
> + tcg_gen_qemu_ld32u(tmp, addr, index);
> + tcg_gen_shri_i32(tmp, tmp, 16);
> + tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
> + tcg_gen_addi_i32(tmp, addr, 4);
> + tcg_gen_qemu_ld64(t64, tmp, index);
> + tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
> + break;
> + case OS_PACKED:
> + tcg_gen_qemu_ld32u(tmp, addr, index);
> + tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
> + tcg_gen_addi_i32(tmp, addr, 4);
> + tcg_gen_qemu_ld64(t64, tmp, index);
> + tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
I don't see how this can be correct. Doesn't the packed-decimal format use all
12 bytes (with two unaligned nibbles unused)?
It would also make me happier if we were to adjust the definition of fl0atx80
to more closely match m68k and those missing zeros. Shouldn't real hardware
move instructions propagate those middle 2 bytes regardless of contents?
Perhaps something like
#ifdef TARGET_M68K
typedef struct {
uint64_t low;
union {
uin32_t high32;
struct {
#ifdef HOST_WORDS_BIGENDIAN
uint16_t high, zero;
#else
uint16_t zero, high;
#endif
};
};
} floatx80;
#else
...
#endif
(with a minor fix to make_floatx80 to use named initializers).
Then you can use full 32-bit store insns when copying data here. Which also
allows you to drop some of the shifts you're needing to add.
And, in future, when you actually implement the packed decimal, you'll be able
to use the high32 field to Do the Right Thing.
All of the rest of the patch looks good.
r~
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally
2017-06-19 20:53 ` Richard Henderson
@ 2017-06-19 21:03 ` Laurent Vivier
2017-06-19 21:42 ` Laurent Vivier
0 siblings, 1 reply; 18+ messages in thread
From: Laurent Vivier @ 2017-06-19 21:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aurelien Jarno
Le 19/06/2017 à 22:53, Richard Henderson a écrit :
> On 06/11/2017 04:16 PM, Laurent Vivier wrote:
>> +static void gen_load_fp(DisasContext *s, int opsize, TCGv addr,
>> TCGv_ptr fp)
>> +{
>> + TCGv tmp;
>> + TCGv_i64 t64;
>> + int index = IS_USER(s);
>> +
>> + t64 = tcg_temp_new_i64();
>> + tmp = tcg_temp_new();
>> + switch (opsize) {
>> + case OS_BYTE:
>> + tcg_gen_qemu_ld8s(tmp, addr, index);
>> + gen_helper_exts32(cpu_env, fp, tmp);
>> + break;
>> + case OS_WORD:
>> + tcg_gen_qemu_ld16s(tmp, addr, index);
>> + gen_helper_exts32(cpu_env, fp, tmp);
>> + break;
>> + case OS_LONG:
>> + tcg_gen_qemu_ld32u(tmp, addr, index);
>> + gen_helper_exts32(cpu_env, fp, tmp);
>> + break;
>> + case OS_SINGLE:
>> + tcg_gen_qemu_ld32u(tmp, addr, index);
>> + gen_helper_extf32(cpu_env, fp, tmp);
>> + break;
>> + case OS_DOUBLE:
>> + tcg_gen_qemu_ld64(t64, addr, index);
>> + gen_helper_extf64(cpu_env, fp, t64);
>> + tcg_temp_free_i64(t64);
>> + break;
>> + case OS_EXTENDED:
>> + tcg_gen_qemu_ld32u(tmp, addr, index);
>> + tcg_gen_shri_i32(tmp, tmp, 16);
>> + tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
>> + tcg_gen_addi_i32(tmp, addr, 4);
>> + tcg_gen_qemu_ld64(t64, tmp, index);
>> + tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
>> + break;
>> + case OS_PACKED:
>> + tcg_gen_qemu_ld32u(tmp, addr, index);
>> + tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
>> + tcg_gen_addi_i32(tmp, addr, 4);
>> + tcg_gen_qemu_ld64(t64, tmp, index);
>> + tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
>
> I don't see how this can be correct. Doesn't the packed-decimal format
> use all 12 bytes (with two unaligned nibbles unused)?
yes, it's totally wrong.
>
> It would also make me happier if we were to adjust the definition of
> fl0atx80 to more closely match m68k and those missing zeros. Shouldn't
> real hardware move instructions propagate those middle 2 bytes
> regardless of contents?
>
> Perhaps something like
>
> #ifdef TARGET_M68K
> typedef struct {
> uint64_t low;
> union {
> uin32_t high32;
> struct {
> #ifdef HOST_WORDS_BIGENDIAN
> uint16_t high, zero;
> #else
> uint16_t zero, high;
> #endif
> };
> };
> } floatx80;
> #else
> ...
> #endif
>
> (with a minor fix to make_floatx80 to use named initializers).
>
> Then you can use full 32-bit store insns when copying data here. Which
> also allows you to drop some of the shifts you're needing to add.
OK, I will.
> And, in future, when you actually implement the packed decimal, you'll
> be able to use the high32 field to Do the Right Thing.
>
> All of the rest of the patch looks good.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 7/7] target-m68k: add FPCR and FPSR
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 7/7] target-m68k: add FPCR and FPSR Laurent Vivier
@ 2017-06-19 21:16 ` Richard Henderson
0 siblings, 0 replies; 18+ messages in thread
From: Richard Henderson @ 2017-06-19 21:16 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Aurelien Jarno
On 06/11/2017 04:16 PM, Laurent Vivier wrote:
> @@ -95,8 +101,14 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
> env->fregs[n].d = float64_to_floatx80(ldfq_p(mem_buf), &s);
> return 8;
> }
> - if (n < 11) {
> - /* FP control registers (not implemented) */
> + switch (n) {
> + case 8: /* fpcontrol */
> + env->fpcr = ldl_p(mem_buf);
> + return 4;
Should use cpu_m68k_set_fpcr.
> +DEF_HELPER_2(set_fpcr, void, env, i32)
Hmm. I suppose the write to env->fpcr means you can't indicate
TCG_CALL_NO_RWG. I wonder if it's better as
uint32_t HELPER(set_fpcr)(CPUM68KState *env, uint32_t val)
{
cpu_m68k_set_fpcr(env, val);
return env->fpcr;
}
DEF_HELPER_FLAGS_2(set_fpcr, i32, env, i32)
gen_helper_set_fpcr(QEMU_FPCR, cpu_env, val);
This skirts the rules of TCG, but it'll work, since we disguise the (incorrect)
write to env->fpcr with a (correct but redundant) write to QEMU_FPCR.
Any time we can avoid spilling all globals we're better off.
As an alternative, is it really that important to represent FPSR and FPCR as
tcg registers? Perhaps it's better to just tcg_gen_ld/st instead?
r~
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally
2017-06-19 21:03 ` Laurent Vivier
@ 2017-06-19 21:42 ` Laurent Vivier
2017-06-19 22:04 ` Richard Henderson
0 siblings, 1 reply; 18+ messages in thread
From: Laurent Vivier @ 2017-06-19 21:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aurelien Jarno
Le 19/06/2017 à 23:03, Laurent Vivier a écrit :
> Le 19/06/2017 à 22:53, Richard Henderson a écrit :
>>
>> It would also make me happier if we were to adjust the definition of
>> fl0atx80 to more closely match m68k and those missing zeros. Shouldn't
>> real hardware move instructions propagate those middle 2 bytes
>> regardless of contents?
>>
>> Perhaps something like
>>
>> #ifdef TARGET_M68K
>> typedef struct {
>> uint64_t low;
>> union {
>> uin32_t high32;
>> struct {
>> #ifdef HOST_WORDS_BIGENDIAN
>> uint16_t high, zero;
>> #else
>> uint16_t zero, high;
>> #endif
>> };
>> };
>> } floatx80;
>> #else
>> ...
>> #endif
>>
>> (with a minor fix to make_floatx80 to use named initializers).
>>
>> Then you can use full 32-bit store insns when copying data here. Which
>> also allows you to drop some of the shifts you're needing to add.
>
> OK, I will.
The softfloat is in the target independent code, so we can't adjust the
size of floatx80 by target, TARGET_XXXX are poisoned when used in
softfloat.h.
Laurent
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally
2017-06-19 21:42 ` Laurent Vivier
@ 2017-06-19 22:04 ` Richard Henderson
0 siblings, 0 replies; 18+ messages in thread
From: Richard Henderson @ 2017-06-19 22:04 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Aurelien Jarno
On 06/19/2017 02:42 PM, Laurent Vivier wrote:
> Le 19/06/2017 à 23:03, Laurent Vivier a écrit :
>> Le 19/06/2017 à 22:53, Richard Henderson a écrit :
>>>
>>> It would also make me happier if we were to adjust the definition of
>>> fl0atx80 to more closely match m68k and those missing zeros. Shouldn't
>>> real hardware move instructions propagate those middle 2 bytes
>>> regardless of contents?
>>>
>>> Perhaps something like
>>>
>>> #ifdef TARGET_M68K
>>> typedef struct {
>>> uint64_t low;
>>> union {
>>> uin32_t high32;
>>> struct {
>>> #ifdef HOST_WORDS_BIGENDIAN
>>> uint16_t high, zero;
>>> #else
>>> uint16_t zero, high;
>>> #endif
>>> };
>>> };
>>> } floatx80;
>>> #else
>>> ...
>>> #endif
>>>
>>> (with a minor fix to make_floatx80 to use named initializers).
>>>
>>> Then you can use full 32-bit store insns when copying data here. Which
>>> also allows you to drop some of the shifts you're needing to add.
>>
>> OK, I will.
>
> The softfloat is in the target independent code, so we can't adjust the
> size of floatx80 by target, TARGET_XXXX are poisoned when used in
> softfloat.h.
Ouch. That means we'd have to add a full set of floatx96.
If you don't want to do that now, I'd understand. I'd prefer that you issue an
undefined opcode exception or something for the packed decimals though, rather
than just silently dropping 2 bytes of data.
I suppose a first go at floatx96 would be just to thunk the data and call to
the floatx80 routines. I do seem to recall that a Proper implementation would
treat m68k un-normals different from x86.
r~
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2017-06-19 22:04 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-11 23:16 [Qemu-devel] [PATCH v4 0/7] target-m68k: implement 680x0 FPU Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 1/7] softfloat: define 680x0 specific values Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 2/7] target-m68k: move FPU helpers to fpu_helper.c Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 3/7] target-m68k: define ext_opsize Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 4/7] target-m68k: move fmove CR to a function Laurent Vivier
2017-06-12 16:13 ` Richard Henderson
2017-06-12 17:56 ` Laurent Vivier
2017-06-12 18:37 ` Richard Henderson
2017-06-12 19:12 ` Philippe Mathieu-Daudé
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 5/7] target-m68k: use floatx80 internally Laurent Vivier
2017-06-13 4:48 ` Thomas Huth
2017-06-19 20:53 ` Richard Henderson
2017-06-19 21:03 ` Laurent Vivier
2017-06-19 21:42 ` Laurent Vivier
2017-06-19 22:04 ` Richard Henderson
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 6/7] target-m68k: define 96bit FP registers for gdb on 680x0 Laurent Vivier
2017-06-11 23:16 ` [Qemu-devel] [PATCH v4 7/7] target-m68k: add FPCR and FPSR Laurent Vivier
2017-06-19 21:16 ` Richard Henderson
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