* [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E
@ 2020-12-01 19:28 Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 1/6] linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() body Philippe Mathieu-Daudé
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 19:28 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Laurent Vivier, Aurelien Jarno, Meng Zhuo
Missing review: #4
Since v2:
- Use extract32() in GET_FEATURE_REG_EQU (rth)
Introduce the GET_FEATURE_REG_SET() and GET_FEATURE_REG_EQU()
macros to check if an instruction set is supported by a CPU
using CP0 read-only bits (instead of QEMU insn_flags which
is not always coherent - we might remove it soon).
Use these macros to test for MSA ASE and Release 6.
Update the ELF HWCAP bits and set the Loongson instructions
so we can run 2F/3E userland binaries.
Philippe Mathieu-Daudé (6):
linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() body
linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN()
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro
linux-user/elfload: Update HWCAP bits from linux 5.7
linux-user: Add support for MIPS Loongson 2F/3E
linux-user/elfload.c | 42 +++++++++++++++++++++++++++++++++++-------
1 file changed, 35 insertions(+), 7 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/6] linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() body
2020-12-01 19:28 [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E Philippe Mathieu-Daudé
@ 2020-12-01 19:28 ` Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 2/6] linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN() Philippe Mathieu-Daudé
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 19:28 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Laurent Vivier, Aurelien Jarno, Meng Zhuo
As we are going to add more macros, keep the function body clear.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/elfload.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 0b02a926025..aae28fd929d 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -989,22 +989,22 @@ enum {
#define ELF_HWCAP get_elf_hwcap()
+#define GET_FEATURE(_flag, _hwcap) \
+ do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0)
+
static uint32_t get_elf_hwcap(void)
{
MIPSCPU *cpu = MIPS_CPU(thread_cpu);
uint32_t hwcaps = 0;
-#define GET_FEATURE(flag, hwcap) \
- do { if (cpu->env.insn_flags & (flag)) { hwcaps |= hwcap; } } while (0)
-
GET_FEATURE(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA);
-#undef GET_FEATURE
-
return hwcaps;
}
+#undef GET_FEATURE
+
#endif /* TARGET_MIPS */
#ifdef TARGET_MICROBLAZE
--
2.26.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/6] linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN()
2020-12-01 19:28 [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 1/6] linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() body Philippe Mathieu-Daudé
@ 2020-12-01 19:28 ` Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 3/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro Philippe Mathieu-Daudé
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 19:28 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Laurent Vivier, Aurelien Jarno, Meng Zhuo
We want to add macros similar to GET_FEATURE().
As this one use the 'insn_flags' field, rename it
GET_FEATURE_INSN().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/elfload.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index aae28fd929d..0e1d7e7677c 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -989,7 +989,7 @@ enum {
#define ELF_HWCAP get_elf_hwcap()
-#define GET_FEATURE(_flag, _hwcap) \
+#define GET_FEATURE_INSN(_flag, _hwcap) \
do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0)
static uint32_t get_elf_hwcap(void)
@@ -997,13 +997,13 @@ static uint32_t get_elf_hwcap(void)
MIPSCPU *cpu = MIPS_CPU(thread_cpu);
uint32_t hwcaps = 0;
- GET_FEATURE(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
- GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA);
+ GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
+ GET_FEATURE_INSN(ASE_MSA, HWCAP_MIPS_MSA);
return hwcaps;
}
-#undef GET_FEATURE
+#undef GET_FEATURE_INSN
#endif /* TARGET_MIPS */
--
2.26.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 3/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro
2020-12-01 19:28 [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 1/6] linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() body Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 2/6] linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN() Philippe Mathieu-Daudé
@ 2020-12-01 19:28 ` Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro Philippe Mathieu-Daudé
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 19:28 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Laurent Vivier, Aurelien Jarno, Meng Zhuo
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_SET() macro which
checks if a CPU register has bits set.
Use the macro to check for MSA (which sets the MSAP bit of
the Config3 register when the ASE implementation is present).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/elfload.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 0e1d7e7677c..b7c6d30723a 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -992,17 +992,21 @@ enum {
#define GET_FEATURE_INSN(_flag, _hwcap) \
do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0)
+#define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \
+ do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0)
+
static uint32_t get_elf_hwcap(void)
{
MIPSCPU *cpu = MIPS_CPU(thread_cpu);
uint32_t hwcaps = 0;
GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
- GET_FEATURE_INSN(ASE_MSA, HWCAP_MIPS_MSA);
+ GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
return hwcaps;
}
+#undef GET_FEATURE_REG_SET
#undef GET_FEATURE_INSN
#endif /* TARGET_MIPS */
--
2.26.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro
2020-12-01 19:28 [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-12-01 19:28 ` [PATCH v3 3/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro Philippe Mathieu-Daudé
@ 2020-12-01 19:28 ` Philippe Mathieu-Daudé
2020-12-01 23:15 ` Richard Henderson
2020-12-01 19:28 ` [PATCH v3 5/6] linux-user/elfload: Update HWCAP bits from linux 5.7 Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E Philippe Mathieu-Daudé
5 siblings, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 19:28 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Laurent Vivier, Aurelien Jarno, Meng Zhuo
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_EQU() macro which
checks if a CPU register has bits set to a specific value.
Use the macro to check the 'Architecture Revision' level
of the Config0 register, which is '2' when the Release 6
ISA is implemented.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/elfload.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index b7c6d30723a..9c475fa5f70 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -7,6 +7,7 @@
#include "qemu.h"
#include "disas/disas.h"
+#include "qemu/bitops.h"
#include "qemu/path.h"
#include "qemu/queue.h"
#include "qemu/guest-random.h"
@@ -995,17 +996,25 @@ enum {
#define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \
do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0)
+#define GET_FEATURE_REG_EQU(_reg, _start, _length, _val, _hwcap) \
+ do { \
+ if (extract32(cpu->env._reg, (_start), (_length)) == (_val)) { \
+ hwcaps |= _hwcap; \
+ } \
+ } while (0)
+
static uint32_t get_elf_hwcap(void)
{
MIPSCPU *cpu = MIPS_CPU(thread_cpu);
uint32_t hwcaps = 0;
- GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
+ GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
return hwcaps;
}
+#undef GET_FEATURE_REG_EQU
#undef GET_FEATURE_REG_SET
#undef GET_FEATURE_INSN
--
2.26.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 5/6] linux-user/elfload: Update HWCAP bits from linux 5.7
2020-12-01 19:28 [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-12-01 19:28 ` [PATCH v3 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro Philippe Mathieu-Daudé
@ 2020-12-01 19:28 ` Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E Philippe Mathieu-Daudé
5 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 19:28 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Laurent Vivier, Aurelien Jarno, Meng Zhuo
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/elfload.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 9c475fa5f70..2ba42d8e4bd 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -986,6 +986,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMIPSState *e
enum {
HWCAP_MIPS_R6 = (1 << 0),
HWCAP_MIPS_MSA = (1 << 1),
+ HWCAP_MIPS_CRC32 = (1 << 2),
+ HWCAP_MIPS_MIPS16 = (1 << 3),
+ HWCAP_MIPS_MDMX = (1 << 4),
+ HWCAP_MIPS_MIPS3D = (1 << 5),
+ HWCAP_MIPS_SMARTMIPS = (1 << 6),
+ HWCAP_MIPS_DSP = (1 << 7),
+ HWCAP_MIPS_DSP2 = (1 << 8),
+ HWCAP_MIPS_DSP3 = (1 << 9),
+ HWCAP_MIPS_MIPS16E2 = (1 << 10),
+ HWCAP_LOONGSON_MMI = (1 << 11),
+ HWCAP_LOONGSON_EXT = (1 << 12),
+ HWCAP_LOONGSON_EXT2 = (1 << 13),
+ HWCAP_LOONGSON_CPUCFG = (1 << 14),
};
#define ELF_HWCAP get_elf_hwcap()
--
2.26.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E
2020-12-01 19:28 [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2020-12-01 19:28 ` [PATCH v3 5/6] linux-user/elfload: Update HWCAP bits from linux 5.7 Philippe Mathieu-Daudé
@ 2020-12-01 19:28 ` Philippe Mathieu-Daudé
2020-12-02 1:01 ` chen huacai
5 siblings, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 19:28 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Laurent Vivier, Aurelien Jarno, Meng Zhuo
Userland ELF binaries using Longsoon SIMD instructions have the
HWCAP_LOONGSON_MMI bit set [1].
Binaries compiled for Longsoon 3E [2] have the HWCAP_LOONGSON_EXT
bit set for the LQ / SQ instructions.
[1] commit 8e2d5831e4b ("target/mips: Legalize Loongson insn flags")
[2] commit af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/elfload.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 2ba42d8e4bd..5a39a7dc021 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1023,6 +1023,8 @@ static uint32_t get_elf_hwcap(void)
GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
+ GET_FEATURE_INSN(ASE_LMMI, HWCAP_LOONGSON_MMI);
+ GET_FEATURE_INSN(ASE_LEXT, HWCAP_LOONGSON_EXT);
return hwcaps;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro
2020-12-01 19:28 ` [PATCH v3 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro Philippe Mathieu-Daudé
@ 2020-12-01 23:15 ` Richard Henderson
2020-12-02 9:29 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 12+ messages in thread
From: Richard Henderson @ 2020-12-01 23:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Laurent Vivier, Aurelien Jarno, Meng Zhuo
On 12/1/20 1:28 PM, Philippe Mathieu-Daudé wrote:
> ISA features are usually denoted in read-only bits from
> CPU registers. Add the GET_FEATURE_REG_EQU() macro which
> checks if a CPU register has bits set to a specific value.
>
> Use the macro to check the 'Architecture Revision' level
> of the Config0 register, which is '2' when the Release 6
> ISA is implemented.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> linux-user/elfload.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index b7c6d30723a..9c475fa5f70 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -7,6 +7,7 @@
>
> #include "qemu.h"
> #include "disas/disas.h"
> +#include "qemu/bitops.h"
> #include "qemu/path.h"
> #include "qemu/queue.h"
> #include "qemu/guest-random.h"
> @@ -995,17 +996,25 @@ enum {
> #define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \
> do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0)
>
> +#define GET_FEATURE_REG_EQU(_reg, _start, _length, _val, _hwcap) \
> + do { \
> + if (extract32(cpu->env._reg, (_start), (_length)) == (_val)) { \
> + hwcaps |= _hwcap; \
> + } \
> + } while (0)
> +
> static uint32_t get_elf_hwcap(void)
> {
> MIPSCPU *cpu = MIPS_CPU(thread_cpu);
> uint32_t hwcaps = 0;
>
> - GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
> + GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
You still get the magic 3.
This is where hw/registerfields.h would come in handy. But that is certainly a
large change to mips' cpu.h. So I guess this is good enough for now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E
2020-12-01 19:28 ` [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E Philippe Mathieu-Daudé
@ 2020-12-02 1:01 ` chen huacai
2020-12-02 9:16 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 12+ messages in thread
From: chen huacai @ 2020-12-02 1:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Aleksandar Rikalo, Richard Henderson, qemu-level, Laurent Vivier,
Meng Zhuo, Huacai Chen, Aurelien Jarno
Hi, Philippe,
On Wed, Dec 2, 2020 at 3:31 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Userland ELF binaries using Longsoon SIMD instructions have the
> HWCAP_LOONGSON_MMI bit set [1].
> Binaries compiled for Longsoon 3E [2] have the HWCAP_LOONGSON_EXT
> bit set for the LQ / SQ instructions.
What is Loongson-3E? I think you want to say Loongson-3A?
Huacai
>
> [1] commit 8e2d5831e4b ("target/mips: Legalize Loongson insn flags")
> [2] commit af868995e1b ("target/mips: Add Loongson-3 CPU definition")
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> linux-user/elfload.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 2ba42d8e4bd..5a39a7dc021 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1023,6 +1023,8 @@ static uint32_t get_elf_hwcap(void)
>
> GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
> GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
> + GET_FEATURE_INSN(ASE_LMMI, HWCAP_LOONGSON_MMI);
> + GET_FEATURE_INSN(ASE_LEXT, HWCAP_LOONGSON_EXT);
>
> return hwcaps;
> }
> --
> 2.26.2
>
>
--
Huacai Chen
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E
2020-12-02 1:01 ` chen huacai
@ 2020-12-02 9:16 ` Philippe Mathieu-Daudé
2020-12-03 3:13 ` chen huacai
0 siblings, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-02 9:16 UTC (permalink / raw)
To: chen huacai
Cc: Aleksandar Rikalo, Richard Henderson, qemu-level, Laurent Vivier,
Aurelien Jarno, Huacai Chen, Meng Zhuo
On 12/2/20 2:01 AM, chen huacai wrote:
> Hi, Philippe,
>
> On Wed, Dec 2, 2020 at 3:31 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> Userland ELF binaries using Longsoon SIMD instructions have the
>> HWCAP_LOONGSON_MMI bit set [1].
>> Binaries compiled for Longsoon 3E [2] have the HWCAP_LOONGSON_EXT
>> bit set for the LQ / SQ instructions.
> What is Loongson-3E? I think you want to say Loongson-3A?
Yes =) I have been confused because I looked at the INSN_LOONGSON2E
and INSN_LOONGSON2F definitions earlier.
Are you OK with this patch if I change
- 3E -> 3A in subject and body
- Longsoon -> Loongson in body?
As you maybe noticed, since Loongson is currently the single MIPS
area with contributions, I am trying to strengthen it and ease its
maintenance by adding (and running) more tests.
>
> Huacai
>>
>> [1] commit 8e2d5831e4b ("target/mips: Legalize Loongson insn flags")
>> [2] commit af868995e1b ("target/mips: Add Loongson-3 CPU definition")
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> linux-user/elfload.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
>> index 2ba42d8e4bd..5a39a7dc021 100644
>> --- a/linux-user/elfload.c
>> +++ b/linux-user/elfload.c
>> @@ -1023,6 +1023,8 @@ static uint32_t get_elf_hwcap(void)
>>
>> GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
>> GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
>> + GET_FEATURE_INSN(ASE_LMMI, HWCAP_LOONGSON_MMI);
>> + GET_FEATURE_INSN(ASE_LEXT, HWCAP_LOONGSON_EXT);
>>
>> return hwcaps;
>> }
>> --
>> 2.26.2
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro
2020-12-01 23:15 ` Richard Henderson
@ 2020-12-02 9:29 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-02 9:29 UTC (permalink / raw)
To: Richard Henderson, Jiaxun Yang, qemu-devel, Huacai Chen
Cc: Aleksandar Rikalo, Laurent Vivier, Aurelien Jarno, Meng Zhuo
On 12/2/20 12:15 AM, Richard Henderson wrote:
> On 12/1/20 1:28 PM, Philippe Mathieu-Daudé wrote:
>> ISA features are usually denoted in read-only bits from
>> CPU registers. Add the GET_FEATURE_REG_EQU() macro which
>> checks if a CPU register has bits set to a specific value.
>>
>> Use the macro to check the 'Architecture Revision' level
>> of the Config0 register, which is '2' when the Release 6
>> ISA is implemented.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> linux-user/elfload.c | 11 ++++++++++-
>> 1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
>> index b7c6d30723a..9c475fa5f70 100644
>> --- a/linux-user/elfload.c
>> +++ b/linux-user/elfload.c
>> @@ -7,6 +7,7 @@
>>
>> #include "qemu.h"
>> #include "disas/disas.h"
>> +#include "qemu/bitops.h"
>> #include "qemu/path.h"
>> #include "qemu/queue.h"
>> #include "qemu/guest-random.h"
>> @@ -995,17 +996,25 @@ enum {
>> #define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \
>> do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0)
>>
>> +#define GET_FEATURE_REG_EQU(_reg, _start, _length, _val, _hwcap) \
>> + do { \
>> + if (extract32(cpu->env._reg, (_start), (_length)) == (_val)) { \
>> + hwcaps |= _hwcap; \
>> + } \
>> + } while (0)
>> +
>> static uint32_t get_elf_hwcap(void)
>> {
>> MIPSCPU *cpu = MIPS_CPU(thread_cpu);
>> uint32_t hwcaps = 0;
>>
>> - GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
>> + GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
>
> You still get the magic 3.
TBH:
$ wc -l target/mips/cpu.h
1323 target/mips/cpu.h
$ egrep _MASK target/mips/cpu.h | wc -l
19
And mask definitions are not useful to use with extract/deposit:
$ egrep _MASK target/mips/cpu.h
#define MSACSR_FS_MASK (1 << MSACSR_FS)
#define MSACSR_NX_MASK (1 << MSACSR_NX)
#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
#define CP0PM_MASK 13
#define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
#define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
#define CP0SC_EU_MASK (1ULL << CP0SC_EU)
#define CP0SC_C_MASK (0x7ULL << CP0SC_C)
...
If you rather I can amend this snippet:
-- >8 --
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 23f8c6f96cd..2639b0ea06c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -844,6 +844,7 @@ struct CPUMIPSState {
#define CP0C0_MT 7 /* 9..7 */
#define CP0C0_VI 3
#define CP0C0_K0 0 /* 2..0 */
+#define CP0C0_AR_LENGTH 3
int32_t CP0_Config1;
#define CP0C1_M 31
#define CP0C1_MMU 25 /* 30..25 */
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 5a39a7dc021..a64050713f2 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1021,7 +1021,8 @@ static uint32_t get_elf_hwcap(void)
MIPSCPU *cpu = MIPS_CPU(thread_cpu);
uint32_t hwcaps = 0;
- GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
+ GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, CP0C0_AR_LENGTH,
+ 2, HWCAP_MIPS_R6);
GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
GET_FEATURE_INSN(ASE_LMMI, HWCAP_LOONGSON_MMI);
GET_FEATURE_INSN(ASE_LEXT, HWCAP_LOONGSON_EXT);
---
> This is where hw/registerfields.h would come in handy. But that is certainly a
> large change to mips' cpu.h. So I guess this is good enough for now.
Yes, that is my preference too, and I plan to get there eventually
(this is on my TODO list). But from here to there is a long way...
First I'd get rid of the cpu->env.insn_flags duplications.
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Thanks!
Phil.
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E
2020-12-02 9:16 ` Philippe Mathieu-Daudé
@ 2020-12-03 3:13 ` chen huacai
0 siblings, 0 replies; 12+ messages in thread
From: chen huacai @ 2020-12-03 3:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Aleksandar Rikalo, Richard Henderson, qemu-level, Laurent Vivier,
Aurelien Jarno, Huacai Chen, Meng Zhuo
Hi, Philippe,
On Wed, Dec 2, 2020 at 5:16 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 12/2/20 2:01 AM, chen huacai wrote:
> > Hi, Philippe,
> >
> > On Wed, Dec 2, 2020 at 3:31 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >>
> >> Userland ELF binaries using Longsoon SIMD instructions have the
> >> HWCAP_LOONGSON_MMI bit set [1].
> >> Binaries compiled for Longsoon 3E [2] have the HWCAP_LOONGSON_EXT
> >> bit set for the LQ / SQ instructions.
> > What is Loongson-3E? I think you want to say Loongson-3A?
>
> Yes =) I have been confused because I looked at the INSN_LOONGSON2E
> and INSN_LOONGSON2F definitions earlier.
>
> Are you OK with this patch if I change
> - 3E -> 3A in subject and body
> - Longsoon -> Loongson in body?
That's OK.
Huacai
>
> As you maybe noticed, since Loongson is currently the single MIPS
> area with contributions, I am trying to strengthen it and ease its
> maintenance by adding (and running) more tests.
>
> >
> > Huacai
> >>
> >> [1] commit 8e2d5831e4b ("target/mips: Legalize Loongson insn flags")
> >> [2] commit af868995e1b ("target/mips: Add Loongson-3 CPU definition")
> >>
> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> >> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> >> ---
> >> linux-user/elfload.c | 2 ++
> >> 1 file changed, 2 insertions(+)
> >>
> >> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> >> index 2ba42d8e4bd..5a39a7dc021 100644
> >> --- a/linux-user/elfload.c
> >> +++ b/linux-user/elfload.c
> >> @@ -1023,6 +1023,8 @@ static uint32_t get_elf_hwcap(void)
> >>
> >> GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, 3, 2, HWCAP_MIPS_R6);
> >> GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
> >> + GET_FEATURE_INSN(ASE_LMMI, HWCAP_LOONGSON_MMI);
> >> + GET_FEATURE_INSN(ASE_LEXT, HWCAP_LOONGSON_EXT);
> >>
> >> return hwcaps;
> >> }
> >> --
> >> 2.26.2
> >
--
Huacai Chen
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-12-03 3:14 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-01 19:28 [PATCH v3 0/6] linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 1/6] linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() body Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 2/6] linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN() Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 3/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro Philippe Mathieu-Daudé
2020-12-01 23:15 ` Richard Henderson
2020-12-02 9:29 ` Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 5/6] linux-user/elfload: Update HWCAP bits from linux 5.7 Philippe Mathieu-Daudé
2020-12-01 19:28 ` [PATCH v3 6/6] linux-user: Add support for MIPS Loongson 2F/3E Philippe Mathieu-Daudé
2020-12-02 1:01 ` chen huacai
2020-12-02 9:16 ` Philippe Mathieu-Daudé
2020-12-03 3:13 ` chen huacai
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