* [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type
@ 2020-02-07 22:50 kbuild test robot
2020-02-09 16:20 ` Liang, Kan
0 siblings, 1 reply; 6+ messages in thread
From: kbuild test robot @ 2020-02-07 22:50 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2134 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/core
head: 60291b1620ac0b5d07624290a0ce909a0b09863e
commit: 60291b1620ac0b5d07624290a0ce909a0b09863e [10/10] perf/x86: Add Intel Tiger Lake uncore support
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.5.0-3) 7.5.0
reproduce:
git checkout 60291b1620ac0b5d07624290a0ce909a0b09863e
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
arch/x86/events/intel/uncore_snb.c: In function 'tgl_uncore_imc_freerunning_init_box':
>> arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type [-Wshift-count-overflow]
addr |= ((resource_size_t)mch_bar << 32);
^~
vim +1111 arch/x86/events/intel/uncore_snb.c
1088
1089 static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
1090 {
1091 struct pci_dev *pdev = tgl_uncore_get_mc_dev();
1092 struct intel_uncore_pmu *pmu = box->pmu;
1093 resource_size_t addr;
1094 u32 mch_bar;
1095
1096 if (!pdev) {
1097 pr_warn("perf uncore: Cannot find matched IMC device.\n");
1098 return;
1099 }
1100
1101 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &mch_bar);
1102 /* MCHBAR is disabled */
1103 if (!(mch_bar & BIT(0))) {
1104 pr_warn("perf uncore: MCHBAR is disabled. Failed to map IMC free-running counters.\n");
1105 return;
1106 }
1107 mch_bar &= ~BIT(0);
1108 addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET * pmu->pmu_idx);
1109
1110 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
> 1111 addr |= ((resource_size_t)mch_bar << 32);
1112
1113 box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
1114 }
1115
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 70349 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type
2020-02-07 22:50 [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type kbuild test robot
@ 2020-02-09 16:20 ` Liang, Kan
2020-02-10 8:47 ` Peter Zijlstra
2020-02-10 17:15 ` Andi Kleen
0 siblings, 2 replies; 6+ messages in thread
From: Liang, Kan @ 2020-02-09 16:20 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3242 bytes --]
On 2/7/2020 5:50 PM, kbuild test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/core
> head: 60291b1620ac0b5d07624290a0ce909a0b09863e
> commit: 60291b1620ac0b5d07624290a0ce909a0b09863e [10/10] perf/x86: Add Intel Tiger Lake uncore support
> config: i386-allyesconfig (attached as .config)
> compiler: gcc-7 (Debian 7.5.0-3) 7.5.0
> reproduce:
> git checkout 60291b1620ac0b5d07624290a0ce909a0b09863e
> # save the attached .config to linux build tree
> make ARCH=i386
>
> If you fix the issue, kindly add following tag
> Reported-by: kbuild test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> arch/x86/events/intel/uncore_snb.c: In function 'tgl_uncore_imc_freerunning_init_box':
>>> arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type [-Wshift-count-overflow]
> addr |= ((resource_size_t)mch_bar << 32);
> ^~
>
The patch as below should fix the warning. But I didn't do any test with
32 bit OS. I'm not sure if we still support 32 bit.
Peter, could you please let me know if I should submit a separate patch
to fix the warning?
diff --git a/arch/x86/events/intel/uncore_snb.c
b/arch/x86/events/intel/uncore_snb.c
index ab67b23b2106..3de1065eefc4 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -1107,8 +1107,10 @@ static void
tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
mch_bar &= ~BIT(0);
addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET *
pmu->pmu_idx);
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
addr |= ((resource_size_t)mch_bar << 32);
+#endif
box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
}
Thanks,
Kan
> vim +1111 arch/x86/events/intel/uncore_snb.c
>
> 1088
> 1089 static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
> 1090 {
> 1091 struct pci_dev *pdev = tgl_uncore_get_mc_dev();
> 1092 struct intel_uncore_pmu *pmu = box->pmu;
> 1093 resource_size_t addr;
> 1094 u32 mch_bar;
> 1095
> 1096 if (!pdev) {
> 1097 pr_warn("perf uncore: Cannot find matched IMC device.\n");
> 1098 return;
> 1099 }
> 1100
> 1101 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &mch_bar);
> 1102 /* MCHBAR is disabled */
> 1103 if (!(mch_bar & BIT(0))) {
> 1104 pr_warn("perf uncore: MCHBAR is disabled. Failed to map IMC free-running counters.\n");
> 1105 return;
> 1106 }
> 1107 mch_bar &= ~BIT(0);
> 1108 addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET * pmu->pmu_idx);
> 1109
> 1110 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
>> 1111 addr |= ((resource_size_t)mch_bar << 32);
> 1112
> 1113 box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
> 1114 }
> 1115
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
>
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type
2020-02-09 16:20 ` Liang, Kan
@ 2020-02-10 8:47 ` Peter Zijlstra
2020-02-10 13:14 ` Liang, Kan
2020-02-10 17:15 ` Andi Kleen
1 sibling, 1 reply; 6+ messages in thread
From: Peter Zijlstra @ 2020-02-10 8:47 UTC (permalink / raw)
To: kbuild-all
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On Sun, Feb 09, 2020 at 11:20:38AM -0500, Liang, Kan wrote:
>
>
> On 2/7/2020 5:50 PM, kbuild test robot wrote:
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/core
> > head: 60291b1620ac0b5d07624290a0ce909a0b09863e
> > commit: 60291b1620ac0b5d07624290a0ce909a0b09863e [10/10] perf/x86: Add Intel Tiger Lake uncore support
> > config: i386-allyesconfig (attached as .config)
> > compiler: gcc-7 (Debian 7.5.0-3) 7.5.0
> > reproduce:
> > git checkout 60291b1620ac0b5d07624290a0ce909a0b09863e
> > # save the attached .config to linux build tree
> > make ARCH=i386
> >
> > If you fix the issue, kindly add following tag
> > Reported-by: kbuild test robot <lkp@intel.com>
> >
> > All warnings (new ones prefixed by >>):
> >
> > arch/x86/events/intel/uncore_snb.c: In function 'tgl_uncore_imc_freerunning_init_box':
> > > > arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type [-Wshift-count-overflow]
> > addr |= ((resource_size_t)mch_bar << 32);
> > ^~
> >
>
> The patch as below should fix the warning. But I didn't do any test with 32
> bit OS. I'm not sure if we still support 32 bit.
Of course we do. The compiler just told you.
Now, personally I'd _love_ it if we were to just delete the entire 32bit
x86 code, but last time we proposed that Linus wasn't convinced to put
it mildly.
Now, if you can get an official Intel statement that Intel no longer
cares about 32bit, that's be awesome. But last I checked we were
actually still selling 32bit only parts :-/
> Peter, could you please let me know if I should submit a separate patch to
> fix the warning?
>
> diff --git a/arch/x86/events/intel/uncore_snb.c
> b/arch/x86/events/intel/uncore_snb.c
> index ab67b23b2106..3de1065eefc4 100644
> --- a/arch/x86/events/intel/uncore_snb.c
> +++ b/arch/x86/events/intel/uncore_snb.c
> @@ -1107,8 +1107,10 @@ static void
> tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
> mch_bar &= ~BIT(0);
> addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET *
> pmu->pmu_idx);
>
> +#ifdef CONFIG_PHYS_ADDR_T_64BIT
> pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
> addr |= ((resource_size_t)mch_bar << 32);
> +#endif
>
> box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
> }
Let me frob that in and see what it does.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type
2020-02-10 8:47 ` Peter Zijlstra
@ 2020-02-10 13:14 ` Liang, Kan
0 siblings, 0 replies; 6+ messages in thread
From: Liang, Kan @ 2020-02-10 13:14 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2690 bytes --]
On 2/10/2020 3:47 AM, Peter Zijlstra wrote:
> On Sun, Feb 09, 2020 at 11:20:38AM -0500, Liang, Kan wrote:
>>
>>
>> On 2/7/2020 5:50 PM, kbuild test robot wrote:
>>> tree: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/core
>>> head: 60291b1620ac0b5d07624290a0ce909a0b09863e
>>> commit: 60291b1620ac0b5d07624290a0ce909a0b09863e [10/10] perf/x86: Add Intel Tiger Lake uncore support
>>> config: i386-allyesconfig (attached as .config)
>>> compiler: gcc-7 (Debian 7.5.0-3) 7.5.0
>>> reproduce:
>>> git checkout 60291b1620ac0b5d07624290a0ce909a0b09863e
>>> # save the attached .config to linux build tree
>>> make ARCH=i386
>>>
>>> If you fix the issue, kindly add following tag
>>> Reported-by: kbuild test robot <lkp@intel.com>
>>>
>>> All warnings (new ones prefixed by >>):
>>>
>>> arch/x86/events/intel/uncore_snb.c: In function 'tgl_uncore_imc_freerunning_init_box':
>>>>> arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type [-Wshift-count-overflow]
>>> addr |= ((resource_size_t)mch_bar << 32);
>>> ^~
>>>
>>
>> The patch as below should fix the warning. But I didn't do any test with 32
>> bit OS. I'm not sure if we still support 32 bit.
>
> Of course we do. The compiler just told you.
>
> Now, personally I'd _love_ it if we were to just delete the entire 32bit
> x86 code, but last time we proposed that Linus wasn't convinced to put
> it mildly.
>
> Now, if you can get an official Intel statement that Intel no longer
> cares about 32bit, that's be awesome. But last I checked we were
> actually still selling 32bit only parts :-/
>
>> Peter, could you please let me know if I should submit a separate patch to
>> fix the warning?
>>
>> diff --git a/arch/x86/events/intel/uncore_snb.c
>> b/arch/x86/events/intel/uncore_snb.c
>> index ab67b23b2106..3de1065eefc4 100644
>> --- a/arch/x86/events/intel/uncore_snb.c
>> +++ b/arch/x86/events/intel/uncore_snb.c
>> @@ -1107,8 +1107,10 @@ static void
>> tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
>> mch_bar &= ~BIT(0);
>> addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET *
>> pmu->pmu_idx);
>>
>> +#ifdef CONFIG_PHYS_ADDR_T_64BIT
>> pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
>> addr |= ((resource_size_t)mch_bar << 32);
>> +#endif
>>
>> box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
>> }
>
> Let me frob that in and see what it does.
>
Thanks. If there is anything I need to do, please let me know.
Thanks,
Kan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type
2020-02-09 16:20 ` Liang, Kan
2020-02-10 8:47 ` Peter Zijlstra
@ 2020-02-10 17:15 ` Andi Kleen
2020-02-10 18:23 ` Liang, Kan
1 sibling, 1 reply; 6+ messages in thread
From: Andi Kleen @ 2020-02-10 17:15 UTC (permalink / raw)
To: kbuild-all
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>
> +#ifdef CONFIG_PHYS_ADDR_T_64BIT
> pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
> addr |= ((resource_size_t)mch_bar << 32);
> +#endif
Should really have a generic helper for this.
I'm sure other drivers have the same problem.
-Andi
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type
2020-02-10 17:15 ` Andi Kleen
@ 2020-02-10 18:23 ` Liang, Kan
0 siblings, 0 replies; 6+ messages in thread
From: Liang, Kan @ 2020-02-10 18:23 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 641 bytes --]
On 2/10/2020 12:15 PM, Andi Kleen wrote:
>>
>> +#ifdef CONFIG_PHYS_ADDR_T_64BIT
>> pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
>> addr |= ((resource_size_t)mch_bar << 32);
>> +#endif
>
> Should really have a generic helper for this.
>
> I'm sure other drivers have the same problem.
The server uncore doesn't need to shift left 32. The warning should not
be triggered for server uncore.
Since both server and client uncore start to support MMIO type of uncore
unit, yes, a generic helper for mmio_init_box() looks better.
I will submit a clean up patch later.
Thanks,
Kan
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-02-10 18:23 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-02-07 22:50 [peterz-queue:perf/core 10/10] arch/x86/events/intel/uncore_snb.c:1111:36: warning: left shift count >= width of type kbuild test robot
2020-02-09 16:20 ` Liang, Kan
2020-02-10 8:47 ` Peter Zijlstra
2020-02-10 13:14 ` Liang, Kan
2020-02-10 17:15 ` Andi Kleen
2020-02-10 18:23 ` Liang, Kan
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