[Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.

[Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.

[He Chen]

From: Luwei Kang <luwei.kang@intel.com>

The spec can be found in Intel Software Developer Manual or in
Instruction Set Extensions Programming Reference.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Piotr Luc <piotr.luc@intel.com>

---
Changes in v2:
* correct TCG_7_0_EDX_FEATURES.
---
 target-i386/cpu.c | 19 ++++++++++++++++++-
 target-i386/cpu.h |  4 ++++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 83998a8..245db9c 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -239,6 +239,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
           CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
           CPUID_7_0_EBX_RDSEED */
 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
+#define TCG_7_0_EDX_FEATURES 0
 #define TCG_APM_FEATURES 0
 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
@@ -444,6 +445,22 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .cpuid_reg = R_ECX,
         .tcg_features = TCG_7_0_ECX_FEATURES,
     },
+    [FEAT_7_0_EDX] = {
+        .feat_names = {
+            NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+        },
+        .cpuid_eax = 7,
+        .cpuid_needs_ecx = true, .cpuid_ecx = 0,
+        .cpuid_reg = R_EDX,
+        .tcg_features = TCG_7_0_EDX_FEATURES,
+    },
     [FEAT_8000_0007_EDX] = {
         .feat_names = {
             NULL, NULL, NULL, NULL,
@@ -2536,7 +2553,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
             if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
                 *ecx |= CPUID_7_0_ECX_OSPKE;
             }
-            *edx = 0; /* Reserved */
+            *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
         } else {
             *eax = 0;
             *ebx = 0;
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 6303d65..c605724 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -443,6 +443,7 @@ typedef enum FeatureWord {
     FEAT_1_ECX,         /* CPUID[1].ECX */
     FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
     FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
+    FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
     FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
     FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
@@ -629,6 +630,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_ECX_OSPKE    (1U << 4)
 #define CPUID_7_0_ECX_RDPID    (1U << 22)
 
+#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
+#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
+
 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
 #define CPUID_XSAVE_XSAVEC     (1U << 1)
 #define CPUID_XSAVE_XGETBV1    (1U << 2)
-- 
2.7.4

Re: [Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.

[no-reply]

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.
Message-id: 1477902446-5932-1-git-send-email-he.chen@linux.intel.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/1477825928-10803-1-git-send-email-david@gibson.dropbear.id.au -> patchew/1477825928-10803-1-git-send-email-david@gibson.dropbear.id.au
 * [new tag]         patchew/1477902446-5932-1-git-send-email-he.chen@linux.intel.com -> patchew/1477902446-5932-1-git-send-email-he.chen@linux.intel.com
Switched to a new branch 'test'
058e5e6 x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.

=== OUTPUT BEGIN ===
fatal: unrecognized argument: --no-patch
Checking PATCH 1/1: ...
WARNING: line over 80 characters
#74: FILE: target-i386/cpu.h:633:
+#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

ERROR: line over 90 characters
#75: FILE: target-i386/cpu.h:634:
+#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

total: 1 errors, 1 warnings, 53 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org

Re: [Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.

[Eduardo Habkost]

On Mon, Oct 31, 2016 at 04:27:26PM +0800, He Chen wrote:
> From: Luwei Kang <luwei.kang@intel.com>
> 
> The spec can be found in Intel Software Developer Manual or in
> Instruction Set Extensions Programming Reference.
> 
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> 
> ---
> Changes in v2:
> * correct TCG_7_0_EDX_FEATURES.

Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>

Applied to x86-next with the following fixup:

diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c605724..6c6f8ae 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -631,7 +631,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_ECX_RDPID    (1U << 22)
 
 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
-#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
+#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation
+                                               * Single Precision */
 
 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
 #define CPUID_XSAVE_XSAVEC     (1U << 1)

-- 
Eduardo

Re: [Qemu-devel] [PATCH v2] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.

[Paolo Bonzini]

On 31/10/2016 18:20, Eduardo Habkost wrote:
> On Mon, Oct 31, 2016 at 04:27:26PM +0800, He Chen wrote:
>> From: Luwei Kang <luwei.kang@intel.com>
>>
>> The spec can be found in Intel Software Developer Manual or in
>> Instruction Set Extensions Programming Reference.
>>
>> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
>> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
>>
>> ---
>> Changes in v2:
>> * correct TCG_7_0_EDX_FEATURES.
> 
> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
> 
> Applied to x86-next with the following fixup:

I have already sent a pull request for this patch, sorry.

Paolo

> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index c605724..6c6f8ae 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -631,7 +631,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>  #define CPUID_7_0_ECX_RDPID    (1U << 22)
>  
>  #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
> -#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
> +#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation
> +                                               * Single Precision */
>  
>  #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
>  #define CPUID_XSAVE_XSAVEC     (1U << 1)
>