* [Intel-gfx] [PATCH v2 01/11] drm/i915: WARN if plane src coords are too big
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-27 11:11 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: Limit plane stride to below TILEOFF.x limit Ville Syrjala
` (11 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Inform us if we're buggy and are about to exceed the size of the
bitfields in the plane TILEOFF/OFFSET registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 7 +++++++
drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b78985c855a5..b1158ce4df92 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -276,6 +276,13 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
}
}
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095);
+ } else if (INTEL_GEN(dev_priv) >= 4 &&
+ fb->modifier == I915_FORMAT_MOD_X_TILED) {
+ drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095);
+ }
+
plane_state->color_plane[0].offset = offset;
plane_state->color_plane[0].x = src_x;
plane_state->color_plane[0].y = src_y;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0189d379a55e..7735c28b2467 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3854,6 +3854,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
}
}
+ drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
+
plane_state->color_plane[0].offset = offset;
plane_state->color_plane[0].x = x;
plane_state->color_plane[0].y = y;
@@ -3926,6 +3928,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
}
}
+ drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
+
plane_state->color_plane[uv_plane].offset = offset;
plane_state->color_plane[uv_plane].x = x;
plane_state->color_plane[uv_plane].y = y;
--
2.26.2
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: WARN if plane src coords are too big
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: WARN if plane src coords are too big Ville Syrjala
@ 2021-01-27 11:11 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-27 11:11 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Inform us if we're buggy and are about to exceed the size of the
> bitfields in the plane TILEOFF/OFFSET registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 7 +++++++
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b78985c855a5..b1158ce4df92 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -276,6 +276,13 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> }
> }
>
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> + drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095);
> + } else if (INTEL_GEN(dev_priv) >= 4 &&
> + fb->modifier == I915_FORMAT_MOD_X_TILED) {
> + drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095);
> + }
> +
> plane_state->color_plane[0].offset = offset;
> plane_state->color_plane[0].x = src_x;
> plane_state->color_plane[0].y = src_y;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0189d379a55e..7735c28b2467 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3854,6 +3854,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> }
> }
>
> + drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
> +
> plane_state->color_plane[0].offset = offset;
> plane_state->color_plane[0].x = x;
> plane_state->color_plane[0].y = y;
> @@ -3926,6 +3928,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
> }
> }
>
> + drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
> +
> plane_state->color_plane[uv_plane].offset = offset;
> plane_state->color_plane[uv_plane].x = x;
> plane_state->color_plane[uv_plane].y = y;
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 02/11] drm/i915: Limit plane stride to below TILEOFF.x limit
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: WARN if plane src coords are too big Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-28 9:41 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Drop redundant parens Ville Syrjala
` (10 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Limit pre-skl plane stride to below 4k or 8k pixels (depending on
the platform). We do this in order guarantee that TILEOFF/OFFSET.x
does not get too big.
Currently this is not a problem as we align SURF to 4k, and so
TILEOFF/OFFSET only have to deal with a single tile's worth of
pixels. But for async flips we're going to have to bump SURF
alignment to 256k, and thus we can no longer guarantee
TILEOFF/OFFSET.x will stay within acceptable bounds. We can avoid
this by borrowing a trick from the skl+ code and limit the max
plane stride to whatever value we can fit into TILEOFF/OFFSET.x.
The slight downside is that we may end up doing GTT remapping in
a few more cases where previously we did not have to. But since
that will only happen with huge buffers I'm not really concerned
about it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 64 ++++++++++++++++++---
drivers/gpu/drm/i915/display/i9xx_plane.h | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++--
3 files changed, 83 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1158ce4df92..7d968ca890da 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -530,21 +530,56 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
+static unsigned int
+hsw_primary_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ const struct drm_format_info *info = drm_format_info(pixel_format);
+ int cpp = info->cpp[0];
+
+ /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
+ return min(8192 * cpp, 32 * 1024);
+}
+
+static unsigned int
+ilk_primary_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ const struct drm_format_info *info = drm_format_info(pixel_format);
+ int cpp = info->cpp[0];
+
+ /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
+ if (modifier == I915_FORMAT_MOD_X_TILED)
+ return min(4096 * cpp, 32 * 1024);
+ else
+ return 32 * 1024;
+}
+
unsigned int
+i965_plane_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ const struct drm_format_info *info = drm_format_info(pixel_format);
+ int cpp = info->cpp[0];
+
+ /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
+ if (modifier == I915_FORMAT_MOD_X_TILED)
+ return min(4096 * cpp, 16 * 1024);
+ else
+ return 32 * 1024;
+}
+
+static unsigned int
i9xx_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- if (!HAS_GMCH(dev_priv)) {
- return 32*1024;
- } else if (INTEL_GEN(dev_priv) >= 4) {
- if (modifier == I915_FORMAT_MOD_X_TILED)
- return 16*1024;
- else
- return 32*1024;
- } else if (INTEL_GEN(dev_priv) >= 3) {
+ if (INTEL_GEN(dev_priv) >= 3) {
if (modifier == I915_FORMAT_MOD_X_TILED)
return 8*1024;
else
@@ -656,7 +691,18 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
else
plane->min_cdclk = i9xx_plane_min_cdclk;
- plane->max_stride = i9xx_plane_max_stride;
+ if (HAS_GMCH(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 4)
+ plane->max_stride = i965_plane_max_stride;
+ else
+ plane->max_stride = i9xx_plane_max_stride;
+ } else {
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ plane->max_stride = hsw_primary_max_stride;
+ else
+ plane->max_stride = ilk_primary_max_stride;
+ }
+
plane->update_plane = i9xx_update_plane;
plane->disable_plane = i9xx_disable_plane;
plane->get_hw_state = i9xx_plane_get_hw_state;
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h
index bc2834a62735..ca963c2a8457 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.h
@@ -13,7 +13,7 @@ struct drm_i915_private;
struct intel_plane;
struct intel_plane_state;
-unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
+unsigned int i965_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..b24c8fc8e83e 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1851,7 +1851,26 @@ g4x_sprite_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation)
{
- return 16384;
+ const struct drm_format_info *info = drm_format_info(pixel_format);
+ int cpp = info->cpp[0];
+
+ /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
+ if (modifier == I915_FORMAT_MOD_X_TILED)
+ return min(4096 * cpp, 16 * 1024);
+ else
+ return 16 * 1024;
+}
+
+static unsigned int
+hsw_sprite_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ const struct drm_format_info *info = drm_format_info(pixel_format);
+ int cpp = info->cpp[0];
+
+ /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
+ return min(8192 * cpp, 16 * 1024);
}
static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
@@ -3398,11 +3417,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
return plane;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- plane->max_stride = i9xx_plane_max_stride;
plane->update_plane = vlv_update_plane;
plane->disable_plane = vlv_disable_plane;
plane->get_hw_state = vlv_plane_get_hw_state;
plane->check_plane = vlv_sprite_check;
+ plane->max_stride = i965_plane_max_stride;
plane->min_cdclk = vlv_plane_min_cdclk;
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -3416,16 +3435,18 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &vlv_sprite_funcs;
} else if (INTEL_GEN(dev_priv) >= 7) {
- plane->max_stride = g4x_sprite_max_stride;
plane->update_plane = ivb_update_plane;
plane->disable_plane = ivb_disable_plane;
plane->get_hw_state = ivb_plane_get_hw_state;
plane->check_plane = g4x_sprite_check;
- if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ plane->max_stride = hsw_sprite_max_stride;
plane->min_cdclk = hsw_plane_min_cdclk;
- else
+ } else {
+ plane->max_stride = g4x_sprite_max_stride;
plane->min_cdclk = ivb_sprite_min_cdclk;
+ }
formats = snb_plane_formats;
num_formats = ARRAY_SIZE(snb_plane_formats);
@@ -3433,11 +3454,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &snb_sprite_funcs;
} else {
- plane->max_stride = g4x_sprite_max_stride;
plane->update_plane = g4x_update_plane;
plane->disable_plane = g4x_disable_plane;
plane->get_hw_state = g4x_plane_get_hw_state;
plane->check_plane = g4x_sprite_check;
+ plane->max_stride = g4x_sprite_max_stride;
plane->min_cdclk = g4x_sprite_min_cdclk;
modifiers = i9xx_plane_format_modifiers;
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 02/11] drm/i915: Limit plane stride to below TILEOFF.x limit
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: Limit plane stride to below TILEOFF.x limit Ville Syrjala
@ 2021-01-28 9:41 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-28 9:41 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Limit pre-skl plane stride to below 4k or 8k pixels (depending on
> the platform). We do this in order guarantee that TILEOFF/OFFSET.x
> does not get too big.
>
> Currently this is not a problem as we align SURF to 4k, and so
> TILEOFF/OFFSET only have to deal with a single tile's worth of
> pixels. But for async flips we're going to have to bump SURF
> alignment to 256k, and thus we can no longer guarantee
> TILEOFF/OFFSET.x will stay within acceptable bounds. We can avoid
> this by borrowing a trick from the skl+ code and limit the max
> plane stride to whatever value we can fit into TILEOFF/OFFSET.x.
>
> The slight downside is that we may end up doing GTT remapping in
> a few more cases where previously we did not have to. But since
> that will only happen with huge buffers I'm not really concerned
> about it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 64 ++++++++++++++++++---
> drivers/gpu/drm/i915/display/i9xx_plane.h | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++--
> 3 files changed, 83 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1158ce4df92..7d968ca890da 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -530,21 +530,56 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> return ret;
> }
>
> +static unsigned int
> +hsw_primary_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + const struct drm_format_info *info = drm_format_info(pixel_format);
> + int cpp = info->cpp[0];
> +
> + /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
> + return min(8192 * cpp, 32 * 1024);
> +}
> +
> +static unsigned int
> +ilk_primary_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + const struct drm_format_info *info = drm_format_info(pixel_format);
> + int cpp = info->cpp[0];
> +
> + /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
> + if (modifier == I915_FORMAT_MOD_X_TILED)
> + return min(4096 * cpp, 32 * 1024);
> + else
> + return 32 * 1024;
> +}
> +
> unsigned int
> +i965_plane_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + const struct drm_format_info *info = drm_format_info(pixel_format);
> + int cpp = info->cpp[0];
> +
> + /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
> + if (modifier == I915_FORMAT_MOD_X_TILED)
> + return min(4096 * cpp, 16 * 1024);
> + else
> + return 32 * 1024;
> +}
> +
> +static unsigned int
> i9xx_plane_max_stride(struct intel_plane *plane,
> u32 pixel_format, u64 modifier,
> unsigned int rotation)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>
> - if (!HAS_GMCH(dev_priv)) {
> - return 32*1024;
> - } else if (INTEL_GEN(dev_priv) >= 4) {
> - if (modifier == I915_FORMAT_MOD_X_TILED)
> - return 16*1024;
> - else
> - return 32*1024;
> - } else if (INTEL_GEN(dev_priv) >= 3) {
> + if (INTEL_GEN(dev_priv) >= 3) {
> if (modifier == I915_FORMAT_MOD_X_TILED)
> return 8*1024;
> else
> @@ -656,7 +691,18 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> else
> plane->min_cdclk = i9xx_plane_min_cdclk;
>
> - plane->max_stride = i9xx_plane_max_stride;
> + if (HAS_GMCH(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 4)
> + plane->max_stride = i965_plane_max_stride;
> + else
> + plane->max_stride = i9xx_plane_max_stride;
> + } else {
> + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> + plane->max_stride = hsw_primary_max_stride;
> + else
> + plane->max_stride = ilk_primary_max_stride;
> + }
> +
> plane->update_plane = i9xx_update_plane;
> plane->disable_plane = i9xx_disable_plane;
> plane->get_hw_state = i9xx_plane_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h
> index bc2834a62735..ca963c2a8457 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.h
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h
> @@ -13,7 +13,7 @@ struct drm_i915_private;
> struct intel_plane;
> struct intel_plane_state;
>
> -unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
> +unsigned int i965_plane_max_stride(struct intel_plane *plane,
> u32 pixel_format, u64 modifier,
> unsigned int rotation);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index cf3589fd0ddb..b24c8fc8e83e 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -1851,7 +1851,26 @@ g4x_sprite_max_stride(struct intel_plane *plane,
> u32 pixel_format, u64 modifier,
> unsigned int rotation)
> {
> - return 16384;
> + const struct drm_format_info *info = drm_format_info(pixel_format);
> + int cpp = info->cpp[0];
> +
> + /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
> + if (modifier == I915_FORMAT_MOD_X_TILED)
> + return min(4096 * cpp, 16 * 1024);
> + else
> + return 16 * 1024;
> +}
> +
> +static unsigned int
> +hsw_sprite_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + const struct drm_format_info *info = drm_format_info(pixel_format);
> + int cpp = info->cpp[0];
> +
> + /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
> + return min(8192 * cpp, 16 * 1024);
> }
>
> static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> @@ -3398,11 +3417,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> return plane;
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - plane->max_stride = i9xx_plane_max_stride;
> plane->update_plane = vlv_update_plane;
> plane->disable_plane = vlv_disable_plane;
> plane->get_hw_state = vlv_plane_get_hw_state;
> plane->check_plane = vlv_sprite_check;
> + plane->max_stride = i965_plane_max_stride;
> plane->min_cdclk = vlv_plane_min_cdclk;
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> @@ -3416,16 +3435,18 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &vlv_sprite_funcs;
> } else if (INTEL_GEN(dev_priv) >= 7) {
> - plane->max_stride = g4x_sprite_max_stride;
> plane->update_plane = ivb_update_plane;
> plane->disable_plane = ivb_disable_plane;
> plane->get_hw_state = ivb_plane_get_hw_state;
> plane->check_plane = g4x_sprite_check;
>
> - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> + plane->max_stride = hsw_sprite_max_stride;
> plane->min_cdclk = hsw_plane_min_cdclk;
> - else
> + } else {
> + plane->max_stride = g4x_sprite_max_stride;
> plane->min_cdclk = ivb_sprite_min_cdclk;
> + }
>
> formats = snb_plane_formats;
> num_formats = ARRAY_SIZE(snb_plane_formats);
> @@ -3433,11 +3454,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> - plane->max_stride = g4x_sprite_max_stride;
> plane->update_plane = g4x_update_plane;
> plane->disable_plane = g4x_disable_plane;
> plane->get_hw_state = g4x_plane_get_hw_state;
> plane->check_plane = g4x_sprite_check;
> + plane->max_stride = g4x_sprite_max_stride;
> plane->min_cdclk = g4x_sprite_min_cdclk;
>
> modifiers = i9xx_plane_format_modifiers;
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 03/11] drm/i915: Drop redundant parens
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: WARN if plane src coords are too big Ville Syrjala
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: Limit plane stride to below TILEOFF.x limit Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-15 10:19 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Generalize the async flip capability check Ville Syrjala
` (9 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Drop the pointless extra parens.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dd1971040bbc..4484609d870d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2079,7 +2079,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
intel_opregion_asle_intr(dev_priv);
for_each_pipe(dev_priv, pipe) {
- if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
+ if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
intel_handle_vblank(dev_priv, pipe);
}
--
2.26.2
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/11] drm/i915: Drop redundant parens
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Drop redundant parens Ville Syrjala
@ 2021-01-15 10:19 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-15 10:19 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Drop the pointless extra parens.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dd1971040bbc..4484609d870d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2079,7 +2079,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
> intel_opregion_asle_intr(dev_priv);
>
> for_each_pipe(dev_priv, pipe) {
> - if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
> + if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
> intel_handle_vblank(dev_priv, pipe);
> }
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 04/11] drm/i915: Generalize the async flip capability check
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (2 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Drop redundant parens Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-15 10:23 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Add plane vfuncs to enable/disable flip_done interrupt Ville Syrjala
` (8 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Only assign the plane->async_flip() vfunc when the plane supports
async flips. For now we keep this artificially limited to the primary
plane since thats the only thing the legacy page flip uapi can target
and there is no async flip support in the atomic uapi yet.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7735c28b2467..1ad92fcaee7b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14377,7 +14377,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
* this(vlv/chv and icl+) should be added when async flip is
* enabled in the atomic IOCTL path.
*/
- if (plane->id != PLANE_PRIMARY)
+ if (!plane->async_flip)
return -EINVAL;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b24c8fc8e83e..0a5648d5dcf8 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3309,7 +3309,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
plane->min_cdclk = skl_plane_min_cdclk;
- plane->async_flip = skl_plane_async_flip;
+
+ if (plane_id == PLANE_PRIMARY)
+ plane->async_flip = skl_plane_async_flip;
if (INTEL_GEN(dev_priv) >= 11)
formats = icl_get_plane_formats(dev_priv, pipe,
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/11] drm/i915: Generalize the async flip capability check
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Generalize the async flip capability check Ville Syrjala
@ 2021-01-15 10:23 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-15 10:23 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Only assign the plane->async_flip() vfunc when the plane supports
> async flips. For now we keep this artificially limited to the primary
> plane since thats the only thing the legacy page flip uapi can target
> and there is no async flip support in the atomic uapi yet.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 4 +++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7735c28b2467..1ad92fcaee7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14377,7 +14377,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> * this(vlv/chv and icl+) should be added when async flip is
> * enabled in the atomic IOCTL path.
> */
> - if (plane->id != PLANE_PRIMARY)
> + if (!plane->async_flip)
> return -EINVAL;
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index b24c8fc8e83e..0a5648d5dcf8 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3309,7 +3309,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->get_hw_state = skl_plane_get_hw_state;
> plane->check_plane = skl_plane_check;
> plane->min_cdclk = skl_plane_min_cdclk;
> - plane->async_flip = skl_plane_async_flip;
> +
> + if (plane_id == PLANE_PRIMARY)
> + plane->async_flip = skl_plane_async_flip;
>
> if (INTEL_GEN(dev_priv) >= 11)
> formats = icl_get_plane_formats(dev_priv, pipe,
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 05/11] drm/i915: Add plane vfuncs to enable/disable flip_done interrupt
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (3 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Generalize the async flip capability check Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-15 11:38 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Move the async_flip bit setup into the .async_flip() hook Ville Syrjala
` (7 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Prepare for more platforms with async flip support by turning
the flip_done interrupt enable/disable into plane vfuncs.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 42 +++++++++++++++++--
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_sprite.c | 27 +++++++++++-
drivers/gpu/drm/i915/i915_irq.c | 26 ------------
drivers/gpu/drm/i915/i915_irq.h | 3 --
5 files changed, 67 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1ad92fcaee7b..f12b74cfe974 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6133,6 +6133,42 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
icl_wa_scalerclkgating(dev_priv, pipe, false);
}
+static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ u8 update_planes = crtc_state->update_planes;
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->enable_flip_done &&
+ plane->pipe == crtc->pipe &&
+ update_planes & BIT(plane->id))
+ plane->enable_flip_done(plane);
+ }
+}
+
+static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ u8 update_planes = crtc_state->update_planes;
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->disable_flip_done &&
+ plane->pipe == crtc->pipe &&
+ update_planes & BIT(plane->id))
+ plane->disable_flip_done(plane);
+ }
+}
+
static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
struct intel_crtc *crtc,
const struct intel_crtc_state *new_crtc_state)
@@ -14333,7 +14369,7 @@ static void kill_bigjoiner_slave(struct intel_atomic_state *state,
* Async flip can only change the plane surface address, so anything else
* changing is rejected from the intel_atomic_check_async() function.
* Once this check is cleared, flip done interrupt is enabled using
- * the skl_enable_flip_done() function.
+ * the intel_crtc_enable_flip_done() function.
*
* As soon as the surface address register is written, flip done interrupt is
* generated and the requested events are sent to the usersapce in the interrupt
@@ -15289,7 +15325,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->uapi.async_flip)
- skl_enable_flip_done(crtc);
+ intel_crtc_enable_flip_done(state, crtc);
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -15314,7 +15350,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->uapi.async_flip)
- skl_disable_flip_done(crtc);
+ intel_crtc_disable_flip_done(state, crtc);
if (new_crtc_state->hw.active &&
!intel_crtc_needs_modeset(new_crtc_state) &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1067bd073c95..255648ab0fa7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1258,6 +1258,8 @@ struct intel_plane {
void (*async_flip)(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+ void (*enable_flip_done)(struct intel_plane *plane);
+ void (*disable_flip_done)(struct intel_plane *plane);
};
struct intel_watermark_params {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 0a5648d5dcf8..8e01cd4ebe36 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -958,6 +958,28 @@ skl_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
+static void
+skl_plane_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(&i915->irq_lock);
+ bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
+ spin_unlock_irq(&i915->irq_lock);
+}
+
+static void
+skl_plane_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(&i915->irq_lock);
+ bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
+ spin_unlock_irq(&i915->irq_lock);
+}
+
static void i9xx_plane_linear_gamma(u16 gamma[8])
{
/* The points are not evenly spaced. */
@@ -3310,8 +3332,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->check_plane = skl_plane_check;
plane->min_cdclk = skl_plane_min_cdclk;
- if (plane_id == PLANE_PRIMARY)
+ if (plane_id == PLANE_PRIMARY) {
plane->async_flip = skl_plane_async_flip;
+ plane->enable_flip_done = skl_plane_enable_flip_done;
+ plane->disable_flip_done = skl_plane_disable_flip_done;
+ }
if (INTEL_GEN(dev_priv) >= 11)
formats = icl_get_plane_formats(dev_priv, pipe,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4484609d870d..33019cf0e630 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2822,19 +2822,6 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
return 0;
}
-void skl_enable_flip_done(struct intel_crtc *crtc)
-{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&i915->irq_lock, irqflags);
-
- bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
-
- spin_unlock_irqrestore(&i915->irq_lock, irqflags);
-}
-
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2899,19 +2886,6 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
-void skl_disable_flip_done(struct intel_crtc *crtc)
-{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&i915->irq_lock, irqflags);
-
- bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
-
- spin_unlock_irqrestore(&i915->irq_lock, irqflags);
-}
-
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 2efe609519ca..25f25cd95818 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -118,9 +118,6 @@ void i965_disable_vblank(struct drm_crtc *crtc);
void ilk_disable_vblank(struct drm_crtc *crtc);
void bdw_disable_vblank(struct drm_crtc *crtc);
-void skl_enable_flip_done(struct intel_crtc *crtc);
-void skl_disable_flip_done(struct intel_crtc *crtc);
-
void gen2_irq_reset(struct intel_uncore *uncore);
void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier);
--
2.26.2
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/11] drm/i915: Add plane vfuncs to enable/disable flip_done interrupt
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Add plane vfuncs to enable/disable flip_done interrupt Ville Syrjala
@ 2021-01-15 11:38 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-15 11:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Prepare for more platforms with async flip support by turning
> the flip_done interrupt enable/disable into plane vfuncs.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 42 +++++++++++++++++--
> .../drm/i915/display/intel_display_types.h | 2 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 27 +++++++++++-
> drivers/gpu/drm/i915/i915_irq.c | 26 ------------
> drivers/gpu/drm/i915/i915_irq.h | 3 --
> 5 files changed, 67 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1ad92fcaee7b..f12b74cfe974 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6133,6 +6133,42 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
> icl_wa_scalerclkgating(dev_priv, pipe, false);
> }
>
> +static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + u8 update_planes = crtc_state->update_planes;
> + const struct intel_plane_state *plane_state;
> + struct intel_plane *plane;
> + int i;
> +
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> + if (plane->enable_flip_done &&
> + plane->pipe == crtc->pipe &&
> + update_planes & BIT(plane->id))
> + plane->enable_flip_done(plane);
> + }
> +}
> +
> +static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + u8 update_planes = crtc_state->update_planes;
> + const struct intel_plane_state *plane_state;
> + struct intel_plane *plane;
> + int i;
> +
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> + if (plane->disable_flip_done &&
> + plane->pipe == crtc->pipe &&
> + update_planes & BIT(plane->id))
> + plane->disable_flip_done(plane);
> + }
> +}
> +
> static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> const struct intel_crtc_state *new_crtc_state)
> @@ -14333,7 +14369,7 @@ static void kill_bigjoiner_slave(struct intel_atomic_state *state,
> * Async flip can only change the plane surface address, so anything else
> * changing is rejected from the intel_atomic_check_async() function.
> * Once this check is cleared, flip done interrupt is enabled using
> - * the skl_enable_flip_done() function.
> + * the intel_crtc_enable_flip_done() function.
> *
> * As soon as the surface address register is written, flip done interrupt is
> * generated and the requested events are sent to the usersapce in the interrupt
> @@ -15289,7 +15325,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (new_crtc_state->uapi.async_flip)
> - skl_enable_flip_done(crtc);
> + intel_crtc_enable_flip_done(state, crtc);
> }
>
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> @@ -15314,7 +15350,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (new_crtc_state->uapi.async_flip)
> - skl_disable_flip_done(crtc);
> + intel_crtc_disable_flip_done(state, crtc);
>
> if (new_crtc_state->hw.active &&
> !intel_crtc_needs_modeset(new_crtc_state) &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1067bd073c95..255648ab0fa7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1258,6 +1258,8 @@ struct intel_plane {
> void (*async_flip)(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> + void (*enable_flip_done)(struct intel_plane *plane);
> + void (*disable_flip_done)(struct intel_plane *plane);
> };
>
> struct intel_watermark_params {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 0a5648d5dcf8..8e01cd4ebe36 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -958,6 +958,28 @@ skl_plane_get_hw_state(struct intel_plane *plane,
> return ret;
> }
>
> +static void
> +skl_plane_enable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> +
> + spin_lock_irq(&i915->irq_lock);
> + bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> +static void
> +skl_plane_disable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> +
> + spin_lock_irq(&i915->irq_lock);
> + bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> static void i9xx_plane_linear_gamma(u16 gamma[8])
> {
> /* The points are not evenly spaced. */
> @@ -3310,8 +3332,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->check_plane = skl_plane_check;
> plane->min_cdclk = skl_plane_min_cdclk;
>
> - if (plane_id == PLANE_PRIMARY)
> + if (plane_id == PLANE_PRIMARY) {
> plane->async_flip = skl_plane_async_flip;
> + plane->enable_flip_done = skl_plane_enable_flip_done;
> + plane->disable_flip_done = skl_plane_disable_flip_done;
> + }
>
> if (INTEL_GEN(dev_priv) >= 11)
> formats = icl_get_plane_formats(dev_priv, pipe,
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4484609d870d..33019cf0e630 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2822,19 +2822,6 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
> return 0;
> }
>
> -void skl_enable_flip_done(struct intel_crtc *crtc)
> -{
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - unsigned long irqflags;
> -
> - spin_lock_irqsave(&i915->irq_lock, irqflags);
> -
> - bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> -
> - spin_unlock_irqrestore(&i915->irq_lock, irqflags);
> -}
> -
> /* Called from drm generic code, passed 'crtc' which
> * we use as a pipe index
> */
> @@ -2899,19 +2886,6 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
>
> -void skl_disable_flip_done(struct intel_crtc *crtc)
> -{
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - unsigned long irqflags;
> -
> - spin_lock_irqsave(&i915->irq_lock, irqflags);
> -
> - bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> -
> - spin_unlock_irqrestore(&i915->irq_lock, irqflags);
> -}
> -
> static void ibx_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 2efe609519ca..25f25cd95818 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -118,9 +118,6 @@ void i965_disable_vblank(struct drm_crtc *crtc);
> void ilk_disable_vblank(struct drm_crtc *crtc);
> void bdw_disable_vblank(struct drm_crtc *crtc);
>
> -void skl_enable_flip_done(struct intel_crtc *crtc);
> -void skl_disable_flip_done(struct intel_crtc *crtc);
> -
> void gen2_irq_reset(struct intel_uncore *uncore);
> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> i915_reg_t iir, i915_reg_t ier);
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 06/11] drm/i915: Move the async_flip bit setup into the .async_flip() hook
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (4 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Add plane vfuncs to enable/disable flip_done interrupt Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-15 11:40 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Reuse the async_flip() hook for the async flip disable w/a Ville Syrjala
` (6 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Set up the async flip PLANE_CTL bit directly in the
.async_flip() hook. Neither .update_plane() nor .disable_plane()
ever need to set this so having it done by skl_plane_ctl_crtc()
is rather pointless.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ---
drivers/gpu/drm/i915/display/intel_sprite.c | 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f12b74cfe974..fc932028c368 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4250,9 +4250,6 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_ctl = 0;
- if (crtc_state->uapi.async_flip)
- plane_ctl |= PLANE_CTL_ASYNC_FLIP;
-
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return plane_ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 8e01cd4ebe36..1188e0f92223 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -782,6 +782,8 @@ skl_plane_async_flip(struct intel_plane *plane,
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+ plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 06/11] drm/i915: Move the async_flip bit setup into the .async_flip() hook
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Move the async_flip bit setup into the .async_flip() hook Ville Syrjala
@ 2021-01-15 11:40 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-15 11:40 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Set up the async flip PLANE_CTL bit directly in the
> .async_flip() hook. Neither .update_plane() nor .disable_plane()
> ever need to set this so having it done by skl_plane_ctl_crtc()
> is rather pointless.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 ++
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f12b74cfe974..fc932028c368 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4250,9 +4250,6 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 plane_ctl = 0;
>
> - if (crtc_state->uapi.async_flip)
> - plane_ctl |= PLANE_CTL_ASYNC_FLIP;
> -
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> return plane_ctl;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 8e01cd4ebe36..1188e0f92223 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -782,6 +782,8 @@ skl_plane_async_flip(struct intel_plane *plane,
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>
> + plane_ctl |= PLANE_CTL_ASYNC_FLIP;
> +
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 07/11] drm/i915: Reuse the async_flip() hook for the async flip disable w/a
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (5 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Move the async_flip bit setup into the .async_flip() hook Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-18 9:27 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Implement async flips for bdw Ville Syrjala
` (5 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On some platforms we need to trigger an extra async flip with
the async flip bit disabled, and then wait for the next vblank
until the async flip bit off state will actually latch.
Currently the w/a is just open coded for skl+ universal planes.
Instead of doing that lets reuse the .async_flip() hook for this
purpose since it needs to write the exact same set of registers.
In order to do this we'll just have the caller pass in the state
of the async flip bit explicitly.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 59 ++++++++-----------
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 7 ++-
4 files changed, 35 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b5e1ee99535c..4683f98f7e54 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -452,7 +452,7 @@ void intel_update_plane(struct intel_plane *plane,
trace_intel_update_plane(&plane->base, crtc);
if (crtc_state->uapi.async_flip && plane->async_flip)
- plane->async_flip(plane, crtc_state, plane_state);
+ plane->async_flip(plane, crtc_state, plane_state, true);
else
plane->update_plane(plane, crtc_state, plane_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fc932028c368..9ea7a89432d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6166,41 +6166,36 @@ static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
}
}
-static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- const struct intel_crtc_state *new_crtc_state)
+static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ u8 update_planes = new_crtc_state->update_planes;
+ const struct intel_plane_state *old_plane_state;
struct intel_plane *plane;
- struct intel_plane_state *new_plane_state;
+ bool need_vbl_wait = false;
int i;
- for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
- u32 update_mask = new_crtc_state->update_planes;
- u32 plane_ctl, surf_addr;
- enum plane_id plane_id;
- unsigned long irqflags;
- enum pipe pipe;
-
- if (crtc->pipe != plane->pipe ||
- !(update_mask & BIT(plane->id)))
- continue;
-
- plane_id = plane->id;
- pipe = plane->pipe;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
- surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
-
- plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
-
- intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
+ if (plane->need_async_flip_disable_wa &&
+ plane->pipe == crtc->pipe &&
+ update_planes & BIT(plane->id)) {
+ /*
+ * Apart from the async flip bit we want to
+ * preserve the old state for the plane.
+ */
+ plane->async_flip(plane, old_crtc_state,
+ old_plane_state, false);
+ need_vbl_wait = true;
+ }
}
- intel_wait_for_vblank(dev_priv, crtc->pipe);
+ if (need_vbl_wait)
+ intel_wait_for_vblank(i915, crtc->pipe);
}
static void intel_pre_plane_update(struct intel_atomic_state *state,
@@ -6293,10 +6288,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* WA for platforms where async address update enable bit
* is double buffered and only latched at start of vblank.
*/
- if (old_crtc_state->uapi.async_flip &&
- !new_crtc_state->uapi.async_flip &&
- IS_GEN_RANGE(dev_priv, 9, 10))
- skl_disable_async_flip_wa(state, crtc, new_crtc_state);
+ if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
+ intel_crtc_async_flip_disable_wa(state, crtc);
}
static void intel_crtc_disable_planes(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 255648ab0fa7..56d9a18ef114 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1221,6 +1221,7 @@ struct intel_plane {
enum pipe pipe;
bool has_fbc;
bool has_ccs;
+ bool need_async_flip_disable_wa;
u32 frontbuffer_bit;
struct {
@@ -1257,7 +1258,8 @@ struct intel_plane {
const struct intel_plane_state *plane_state);
void (*async_flip)(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
+ const struct intel_plane_state *plane_state,
+ bool async_flip);
void (*enable_flip_done)(struct intel_plane *plane);
void (*disable_flip_done)(struct intel_plane *plane);
};
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 1188e0f92223..d7fd01e1ef77 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -771,7 +771,8 @@ icl_program_input_csc(struct intel_plane *plane,
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+ const struct intel_plane_state *plane_state,
+ bool async_flip)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
unsigned long irqflags;
@@ -782,7 +783,8 @@ skl_plane_async_flip(struct intel_plane *plane,
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
- plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+ if (async_flip)
+ plane_ctl |= PLANE_CTL_ASYNC_FLIP;
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
@@ -3335,6 +3337,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->min_cdclk = skl_plane_min_cdclk;
if (plane_id == PLANE_PRIMARY) {
+ plane->need_async_flip_disable_wa = IS_GEN_RANGE(dev_priv, 9, 10);
plane->async_flip = skl_plane_async_flip;
plane->enable_flip_done = skl_plane_enable_flip_done;
plane->disable_flip_done = skl_plane_disable_flip_done;
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 07/11] drm/i915: Reuse the async_flip() hook for the async flip disable w/a
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Reuse the async_flip() hook for the async flip disable w/a Ville Syrjala
@ 2021-01-18 9:27 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-18 9:27 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On some platforms we need to trigger an extra async flip with
> the async flip bit disabled, and then wait for the next vblank
> until the async flip bit off state will actually latch.
>
> Currently the w/a is just open coded for skl+ universal planes.
> Instead of doing that lets reuse the .async_flip() hook for this
> purpose since it needs to write the exact same set of registers.
> In order to do this we'll just have the caller pass in the state
> of the async flip bit explicitly.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 59 ++++++++-----------
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 7 ++-
> 4 files changed, 35 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index b5e1ee99535c..4683f98f7e54 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -452,7 +452,7 @@ void intel_update_plane(struct intel_plane *plane,
> trace_intel_update_plane(&plane->base, crtc);
>
> if (crtc_state->uapi.async_flip && plane->async_flip)
> - plane->async_flip(plane, crtc_state, plane_state);
> + plane->async_flip(plane, crtc_state, plane_state, true);
> else
> plane->update_plane(plane, crtc_state, plane_state);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fc932028c368..9ea7a89432d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6166,41 +6166,36 @@ static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
> }
> }
>
> -static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - const struct intel_crtc_state *new_crtc_state)
> +static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + u8 update_planes = new_crtc_state->update_planes;
> + const struct intel_plane_state *old_plane_state;
> struct intel_plane *plane;
> - struct intel_plane_state *new_plane_state;
> + bool need_vbl_wait = false;
> int i;
>
> - for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
> - u32 update_mask = new_crtc_state->update_planes;
> - u32 plane_ctl, surf_addr;
> - enum plane_id plane_id;
> - unsigned long irqflags;
> - enum pipe pipe;
> -
> - if (crtc->pipe != plane->pipe ||
> - !(update_mask & BIT(plane->id)))
> - continue;
> -
> - plane_id = plane->id;
> - pipe = plane->pipe;
> -
> - spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> - plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
> - surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
> -
> - plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
> -
> - intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
> - spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> + for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
> + if (plane->need_async_flip_disable_wa &&
> + plane->pipe == crtc->pipe &&
> + update_planes & BIT(plane->id)) {
> + /*
> + * Apart from the async flip bit we want to
> + * preserve the old state for the plane.
> + */
> + plane->async_flip(plane, old_crtc_state,
> + old_plane_state, false);
> + need_vbl_wait = true;
> + }
> }
>
> - intel_wait_for_vblank(dev_priv, crtc->pipe);
> + if (need_vbl_wait)
> + intel_wait_for_vblank(i915, crtc->pipe);
> }
>
> static void intel_pre_plane_update(struct intel_atomic_state *state,
> @@ -6293,10 +6288,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
> * WA for platforms where async address update enable bit
> * is double buffered and only latched at start of vblank.
> */
> - if (old_crtc_state->uapi.async_flip &&
> - !new_crtc_state->uapi.async_flip &&
> - IS_GEN_RANGE(dev_priv, 9, 10))
> - skl_disable_async_flip_wa(state, crtc, new_crtc_state);
> + if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
> + intel_crtc_async_flip_disable_wa(state, crtc);
> }
>
> static void intel_crtc_disable_planes(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 255648ab0fa7..56d9a18ef114 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1221,6 +1221,7 @@ struct intel_plane {
> enum pipe pipe;
> bool has_fbc;
> bool has_ccs;
> + bool need_async_flip_disable_wa;
> u32 frontbuffer_bit;
>
> struct {
> @@ -1257,7 +1258,8 @@ struct intel_plane {
> const struct intel_plane_state *plane_state);
> void (*async_flip)(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state);
> + const struct intel_plane_state *plane_state,
> + bool async_flip);
> void (*enable_flip_done)(struct intel_plane *plane);
> void (*disable_flip_done)(struct intel_plane *plane);
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1188e0f92223..d7fd01e1ef77 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -771,7 +771,8 @@ icl_program_input_csc(struct intel_plane *plane,
> static void
> skl_plane_async_flip(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> + const struct intel_plane_state *plane_state,
> + bool async_flip)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> unsigned long irqflags;
> @@ -782,7 +783,8 @@ skl_plane_async_flip(struct intel_plane *plane,
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>
> - plane_ctl |= PLANE_CTL_ASYNC_FLIP;
> + if (async_flip)
> + plane_ctl |= PLANE_CTL_ASYNC_FLIP;
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> @@ -3335,6 +3337,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->min_cdclk = skl_plane_min_cdclk;
>
> if (plane_id == PLANE_PRIMARY) {
> + plane->need_async_flip_disable_wa = IS_GEN_RANGE(dev_priv, 9, 10);
> plane->async_flip = skl_plane_async_flip;
> plane->enable_flip_done = skl_plane_enable_flip_done;
> plane->disable_flip_done = skl_plane_disable_flip_done;
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 08/11] drm/i915: Implement async flips for bdw
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (6 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Reuse the async_flip() hook for the async flip disable w/a Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-18 9:44 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Implement async flip for ivb/hsw Ville Syrjala
` (4 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Implement async flip support for BDW. The implementation is
similar to the skl+ code. And just like skl/bxt/glk bdw also
needs the disable w/a, thus we need to plumb the desired state
of the async flip all the way down to i9xx_plane_ctl_crtc().
According to the spec we do need to bump the surface alignment
to 256KiB for this. Async flips require an X-tiled buffer so
we don't have to worry about linear.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 51 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.c | 10 ++--
drivers/gpu/drm/i915/i915_irq.c | 25 +++++-----
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 73 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 7d968ca890da..44004558ebbd 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -495,6 +495,50 @@ static void i9xx_disable_plane(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
+static void
+g4x_primary_async_flip(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ bool async_flip)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
+ u32 dspaddr_offset = plane_state->color_plane[0].offset;
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ unsigned long irqflags;
+
+ if (async_flip)
+ dspcntr |= DISPPLANE_ASYNC_FLIP;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+bdw_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(&i915->irq_lock);
+ bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
+ spin_unlock_irq(&i915->irq_lock);
+}
+
+static void
+bdw_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(&i915->irq_lock);
+ bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
+ spin_unlock_irq(&i915->irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -708,6 +752,13 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->get_hw_state = i9xx_plane_get_hw_state;
plane->check_plane = i9xx_plane_check;
+ if (IS_BROADWELL(dev_priv)) {
+ plane->need_async_flip_disable_wa = true;
+ plane->async_flip = g4x_primary_async_flip;
+ plane->enable_flip_done = bdw_primary_enable_flip_done;
+ plane->disable_flip_done = bdw_primary_disable_flip_done;
+ }
+
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9ea7a89432d6..6db3e6b69a53 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2120,6 +2120,11 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
return 0;
}
+static bool has_async_flips(struct drm_i915_private *i915)
+{
+ return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915);
+}
+
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
int color_plane)
{
@@ -2134,7 +2139,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case DRM_FORMAT_MOD_LINEAR:
return intel_linear_alignment(dev_priv);
case I915_FORMAT_MOD_X_TILED:
- if (INTEL_GEN(dev_priv) >= 9)
+ if (has_async_flips(dev_priv))
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
@@ -17097,8 +17102,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
mode_config->funcs = &intel_mode_funcs;
- if (INTEL_GEN(i915) >= 9)
- mode_config->async_page_flip = true;
+ mode_config->async_page_flip = has_async_flips(i915);
/*
* Maximum framebuffer dimensions, chosen to match
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 33019cf0e630..407a9dd0a21e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2357,6 +2357,14 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
}
+static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
+{
+ if (INTEL_GEN(i915) >= 9)
+ return GEN9_PIPE_PLANE1_FLIP_DONE;
+ else
+ return GEN8_PIPE_PRIMARY_FLIP_DONE;
+}
+
static irqreturn_t
gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
{
@@ -2459,7 +2467,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & GEN8_PIPE_VBLANK)
intel_handle_vblank(dev_priv, pipe);
- if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+ if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
flip_done_handler(dev_priv, pipe);
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
@@ -3078,13 +3086,10 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
struct intel_uncore *uncore = &dev_priv->uncore;
-
- u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
+ u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
+ gen8_de_pipe_flip_done_mask(dev_priv);
enum pipe pipe;
- if (INTEL_GEN(dev_priv) >= 9)
- extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
-
spin_lock_irq(&dev_priv->irq_lock);
if (!intel_irqs_enabled(dev_priv)) {
@@ -3656,11 +3661,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_port_masked |= DSI0_TE | DSI1_TE;
}
- de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
- GEN8_PIPE_FIFO_UNDERRUN;
-
- if (INTEL_GEN(dev_priv) >= 9)
- de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+ de_pipe_enables = de_pipe_masked |
+ GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
+ gen8_de_pipe_flip_done_mask(dev_priv);
de_port_enables = de_port_masked;
if (IS_GEN9_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d8ba10847ca..2646478963a5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6614,6 +6614,7 @@ enum {
#define DISPPLANE_ROTATE_180 (1 << 15)
#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
#define DISPPLANE_TILED (1 << 10)
+#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
#define _DSPAADDR 0x70184
#define _DSPASTRIDE 0x70188
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 08/11] drm/i915: Implement async flips for bdw
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Implement async flips for bdw Ville Syrjala
@ 2021-01-18 9:44 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-18 9:44 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Implement async flip support for BDW. The implementation is
> similar to the skl+ code. And just like skl/bxt/glk bdw also
> needs the disable w/a, thus we need to plumb the desired state
> of the async flip all the way down to i9xx_plane_ctl_crtc().
>
> According to the spec we do need to bump the surface alignment
> to 256KiB for this. Async flips require an X-tiled buffer so
> we don't have to worry about linear.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 51 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++--
> drivers/gpu/drm/i915/i915_irq.c | 25 +++++-----
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 4 files changed, 73 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 7d968ca890da..44004558ebbd 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -495,6 +495,50 @@ static void i9xx_disable_plane(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> +static void
> +g4x_primary_async_flip(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + bool async_flip)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
> + u32 dspaddr_offset = plane_state->color_plane[0].offset;
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> + unsigned long irqflags;
> +
> + if (async_flip)
> + dspcntr |= DISPPLANE_ASYNC_FLIP;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
> + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
> + intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void
> +bdw_primary_enable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> +
> + spin_lock_irq(&i915->irq_lock);
> + bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> +static void
> +bdw_primary_disable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> +
> + spin_lock_irq(&i915->irq_lock);
> + bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> @@ -708,6 +752,13 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->get_hw_state = i9xx_plane_get_hw_state;
> plane->check_plane = i9xx_plane_check;
>
> + if (IS_BROADWELL(dev_priv)) {
> + plane->need_async_flip_disable_wa = true;
> + plane->async_flip = g4x_primary_async_flip;
> + plane->enable_flip_done = bdw_primary_enable_flip_done;
> + plane->disable_flip_done = bdw_primary_disable_flip_done;
> + }
> +
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> 0, plane_funcs,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9ea7a89432d6..6db3e6b69a53 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2120,6 +2120,11 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
> return 0;
> }
>
> +static bool has_async_flips(struct drm_i915_private *i915)
> +{
> + return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915);
> +}
> +
> static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> int color_plane)
> {
> @@ -2134,7 +2139,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case DRM_FORMAT_MOD_LINEAR:
> return intel_linear_alignment(dev_priv);
> case I915_FORMAT_MOD_X_TILED:
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (has_async_flips(dev_priv))
> return 256 * 1024;
> return 0;
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> @@ -17097,8 +17102,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
>
> mode_config->funcs = &intel_mode_funcs;
>
> - if (INTEL_GEN(i915) >= 9)
> - mode_config->async_page_flip = true;
> + mode_config->async_page_flip = has_async_flips(i915);
>
> /*
> * Maximum framebuffer dimensions, chosen to match
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 33019cf0e630..407a9dd0a21e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2357,6 +2357,14 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
> intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
> }
>
> +static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
> +{
> + if (INTEL_GEN(i915) >= 9)
> + return GEN9_PIPE_PLANE1_FLIP_DONE;
> + else
> + return GEN8_PIPE_PRIMARY_FLIP_DONE;
> +}
> +
> static irqreturn_t
> gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> {
> @@ -2459,7 +2467,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> if (iir & GEN8_PIPE_VBLANK)
> intel_handle_vblank(dev_priv, pipe);
>
> - if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
> + if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
> flip_done_handler(dev_priv, pipe);
>
> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> @@ -3078,13 +3086,10 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> u8 pipe_mask)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> -
> - u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> + u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
> + gen8_de_pipe_flip_done_mask(dev_priv);
> enum pipe pipe;
>
> - if (INTEL_GEN(dev_priv) >= 9)
> - extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
> -
> spin_lock_irq(&dev_priv->irq_lock);
>
> if (!intel_irqs_enabled(dev_priv)) {
> @@ -3656,11 +3661,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> de_port_masked |= DSI0_TE | DSI1_TE;
> }
>
> - de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
> - GEN8_PIPE_FIFO_UNDERRUN;
> -
> - if (INTEL_GEN(dev_priv) >= 9)
> - de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
> + de_pipe_enables = de_pipe_masked |
> + GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
> + gen8_de_pipe_flip_done_mask(dev_priv);
>
> de_port_enables = de_port_masked;
> if (IS_GEN9_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1d8ba10847ca..2646478963a5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6614,6 +6614,7 @@ enum {
> #define DISPPLANE_ROTATE_180 (1 << 15)
> #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
> #define DISPPLANE_TILED (1 << 10)
> +#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
> #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
> #define _DSPAADDR 0x70184
> #define _DSPASTRIDE 0x70188
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 09/11] drm/i915: Implement async flip for ivb/hsw
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (7 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Implement async flips for bdw Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-18 10:45 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Implement async flip for ilk/snb Ville Syrjala
` (3 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add support for async flips on ivb/hsw. Unlike bdw+ we don't need
any workarounds to disable async flips. Apart from that the only
real difference from the bdw implementation is the location of the
flip_done interrupt bits.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/i915_irq.c | 6 +++++
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 44004558ebbd..f75be2292caa 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -539,6 +539,26 @@ bdw_primary_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(&i915->irq_lock);
}
+static void
+ivb_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(&i915->irq_lock);
+ ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
+ spin_unlock_irq(&i915->irq_lock);
+}
+
+static void
+ivb_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(&i915->irq_lock);
+ ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
+ spin_unlock_irq(&i915->irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -757,6 +777,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = bdw_primary_enable_flip_done;
plane->disable_flip_done = bdw_primary_disable_flip_done;
+ } else if (IS_HASWELL(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
+ plane->async_flip = g4x_primary_async_flip;
+ plane->enable_flip_done = ivb_primary_enable_flip_done;
+ plane->disable_flip_done = ivb_primary_disable_flip_done;
}
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6db3e6b69a53..25da68f12df1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2122,7 +2122,8 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
static bool has_async_flips(struct drm_i915_private *i915)
{
- return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915);
+ return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
+ IS_HASWELL(i915) || IS_IVYBRIDGE(i915);
}
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 407a9dd0a21e..3518f6f23896 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2081,6 +2081,9 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
for_each_pipe(dev_priv, pipe) {
if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
intel_handle_vblank(dev_priv, pipe);
+
+ if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
+ flip_done_handler(dev_priv, pipe);
}
/* check event from PCH */
@@ -3564,6 +3567,9 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
+ DE_PLANE_FLIP_DONE_IVB(PLANE_C) |
+ DE_PLANE_FLIP_DONE_IVB(PLANE_B) |
+ DE_PLANE_FLIP_DONE_IVB(PLANE_A) |
DE_DP_A_HOTPLUG_IVB);
} else {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
--
2.26.2
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 09/11] drm/i915: Implement async flip for ivb/hsw
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Implement async flip for ivb/hsw Ville Syrjala
@ 2021-01-18 10:45 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-18 10:45 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add support for async flips on ivb/hsw. Unlike bdw+ we don't need
> any workarounds to disable async flips. Apart from that the only
> real difference from the bdw implementation is the location of the
> flip_done interrupt bits.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> drivers/gpu/drm/i915/i915_irq.c | 6 +++++
> 3 files changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 44004558ebbd..f75be2292caa 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -539,6 +539,26 @@ bdw_primary_disable_flip_done(struct intel_plane *plane)
> spin_unlock_irq(&i915->irq_lock);
> }
>
> +static void
> +ivb_primary_enable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + spin_lock_irq(&i915->irq_lock);
> + ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> +static void
> +ivb_primary_disable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + spin_lock_irq(&i915->irq_lock);
> + ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> @@ -757,6 +777,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->async_flip = g4x_primary_async_flip;
> plane->enable_flip_done = bdw_primary_enable_flip_done;
> plane->disable_flip_done = bdw_primary_disable_flip_done;
> + } else if (IS_HASWELL(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
> + plane->async_flip = g4x_primary_async_flip;
> + plane->enable_flip_done = ivb_primary_enable_flip_done;
> + plane->disable_flip_done = ivb_primary_disable_flip_done;
> }
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6db3e6b69a53..25da68f12df1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2122,7 +2122,8 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
>
> static bool has_async_flips(struct drm_i915_private *i915)
> {
> - return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915);
> + return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
> + IS_HASWELL(i915) || IS_IVYBRIDGE(i915);
> }
>
> static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 407a9dd0a21e..3518f6f23896 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2081,6 +2081,9 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
> for_each_pipe(dev_priv, pipe) {
> if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
> intel_handle_vblank(dev_priv, pipe);
> +
> + if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
> + flip_done_handler(dev_priv, pipe);
> }
>
> /* check event from PCH */
> @@ -3564,6 +3567,9 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
> extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
> DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
> + DE_PLANE_FLIP_DONE_IVB(PLANE_C) |
> + DE_PLANE_FLIP_DONE_IVB(PLANE_B) |
> + DE_PLANE_FLIP_DONE_IVB(PLANE_A) |
> DE_DP_A_HOTPLUG_IVB);
> } else {
> display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 10/11] drm/i915: Implement async flip for ilk/snb
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (8 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Implement async flip for ivb/hsw Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-18 11:08 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Implement async flips for vlv/chv Ville Syrjala
` (2 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add support for async flips on ivb/hsw. Again no need for any
workarounds and just have to deal with the interrupt bits being
shuffled around a bit.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/i915_irq.c | 5 ++++
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index f75be2292caa..488ed01bb342 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -559,6 +559,26 @@ ivb_primary_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(&i915->irq_lock);
}
+static void
+ilk_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(&i915->irq_lock);
+ ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
+ spin_unlock_irq(&i915->irq_lock);
+}
+
+static void
+ilk_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ spin_lock_irq(&i915->irq_lock);
+ ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
+ spin_unlock_irq(&i915->irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -781,6 +801,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ivb_primary_enable_flip_done;
plane->disable_flip_done = ivb_primary_disable_flip_done;
+ } else if (IS_GEN_RANGE(dev_priv, 5, 6)) {
+ plane->async_flip = g4x_primary_async_flip;
+ plane->enable_flip_done = ilk_primary_enable_flip_done;
+ plane->disable_flip_done = ilk_primary_disable_flip_done;
}
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 25da68f12df1..67add1166d5a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2123,7 +2123,8 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
static bool has_async_flips(struct drm_i915_private *i915)
{
return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
- IS_HASWELL(i915) || IS_IVYBRIDGE(i915);
+ IS_HASWELL(i915) || IS_IVYBRIDGE(i915) ||
+ IS_GEN_RANGE(i915, 5, 6);
}
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3518f6f23896..9e04c6b28c12 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2029,6 +2029,9 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
if (de_iir & DE_PIPE_VBLANK(pipe))
intel_handle_vblank(dev_priv, pipe);
+ if (de_iir & DE_PLANE_FLIP_DONE(pipe))
+ flip_done_handler(dev_priv, pipe);
+
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
@@ -3577,6 +3580,8 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
DE_PIPEA_CRC_DONE | DE_POISON);
extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
+ DE_PLANE_FLIP_DONE(PLANE_A) |
+ DE_PLANE_FLIP_DONE(PLANE_B) |
DE_DP_A_HOTPLUG);
}
--
2.26.2
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 10/11] drm/i915: Implement async flip for ilk/snb
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Implement async flip for ilk/snb Ville Syrjala
@ 2021-01-18 11:08 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-18 11:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add support for async flips on ivb/hsw. Again no need for any
> workarounds and just have to deal with the interrupt bits being
> shuffled around a bit.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> drivers/gpu/drm/i915/i915_irq.c | 5 ++++
> 3 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index f75be2292caa..488ed01bb342 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -559,6 +559,26 @@ ivb_primary_disable_flip_done(struct intel_plane *plane)
> spin_unlock_irq(&i915->irq_lock);
> }
>
> +static void
> +ilk_primary_enable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + spin_lock_irq(&i915->irq_lock);
> + ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> +static void
> +ilk_primary_disable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + spin_lock_irq(&i915->irq_lock);
> + ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> @@ -781,6 +801,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->async_flip = g4x_primary_async_flip;
> plane->enable_flip_done = ivb_primary_enable_flip_done;
> plane->disable_flip_done = ivb_primary_disable_flip_done;
> + } else if (IS_GEN_RANGE(dev_priv, 5, 6)) {
> + plane->async_flip = g4x_primary_async_flip;
> + plane->enable_flip_done = ilk_primary_enable_flip_done;
> + plane->disable_flip_done = ilk_primary_disable_flip_done;
> }
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 25da68f12df1..67add1166d5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2123,7 +2123,8 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
> static bool has_async_flips(struct drm_i915_private *i915)
> {
> return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
> - IS_HASWELL(i915) || IS_IVYBRIDGE(i915);
> + IS_HASWELL(i915) || IS_IVYBRIDGE(i915) ||
> + IS_GEN_RANGE(i915, 5, 6);
> }
>
> static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3518f6f23896..9e04c6b28c12 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2029,6 +2029,9 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
> if (de_iir & DE_PIPE_VBLANK(pipe))
> intel_handle_vblank(dev_priv, pipe);
>
> + if (de_iir & DE_PLANE_FLIP_DONE(pipe))
> + flip_done_handler(dev_priv, pipe);
> +
> if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
> intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
>
> @@ -3577,6 +3580,8 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> DE_PIPEA_CRC_DONE | DE_POISON);
> extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
> DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
> + DE_PLANE_FLIP_DONE(PLANE_A) |
> + DE_PLANE_FLIP_DONE(PLANE_B) |
> DE_DP_A_HOTPLUG);
> }
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 11/11] drm/i915: Implement async flips for vlv/chv
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (9 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Implement async flip for ilk/snb Ville Syrjala
@ 2021-01-11 16:37 ` Ville Syrjala
2021-01-27 8:09 ` Karthik B S
2021-01-11 17:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Async flips for all ilk+ platforms (rev2) Patchwork
2021-01-11 18:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
12 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjala @ 2021-01-11 16:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add support for async flips on vlv/chv. Unlike all the other
platforms vlv/chv do not use the async flip bit in DSPCNTR and
instead we select between async vs. sync flips based on the
surface address register. The normal DSPSURF generates sync
flips DSPADDR_VLV generates async flips. And as usual the
interrupt bits are different from the other platforms.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 49 ++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/i915_irq.c | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 2 +
4 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 488ed01bb342..d30374df67f0 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -517,6 +517,23 @@ g4x_primary_async_flip(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
+static void
+vlv_primary_async_flip(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ bool async_flip)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ u32 dspaddr_offset = plane_state->color_plane[0].offset;
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
+ intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
static void
bdw_primary_enable_flip_done(struct intel_plane *plane)
{
@@ -579,6 +596,28 @@ ilk_primary_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(&i915->irq_lock);
}
+static void
+vlv_primary_enable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(&i915->irq_lock);
+ i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
+ spin_unlock_irq(&i915->irq_lock);
+}
+
+static void
+vlv_primary_disable_flip_done(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ spin_lock_irq(&i915->irq_lock);
+ i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
+ spin_unlock_irq(&i915->irq_lock);
+}
+
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
@@ -792,16 +831,20 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->get_hw_state = i9xx_plane_get_hw_state;
plane->check_plane = i9xx_plane_check;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ plane->async_flip = vlv_primary_async_flip;
+ plane->enable_flip_done = vlv_primary_enable_flip_done;
+ plane->disable_flip_done = vlv_primary_disable_flip_done;
+ } else if (IS_BROADWELL(dev_priv)) {
plane->need_async_flip_disable_wa = true;
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = bdw_primary_enable_flip_done;
plane->disable_flip_done = bdw_primary_disable_flip_done;
- } else if (IS_HASWELL(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
+ } else if (INTEL_GEN(dev_priv) >= 7) {
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ivb_primary_enable_flip_done;
plane->disable_flip_done = ivb_primary_disable_flip_done;
- } else if (IS_GEN_RANGE(dev_priv, 5, 6)) {
+ } else if (INTEL_GEN(dev_priv) >= 5) {
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ilk_primary_enable_flip_done;
plane->disable_flip_done = ilk_primary_disable_flip_done;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 67add1166d5a..8cf0777535ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2122,9 +2122,7 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
static bool has_async_flips(struct drm_i915_private *i915)
{
- return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
- IS_HASWELL(i915) || IS_IVYBRIDGE(i915) ||
- IS_GEN_RANGE(i915, 5, 6);
+ return INTEL_GEN(i915) >= 5;
}
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9e04c6b28c12..19e367f6a3b2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1517,6 +1517,9 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
intel_handle_vblank(dev_priv, pipe);
+ if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
+ flip_done_handler(dev_priv, pipe);
+
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
i9xx_pipe_crc_irq_handler(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2646478963a5..21589518de73 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6578,6 +6578,7 @@ enum {
#define TGL_CURSOR_D_OFFSET 0x73080
/* Display A control */
+#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
#define _DSPACNTR 0x70180
#define DISPLAY_PLANE_ENABLE (1 << 31)
#define DISPLAY_PLANE_DISABLE 0
@@ -6626,6 +6627,7 @@ enum {
#define _DSPASURFLIVE 0x701AC
#define _DSPAGAMC 0x701E0
+#define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
--
2.26.2
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 11/11] drm/i915: Implement async flips for vlv/chv
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Implement async flips for vlv/chv Ville Syrjala
@ 2021-01-27 8:09 ` Karthik B S
0 siblings, 0 replies; 25+ messages in thread
From: Karthik B S @ 2021-01-27 8:09 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add support for async flips on vlv/chv. Unlike all the other
> platforms vlv/chv do not use the async flip bit in DSPCNTR and
> instead we select between async vs. sync flips based on the
> surface address register. The normal DSPSURF generates sync
> flips DSPADDR_VLV generates async flips. And as usual the
> interrupt bits are different from the other platforms.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 49 ++++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> drivers/gpu/drm/i915/i915_irq.c | 3 ++
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> 4 files changed, 52 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 488ed01bb342..d30374df67f0 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -517,6 +517,23 @@ g4x_primary_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> +static void
> +vlv_primary_async_flip(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + bool async_flip)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + u32 dspaddr_offset = plane_state->color_plane[0].offset;
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> + intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
> + intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> static void
> bdw_primary_enable_flip_done(struct intel_plane *plane)
> {
> @@ -579,6 +596,28 @@ ilk_primary_disable_flip_done(struct intel_plane *plane)
> spin_unlock_irq(&i915->irq_lock);
> }
>
> +static void
> +vlv_primary_enable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> +
> + spin_lock_irq(&i915->irq_lock);
> + i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> +static void
> +vlv_primary_disable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> +
> + spin_lock_irq(&i915->irq_lock);
> + i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> @@ -792,16 +831,20 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->get_hw_state = i9xx_plane_get_hw_state;
> plane->check_plane = i9xx_plane_check;
>
> - if (IS_BROADWELL(dev_priv)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> + plane->async_flip = vlv_primary_async_flip;
> + plane->enable_flip_done = vlv_primary_enable_flip_done;
> + plane->disable_flip_done = vlv_primary_disable_flip_done;
> + } else if (IS_BROADWELL(dev_priv)) {
> plane->need_async_flip_disable_wa = true;
> plane->async_flip = g4x_primary_async_flip;
> plane->enable_flip_done = bdw_primary_enable_flip_done;
> plane->disable_flip_done = bdw_primary_disable_flip_done;
> - } else if (IS_HASWELL(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> plane->async_flip = g4x_primary_async_flip;
> plane->enable_flip_done = ivb_primary_enable_flip_done;
> plane->disable_flip_done = ivb_primary_disable_flip_done;
> - } else if (IS_GEN_RANGE(dev_priv, 5, 6)) {
> + } else if (INTEL_GEN(dev_priv) >= 5) {
> plane->async_flip = g4x_primary_async_flip;
> plane->enable_flip_done = ilk_primary_enable_flip_done;
> plane->disable_flip_done = ilk_primary_disable_flip_done;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 67add1166d5a..8cf0777535ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2122,9 +2122,7 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
>
> static bool has_async_flips(struct drm_i915_private *i915)
> {
> - return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
> - IS_HASWELL(i915) || IS_IVYBRIDGE(i915) ||
> - IS_GEN_RANGE(i915, 5, 6);
> + return INTEL_GEN(i915) >= 5;
> }
>
> static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9e04c6b28c12..19e367f6a3b2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1517,6 +1517,9 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
> if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
> intel_handle_vblank(dev_priv, pipe);
>
> + if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
> + flip_done_handler(dev_priv, pipe);
> +
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> i9xx_pipe_crc_irq_handler(dev_priv, pipe);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2646478963a5..21589518de73 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6578,6 +6578,7 @@ enum {
> #define TGL_CURSOR_D_OFFSET 0x73080
>
> /* Display A control */
> +#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> #define _DSPACNTR 0x70180
> #define DISPLAY_PLANE_ENABLE (1 << 31)
> #define DISPLAY_PLANE_DISABLE 0
> @@ -6626,6 +6627,7 @@ enum {
> #define _DSPASURFLIVE 0x701AC
> #define _DSPAGAMC 0x701E0
>
> +#define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
> #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
> #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
> #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Async flips for all ilk+ platforms (rev2)
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (10 preceding siblings ...)
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Implement async flips for vlv/chv Ville Syrjala
@ 2021-01-11 17:23 ` Patchwork
2021-01-11 18:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-01-11 17:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3700 bytes --]
== Series Details ==
Series: drm/i915: Async flips for all ilk+ platforms (rev2)
URL : https://patchwork.freedesktop.org/series/85627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9580 -> Patchwork_19315
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/index.html
Known issues
------------
Here are the changes found in Patchwork_19315 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@basic:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/fi-tgl-y/igt@gem_flink_basic@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/fi-tgl-y/igt@gem_flink_basic@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-byt-j1900: NOTRUN -> [SKIP][3] ([fdo#109271]) +27 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/fi-byt-j1900/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][4] -> [SKIP][5] ([fdo#109271])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/fi-byt-j1900/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@vgem_basic@dmabuf-fence-before:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/fi-tgl-y/igt@vgem_basic@dmabuf-fence-before.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/fi-tgl-y/igt@vgem_basic@dmabuf-fence-before.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
------------------------------
Additional (1): fi-byt-j1900
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-cml-drallion fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9580 -> Patchwork_19315
CI-20190529: 20190529
CI_DRM_9580: 117f9c9bca0ebb0e22ce282eab531575f5154055 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5953: 65c5eea699141e6f942ce0a8fc85db76ce53cd19 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19315: b5239b3cf416cfc73090ddd8ec7bba725278ecaa @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b5239b3cf416 drm/i915: Implement async flips for vlv/chv
6601effeab9e drm/i915: Implement async flip for ilk/snb
711c4297a93a drm/i915: Implement async flip for ivb/hsw
2fd4cac00c8a drm/i915: Implement async flips for bdw
94917f63b8f7 drm/i915: Reuse the async_flip() hook for the async flip disable w/a
89770394ed91 drm/i915: Move the async_flip bit setup into the .async_flip() hook
9655ad213677 drm/i915: Add plane vfuncs to enable/disable flip_done interrupt
2e1ed4a184df drm/i915: Generalize the async flip capability check
87a8d5da85f9 drm/i915: Drop redundant parens
492c717aeb30 drm/i915: Limit plane stride to below TILEOFF.x limit
27179a0516e5 drm/i915: WARN if plane src coords are too big
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/index.html
[-- Attachment #1.2: Type: text/html, Size: 4675 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Async flips for all ilk+ platforms (rev2)
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
` (11 preceding siblings ...)
2021-01-11 17:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Async flips for all ilk+ platforms (rev2) Patchwork
@ 2021-01-11 18:58 ` Patchwork
12 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-01-11 18:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 24372 bytes --]
== Series Details ==
Series: drm/i915: Async flips for all ilk+ platforms (rev2)
URL : https://patchwork.freedesktop.org/series/85627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9580_full -> Patchwork_19315_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_19315_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19315_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19315_full:
### IGT changes ###
#### Warnings ####
* igt@kms_async_flips@invalid-async-flip:
- shard-snb: [SKIP][1] ([fdo#109271]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-snb2/igt@kms_async_flips@invalid-async-flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-snb5/igt@kms_async_flips@invalid-async-flip.html
Known issues
------------
Here are the changes found in Patchwork_19315_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb2/igt@feature_discovery@psr2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb7/igt@feature_discovery@psr2.html
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-glk5/igt@gem_exec_whisper@basic-contexts-priority.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-glk8/igt@gem_exec_whisper@basic-contexts-priority.html
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-iclb: NOTRUN -> [SKIP][7] ([i915#768])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-iclb: NOTRUN -> [SKIP][8] ([fdo#110426] / [i915#1704])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gen3_render_linear_blits:
- shard-iclb: NOTRUN -> [SKIP][9] ([fdo#109289])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@gen3_render_linear_blits.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#454])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live@gem:
- shard-skl: [PASS][12] -> [DMESG-FAIL][13] ([i915#2927])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl2/igt@i915_selftest@live@gem.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl2/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][14] -> [DMESG-FAIL][15] ([i915#2291] / [i915#541])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl2/igt@i915_selftest@live@gt_heartbeat.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl2/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@perf:
- shard-skl: [PASS][16] -> [SKIP][17] ([fdo#109271]) +12 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl2/igt@i915_selftest@live@perf.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl2/igt@i915_selftest@live@perf.html
* igt@kms_color@pipe-d-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109278] / [i915#1149])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@kms_color@pipe-d-ctm-max.html
* igt@kms_color_chamelium@pipe-a-gamma:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@kms_color_chamelium@pipe-a-gamma.html
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl3/igt@kms_color_chamelium@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) +6 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-d-cursor-128x42-sliding:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271]) +27 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl4/igt@kms_cursor_crc@pipe-d-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-skl: [PASS][24] -> [FAIL][25] ([i915#2346])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-skl: [PASS][26] -> [INCOMPLETE][27] ([i915#2295])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
- shard-snb: [PASS][28] -> [FAIL][29] ([i915#2546]) +15 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109280]) +6 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#533])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl3/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][32] -> [FAIL][33] ([fdo#108145] / [i915#265])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl5/igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109278]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109441])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][39] -> [FAIL][40] ([i915#1542])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl6/igt@perf@polling-parameterized.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl7/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@drm_mm@all@insert_range:
- shard-skl: [INCOMPLETE][41] ([CI#80] / [i915#2485]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl1/igt@drm_mm@all@insert_range.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl5/igt@drm_mm@all@insert_range.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-glk: [TIMEOUT][43] ([i915#2918]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-glk5/igt@gem_ctx_persistence@close-replace-race.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-glk8/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [DMESG-WARN][45] ([i915#1037] / [i915#180]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl3/igt@gem_eio@in-flight-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl4/igt@gem_eio@in-flight-suspend.html
* {igt@gem_exec_fair@basic-deadline}:
- shard-glk: [FAIL][47] ([i915#2846]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-glk3/igt@gem_exec_fair@basic-deadline.html
* {igt@gem_exec_fair@basic-none-solo@rcs0}:
- shard-kbl: [FAIL][49] ([i915#2842]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* {igt@gem_exec_schedule@u-fairslice@bcs0}:
- shard-tglb: [DMESG-WARN][51] ([i915#2803]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-tglb1/igt@gem_exec_schedule@u-fairslice@bcs0.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-tglb3/igt@gem_exec_schedule@u-fairslice@bcs0.html
* {igt@gem_exec_schedule@u-fairslice@rcs0}:
- shard-kbl: [DMESG-WARN][53] ([i915#1610] / [i915#2803]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl3/igt@gem_exec_schedule@u-fairslice@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl3/igt@gem_exec_schedule@u-fairslice@rcs0.html
* {igt@gem_exec_schedule@u-fairslice@vecs0}:
- shard-iclb: [DMESG-WARN][55] ([i915#2803]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb2/igt@gem_exec_schedule@u-fairslice@vecs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [DMESG-WARN][57] ([i915#118] / [i915#95]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-glk6/igt@gem_exec_whisper@basic-fds-forked-all.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-glk4/igt@gem_exec_whisper@basic-fds-forked-all.html
* {igt@gem_vm_create@destroy-race}:
- shard-tglb: [TIMEOUT][59] ([i915#2795]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-tglb7/igt@gem_vm_create@destroy-race.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-tglb6/igt@gem_vm_create@destroy-race.html
* igt@kms_async_flips@test-time-stamp:
- shard-snb: [SKIP][61] ([fdo#109271]) -> [PASS][62] +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-snb5/igt@kms_async_flips@test-time-stamp.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-snb2/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
- shard-skl: [FAIL][63] ([i915#54]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-tglb: [FAIL][65] ([i915#79]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][67] ([i915#2598]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][69] ([i915#2122]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][71] ([i915#1188]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb7/igt@kms_psr@psr2_basic.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb2/igt@kms_psr@psr2_basic.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][77] ([i915#1804] / [i915#2684]) -> [WARN][78] ([i915#2684])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][79] ([i915#2684]) -> [WARN][80] ([i915#1804] / [i915#2684])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][81] ([i915#1188]) -> [INCOMPLETE][82] ([i915#198])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [DMESG-WARN][83] ([i915#1602]) -> [INCOMPLETE][84] ([i915#155])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][85], [FAIL][86], [FAIL][87], [FAIL][88]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#2426] / [i915#2505]) -> [FAIL][89] ([i915#2295])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl3/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl3/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl2/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-kbl6/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-kbl7/igt@runner@aborted.html
- shard-iclb: ([FAIL][90], [FAIL][91], [FAIL][92]) ([i915#1814] / [i915#2295] / [i915#2426] / [i915#2724]) -> ([FAIL][93], [FAIL][94]) ([i915#1814] / [i915#2295] / [i915#2724])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb2/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb1/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-iclb8/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb4/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-iclb1/igt@runner@aborted.html
- shard-tglb: ([FAIL][95], [FAIL][96], [FAIL][97]) ([i915#1814] / [i915#2295] / [i915#2426] / [i915#2667] / [i915#2803]) -> ([FAIL][98], [FAIL][99], [FAIL][100]) ([i915#1764] / [i915#1814] / [i915#2295] / [i915#2426] / [i915#2667] / [i915#2803])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-tglb5/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-tglb5/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-tglb1/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-tglb1/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-tglb3/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-tglb3/igt@runner@aborted.html
- shard-skl: ([FAIL][101], [FAIL][102]) ([i915#2295] / [i915#2426]) -> ([FAIL][103], [FAIL][104], [FAIL][105]) ([i915#1436] / [i915#2295] / [i915#2426])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl2/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9580/shard-skl3/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl2/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl4/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/shard-skl9/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110426]: https://bugs.freedesktop.org/show_bug.cgi?id=110426
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1704]: https://gitlab.freedesktop.org/drm/intel/issues/1704
[i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2485]: https://gitlab.freedesktop.org/drm/intel/issues/2485
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2667]: https://gitlab.freedesktop.org/drm/intel/issues/2667
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
[i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2918]: https://gitlab.freedesktop.org/drm/intel/issues/2918
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9580 -> Patchwork_19315
CI-20190529: 20190529
CI_DRM_9580: 117f9c9bca0ebb0e22ce282eab531575f5154055 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5953: 65c5eea699141e6f942ce0a8fc85db76ce53cd19 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19315: b5239b3cf416cfc73090ddd8ec7bba725278ecaa @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19315/index.html
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