[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

[Dave Liu]

The CSIZE is L1CFG0[56-63] in the e500 and e500mc core,
so we should mask 0xff, not 0x1ff.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 cpu/mpc85xx/start.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 80f9677..cfa53c0 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -244,7 +244,7 @@ switch_as:
 	lis	r3,CONFIG_SYS_INIT_RAM_ADDR at h
 	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR at l
 	mfspr	r2, L1CFG0
-	andi.	r2, r2, 0x1ff
+	andi.	r2, r2, 0xff
 	/* cache size * 1024 / (2 * L1 line size) */
 	slwi	r2, r2, (10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r2
@@ -1004,7 +1004,7 @@ unlock_ram_in_cache:
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
 	ori	r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
 	mfspr	r4,L1CFG0
-	andi.	r4,r4,0x1ff
+	andi.	r4,r4,0xff
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r4
 1:	dcbi	r0,r3
-- 
1.5.4

[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

[Kumar Gala]

On Dec 15, 2008, at 10:09 PM, Dave Liu wrote:

> The CSIZE is L1CFG0[56-63] in the e500 and e500mc core,
> so we should mask 0xff, not 0x1ff.
>
> Signed-off-by: Dave Liu <daveliu@freescale.com>
> ---
> cpu/mpc85xx/start.S |    4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)

was code breaking or just fixing it up to match the docs?

- k

[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

[Liu Dave]

> was code breaking or just fixing it up to match the docs?

not break the system, because the bit[55] is reserved zero for
e500/e500mc.
so just fixied it to match the e500/e500mc docs.

[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

[Kumar Gala]

On Dec 16, 2008, at 5:47 PM, Liu Dave wrote:

>> was code breaking or just fixing it up to match the docs?
>
> not break the system, because the bit[55] is reserved zero for
> e500/e500mc.
> so just fixied it to match the e500/e500mc docs.

Ok. I'd prefer we just expand the field to 0x3ff to match the EREF  
spec since the upper bits are reserved we'll always read them as 0 so  
no harm.  And we dont have to change the code again in the future if  
we expand into those upper bits.

- k

[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

[Liu Dave]

> Ok. I'd prefer we just expand the field to 0x3ff to match the EREF  
> spec since the upper bits are reserved we'll always read them 
> as 0 so no harm.  And we dont have to change the code again in
> the future if we expand into those upper bits.

If match the EREF, it should be 0x7ff.
and it also cause our customers confuse why not use the mask
in e500UM.
Anyway, it is easy to change them to 0x7ff for me.