From: Greentime Hu <greentime.hu@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 01/16] riscv: Rename __switch_to_aux -> fpu Date: Wed, 11 May 2022 08:31:11 +0000 [thread overview] Message-ID: <7bf1e003db9845e2a13eff15c33e3a490d34810a.1652257230.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1652257230.git.greentime.hu@sifive.com> In-Reply-To: <cover.1652257230.git.greentime.hu@sifive.com> From: Guo Ren <ren_guo@c-sky.com> The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> --- arch/riscv/include/asm/switch_to.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 0a3f4f95c555..ec83770b3d98 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -45,7 +45,7 @@ static inline void fstate_restore(struct task_struct *task, } } -static inline void __switch_to_aux(struct task_struct *prev, +static inline void __switch_to_fpu(struct task_struct *prev, struct task_struct *next) { struct pt_regs *regs; @@ -65,7 +65,7 @@ static __always_inline bool has_fpu(void) static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) #define fstate_restore(task, regs) do { } while (0) -#define __switch_to_aux(__prev, __next) do { } while (0) +#define __switch_to_fpu(__prev, __next) do { } while (0) #endif extern struct task_struct *__switch_to(struct task_struct *, @@ -76,7 +76,7 @@ do { \ struct task_struct *__prev = (prev); \ struct task_struct *__next = (next); \ if (has_fpu()) \ - __switch_to_aux(__prev, __next); \ + __switch_to_fpu(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 01/16] riscv: Rename __switch_to_aux -> fpu Date: Wed, 11 May 2022 08:31:11 +0000 [thread overview] Message-ID: <7bf1e003db9845e2a13eff15c33e3a490d34810a.1652257230.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1652257230.git.greentime.hu@sifive.com> In-Reply-To: <cover.1652257230.git.greentime.hu@sifive.com> From: Guo Ren <ren_guo@c-sky.com> The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> --- arch/riscv/include/asm/switch_to.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 0a3f4f95c555..ec83770b3d98 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -45,7 +45,7 @@ static inline void fstate_restore(struct task_struct *task, } } -static inline void __switch_to_aux(struct task_struct *prev, +static inline void __switch_to_fpu(struct task_struct *prev, struct task_struct *next) { struct pt_regs *regs; @@ -65,7 +65,7 @@ static __always_inline bool has_fpu(void) static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) #define fstate_restore(task, regs) do { } while (0) -#define __switch_to_aux(__prev, __next) do { } while (0) +#define __switch_to_fpu(__prev, __next) do { } while (0) #endif extern struct task_struct *__switch_to(struct task_struct *, @@ -76,7 +76,7 @@ do { \ struct task_struct *__prev = (prev); \ struct task_struct *__next = (next); \ if (has_fpu()) \ - __switch_to_aux(__prev, __next); \ + __switch_to_fpu(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-11 8:32 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-11 8:31 [PATCH v10 00/16] riscv: Add vector ISA support Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` Greentime Hu [this message] 2022-05-11 8:31 ` [PATCH v10 01/16] riscv: Rename __switch_to_aux -> fpu Greentime Hu 2022-05-11 8:31 ` [PATCH v10 02/16] riscv: Extending cpufeature.c to detect V-extension Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 03/16] riscv: Add new csr defines related to vector extension Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 04/16] riscv: Add vector feature to compile Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 05/16] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-16 6:47 ` Christoph Hellwig 2022-05-16 6:47 ` Christoph Hellwig 2022-11-08 17:25 ` Vineet Gupta 2022-11-08 17:25 ` Vineet Gupta 2022-05-11 8:31 ` [PATCH v10 06/16] riscv: Reset vector register Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 07/16] riscv: Add vector struct and assembler definitions Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 08/16] riscv: Add task switch support for vector Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 14:54 ` kernel test robot 2022-05-11 14:54 ` kernel test robot 2022-05-11 17:28 ` kernel test robot 2022-05-11 17:28 ` kernel test robot 2022-05-11 8:31 ` [PATCH v10 09/16] riscv: Add ptrace vector support Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 10/16] riscv: Add sigcontext save/restore for vector Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 11/16] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 12/16] riscv: Add support for kernel mode vector Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 13/16] riscv: Add vector extension XOR implementation Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 14/16] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-14 8:56 ` Guo Ren 2022-05-14 8:56 ` Guo Ren 2022-05-11 8:31 ` [PATCH v10 15/16] riscv: Add V extension to KVM ISA allow list Greentime Hu 2022-05-11 8:31 ` Greentime Hu 2022-05-11 8:31 ` [PATCH v10 16/16] riscv: KVM: Add vector lazy save/restore support Greentime Hu 2022-05-11 8:31 ` Greentime Hu
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