From: Like Xu <like.xu@linux.intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
kvm list <kvm@vger.kernel.org>, Thomas Huth <thuth@redhat.com>,
Andrew Jones <drjones@redhat.com>
Subject: Re: [kvm-unit-tests PATCH] x86: pmu: Test full-width counter writes support
Date: Wed, 12 May 2021 14:33:44 +0800 [thread overview]
Message-ID: <7c44617d-39f5-4e82-ee45-f0d142ba0dbc@linux.intel.com> (raw)
In-Reply-To: <CALMp9eQNZsk-odGHNkLkkakk+Y01qqY5Mzm3x8n0A3YizfUJ7Q@mail.gmail.com>
On 2021/5/12 5:27, Jim Mattson wrote:
> On Fri, May 29, 2020 at 12:44 AM Like Xu <like.xu@linux.intel.com> wrote:
>>
>> When the full-width writes capability is set, use the alternative MSR
>> range to write larger sign counter values (up to GP counter width).
>>
>> Signed-off-by: Like Xu <like.xu@linux.intel.com>
>> ---
>
>> + /*
>> + * MSR_IA32_PMCn supports writing values ​​up to GP counter width,
>> + * and only the lowest bits of GP counter width are valid.
>> + */
>
> Could you rewrite this comment in ASCII, please? I would do it, but
> I'm not sure what the correct translation is.
>
My first submitted patch says that
they are just Unicode "ZERO WIDTH SPACE".
https://lore.kernel.org/kvm/20200508083218.120559-2-like.xu@linux.intel.com/
Here you go:
---
From 1b058846aabcd7a85b5c5f41cb2b63b6a348bdc4 Mon Sep 17 00:00:00 2001
From: Like Xu <like.xu@linux.intel.com>
Date: Wed, 12 May 2021 14:26:40 +0800
Subject: [PATCH] x86: pmu: Fix a comment about full-width counter writes
support
Remove two Unicode characters 'ZERO WIDTH SPACE' (U+200B).
Fixes: 22f2901a0e ("x86: pmu: Test full-width counter writes support")
Reported-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
---
x86/pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/x86/pmu.c b/x86/pmu.c
index 5a3d55b..6cb3506 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -510,7 +510,7 @@ static void check_gp_counters_write_width(void)
}
/*
- * MSR_IA32_PMCn supports writing values ​​up to GP
counter width,
+ * MSR_IA32_PMCn supports writing values up to GP counter width,
* and only the lowest bits of GP counter width are valid.
*/
for (i = 0; i < num_counters; i++) {
--
2.31.1
next prev parent reply other threads:[~2021-05-12 6:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 7:43 [PATCH RESEND] Enable full width counting for KVM: x86/pmu Like Xu
2020-05-29 7:43 ` [PATCH RESEND v4 1/2] KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in Like Xu
2020-05-29 7:43 ` [PATCH RESEND v4 2/2] KVM: x86/pmu: Support full width counting Like Xu
2020-05-29 7:43 ` [kvm-unit-tests PATCH] x86: pmu: Test full-width counter writes support Like Xu
2020-06-16 10:49 ` Thomas Huth
2020-06-16 12:28 ` Paolo Bonzini
2020-06-19 19:46 ` Nadav Amit
2021-05-11 21:27 ` Jim Mattson
2021-05-12 6:33 ` Like Xu [this message]
2022-01-08 0:06 ` Jim Mattson
2022-01-10 6:34 ` Like Xu
2022-03-11 16:36 ` Thomas Huth
2020-05-29 7:43 ` [Qemu-devel PATCH] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES Like Xu
2020-05-29 7:43 ` Like Xu
2020-05-29 10:23 ` Paolo Bonzini
2020-05-29 10:23 ` Paolo Bonzini
2020-05-29 8:47 ` [PATCH RESEND] Enable full width counting for KVM: x86/pmu Paolo Bonzini
2020-05-29 8:52 ` Xu, Like
-- strict thread matches above, loose matches on Subject: below --
2020-05-08 8:32 [PATCH v3] KVM: x86/pmu: Support full width counting Like Xu
2020-05-08 8:32 ` [kvm-unit-tests PATCH] x86: pmu: Test full-width counter writes support Like Xu
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