From: Paolo Bonzini <pbonzini@redhat.com>
To: Like Xu <like.xu@linux.intel.com>
Cc: Sean Christopherson <sean.j.christopherson@intel.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Richard Henderson <rth@twiddle.net>,
Eduardo Habkost <ehabkost@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel PATCH] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES
Date: Fri, 29 May 2020 12:23:59 +0200 [thread overview]
Message-ID: <1aa68600-e48d-fa83-b2e2-b070a486afd4@redhat.com> (raw)
In-Reply-To: <20200529074347.124619-5-like.xu@linux.intel.com>
On 29/05/20 09:43, Like Xu wrote:
> + if (!cpu->enable_pmu) {
> + *ecx &= ~CPUID_EXT_PDCM;
> + }
> break;
> case 2:
> /* cache info: needed for Pentium Pro compatibility */
> @@ -6505,6 +6528,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
> }
> }
>
> + if (kvm_enabled() && cpu->enable_pmu &&
> + (kvm_arch_get_supported_cpuid(kvm_state, 1, 0, R_ECX) &
> + CPUID_EXT_PDCM)) {
> + env->features[FEAT_1_ECX] |= CPUID_EXT_PDCM;
> + }
> +
I'm dropping this hunk two hunks because it's going to break live
migration with e.g. "-cpu IvyBridge,pmu=on". We will have to add PDCM
by default only to future CPU models, but "-cpu host,pmu=on" will pick
it up automatically.
Paolo
WARNING: multiple messages have this Message-ID (diff)
From: Paolo Bonzini <pbonzini@redhat.com>
To: Like Xu <like.xu@linux.intel.com>
Cc: Wanpeng Li <wanpengli@tencent.com>,
Eduardo Habkost <ehabkost@redhat.com>,
kvm@vger.kernel.org, Joerg Roedel <joro@8bytes.org>,
Marcelo Tosatti <mtosatti@redhat.com>,
linux-kernel@vger.kernel.org,
Sean Christopherson <sean.j.christopherson@intel.com>,
qemu-devel@nongnu.org, Vitaly Kuznetsov <vkuznets@redhat.com>,
Richard Henderson <rth@twiddle.net>,
Jim Mattson <jmattson@google.com>
Subject: Re: [Qemu-devel PATCH] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES
Date: Fri, 29 May 2020 12:23:59 +0200 [thread overview]
Message-ID: <1aa68600-e48d-fa83-b2e2-b070a486afd4@redhat.com> (raw)
In-Reply-To: <20200529074347.124619-5-like.xu@linux.intel.com>
On 29/05/20 09:43, Like Xu wrote:
> + if (!cpu->enable_pmu) {
> + *ecx &= ~CPUID_EXT_PDCM;
> + }
> break;
> case 2:
> /* cache info: needed for Pentium Pro compatibility */
> @@ -6505,6 +6528,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
> }
> }
>
> + if (kvm_enabled() && cpu->enable_pmu &&
> + (kvm_arch_get_supported_cpuid(kvm_state, 1, 0, R_ECX) &
> + CPUID_EXT_PDCM)) {
> + env->features[FEAT_1_ECX] |= CPUID_EXT_PDCM;
> + }
> +
I'm dropping this hunk two hunks because it's going to break live
migration with e.g. "-cpu IvyBridge,pmu=on". We will have to add PDCM
by default only to future CPU models, but "-cpu host,pmu=on" will pick
it up automatically.
Paolo
next prev parent reply other threads:[~2020-05-29 10:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 7:43 [PATCH RESEND] Enable full width counting for KVM: x86/pmu Like Xu
2020-05-29 7:43 ` [PATCH RESEND v4 1/2] KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in Like Xu
2020-05-29 7:43 ` [PATCH RESEND v4 2/2] KVM: x86/pmu: Support full width counting Like Xu
2020-05-29 7:43 ` [kvm-unit-tests PATCH] x86: pmu: Test full-width counter writes support Like Xu
2020-06-16 10:49 ` Thomas Huth
2020-06-16 12:28 ` Paolo Bonzini
2020-06-19 19:46 ` Nadav Amit
2021-05-11 21:27 ` Jim Mattson
2021-05-12 6:33 ` Like Xu
2022-01-08 0:06 ` Jim Mattson
2022-01-10 6:34 ` Like Xu
2022-03-11 16:36 ` Thomas Huth
2020-05-29 7:43 ` [Qemu-devel PATCH] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES Like Xu
2020-05-29 7:43 ` Like Xu
2020-05-29 10:23 ` Paolo Bonzini [this message]
2020-05-29 10:23 ` Paolo Bonzini
2020-05-29 8:47 ` [PATCH RESEND] Enable full width counting for KVM: x86/pmu Paolo Bonzini
2020-05-29 8:52 ` Xu, Like
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