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* [PATCH 1/2] drm/amdgpu: add gfx rlc enter/exit safe mode through emit ring
@ 2021-06-16 10:14 Changfeng
  2021-06-16 11:01 ` Christian König
  0 siblings, 1 reply; 2+ messages in thread
From: Changfeng @ 2021-06-16 10:14 UTC (permalink / raw)
  To: Ray.Huang, amd-gfx; +Cc: changzhu

From: changzhu <Changfeng.Zhu@amd.com>

From: Changfeng <Changfeng.Zhu@amd.com>

Change-Id: Ib6065f39d61872ac0497afd11789d98e56434b40
Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 34 +++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h |  4 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 26 +++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/soc15.h      |  4 +--
 4 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
index 6373bfb47d55..d5978c3a0e02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
@@ -51,6 +51,23 @@ void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev)
 	}
 }
 
+void amdgpu_gfx_rlc_emit_enter_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+{
+	if (adev->gfx.rlc.in_safe_mode)
+		return;
+
+	/* if RLC is not enabled, do nothing */
+	if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
+		return;
+
+	if (adev->cg_flags &
+	    (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
+	     AMD_CG_SUPPORT_GFX_3D_CGCG)) {
+		adev->gfx.rlc.funcs->emit_set_safe_mode(adev, ring);
+		adev->gfx.rlc.in_safe_mode = true;
+	}
+}
+
 /**
  * amdgpu_gfx_rlc_exit_safe_mode - Set RLC out of safe mode
  *
@@ -75,6 +92,23 @@ void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev)
 	}
 }
 
+void amdgpu_gfx_rlc_emit_exit_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+{
+	if (!(adev->gfx.rlc.in_safe_mode))
+		return;
+
+	/* if RLC is not enabled, do nothing */
+	if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
+		return;
+
+	if (adev->cg_flags &
+	    (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
+	     AMD_CG_SUPPORT_GFX_3D_CGCG)) {
+		adev->gfx.rlc.funcs->emit_unset_safe_mode(adev, ring);
+		adev->gfx.rlc.in_safe_mode = false;
+	}
+}
+
 /**
  * amdgpu_gfx_rlc_init_sr - Init save restore block
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index 7a4775ab6804..9e0eb4882b84 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -117,7 +117,9 @@ typedef struct _RLC_TABLE_OF_CONTENT {
 struct amdgpu_rlc_funcs {
 	bool (*is_rlc_enabled)(struct amdgpu_device *adev);
 	void (*set_safe_mode)(struct amdgpu_device *adev);
+	void (*emit_set_safe_mode)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 	void (*unset_safe_mode)(struct amdgpu_device *adev);
+	void (*emit_unset_safe_mode)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 	int  (*init)(struct amdgpu_device *adev);
 	u32  (*get_csb_size)(struct amdgpu_device *adev);
 	void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
@@ -194,7 +196,9 @@ struct amdgpu_rlc {
 };
 
 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
+void amdgpu_gfx_rlc_emit_enter_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);
+void amdgpu_gfx_rlc_emit_exit_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 14136de8abb8..3c93fcfffa85 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4822,6 +4822,19 @@ static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
 	}
 }
 
+static void gfx_v9_0_emit_set_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+{
+	uint32_t data;
+	uint32_t reg;
+
+	data = RLC_SAFE_MODE__CMD_MASK;
+	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
+	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE);
+
+	amdgpu_ring_emit_reg_write_reg_wait(ring, reg, reg, data, data);
+
+}
+
 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
 {
 	uint32_t data;
@@ -4830,6 +4843,17 @@ static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
 }
 
+static void gfx_v9_0_emit_unset_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+{
+	uint32_t data;
+	uint32_t reg;
+
+	data = RLC_SAFE_MODE__CMD_MASK;
+	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE);
+
+	amdgpu_ring_emit_reg_write_reg_wait(ring, reg, reg, data, data);
+}
+
 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
 						bool enable)
 {
@@ -5121,7 +5145,9 @@ static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset
 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
 	.is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
 	.set_safe_mode = gfx_v9_0_set_safe_mode,
+	.emit_set_safe_mode = gfx_v9_0_emit_set_safe_mode,
 	.unset_safe_mode = gfx_v9_0_unset_safe_mode,
+	.emit_unset_safe_mode = gfx_v9_0_emit_unset_safe_mode,
 	.init = gfx_v9_0_rlc_init,
 	.get_csb_size = gfx_v9_0_get_csb_size,
 	.get_csb_buffer = gfx_v9_0_get_csb_buffer,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 034cfdfc4dbe..717abf73f718 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -28,8 +28,8 @@
 #include "nbio_v7_0.h"
 #include "nbio_v7_4.h"
 
-#define SOC15_FLUSH_GPU_TLB_NUM_WREG		6
-#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	3
+#define SOC15_FLUSH_GPU_TLB_NUM_WREG		8
+#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	5
 
 extern const struct amd_ip_funcs soc15_common_ip_funcs;
 
-- 
2.17.1

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amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 2+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: add gfx rlc enter/exit safe mode through emit ring
  2021-06-16 10:14 [PATCH 1/2] drm/amdgpu: add gfx rlc enter/exit safe mode through emit ring Changfeng
@ 2021-06-16 11:01 ` Christian König
  0 siblings, 0 replies; 2+ messages in thread
From: Christian König @ 2021-06-16 11:01 UTC (permalink / raw)
  To: Changfeng, Ray.Huang, amd-gfx

This needs a commit message and a bit of justification.

Christian.

Am 16.06.21 um 12:14 schrieb Changfeng:
> From: changzhu <Changfeng.Zhu@amd.com>
>
> From: Changfeng <Changfeng.Zhu@amd.com>
>
> Change-Id: Ib6065f39d61872ac0497afd11789d98e56434b40
> Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 34 +++++++++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h |  4 +++
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 26 +++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/soc15.h      |  4 +--
>   4 files changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> index 6373bfb47d55..d5978c3a0e02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> @@ -51,6 +51,23 @@ void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev)
>   	}
>   }
>   
> +void amdgpu_gfx_rlc_emit_enter_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
> +{
> +	if (adev->gfx.rlc.in_safe_mode)
> +		return;
> +
> +	/* if RLC is not enabled, do nothing */
> +	if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
> +		return;
> +
> +	if (adev->cg_flags &
> +	    (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
> +	     AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> +		adev->gfx.rlc.funcs->emit_set_safe_mode(adev, ring);
> +		adev->gfx.rlc.in_safe_mode = true;
> +	}
> +}
> +
>   /**
>    * amdgpu_gfx_rlc_exit_safe_mode - Set RLC out of safe mode
>    *
> @@ -75,6 +92,23 @@ void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev)
>   	}
>   }
>   
> +void amdgpu_gfx_rlc_emit_exit_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
> +{
> +	if (!(adev->gfx.rlc.in_safe_mode))
> +		return;
> +
> +	/* if RLC is not enabled, do nothing */
> +	if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
> +		return;
> +
> +	if (adev->cg_flags &
> +	    (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
> +	     AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> +		adev->gfx.rlc.funcs->emit_unset_safe_mode(adev, ring);
> +		adev->gfx.rlc.in_safe_mode = false;
> +	}
> +}
> +
>   /**
>    * amdgpu_gfx_rlc_init_sr - Init save restore block
>    *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> index 7a4775ab6804..9e0eb4882b84 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> @@ -117,7 +117,9 @@ typedef struct _RLC_TABLE_OF_CONTENT {
>   struct amdgpu_rlc_funcs {
>   	bool (*is_rlc_enabled)(struct amdgpu_device *adev);
>   	void (*set_safe_mode)(struct amdgpu_device *adev);
> +	void (*emit_set_safe_mode)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
>   	void (*unset_safe_mode)(struct amdgpu_device *adev);
> +	void (*emit_unset_safe_mode)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
>   	int  (*init)(struct amdgpu_device *adev);
>   	u32  (*get_csb_size)(struct amdgpu_device *adev);
>   	void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
> @@ -194,7 +196,9 @@ struct amdgpu_rlc {
>   };
>   
>   void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
> +void amdgpu_gfx_rlc_emit_enter_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring);
>   void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);
> +void amdgpu_gfx_rlc_emit_exit_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring);
>   int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
>   int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
>   int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 14136de8abb8..3c93fcfffa85 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4822,6 +4822,19 @@ static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
>   	}
>   }
>   
> +static void gfx_v9_0_emit_set_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
> +{
> +	uint32_t data;
> +	uint32_t reg;
> +
> +	data = RLC_SAFE_MODE__CMD_MASK;
> +	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
> +	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE);
> +
> +	amdgpu_ring_emit_reg_write_reg_wait(ring, reg, reg, data, data);
> +
> +}
> +
>   static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
>   {
>   	uint32_t data;
> @@ -4830,6 +4843,17 @@ static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
>   	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
>   }
>   
> +static void gfx_v9_0_emit_unset_safe_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring)
> +{
> +	uint32_t data;
> +	uint32_t reg;
> +
> +	data = RLC_SAFE_MODE__CMD_MASK;
> +	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE);
> +
> +	amdgpu_ring_emit_reg_write_reg_wait(ring, reg, reg, data, data);
> +}
> +
>   static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
>   						bool enable)
>   {
> @@ -5121,7 +5145,9 @@ static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset
>   static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
>   	.is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
>   	.set_safe_mode = gfx_v9_0_set_safe_mode,
> +	.emit_set_safe_mode = gfx_v9_0_emit_set_safe_mode,
>   	.unset_safe_mode = gfx_v9_0_unset_safe_mode,
> +	.emit_unset_safe_mode = gfx_v9_0_emit_unset_safe_mode,
>   	.init = gfx_v9_0_rlc_init,
>   	.get_csb_size = gfx_v9_0_get_csb_size,
>   	.get_csb_buffer = gfx_v9_0_get_csb_buffer,
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index 034cfdfc4dbe..717abf73f718 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -28,8 +28,8 @@
>   #include "nbio_v7_0.h"
>   #include "nbio_v7_4.h"
>   
> -#define SOC15_FLUSH_GPU_TLB_NUM_WREG		6
> -#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	3
> +#define SOC15_FLUSH_GPU_TLB_NUM_WREG		8
> +#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	5
>   
>   extern const struct amd_ip_funcs soc15_common_ip_funcs;
>   

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-06-16 11:01 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
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2021-06-16 10:14 [PATCH 1/2] drm/amdgpu: add gfx rlc enter/exit safe mode through emit ring Changfeng
2021-06-16 11:01 ` Christian König

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