* [Intel-gfx] [PATCH v3 01/18] drm/i915: move and group hdcp under display.hdcp
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 02/18] drm/i915: move and group max_bw and bw_obj under display.bw Jani Nikula
` (21 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display hdcp related members under drm_i915_private display
sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 9 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +++++++++---------
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 -
4 files changed, 77 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index fbe329e90c1e..4a184eac57c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -19,6 +19,7 @@
struct drm_i915_private;
struct i915_audio_component;
+struct i915_hdcp_comp_master;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_funcs;
@@ -231,6 +232,14 @@ struct intel_display {
wait_queue_head_t wait_queue;
} gmbus;
+ struct {
+ struct i915_hdcp_comp_master *master;
+ bool comp_added;
+
+ /* Mutex to protect the above hdcp component related values. */
+ struct mutex comp_mutex;
+ } hdcp;
+
struct {
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 638495991c49..6406fd487ee5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -210,12 +210,12 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
return false;
/* MEI interface is solid */
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ if (!dev_priv->display.hdcp.comp_added || !dev_priv->display.hdcp.master) {
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return false;
}
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
/* Sink's capability for HDCP2.2 */
hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
@@ -1146,11 +1146,11 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1158,7 +1158,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
if (ret)
drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1176,11 +1176,11 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1190,7 +1190,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1204,18 +1204,18 @@ static int hdcp2_verify_hprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1230,11 +1230,11 @@ hdcp2_store_pairing_info(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1242,7 +1242,7 @@ hdcp2_store_pairing_info(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Store pairing info failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1257,11 +1257,11 @@ hdcp2_prepare_lc_init(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1269,7 +1269,7 @@ hdcp2_prepare_lc_init(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Prepare lc_init failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1284,11 +1284,11 @@ hdcp2_verify_lprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1296,7 +1296,7 @@ hdcp2_verify_lprime(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify L_Prime failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1310,11 +1310,11 @@ static int hdcp2_prepare_skey(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1322,7 +1322,7 @@ static int hdcp2_prepare_skey(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Get session key failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1339,11 +1339,11 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1353,7 +1353,7 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm,
"Verify rep topology failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1368,18 +1368,18 @@ hdcp2_verify_mprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify mprime failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1392,11 +1392,11 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1404,7 +1404,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1416,17 +1416,17 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
ret = comp->ops->close_hdcp_session(comp->mei_dev,
&dig_port->hdcp_port_data);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -2144,10 +2144,10 @@ static int i915_hdcp_component_bind(struct device *i915_kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
drm_dbg(&dev_priv->drm, "I915 HDCP comp bind\n");
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data;
- dev_priv->hdcp_master->mei_dev = mei_kdev;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ dev_priv->display.hdcp.master = (struct i915_hdcp_comp_master *)data;
+ dev_priv->display.hdcp.master->mei_dev = mei_kdev;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return 0;
}
@@ -2158,9 +2158,9 @@ static void i915_hdcp_component_unbind(struct device *i915_kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
drm_dbg(&dev_priv->drm, "I915 HDCP comp unbind\n");
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_master = NULL;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ dev_priv->display.hdcp.master = NULL;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
}
static const struct component_ops i915_hdcp_component_ops = {
@@ -2251,19 +2251,19 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
if (!is_hdcp2_supported(dev_priv))
return;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display.hdcp.comp_added);
- dev_priv->hdcp_comp_added = true;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ dev_priv->display.hdcp.comp_added = true;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops,
I915_COMPONENT_HDCP);
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n",
ret);
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_comp_added = false;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ dev_priv->display.hdcp.comp_added = false;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return;
}
}
@@ -2476,14 +2476,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv)
{
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- if (!dev_priv->hdcp_comp_added) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ if (!dev_priv->display.hdcp.comp_added) {
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return;
}
- dev_priv->hdcp_comp_added = false;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ dev_priv->display.hdcp.comp_added = false;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 053a7dab5506..e1f77b0973d7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -338,7 +338,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->display.audio.mutex);
mutex_init(&dev_priv->display.wm.wm_mutex);
mutex_init(&dev_priv->display.pps.mutex);
- mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->display.hdcp.comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 443ed6dac92a..51afb5e744d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -538,12 +538,6 @@ struct drm_i915_private {
struct i915_drm_clients clients;
- struct i915_hdcp_comp_master *hdcp_master;
- bool hdcp_comp_added;
-
- /* Mutex to protect the above hdcp component related values. */
- struct mutex hdcp_comp_mutex;
-
/* The TTM device structure. */
struct ttm_device bdev;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 02/18] drm/i915: move and group max_bw and bw_obj under display.bw
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 01/18] drm/i915: move and group hdcp under display.hdcp Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 03/18] drm/i915: move opregion to display.opregion Jani Nikula
` (20 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display bandwidth related members under drm_i915_private display
sub-struct.
v2: Rebase
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 42 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 21 ++++++++++
.../drm/i915/display/intel_modeset_setup.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 19 ---------
4 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index c87bc3117ae4..61308ebe48aa 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -324,7 +324,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
int ipqdepth, ipqdepthpch = 16;
int dclk_max;
int maxdebw;
- int num_groups = ARRAY_SIZE(dev_priv->max_bw);
+ int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
int i, ret;
ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
@@ -340,7 +340,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &dev_priv->max_bw[i];
+ struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
int clpchgroup;
int j;
@@ -395,7 +395,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
int dclk_max;
int maxdebw, peakbw;
int clperchgroup;
- int num_groups = ARRAY_SIZE(dev_priv->max_bw);
+ int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
int i, ret;
ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
@@ -431,7 +431,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &dev_priv->max_bw[i];
+ struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
struct intel_bw_info *bi_next;
int clpchgroup;
int j;
@@ -439,7 +439,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
if (i < num_groups - 1) {
- bi_next = &dev_priv->max_bw[i + 1];
+ bi_next = &dev_priv->display.bw.max[i + 1];
if (clpchgroup < clperchgroup)
bi_next->num_planes = (ipqdepth - clpchgroup) /
@@ -500,7 +500,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
static void dg2_get_bw_info(struct drm_i915_private *i915)
{
unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
- int num_groups = ARRAY_SIZE(i915->max_bw);
+ int num_groups = ARRAY_SIZE(i915->display.bw.max);
int i;
/*
@@ -511,7 +511,7 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
* whereas DG2-G11 platforms have 38 GB/s.
*/
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &i915->max_bw[i];
+ struct intel_bw_info *bi = &i915->display.bw.max[i];
bi->num_planes = 1;
/* Need only one dummy QGV point per group */
@@ -532,9 +532,9 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
*/
num_planes = max(1, num_planes);
- for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
+ for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
const struct intel_bw_info *bi =
- &dev_priv->max_bw[i];
+ &dev_priv->display.bw.max[i];
/*
* Pcode will not expose all QGV points when
@@ -560,9 +560,9 @@ static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
*/
num_planes = max(1, num_planes);
- for (i = ARRAY_SIZE(dev_priv->max_bw) - 1; i >= 0; i--) {
+ for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
const struct intel_bw_info *bi =
- &dev_priv->max_bw[i];
+ &dev_priv->display.bw.max[i];
/*
* Pcode will not expose all QGV points when
@@ -575,14 +575,14 @@ static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
return bi->deratedbw[qgv_point];
}
- return dev_priv->max_bw[0].deratedbw[qgv_point];
+ return dev_priv->display.bw.max[0].deratedbw[qgv_point];
}
static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
int psf_gv_point)
{
const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
+ &dev_priv->display.bw.max[0];
return bi->psf_bw[psf_gv_point];
}
@@ -703,7 +703,7 @@ intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
- bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
+ bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
return to_intel_bw_state(bw_state);
}
@@ -714,7 +714,7 @@ intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
- bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
+ bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
return to_intel_bw_state(bw_state);
}
@@ -725,7 +725,7 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
- bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj);
+ bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
if (IS_ERR(bw_state))
return ERR_CAST(bw_state);
@@ -932,8 +932,8 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
{
- unsigned int num_psf_gv_points = i915->max_bw[0].num_psf_gv_points;
- unsigned int num_qgv_points = i915->max_bw[0].num_qgv_points;
+ unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
u16 qgv_points = 0, psf_points = 0;
/*
@@ -1006,8 +1006,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
int i, ret;
u16 qgv_points = 0, psf_points = 0;
unsigned int max_bw_point = 0, max_bw = 0;
- unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
- unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
+ unsigned int num_qgv_points = dev_priv->display.bw.max[0].num_qgv_points;
+ unsigned int num_psf_gv_points = dev_priv->display.bw.max[0].num_psf_gv_points;
bool changed = false;
/* FIXME earlier gens need some checks too */
@@ -1162,7 +1162,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv)
if (!state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
&state->base, &intel_bw_funcs);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 4a184eac57c3..0ea479b6c0c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -14,6 +14,7 @@
#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
+#include "intel_global_state.h"
#include "intel_gmbus.h"
#include "intel_pm_types.h"
@@ -34,6 +35,12 @@ struct intel_hotplug_funcs;
struct intel_initial_plane_config;
struct intel_overlay;
+/* Amount of SAGV/QGV points, BSpec precisely defines this */
+#define I915_NUM_QGV_POINTS 8
+
+/* Amount of PSF GV points, BSpec precisely defines this */
+#define I915_NUM_PSF_GV_POINTS 3
+
struct intel_display_funcs {
/*
* Returns the active state of the crtc, and if the crtc is active,
@@ -208,6 +215,20 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ struct intel_global_obj obj;
+
+ struct intel_bw_info {
+ /* for each QGV point */
+ unsigned int deratedbw[I915_NUM_QGV_POINTS];
+ /* for each PSF GV point */
+ unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
+ u8 num_qgv_points;
+ u8 num_psf_gv_points;
+ u8 num_planes;
+ } max[6];
+ } bw;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 4b30e8228a5e..5010a18fd993 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -30,7 +30,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_encoder *encoder;
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_bw_state *bw_state =
- to_intel_bw_state(i915->bw_obj.state);
+ to_intel_bw_state(i915->display.bw.obj.state);
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
@@ -535,7 +535,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
for_each_intel_crtc(&i915->drm, crtc) {
struct intel_bw_state *bw_state =
- to_intel_bw_state(i915->bw_obj.state);
+ to_intel_bw_state(i915->display.bw.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51afb5e744d7..2c63cdb64511 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -44,7 +44,6 @@
#include "display/intel_dsb.h"
#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
-#include "display/intel_global_state.h"
#include "display/intel_opregion.h"
#include "gem/i915_gem_context_types.h"
@@ -204,14 +203,8 @@ i915_fence_timeout(const struct drm_i915_private *i915)
return i915_fence_context_timeout(i915, U64_MAX);
}
-/* Amount of SAGV/QGV points, BSpec precisely defines this */
-#define I915_NUM_QGV_POINTS 8
-
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-/* Amount of PSF GV points, BSpec precisely defines this */
-#define I915_NUM_PSF_GV_POINTS 3
-
struct intel_vbt_data {
/* bdb version */
u16 version;
@@ -470,18 +463,6 @@ struct drm_i915_private {
u8 num_psf_gv_points;
} dram_info;
- struct intel_bw_info {
- /* for each QGV point */
- unsigned int deratedbw[I915_NUM_QGV_POINTS];
- /* for each PSF GV point */
- unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
- u8 num_qgv_points;
- u8 num_psf_gv_points;
- u8 num_planes;
- } max_bw[6];
-
- struct intel_global_obj bw_obj;
-
struct intel_runtime_pm runtime_pm;
struct i915_perf perf;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 03/18] drm/i915: move opregion to display.opregion
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 01/18] drm/i915: move and group hdcp under display.hdcp Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 02/18] drm/i915: move and group max_bw and bw_obj under display.bw Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 04/18] drm/i915: move and group cdclk under display.cdclk Jani Nikula
` (19 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display opregion related members under drm_i915_private display
sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
.../gpu/drm/i915/display/intel_display_core.h | 2 +
.../drm/i915/display/intel_display_debugfs.c | 6 ++-
drivers/gpu/drm/i915/display/intel_opregion.c | 42 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_irq.c | 2 +-
6 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 81d6cfbd2615..cc47c49d7e3d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3080,7 +3080,7 @@ static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
*/
void intel_bios_init(struct drm_i915_private *i915)
{
- const struct vbt_header *vbt = i915->opregion.vbt;
+ const struct vbt_header *vbt = i915->display.opregion.vbt;
struct vbt_header *oprom_vbt = NULL;
const struct bdb_header *bdb;
@@ -3287,7 +3287,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin)
* additional data. Trust that if the VBT was written into
* the OpRegion then they have validated the LVDS's existence.
*/
- if (i915->opregion.vbt)
+ if (i915->display.opregion.vbt)
return true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 0ea479b6c0c9..4257555fcc3a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
#include "intel_dpll_mgr.h"
#include "intel_global_state.h"
#include "intel_gmbus.h"
+#include "intel_opregion.h"
#include "intel_pm_types.h"
struct drm_i915_private;
@@ -284,6 +285,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_hotplug hotplug;
+ struct intel_opregion opregion;
struct intel_overlay *overlay;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 13c855b59f7d..619523f85a18 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -103,7 +103,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
static int i915_opregion(struct seq_file *m, void *unused)
{
- struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_opregion *opregion = &i915->display.opregion;
if (opregion->header)
seq_write(m, opregion->header, OPREGION_SIZE);
@@ -113,7 +114,8 @@ static int i915_opregion(struct seq_file *m, void *unused)
static int i915_vbt(struct seq_file *m, void *unused)
{
- struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_opregion *opregion = &i915->display.opregion;
if (opregion->vbt)
seq_write(m, opregion->vbt, opregion->vbt_size);
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 1c0c745c142d..caa07ef34f21 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -252,7 +252,7 @@ struct opregion_asle_ext {
static int check_swsci_function(struct drm_i915_private *i915, u32 function)
{
- struct opregion_swsci *swsci = i915->opregion.swsci;
+ struct opregion_swsci *swsci = i915->display.opregion.swsci;
u32 main_function, sub_function;
if (!swsci)
@@ -265,11 +265,11 @@ static int check_swsci_function(struct drm_i915_private *i915, u32 function)
/* Check if we can call the function. See swsci_setup for details. */
if (main_function == SWSCI_SBCB) {
- if ((i915->opregion.swsci_sbcb_sub_functions &
+ if ((i915->display.opregion.swsci_sbcb_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
} else if (main_function == SWSCI_GBDA) {
- if ((i915->opregion.swsci_gbda_sub_functions &
+ if ((i915->display.opregion.swsci_gbda_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
}
@@ -280,7 +280,7 @@ static int check_swsci_function(struct drm_i915_private *i915, u32 function)
static int swsci(struct drm_i915_private *dev_priv,
u32 function, u32 parm, u32 *parm_out)
{
- struct opregion_swsci *swsci = dev_priv->opregion.swsci;
+ struct opregion_swsci *swsci = dev_priv->display.opregion.swsci;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
u32 scic, dslp;
u16 swsci_val;
@@ -462,7 +462,7 @@ static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp)
{
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
- struct opregion_asle *asle = dev_priv->opregion.asle;
+ struct opregion_asle *asle = dev_priv->display.opregion.asle;
struct drm_device *dev = &dev_priv->drm;
drm_dbg(&dev_priv->drm, "bclp = 0x%08x\n", bclp);
@@ -586,8 +586,8 @@ static void asle_work(struct work_struct *work)
struct intel_opregion *opregion =
container_of(work, struct intel_opregion, asle_work);
struct drm_i915_private *dev_priv =
- container_of(opregion, struct drm_i915_private, opregion);
- struct opregion_asle *asle = dev_priv->opregion.asle;
+ container_of(opregion, struct drm_i915_private, display.opregion);
+ struct opregion_asle *asle = dev_priv->display.opregion.asle;
u32 aslc_stat = 0;
u32 aslc_req;
@@ -635,8 +635,8 @@ static void asle_work(struct work_struct *work)
void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
- if (dev_priv->opregion.asle)
- schedule_work(&dev_priv->opregion.asle_work);
+ if (dev_priv->display.opregion.asle)
+ schedule_work(&dev_priv->display.opregion.asle_work);
}
#define ACPI_EV_DISPLAY_SWITCH (1<<0)
@@ -692,7 +692,7 @@ static void set_did(struct intel_opregion *opregion, int i, u32 val)
static void intel_didl_outputs(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
int i = 0, max_outputs;
@@ -731,7 +731,7 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv)
static void intel_setup_cadls(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
int i = 0;
@@ -761,7 +761,7 @@ static void intel_setup_cadls(struct drm_i915_private *dev_priv)
static void swsci_setup(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
bool requested_callbacks = false;
u32 tmp;
@@ -839,7 +839,7 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = {
static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
const struct firmware *fw = NULL;
const char *name = dev_priv->params.vbt_firmware;
int ret;
@@ -879,7 +879,7 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv)
int intel_opregion_setup(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
u32 asls, mboxes;
char buf[sizeof(OPREGION_SIGNATURE)];
@@ -1106,7 +1106,7 @@ struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
{
struct drm_connector *connector = &intel_connector->base;
struct drm_i915_private *i915 = to_i915(connector->dev);
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
const void *in_edid;
const struct edid *edid;
struct edid *new_edid;
@@ -1141,7 +1141,7 @@ struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
bool intel_opregion_headless_sku(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
struct opregion_header *header = opregion->header;
if (!header || header->over.major < 2 ||
@@ -1153,7 +1153,7 @@ bool intel_opregion_headless_sku(struct drm_i915_private *i915)
void intel_opregion_register(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
if (!opregion->header)
return;
@@ -1169,7 +1169,7 @@ void intel_opregion_register(struct drm_i915_private *i915)
void intel_opregion_resume(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
if (!opregion->header)
return;
@@ -1200,7 +1200,7 @@ void intel_opregion_resume(struct drm_i915_private *i915)
void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
if (!opregion->header)
return;
@@ -1210,7 +1210,7 @@ void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state)
if (opregion->asle)
opregion->asle->ardy = ASLE_ARDY_NOT_READY;
- cancel_work_sync(&i915->opregion.asle_work);
+ cancel_work_sync(&i915->display.opregion.asle_work);
if (opregion->acpi)
opregion->acpi->drdy = 0;
@@ -1218,7 +1218,7 @@ void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state)
void intel_opregion_unregister(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
intel_opregion_suspend(i915, PCI_D1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c63cdb64511..21a7d2d83703 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -44,7 +44,6 @@
#include "display/intel_dsb.h"
#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
-#include "display/intel_opregion.h"
#include "gem/i915_gem_context_types.h"
#include "gem/i915_gem_lmem.h"
@@ -331,7 +330,6 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct intel_fbc *fbc[I915_MAX_FBCS];
- struct intel_opregion opregion;
struct intel_vbt_data vbt;
bool preserve_bios_swizzle;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c2f2d7b8d964..515648cd1233 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -595,7 +595,7 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
static bool i915_has_asle(struct drm_i915_private *dev_priv)
{
- if (!dev_priv->opregion.asle)
+ if (!dev_priv->display.opregion.asle)
return false;
return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 04/18] drm/i915: move and group cdclk under display.cdclk
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (2 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 03/18] drm/i915: move opregion to display.opregion Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 05/18] drm/i915: move backlight to display.backlight Jani Nikula
` (18 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display cdclk related members under drm_i915_private display
sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
drivers/gpu/drm/i915/display/intel_audio.c | 6 +-
.../gpu/drm/i915/display/intel_backlight.c | 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 206 +++++++++---------
drivers/gpu/drm/i915/display/intel_cdclk.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
.../gpu/drm/i915/display/intel_display_core.h | 14 ++
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 15 --
15 files changed, 141 insertions(+), 142 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 861dcd2eb890..a5be4af792cb 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -202,7 +202,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
* Should measure whether using a lower cdclk w/o IPS
*/
if (IS_BROADWELL(i915) &&
- crtc_state->pixel_rate > i915->max_cdclk_freq * 95 / 100)
+ crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)
return false;
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index a74fc79b7910..aacbc6da84ef 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -532,7 +532,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
vdsc_bpp = crtc_state->dsc.compressed_bpp;
- cdclk = i915->cdclk.hw.cdclk;
+ cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
link_clk = crtc_state->port_clock;
@@ -971,7 +971,7 @@ void intel_audio_cdclk_change_post(struct drm_i915_private *i915)
struct aud_ts_cdclk_m_n aud_ts;
if (DISPLAY_VER(i915) >= 13) {
- get_aud_ts_cdclk_m_n(i915->cdclk.hw.ref, i915->cdclk.hw.cdclk, &aud_ts);
+ get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);
intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);
intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
@@ -1119,7 +1119,7 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev)
if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
return -ENODEV;
- return dev_priv->cdclk.hw.cdclk;
+ return dev_priv->display.cdclk.hw.cdclk;
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 681ebcda97ad..354e2794ed92 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1113,7 +1113,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_PINEVIEW(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);
}
@@ -1131,7 +1131,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_G4X(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d8f7bccf9ff9..ed05070b7307 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -548,7 +548,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -1026,7 +1026,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
drm_err(&dev_priv->drm, "DPLL0 not locked\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
/* We'll want to keep using the current vco from now on. */
skl_set_preferred_cdclk_vco(dev_priv, vco);
@@ -1040,7 +1040,7 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
@@ -1049,7 +1049,7 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
switch (cdclk) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display.cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 308571:
@@ -1098,13 +1098,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
skl_dpll0_disable(dev_priv);
cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco) {
+ if (dev_priv->display.cdclk.hw.vco != vco) {
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
@@ -1116,7 +1116,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
intel_de_posting_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
skl_dpll0_enable(dev_priv, vco);
/* Wa Display #1183: skl,kbl,cfl */
@@ -1151,11 +1151,11 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
goto sanitize;
intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display.cdclk.hw.vco == 0 ||
+ dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1166,7 +1166,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
*/
cdctl = intel_de_read(dev_priv, CDCLK_CTL);
expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
- skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+ skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
if (cdctl == expected)
/* All well; nothing to sanitize */
return;
@@ -1175,9 +1175,9 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display.cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display.cdclk.hw.vco = -1;
}
static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1186,19 +1186,19 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
skl_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0) {
+ if (dev_priv->display.cdclk.hw.cdclk != 0 &&
+ dev_priv->display.cdclk.hw.vco != 0) {
/*
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
if (dev_priv->skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display.cdclk.hw.vco);
return;
}
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
@@ -1211,7 +1211,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1352,35 +1352,35 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk >= min_cdclk)
return table[i].cdclk;
drm_WARN(&dev_priv->drm, 1,
"Cannot satisfy minimum cdclk %d with refclk %u\n",
- min_cdclk, dev_priv->cdclk.hw.ref);
+ min_cdclk, dev_priv->display.cdclk.hw.ref);
return 0;
}
static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
- if (cdclk == dev_priv->cdclk.hw.bypass)
+ if (cdclk == dev_priv->display.cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk == cdclk)
- return dev_priv->cdclk.hw.ref * table[i].ratio;
+ return dev_priv->display.cdclk.hw.ref * table[i].ratio;
drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->cdclk.hw.ref);
+ cdclk, dev_priv->display.cdclk.hw.ref);
return 0;
}
@@ -1554,12 +1554,12 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
@@ -1571,7 +1571,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
@@ -1583,12 +1583,12 @@ static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
u32 val;
val = ICL_CDCLK_PLL_RATIO(ratio);
@@ -1601,12 +1601,12 @@ static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
u32 val;
/* Write PLL ratio without disabling */
@@ -1625,7 +1625,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
val &= ~BXT_DE_PLL_FREQ_REQ;
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
@@ -1655,7 +1655,7 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display.cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 2:
@@ -1672,19 +1672,19 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
- if (cdclk == dev_priv->cdclk.hw.bypass)
+ if (cdclk == dev_priv->display.cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk == cdclk)
return table[i].waveform;
drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->cdclk.hw.ref);
+ cdclk, dev_priv->display.cdclk.hw.ref);
return 0xffff;
}
@@ -1721,22 +1721,22 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
- if (dev_priv->cdclk.hw.vco != vco)
+ if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
icl_cdclk_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
icl_cdclk_pll_enable(dev_priv, vco);
} else {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
bxt_de_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
bxt_de_pll_enable(dev_priv, vco);
}
@@ -1803,7 +1803,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* Can't read out the voltage level :(
* Let's just assume everything is as expected.
*/
- dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+ dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
@@ -1812,10 +1812,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
int cdclk, clock, vco;
intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display.cdclk.hw.vco == 0 ||
+ dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1833,32 +1833,32 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
/* Make sure this is a legal cdclk value for the platform */
- cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
- if (cdclk != dev_priv->cdclk.hw.cdclk)
+ cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
+ if (cdclk != dev_priv->display.cdclk.hw.cdclk)
goto sanitize;
/* Make sure the VCO is correct for the cdclk */
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- if (vco != dev_priv->cdclk.hw.vco)
+ if (vco != dev_priv->display.cdclk.hw.vco)
goto sanitize;
expected = skl_cdclk_decimal(cdclk);
/* Figure out what CD2X divider we should be using for this cdclk */
if (has_cdclk_squasher(dev_priv))
- clock = dev_priv->cdclk.hw.vco / 2;
+ clock = dev_priv->display.cdclk.hw.vco / 2;
else
- clock = dev_priv->cdclk.hw.cdclk;
+ clock = dev_priv->display.cdclk.hw.cdclk;
expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display.cdclk.hw.vco);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
* enable otherwise.
*/
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
- dev_priv->cdclk.hw.cdclk >= 500000)
+ dev_priv->display.cdclk.hw.cdclk >= 500000)
expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
if (cdctl == expected)
@@ -1869,10 +1869,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display.cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display.cdclk.hw.vco = -1;
}
static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1881,11 +1881,11 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
bxt_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0)
+ if (dev_priv->display.cdclk.hw.cdclk != 0 &&
+ dev_priv->display.cdclk.hw.vco != 0)
return;
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display.cdclk.hw;
/*
* FIXME:
@@ -1902,7 +1902,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1916,7 +1916,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
* intel_cdclk_init_hw - Initialize CDCLK hardware
* @i915: i915 device
*
- * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
+ * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
* sanitizing the state of the hardware if needed. This is generally done only
* during the display core initialization sequence, after which the DMC will
* take care of turning CDCLK off/on as needed.
@@ -2077,7 +2077,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
+ if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
@@ -2124,9 +2124,9 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
intel_audio_cdclk_change_post(dev_priv);
if (drm_WARN(&dev_priv->drm,
- intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
+ intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
}
}
@@ -2315,7 +2315,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
*/
min_cdclk = max_t(int, min_cdclk,
min_t(int, crtc_state->pixel_rate,
- dev_priv->max_cdclk_freq));
+ dev_priv->display.cdclk.max_cdclk_freq));
}
return min_cdclk;
@@ -2368,10 +2368,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
for_each_pipe(dev_priv, pipe)
min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
- if (min_cdclk > dev_priv->max_cdclk_freq) {
+ if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
drm_dbg_kms(&dev_priv->drm,
"required cdclk (%d kHz) exceeds max (%d kHz)\n",
- min_cdclk, dev_priv->max_cdclk_freq);
+ min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
return -EINVAL;
}
@@ -2643,7 +2643,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *cdclk_state;
- cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
+ cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
if (IS_ERR(cdclk_state))
return ERR_CAST(cdclk_state);
@@ -2693,7 +2693,7 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
if (!cdclk_state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
&cdclk_state->base, &intel_cdclk_funcs);
return 0;
@@ -2799,7 +2799,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
- int max_cdclk_freq = dev_priv->max_cdclk_freq;
+ int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
if (DISPLAY_VER(dev_priv) >= 10)
return 2 * max_cdclk_freq;
@@ -2825,19 +2825,19 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
if (IS_JSL_EHL(dev_priv)) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 552000;
+ if (dev_priv->display.cdclk.hw.ref == 24000)
+ dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
- dev_priv->max_cdclk_freq = 556800;
+ dev_priv->display.cdclk.max_cdclk_freq = 556800;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 648000;
+ if (dev_priv->display.cdclk.hw.ref == 24000)
+ dev_priv->display.cdclk.max_cdclk_freq = 648000;
else
- dev_priv->max_cdclk_freq = 652800;
+ dev_priv->display.cdclk.max_cdclk_freq = 652800;
} else if (IS_GEMINILAKE(dev_priv)) {
- dev_priv->max_cdclk_freq = 316800;
+ dev_priv->display.cdclk.max_cdclk_freq = 316800;
} else if (IS_BROXTON(dev_priv)) {
- dev_priv->max_cdclk_freq = 624000;
+ dev_priv->display.cdclk.max_cdclk_freq = 624000;
} else if (DISPLAY_VER(dev_priv) == 9) {
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
@@ -2859,7 +2859,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
else
max_cdclk = 308571;
- dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
+ dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
} else if (IS_BROADWELL(dev_priv)) {
/*
* FIXME with extra cooling we can allow
@@ -2868,26 +2868,26 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
* available? PCI ID, VTB, something else?
*/
if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display.cdclk.max_cdclk_freq = 450000;
else if (IS_BDW_ULX(dev_priv))
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display.cdclk.max_cdclk_freq = 450000;
else if (IS_BDW_ULT(dev_priv))
- dev_priv->max_cdclk_freq = 540000;
+ dev_priv->display.cdclk.max_cdclk_freq = 540000;
else
- dev_priv->max_cdclk_freq = 675000;
+ dev_priv->display.cdclk.max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 320000;
+ dev_priv->display.cdclk.max_cdclk_freq = 320000;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 400000;
+ dev_priv->display.cdclk.max_cdclk_freq = 400000;
} else {
/* otherwise assume cdclk is fixed */
- dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
+ dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
}
dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
- dev_priv->max_cdclk_freq);
+ dev_priv->display.cdclk.max_cdclk_freq);
drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
dev_priv->max_dotclk_freq);
@@ -2901,7 +2901,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2911,7 +2911,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
*/
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_de_write(dev_priv, GMBUSFREQ_VLV,
- DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
+ DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
}
static int dg1_rawclk(struct drm_i915_private *dev_priv)
@@ -3195,32 +3195,32 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->cdclk.table = dg2_cdclk_table;
+ dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+ dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
else
- dev_priv->cdclk.table = adlp_cdclk_table;
+ dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->cdclk.table = rkl_cdclk_table;
+ dev_priv->display.cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
if (IS_GEMINILAKE(dev_priv))
- dev_priv->cdclk.table = glk_cdclk_table;
+ dev_priv->display.cdclk.table = glk_cdclk_table;
else
- dev_priv->cdclk.table = bxt_cdclk_table;
+ dev_priv->display.cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
} else if (IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b535cf6a7d9e..c674879a84a5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -77,9 +77,9 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
#define intel_atomic_get_old_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
#define intel_atomic_get_new_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
int intel_cdclk_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 72e2091d9fcb..7f978612ddc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2658,7 +2658,7 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
if (DISPLAY_VER(i915) < 4) {
- clock_limit = i915->max_cdclk_freq * 9 / 10;
+ clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
/*
* Enable double wide mode when the dot clock
@@ -8394,11 +8394,11 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
+ cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
intel_update_cdclk(i915);
- intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
- cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
+ intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
+ cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
}
static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
@@ -8765,7 +8765,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
intel_hdcp_component_init(i915);
- if (i915->max_cdclk_freq == 0)
+ if (i915->display.cdclk.max_cdclk_freq == 0)
intel_update_max_cdclk(i915);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 4257555fcc3a..88e6bc61f5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -11,6 +11,7 @@
#include <linux/wait.h>
#include <linux/workqueue.h>
+#include "intel_cdclk.h"
#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
@@ -25,6 +26,7 @@ struct i915_hdcp_comp_master;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_funcs;
+struct intel_cdclk_vals;
struct intel_color_funcs;
struct intel_crtc;
struct intel_crtc_state;
@@ -230,6 +232,18 @@ struct intel_display {
} max[6];
} bw;
+ struct {
+ /* The current hardware cdclk configuration */
+ struct intel_cdclk_config hw;
+
+ /* cdclk, divider, and ratio table from bspec */
+ const struct intel_cdclk_vals *table;
+
+ struct intel_global_obj obj;
+
+ unsigned int max_cdclk_freq;
+ } cdclk;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b19a1bc26277..438a368ba358 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1310,7 +1310,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e442055f1d6c..7482580f62fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -972,7 +972,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
- intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
+ intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw,
&cdclk_config));
gen9_assert_dbuf_enabled(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6cb695e506f5..9a230857ca63 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -720,7 +720,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (bigjoiner) {
u32 max_bpp_bigjoiner =
- i915->max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * 48 /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
@@ -1546,7 +1546,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
- if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+ if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq ||
pipe_config->bigjoiner_pipes) {
if (pipe_config->dsc.slice_count < 2) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 227fbee88b89..f2ad1d09ab43 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -86,7 +86,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
* divide by 2000 and use that
*/
if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
+ freq = dev_priv->display.cdclk.hw.cdclk;
else
freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
return DIV_ROUND_CLOSEST(freq, 2000);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bbe142056c7c..d324bc8b5ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1858,7 +1858,7 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
}
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -3967,7 +3967,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 5010a18fd993..def782794184 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -32,7 +32,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_bw_state *bw_state =
to_intel_bw_state(i915->display.bw.obj.state);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(i915->cdclk.obj.state);
+ to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->dbuf.obj.state);
struct intel_crtc_state *crtc_state =
@@ -415,7 +415,7 @@ static void readout_plane_state(struct drm_i915_private *i915)
static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
{
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(i915->cdclk.obj.state);
+ to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->dbuf.obj.state);
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 40bdd4cb629f..108b9e76c32e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -504,8 +504,8 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
drm_puts(p, "no P-state info available\n");
}
- drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
- drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
+ drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
+ drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
intel_runtime_pm_put(uncore->rpm, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21a7d2d83703..2dd9233ebc63 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -37,7 +37,6 @@
#include <drm/drm_connector.h>
#include <drm/ttm/ttm_device.h>
-#include "display/intel_cdclk.h"
#include "display/intel_display.h"
#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
@@ -74,9 +73,6 @@
struct drm_i915_clock_gating_funcs;
struct drm_i915_gem_object;
struct drm_i915_private;
-struct intel_cdclk_config;
-struct intel_cdclk_state;
-struct intel_cdclk_vals;
struct intel_connector;
struct intel_dp;
struct intel_encoder;
@@ -339,23 +335,12 @@ struct drm_i915_private {
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
- unsigned int max_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
- struct {
- /* The current hardware cdclk configuration */
- struct intel_cdclk_config hw;
-
- /* cdclk, divider, and ratio table from bspec */
- const struct intel_cdclk_vals *table;
-
- struct intel_global_obj obj;
- } cdclk;
-
struct {
/* The current hardware dbuf configuration */
u8 enabled_slices;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 05/18] drm/i915: move backlight to display.backlight
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (3 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 04/18] drm/i915: move and group cdclk under display.cdclk Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 06/18] drm/i915: move mipi_mmio_base to display.dsi Jani Nikula
` (17 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display backlight related members under drm_i915_private display
sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_backlight.c | 28 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 5 ++++
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 --
4 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 354e2794ed92..f20f3c06ca96 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -305,7 +305,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state,
if (!panel->backlight.present || !conn_state->crtc)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0);
@@ -321,7 +321,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state,
if (panel->backlight.enabled)
intel_panel_actually_set_backlight(conn_state, hw_level);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level)
@@ -465,14 +465,14 @@ void intel_backlight_disable(const struct drm_connector_state *old_conn_state)
return;
}
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
if (panel->backlight.device)
panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
panel->backlight.enabled = false;
panel->backlight.funcs->disable(old_conn_state, 0);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,
@@ -815,11 +815,11 @@ void intel_backlight_enable(const struct intel_crtc_state *crtc_state,
drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(pipe));
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
__intel_backlight_enable(crtc_state, conn_state);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
@@ -829,12 +829,12 @@ static u32 intel_panel_get_backlight(struct intel_connector *connector)
struct intel_panel *panel = &connector->panel;
u32 val = 0;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
if (panel->backlight.enabled)
val = panel->backlight.funcs->get(connector, intel_connector_get_pipe(connector));
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
drm_dbg_kms(&dev_priv->drm, "get backlight PWM = %d\n", val);
return val;
@@ -862,7 +862,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta
if (!panel->backlight.present)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0);
@@ -872,7 +872,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta
if (panel->backlight.enabled)
intel_panel_actually_set_backlight(conn_state, hw_level);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
static int intel_backlight_device_update_status(struct backlight_device *bd)
@@ -1591,11 +1591,11 @@ void intel_backlight_update(struct intel_atomic_state *state,
if (!panel->backlight.present)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
if (!panel->backlight.enabled)
__intel_backlight_enable(crtc_state, conn_state);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
@@ -1620,9 +1620,9 @@ int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
return -ENODEV;
/* set level and max in panel struct */
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
ret = panel->backlight.funcs->setup(connector, pipe);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 88e6bc61f5e6..cc54793ae9bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -218,6 +218,11 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ /* backlight registers and fields in struct intel_panel */
+ struct mutex lock;
+ } backlight;
+
struct {
struct intel_global_obj obj;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index e1f77b0973d7..3aedc33ded57 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -330,7 +330,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
- mutex_init(&dev_priv->backlight_lock);
+ mutex_init(&dev_priv->display.backlight.lock);
mutex_init(&dev_priv->sb_lock);
cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2dd9233ebc63..5241195c7afb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -330,9 +330,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
- /* backlight registers and fields in struct intel_panel */
- struct mutex backlight_lock;
-
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 06/18] drm/i915: move mipi_mmio_base to display.dsi
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (4 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 05/18] drm/i915: move backlight to display.backlight Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 07/18] drm/i915: move vbt to display.vbt Jani Nikula
` (16 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display DSI related members under drm_i915_private display
sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Abstract mmio base member access in register definitions in a macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 5 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 188 +++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 3 -
4 files changed, 102 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index cc54793ae9bf..63ff660b9479 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -249,6 +249,11 @@ struct intel_display {
unsigned int max_cdclk_freq;
} cdclk;
+ struct {
+ /* VLV/CHV/BXT/GLK DSI MMIO register base address */
+ u32 mmio_base;
+ } dsi;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 784ae52059d1..233d0a8902ec 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1872,9 +1872,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
return;
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
+ dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
else
- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+ dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
if (!intel_dsi)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
index 356e51515346..e065b8f2ee08 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
@@ -11,6 +11,8 @@
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000
+#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base)
+
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
@@ -96,8 +98,8 @@
/* MIPI DSI Controller and D-PHY registers */
-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
+#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
+#define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800)
#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
#define ULPS_STATE_MASK (3 << 1)
@@ -106,11 +108,11 @@
#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
#define DEVICE_READY (1 << 0)
-#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
-#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
+#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004)
+#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804)
#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
-#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
-#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
+#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008)
+#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808)
#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
#define TEARING_EFFECT (1 << 31)
#define SPL_PKT_SENT_INTERRUPT (1 << 30)
@@ -145,8 +147,8 @@
#define RXSOT_SYNC_ERROR (1 << 1)
#define RXSOT_ERROR (1 << 0)
-#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
-#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
+#define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c)
+#define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c)
#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
#define CMD_MODE_NOT_SUPPORTED (0 << 13)
@@ -168,76 +170,76 @@
#define DATA_LANES_PRG_REG_SHIFT 0
#define DATA_LANES_PRG_REG_MASK (7 << 0)
-#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
-#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
+#define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010)
+#define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810)
#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
-#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
+#define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014)
+#define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814)
#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
-#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
+#define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018)
+#define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818)
#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
#define TURN_AROUND_TIMEOUT_MASK 0x3f
-#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
-#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
+#define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c)
+#define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c)
#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
#define DEVICE_RESET_TIMER_MASK 0xffff
-#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
-#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
+#define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020)
+#define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820)
#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
#define VERTICAL_ADDRESS_SHIFT 16
#define VERTICAL_ADDRESS_MASK (0xffff << 16)
#define HORIZONTAL_ADDRESS_SHIFT 0
#define HORIZONTAL_ADDRESS_MASK 0xffff
-#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
-#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
+#define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024)
+#define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824)
#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
#define DBI_FIFO_EMPTY_HALF (0 << 0)
#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
/* regs below are bits 15:0 */
-#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
-#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
+#define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028)
+#define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828)
#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
-#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
-#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
+#define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c)
+#define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c)
#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
-#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
-#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
+#define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030)
+#define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830)
#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
-#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
-#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
+#define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034)
+#define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834)
#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
-#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
-#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
+#define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038)
+#define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838)
#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
-#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
-#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
+#define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c)
+#define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c)
#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
-#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
-#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
+#define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040)
+#define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840)
#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
-#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
-#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
+#define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044)
+#define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844)
#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
-#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
-#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
+#define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048)
+#define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848)
#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
#define DPI_LP_MODE (1 << 6)
#define BACKLIGHT_OFF (1 << 5)
@@ -247,27 +249,27 @@
#define TURN_ON (1 << 1)
#define SHUTDOWN (1 << 0)
-#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
-#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
+#define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c)
+#define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c)
#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
#define COMMAND_BYTE_SHIFT 0
#define COMMAND_BYTE_MASK (0x3f << 0)
-#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
-#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
+#define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050)
+#define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850)
#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
#define MASTER_INIT_TIMER_SHIFT 0
#define MASTER_INIT_TIMER_MASK (0xffff << 0)
-#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
-#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
+#define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054)
+#define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854)
#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
#define MAX_RETURN_PKT_SIZE_SHIFT 0
#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
-#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
-#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
+#define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058)
+#define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858)
#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
#define DISABLE_VIDEO_BTA (1 << 3)
@@ -276,8 +278,8 @@
#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
#define VIDEO_MODE_BURST (3 << 0)
-#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
-#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
+#define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c)
+#define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c)
#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
#define BXT_DPHY_DEFEATURE_EN (1 << 8)
@@ -290,35 +292,35 @@
#define CLOCKSTOP (1 << 1)
#define EOT_DISABLE (1 << 0)
-#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
-#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
+#define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060)
+#define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860)
#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
-#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
-#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
+#define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4)
#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
-#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
-#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
+#define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898)
#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
/* bits 31:0 */
-#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
-#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
+#define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064)
+#define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864)
#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
/* bits 31:0 */
-#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
-#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
+#define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068)
+#define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868)
#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
-#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
-#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
+#define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c)
+#define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c)
#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
-#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
-#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
+#define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070)
+#define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870)
#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
#define LONG_PACKET_WORD_COUNT_SHIFT 8
#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
@@ -330,8 +332,8 @@
#define DATA_TYPE_MASK (0x3f << 0)
/* data type values, see include/video/mipi_display.h */
-#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
-#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
+#define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074)
+#define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874)
#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
#define DPI_FIFO_EMPTY (1 << 28)
#define DBI_FIFO_EMPTY (1 << 27)
@@ -348,15 +350,15 @@
#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
#define HS_DATA_FIFO_FULL (1 << 0)
-#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
-#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
+#define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078)
+#define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878)
#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
#define DBI_HS_LP_MODE_MASK (1 << 0)
#define DBI_LP_MODE (1 << 0)
#define DBI_HS_MODE (0 << 0)
-#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
-#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
+#define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080)
+#define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880)
#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
#define EXIT_ZERO_COUNT_SHIFT 24
#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
@@ -367,34 +369,34 @@
#define PREPARE_COUNT_SHIFT 0
#define PREPARE_COUNT_MASK (0x3f << 0)
-#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
-#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
+#define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084)
+#define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884)
#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
-#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
-#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088)
+#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888)
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
#define LP_HS_SSW_CNT_SHIFT 16
#define LP_HS_SSW_CNT_MASK (0xffff << 16)
#define HS_LP_PWR_SW_CNT_SHIFT 0
#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
-#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
-#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
+#define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c)
+#define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c)
#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
#define STOP_STATE_STALL_COUNTER_SHIFT 0
#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
-#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
-#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
+#define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090)
+#define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890)
#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
-#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
-#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
+#define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094)
+#define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894)
#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
#define RX_CONTENTION_DETECTED (1 << 0)
/* XXX: only pipe A ?!? */
-#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
+#define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100)
#define DBI_TYPEC_ENABLE (1 << 31)
#define DBI_TYPEC_WIP (1 << 30)
#define DBI_TYPEC_OPTION_SHIFT 28
@@ -407,8 +409,8 @@
/* MIPI adapter registers */
-#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
-#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
+#define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104)
+#define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904)
#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
@@ -440,21 +442,21 @@
#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
#define GLK_MIPIIO_ENABLE (1 << 0)
-#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
-#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
+#define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108)
+#define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908)
#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
#define DATA_MEM_ADDRESS_SHIFT 5
#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
#define DATA_VALID (1 << 0)
-#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
-#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
+#define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c)
+#define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c)
#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
#define DATA_LENGTH_SHIFT 0
#define DATA_LENGTH_MASK (0xfffff << 0)
-#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
-#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
+#define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110)
+#define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910)
#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
#define COMMAND_MEM_ADDRESS_SHIFT 5
#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
@@ -462,18 +464,18 @@
#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
#define COMMAND_VALID (1 << 0)
-#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
-#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
+#define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114)
+#define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914)
#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
-#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
-#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
+#define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118)
+#define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918)
#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
-#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
-#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
+#define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138)
+#define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938)
#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
#define READ_DATA_VALID(n) (1 << (n))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5241195c7afb..a8fc77a852b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -299,9 +299,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- /* MMIO base address for MIPI regs */
- u32 mipi_mmio_base;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 07/18] drm/i915: move vbt to display.vbt
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (5 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 06/18] drm/i915: move mipi_mmio_base to display.dsi Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 08/18] drm/i915: move fbc to display.fbc Jani Nikula
` (15 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display VBT related members under drm_i915_private display
sub-struct.
v2: Rebase
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 212 +++++++++---------
drivers/gpu/drm/i915/display/intel_crt.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_display_core.h | 38 ++++
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 14 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/display/intel_panel.c | 2 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 18 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 37 ---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
15 files changed, 188 insertions(+), 187 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index cc47c49d7e3d..a18eedca9ab3 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -159,7 +159,7 @@ find_section(struct drm_i915_private *i915,
{
struct bdb_block_entry *entry;
- list_for_each_entry(entry, &i915->vbt.bdb_blocks, node) {
+ list_for_each_entry(entry, &i915->display.vbt.bdb_blocks, node) {
if (entry->section_id == section_id)
return entry->data + 3;
}
@@ -501,7 +501,7 @@ init_bdb_block(struct drm_i915_private *i915,
return;
}
- list_add_tail(&entry->node, &i915->vbt.bdb_blocks);
+ list_add_tail(&entry->node, &i915->display.vbt.bdb_blocks);
}
static void init_bdb_blocks(struct drm_i915_private *i915,
@@ -878,7 +878,7 @@ parse_lfp_data(struct drm_i915_private *i915,
if (!tail)
return;
- if (i915->vbt.version >= 188) {
+ if (i915->display.vbt.version >= 188) {
panel->vbt.seamless_drrs_min_refresh_rate =
tail->seamless_drrs_min_refresh_rate[panel_type];
drm_dbg_kms(&i915->drm,
@@ -904,7 +904,7 @@ parse_generic_dtd(struct drm_i915_private *i915,
* first on VBT >= 229, but still fall back to trying the old LFP
* block if that fails.
*/
- if (i915->vbt.version < 229)
+ if (i915->display.vbt.version < 229)
return;
generic_dtd = find_section(i915, BDB_GENERIC_DTD);
@@ -1008,12 +1008,12 @@ parse_lfp_backlight(struct drm_i915_private *i915,
}
panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
- if (i915->vbt.version >= 191) {
+ if (i915->display.vbt.version >= 191) {
size_t exp_size;
- if (i915->vbt.version >= 236)
+ if (i915->display.vbt.version >= 236)
exp_size = sizeof(struct bdb_lfp_backlight_data);
- else if (i915->vbt.version >= 234)
+ else if (i915->display.vbt.version >= 234)
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
else
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
@@ -1030,14 +1030,14 @@ parse_lfp_backlight(struct drm_i915_private *i915,
panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
panel->vbt.backlight.active_low_pwm = entry->active_low_pwm;
- if (i915->vbt.version >= 234) {
+ if (i915->display.vbt.version >= 234) {
u16 min_level;
bool scale;
level = backlight_data->brightness_level[panel_type].level;
min_level = backlight_data->brightness_min_level[panel_type].level;
- if (i915->vbt.version >= 236)
+ if (i915->display.vbt.version >= 236)
scale = backlight_data->brightness_precision_bits[panel_type] == 16;
else
scale = level > 255;
@@ -1134,37 +1134,37 @@ parse_general_features(struct drm_i915_private *i915)
if (!general)
return;
- i915->vbt.int_tv_support = general->int_tv_support;
+ i915->display.vbt.int_tv_support = general->int_tv_support;
/* int_crt_support can't be trusted on earlier platforms */
- if (i915->vbt.version >= 155 &&
+ if (i915->display.vbt.version >= 155 &&
(HAS_DDI(i915) || IS_VALLEYVIEW(i915)))
- i915->vbt.int_crt_support = general->int_crt_support;
- i915->vbt.lvds_use_ssc = general->enable_ssc;
- i915->vbt.lvds_ssc_freq =
+ i915->display.vbt.int_crt_support = general->int_crt_support;
+ i915->display.vbt.lvds_use_ssc = general->enable_ssc;
+ i915->display.vbt.lvds_ssc_freq =
intel_bios_ssc_frequency(i915, general->ssc_freq);
- i915->vbt.display_clock_mode = general->display_clock_mode;
- i915->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
- if (i915->vbt.version >= 181) {
- i915->vbt.orientation = general->rotate_180 ?
+ i915->display.vbt.display_clock_mode = general->display_clock_mode;
+ i915->display.vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
+ if (i915->display.vbt.version >= 181) {
+ i915->display.vbt.orientation = general->rotate_180 ?
DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP :
DRM_MODE_PANEL_ORIENTATION_NORMAL;
} else {
- i915->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ i915->display.vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
}
- if (i915->vbt.version >= 249 && general->afc_startup_config) {
- i915->vbt.override_afc_startup = true;
- i915->vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7;
+ if (i915->display.vbt.version >= 249 && general->afc_startup_config) {
+ i915->display.vbt.override_afc_startup = true;
+ i915->display.vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7;
}
drm_dbg_kms(&i915->drm,
"BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
- i915->vbt.int_tv_support,
- i915->vbt.int_crt_support,
- i915->vbt.lvds_use_ssc,
- i915->vbt.lvds_ssc_freq,
- i915->vbt.display_clock_mode,
- i915->vbt.fdi_rx_polarity_inverted);
+ i915->display.vbt.int_tv_support,
+ i915->display.vbt.int_crt_support,
+ i915->display.vbt.lvds_use_ssc,
+ i915->display.vbt.lvds_ssc_freq,
+ i915->display.vbt.display_clock_mode,
+ i915->display.vbt.fdi_rx_polarity_inverted);
}
static const struct child_device_config *
@@ -1190,7 +1190,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915)
return;
}
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (child->slave_addr != SLAVE_ADDR1 &&
@@ -1214,7 +1214,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915)
child->slave_addr,
(child->dvo_port == DEVICE_PORT_DVOB) ?
"SDVOB" : "SDVOC");
- mapping = &i915->vbt.sdvo_mappings[child->dvo_port - 1];
+ mapping = &i915->display.vbt.sdvo_mappings[child->dvo_port - 1];
if (!mapping->initialized) {
mapping->dvo_port = child->dvo_port;
mapping->slave_addr = child->slave_addr;
@@ -1265,7 +1265,7 @@ parse_driver_features(struct drm_i915_private *i915)
* interpretation, but real world VBTs seem to.
*/
if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)
- i915->vbt.int_lvds_support = 0;
+ i915->display.vbt.int_lvds_support = 0;
} else {
/*
* FIXME it's not clear which BDB version has the LVDS config
@@ -1278,10 +1278,10 @@ parse_driver_features(struct drm_i915_private *i915)
* in the wild with the bits correctly populated. Version
* 108 (on i85x) does not have the bits correctly populated.
*/
- if (i915->vbt.version >= 134 &&
+ if (i915->display.vbt.version >= 134 &&
driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&
driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
- i915->vbt.int_lvds_support = 0;
+ i915->display.vbt.int_lvds_support = 0;
}
}
@@ -1295,7 +1295,7 @@ parse_panel_driver_features(struct drm_i915_private *i915,
if (!driver)
return;
- if (i915->vbt.version < 228) {
+ if (i915->display.vbt.version < 228) {
drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n",
driver->drrs_enabled);
/*
@@ -1328,7 +1328,7 @@ parse_power_conservation_features(struct drm_i915_private *i915,
panel->vbt.vrr = true; /* matches Windows behaviour */
- if (i915->vbt.version < 228)
+ if (i915->display.vbt.version < 228)
return;
power = find_section(i915, BDB_LFP_POWER);
@@ -1354,10 +1354,10 @@ parse_power_conservation_features(struct drm_i915_private *i915,
panel->vbt.drrs_type = DRRS_TYPE_NONE;
}
- if (i915->vbt.version >= 232)
+ if (i915->display.vbt.version >= 232)
panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type);
- if (i915->vbt.version >= 233)
+ if (i915->display.vbt.version >= 233)
panel->vbt.vrr = panel_bool(power->vrr_feature_enabled,
panel_type);
}
@@ -1393,7 +1393,7 @@ parse_edp(struct drm_i915_private *i915,
panel->vbt.edp.pps = *edp_pps;
- if (i915->vbt.version >= 224) {
+ if (i915->display.vbt.version >= 224) {
panel->vbt.edp.rate =
edp->edp_fast_link_training_rate[panel_type] * 20;
} else {
@@ -1472,7 +1472,7 @@ parse_edp(struct drm_i915_private *i915,
break;
}
- if (i915->vbt.version >= 173) {
+ if (i915->display.vbt.version >= 173) {
u8 vswing;
/* Don't read from VBT if module parameter has valid value*/
@@ -1488,7 +1488,7 @@ parse_edp(struct drm_i915_private *i915,
panel->vbt.edp.drrs_msa_timing_delay =
panel_bits(edp->sdrrs_msa_timing_delay, panel_type, 2);
- if (i915->vbt.version >= 244)
+ if (i915->display.vbt.version >= 244)
panel->vbt.edp.max_link_rate =
edp->edp_max_port_link_rate[panel_type] * 20;
}
@@ -1520,7 +1520,7 @@ parse_psr(struct drm_i915_private *i915,
* New psr options 0=500us, 1=100us, 2=2500us, 3=0us
* Old decimal value is wake up time in multiples of 100 us.
*/
- if (i915->vbt.version >= 205 &&
+ if (i915->display.vbt.version >= 205 &&
(DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
switch (psr_table->tp1_wakeup_time) {
case 0:
@@ -1566,7 +1566,7 @@ parse_psr(struct drm_i915_private *i915,
panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
}
- if (i915->vbt.version >= 226) {
+ if (i915->display.vbt.version >= 226) {
u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
wakeup_time = panel_bits(wakeup_time, panel_type, 2);
@@ -1598,7 +1598,7 @@ static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
{
enum port port_bc = DISPLAY_VER(i915) >= 11 ? PORT_B : PORT_C;
- if (!panel->vbt.dsi.config->dual_link || i915->vbt.version < 197) {
+ if (!panel->vbt.dsi.config->dual_link || i915->display.vbt.version < 197) {
panel->vbt.dsi.bl_ports = BIT(port);
if (panel->vbt.dsi.config->cabc_supported)
panel->vbt.dsi.cabc_ports = BIT(port);
@@ -2053,7 +2053,7 @@ parse_compression_parameters(struct drm_i915_private *i915)
u16 block_size;
int index;
- if (i915->vbt.version < 198)
+ if (i915->display.vbt.version < 198)
return;
params = find_section(i915, BDB_COMPRESSION_PARAMETERS);
@@ -2073,7 +2073,7 @@ parse_compression_parameters(struct drm_i915_private *i915)
}
}
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (!child->compression_enable)
@@ -2207,7 +2207,7 @@ static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
return PORT_NONE;
for_each_port(port) {
- devdata = i915->vbt.ports[port];
+ devdata = i915->display.vbt.ports[port];
if (devdata && ddc_pin == devdata->child.ddc_pin)
return port;
@@ -2256,7 +2256,7 @@ static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata,
* there are real machines (eg. Asrock B250M-HDV) where VBT has both
* port A and port E with the same AUX ch and we must pick port E :(
*/
- child = &i915->vbt.ports[p]->child;
+ child = &i915->display.vbt.ports[p]->child;
child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
@@ -2273,7 +2273,7 @@ static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
return PORT_NONE;
for_each_port(port) {
- devdata = i915->vbt.ports[port];
+ devdata = i915->display.vbt.ports[port];
if (devdata && aux_ch == devdata->child.aux_channel)
return port;
@@ -2308,7 +2308,7 @@ static void sanitize_aux_ch(struct intel_bios_encoder_data *devdata,
* there are real machines (eg. Asrock B250M-HDV) where VBT has both
* port A and port E with the same AUX ch and we must pick port E :(
*/
- child = &i915->vbt.ports[p]->child;
+ child = &i915->display.vbt.ports[p]->child;
child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
child->aux_channel = 0;
@@ -2482,10 +2482,10 @@ static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate)
static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 216)
+ if (!devdata || devdata->i915->display.vbt.version < 216)
return 0;
- if (devdata->i915->vbt.version >= 230)
+ if (devdata->i915->display.vbt.version >= 230)
return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate);
else
return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
@@ -2546,7 +2546,7 @@ intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)
static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 158)
+ if (!devdata || devdata->i915->display.vbt.version < 158)
return -1;
return devdata->child.hdmi_level_shifter_value;
@@ -2554,7 +2554,7 @@ static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *de
static int _intel_bios_max_tmds_clock(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 204)
+ if (!devdata || devdata->i915->display.vbt.version < 204)
return 0;
switch (devdata->child.hdmi_max_data_rate) {
@@ -2663,7 +2663,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
return;
}
- if (i915->vbt.ports[port]) {
+ if (i915->display.vbt.ports[port]) {
drm_dbg_kms(&i915->drm,
"More than one child device for port %c in VBT, using the first.\n",
port_name(port));
@@ -2678,7 +2678,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
if (intel_bios_encoder_supports_dp(devdata))
sanitize_aux_ch(devdata, port);
- i915->vbt.ports[port] = devdata;
+ i915->display.vbt.ports[port] = devdata;
}
static bool has_ddi_port_info(struct drm_i915_private *i915)
@@ -2694,12 +2694,12 @@ static void parse_ddi_ports(struct drm_i915_private *i915)
if (!has_ddi_port_info(i915))
return;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node)
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node)
parse_ddi_port(devdata);
for_each_port(port) {
- if (i915->vbt.ports[port])
- print_ddi_port(i915->vbt.ports[port], port);
+ if (i915->display.vbt.ports[port])
+ print_ddi_port(i915->display.vbt.ports[port], port);
}
}
@@ -2732,33 +2732,33 @@ parse_general_definitions(struct drm_i915_private *i915)
bus_pin = defs->crt_ddc_gmbus_pin;
drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
if (intel_gmbus_is_valid_pin(i915, bus_pin))
- i915->vbt.crt_ddc_pin = bus_pin;
+ i915->display.vbt.crt_ddc_pin = bus_pin;
- if (i915->vbt.version < 106) {
+ if (i915->display.vbt.version < 106) {
expected_size = 22;
- } else if (i915->vbt.version < 111) {
+ } else if (i915->display.vbt.version < 111) {
expected_size = 27;
- } else if (i915->vbt.version < 195) {
+ } else if (i915->display.vbt.version < 195) {
expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
- } else if (i915->vbt.version == 195) {
+ } else if (i915->display.vbt.version == 195) {
expected_size = 37;
- } else if (i915->vbt.version <= 215) {
+ } else if (i915->display.vbt.version <= 215) {
expected_size = 38;
- } else if (i915->vbt.version <= 237) {
+ } else if (i915->display.vbt.version <= 237) {
expected_size = 39;
} else {
expected_size = sizeof(*child);
BUILD_BUG_ON(sizeof(*child) < 39);
drm_dbg(&i915->drm,
"Expected child device config size for VBT version %u not known; assuming %u\n",
- i915->vbt.version, expected_size);
+ i915->display.vbt.version, expected_size);
}
/* Flag an error for unexpected size, but continue anyway. */
if (defs->child_dev_size != expected_size)
drm_err(&i915->drm,
"Unexpected child device config size %u (expected %u for VBT version %u)\n",
- defs->child_dev_size, expected_size, i915->vbt.version);
+ defs->child_dev_size, expected_size, i915->display.vbt.version);
/* The legacy sized child device config is the minimum we need. */
if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
@@ -2794,10 +2794,10 @@ parse_general_definitions(struct drm_i915_private *i915)
memcpy(&devdata->child, child,
min_t(size_t, defs->child_dev_size, sizeof(*child)));
- list_add_tail(&devdata->node, &i915->vbt.display_devices);
+ list_add_tail(&devdata->node, &i915->display.vbt.display_devices);
}
- if (list_empty(&i915->vbt.display_devices))
+ if (list_empty(&i915->display.vbt.display_devices))
drm_dbg_kms(&i915->drm,
"no child dev is parsed from VBT\n");
}
@@ -2806,25 +2806,25 @@ parse_general_definitions(struct drm_i915_private *i915)
static void
init_vbt_defaults(struct drm_i915_private *i915)
{
- i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
+ i915->display.vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
/* general features */
- i915->vbt.int_tv_support = 1;
- i915->vbt.int_crt_support = 1;
+ i915->display.vbt.int_tv_support = 1;
+ i915->display.vbt.int_crt_support = 1;
/* driver features */
- i915->vbt.int_lvds_support = 1;
+ i915->display.vbt.int_lvds_support = 1;
/* Default to using SSC */
- i915->vbt.lvds_use_ssc = 1;
+ i915->display.vbt.lvds_use_ssc = 1;
/*
* Core/SandyBridge/IvyBridge use alternative (120MHz) reference
* clock for LVDS.
*/
- i915->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915,
- !HAS_PCH_SPLIT(i915));
+ i915->display.vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915,
+ !HAS_PCH_SPLIT(i915));
drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n",
- i915->vbt.lvds_ssc_freq);
+ i915->display.vbt.lvds_ssc_freq);
}
/* Common defaults which may be overridden by VBT. */
@@ -2885,7 +2885,7 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
if (port == PORT_A)
child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR;
- list_add_tail(&devdata->node, &i915->vbt.display_devices);
+ list_add_tail(&devdata->node, &i915->display.vbt.display_devices);
drm_dbg_kms(&i915->drm,
"Generating default VBT child device with type 0x04%x on port %c\n",
@@ -2893,7 +2893,7 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
}
/* Bypass some minimum baseline VBT version checks */
- i915->vbt.version = 155;
+ i915->display.vbt.version = 155;
}
static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
@@ -3084,8 +3084,8 @@ void intel_bios_init(struct drm_i915_private *i915)
struct vbt_header *oprom_vbt = NULL;
const struct bdb_header *bdb;
- INIT_LIST_HEAD(&i915->vbt.display_devices);
- INIT_LIST_HEAD(&i915->vbt.bdb_blocks);
+ INIT_LIST_HEAD(&i915->display.vbt.display_devices);
+ INIT_LIST_HEAD(&i915->display.vbt.bdb_blocks);
if (!HAS_DISPLAY(i915)) {
drm_dbg_kms(&i915->drm,
@@ -3113,11 +3113,11 @@ void intel_bios_init(struct drm_i915_private *i915)
goto out;
bdb = get_bdb_header(vbt);
- i915->vbt.version = bdb->version;
+ i915->display.vbt.version = bdb->version;
drm_dbg_kms(&i915->drm,
"VBT signature \"%.*s\", BDB version %d\n",
- (int)sizeof(vbt->signature), vbt->signature, i915->vbt.version);
+ (int)sizeof(vbt->signature), vbt->signature, i915->display.vbt.version);
init_bdb_blocks(i915, bdb);
@@ -3174,13 +3174,13 @@ void intel_bios_driver_remove(struct drm_i915_private *i915)
struct intel_bios_encoder_data *devdata, *nd;
struct bdb_block_entry *entry, *ne;
- list_for_each_entry_safe(devdata, nd, &i915->vbt.display_devices, node) {
+ list_for_each_entry_safe(devdata, nd, &i915->display.vbt.display_devices, node) {
list_del(&devdata->node);
kfree(devdata->dsc);
kfree(devdata);
}
- list_for_each_entry_safe(entry, ne, &i915->vbt.bdb_blocks, node) {
+ list_for_each_entry_safe(entry, ne, &i915->display.vbt.bdb_blocks, node) {
list_del(&entry->node);
kfree(entry);
}
@@ -3214,13 +3214,13 @@ bool intel_bios_is_tv_present(struct drm_i915_private *i915)
const struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
- if (!i915->vbt.int_tv_support)
+ if (!i915->display.vbt.int_tv_support)
return false;
- if (list_empty(&i915->vbt.display_devices))
+ if (list_empty(&i915->display.vbt.display_devices))
return true;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
/*
@@ -3257,10 +3257,10 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin)
const struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
- if (list_empty(&i915->vbt.display_devices))
+ if (list_empty(&i915->display.vbt.display_devices))
return true;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
/* If the device type is not LFP, continue.
@@ -3306,7 +3306,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port)
if (WARN_ON(!has_ddi_port_info(i915)))
return true;
- return i915->vbt.ports[port];
+ return i915->display.vbt.ports[port];
}
/**
@@ -3366,7 +3366,7 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *i915,
const struct child_device_config *child;
u8 dvo_port;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
@@ -3465,7 +3465,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
const struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
@@ -3496,7 +3496,7 @@ bool
intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
if (drm_WARN_ON_ONCE(&i915->drm,
!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)))
@@ -3516,7 +3516,7 @@ bool
intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
return HAS_LSPCON(i915) && devdata && devdata->child.lspcon;
}
@@ -3532,7 +3532,7 @@ bool
intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
return devdata && devdata->child.lane_reversal;
}
@@ -3540,7 +3540,7 @@ intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915,
enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
enum aux_ch aux_ch;
if (!devdata || !devdata->child.aux_channel) {
@@ -3634,7 +3634,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
int intel_bios_max_tmds_clock(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
return _intel_bios_max_tmds_clock(devdata);
}
@@ -3643,14 +3643,14 @@ int intel_bios_max_tmds_clock(struct intel_encoder *encoder)
int intel_bios_hdmi_level_shift(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
return _intel_bios_hdmi_level_shift(devdata);
}
int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost)
+ if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost)
return 0;
return translate_iboost(devdata->child.dp_iboost_level);
@@ -3658,7 +3658,7 @@ int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devd
int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost)
+ if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost)
return 0;
return translate_iboost(devdata->child.hdmi_iboost_level);
@@ -3667,7 +3667,7 @@ int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *de
int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
return _intel_bios_dp_max_link_rate(devdata);
}
@@ -3675,7 +3675,7 @@ int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
if (!devdata || !devdata->child.ddc_pin)
return 0;
@@ -3685,16 +3685,16 @@ int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
{
- return devdata->i915->vbt.version >= 195 && devdata->child.dp_usb_type_c;
+ return devdata->i915->display.vbt.version >= 195 && devdata->child.dp_usb_type_c;
}
bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
{
- return devdata->i915->vbt.version >= 209 && devdata->child.tbt;
+ return devdata->i915->display.vbt.version >= 209 && devdata->child.tbt;
}
const struct intel_bios_encoder_data *
intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port)
{
- return i915->vbt.ports[port];
+ return i915->display.vbt.ports[port];
}
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 6a3893c8ff22..760b5788eb43 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -645,7 +645,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
- i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
+ i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
edid = intel_crt_get_edid(connector, i2c);
if (edid) {
@@ -931,7 +931,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
- i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
+ i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
ret = intel_crt_ddc_get_modes(connector, i2c);
if (ret || !IS_G4X(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7f978612ddc6..b347165ac2cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2771,12 +2771,12 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
PCH_DREF_CONTROL) &
DREF_SSC1_ENABLE;
- if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
+ if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
drm_dbg_kms(&dev_priv->drm,
"SSC %s by BIOS, overriding VBT which says %s\n",
str_enabled_disabled(bios_lvds_use_ssc),
- str_enabled_disabled(dev_priv->vbt.lvds_use_ssc));
- dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
+ str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
+ dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
}
}
}
@@ -4372,7 +4372,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
u32 dpll = pipe_config->dpll_hw_state.dpll;
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
- return dev_priv->vbt.lvds_ssc_freq;
+ return dev_priv->display.vbt.lvds_ssc_freq;
else if (HAS_PCH_SPLIT(dev_priv))
return 120000;
else if (DISPLAY_VER(dev_priv) != 2)
@@ -7923,7 +7923,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
return false;
- if (!dev_priv->vbt.int_crt_support)
+ if (!dev_priv->display.vbt.int_crt_support)
return false;
return true;
@@ -8058,7 +8058,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
bool has_edp, has_port;
- if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
+ if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
intel_crt_init(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 63ff660b9479..4eeb6a8caf67 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -6,11 +6,14 @@
#ifndef __INTEL_DISPLAY_CORE_H__
#define __INTEL_DISPLAY_CORE_H__
+#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
+#include <drm/drm_connector.h>
+
#include "intel_cdclk.h"
#include "intel_display.h"
#include "intel_dmc.h"
@@ -25,6 +28,7 @@ struct i915_audio_component;
struct i915_hdcp_comp_master;
struct intel_atomic_state;
struct intel_audio_funcs;
+struct intel_bios_encoder_data;
struct intel_cdclk_funcs;
struct intel_cdclk_vals;
struct intel_color_funcs;
@@ -153,6 +157,39 @@ struct intel_hotplug {
struct workqueue_struct *dp_wq;
};
+struct intel_vbt_data {
+ /* bdb version */
+ u16 version;
+
+ /* Feature bits */
+ unsigned int int_tv_support:1;
+ unsigned int int_crt_support:1;
+ unsigned int lvds_use_ssc:1;
+ unsigned int int_lvds_support:1;
+ unsigned int display_clock_mode:1;
+ unsigned int fdi_rx_polarity_inverted:1;
+ int lvds_ssc_freq;
+ enum drm_panel_orientation orientation;
+
+ bool override_afc_startup;
+ u8 override_afc_startup_val;
+
+ int crt_ddc_pin;
+
+ struct list_head display_devices;
+ struct list_head bdb_blocks;
+
+ struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
+ struct sdvo_device_mapping {
+ u8 initialized;
+ u8 dvo_port;
+ u8 slave_addr;
+ u8 dvo_wiring;
+ u8 i2c_pin;
+ u8 ddc_pin;
+ } sdvo_mappings[2];
+};
+
struct intel_wm {
/*
* Raw watermark latency values:
@@ -311,6 +348,7 @@ struct intel_display {
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
+ struct intel_vbt_data vbt;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9a230857ca63..d4e037450ac5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5202,7 +5202,7 @@ intel_edp_add_properties(struct intel_dp *intel_dp)
return;
drm_connector_set_panel_orientation_with_quirk(&connector->base,
- i915->vbt.orientation,
+ i915->display.vbt.orientation,
fixed_mode->hdisplay,
fixed_mode->vdisplay);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 87899702a522..81655fdf2c89 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -991,7 +991,7 @@ static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
factor = 21;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if ((intel_panel_use_ssc(dev_priv) &&
- dev_priv->vbt.lvds_ssc_freq == 100000) ||
+ dev_priv->display.vbt.lvds_ssc_freq == 100000) ||
(HAS_PCH_IBX(dev_priv) &&
intel_is_dual_link_lvds(dev_priv)))
factor = 25;
@@ -1105,8 +1105,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_panel_use_ssc(dev_priv)) {
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
- dev_priv->vbt.lvds_ssc_freq);
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ dev_priv->display.vbt.lvds_ssc_freq);
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
}
if (intel_is_dual_link_lvds(dev_priv)) {
@@ -1231,7 +1231,7 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
@@ -1273,7 +1273,7 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
@@ -1306,7 +1306,7 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
@@ -1339,7 +1339,7 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d324bc8b5ef0..4c79e15d156d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2769,8 +2769,8 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
else
pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
- if (i915->vbt.override_afc_startup)
- pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->vbt.override_afc_startup_val);
+ if (i915->display.vbt.override_afc_startup)
+ pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
}
static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
@@ -2965,8 +2965,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
DKL_PLL_DIV0_FBPREDIV(m1div) |
DKL_PLL_DIV0_FBDIV_INT(m2div_int);
- if (dev_priv->vbt.override_afc_startup) {
- u8 val = dev_priv->vbt.override_afc_startup_val;
+ if (dev_priv->display.vbt.override_afc_startup) {
+ u8 val = dev_priv->display.vbt.override_afc_startup_val;
pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
}
@@ -3502,7 +3502,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port));
val = DKL_PLL_DIV0_MASK;
- if (dev_priv->vbt.override_afc_startup)
+ if (dev_priv->display.vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
hw_state->mg_pll_div0 &= val;
@@ -3566,7 +3566,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
TGL_DPLL_CFGCR1(id));
- if (dev_priv->vbt.override_afc_startup) {
+ if (dev_priv->display.vbt.override_afc_startup) {
hw_state->div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id));
hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
}
@@ -3638,9 +3638,9 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0);
intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1);
- drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->vbt.override_afc_startup &&
+ drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->display.vbt.override_afc_startup &&
!i915_mmio_reg_valid(div0_reg));
- if (dev_priv->vbt.override_afc_startup &&
+ if (dev_priv->display.vbt.override_afc_startup &&
i915_mmio_reg_valid(div0_reg))
intel_de_rmw(dev_priv, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK,
hw_state->div0);
@@ -3732,7 +3732,7 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
val = DKL_PLL_DIV0_MASK;
- if (dev_priv->vbt.override_afc_startup)
+ if (dev_priv->display.vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
intel_de_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val,
hw_state->mg_pll_div0);
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index 35e121cd226c..5efdd471ac2b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -106,7 +106,7 @@ intel_dsi_get_panel_orientation(struct intel_connector *connector)
if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return orientation;
- orientation = dev_priv->vbt.orientation;
+ orientation = dev_priv->display.vbt.orientation;
if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return orientation;
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 730480ac3300..9aa38e8141b5 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -837,12 +837,12 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
/* Skip init on machines we know falsely report LVDS */
if (dmi_check_system(intel_no_lvds)) {
- drm_WARN(dev, !dev_priv->vbt.int_lvds_support,
+ drm_WARN(dev, !dev_priv->display.vbt.int_lvds_support,
"Useless DMI match. Internal LVDS support disabled by VBT\n");
return;
}
- if (!dev_priv->vbt.int_lvds_support) {
+ if (!dev_priv->display.vbt.int_lvds_support) {
drm_dbg_kms(&dev_priv->drm,
"Internal LVDS support disabled by VBT\n");
return;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 237a40623dd7..43dbc5a3ec37 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -42,7 +42,7 @@ bool intel_panel_use_ssc(struct drm_i915_private *i915)
{
if (i915->params.panel_use_ssc >= 0)
return i915->params.panel_use_ssc != 0;
- return i915->vbt.lvds_use_ssc
+ return i915->display.vbt.lvds_use_ssc
&& !(i915->quirks & QUIRK_LVDS_SSC_DISABLE);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index ee72400759a3..33bd4d7df465 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -514,7 +514,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
if (HAS_PCH_IBX(dev_priv)) {
- has_ck505 = dev_priv->vbt.display_clock_mode;
+ has_ck505 = dev_priv->display.vbt.display_clock_mode;
can_ssc = has_ck505;
} else {
has_ck505 = false;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 19122bc6d2ab..f5b744bef18f 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2016,7 +2016,7 @@ intel_sdvo_get_analog_edid(struct drm_connector *connector)
return drm_get_edid(connector,
intel_gmbus_get_adapter(dev_priv,
- dev_priv->vbt.crt_ddc_pin));
+ dev_priv->display.vbt.crt_ddc_pin));
}
static enum drm_connector_status
@@ -2581,9 +2581,9 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
struct sdvo_device_mapping *mapping;
if (sdvo->port == PORT_B)
- mapping = &dev_priv->vbt.sdvo_mappings[0];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[0];
else
- mapping = &dev_priv->vbt.sdvo_mappings[1];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[1];
if (mapping->initialized)
sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
@@ -2599,9 +2599,9 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
u8 pin;
if (sdvo->port == PORT_B)
- mapping = &dev_priv->vbt.sdvo_mappings[0];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[0];
else
- mapping = &dev_priv->vbt.sdvo_mappings[1];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[1];
if (mapping->initialized &&
intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
@@ -2639,11 +2639,11 @@ intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
struct sdvo_device_mapping *my_mapping, *other_mapping;
if (sdvo->port == PORT_B) {
- my_mapping = &dev_priv->vbt.sdvo_mappings[0];
- other_mapping = &dev_priv->vbt.sdvo_mappings[1];
+ my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
+ other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
} else {
- my_mapping = &dev_priv->vbt.sdvo_mappings[1];
- other_mapping = &dev_priv->vbt.sdvo_mappings[0];
+ my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
+ other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
}
/* If the BIOS described our SDVO device, take advantage of it. */
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 509b0a419c20..d474f5130aea 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -362,10 +362,10 @@ enum vbt_gmbus_ddi {
* basically any of the fields to ensure the correct interpretation for the BDB
* version in question.
*
- * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
- * space for the full structure below, and initialize the tail not actually
- * present in VBT to zeros. Accessing those fields is fine, as long as the
- * default zero is taken into account, again according to the BDB version.
+ * When we copy the child device configs to dev_priv->display.vbt.child_dev, we
+ * reserve space for the full structure below, and initialize the tail not
+ * actually present in VBT to zeros. Accessing those fields is fine, as long as
+ * the default zero is taken into account, again according to the BDB version.
*
* BDB versions 155 and below are considered legacy, and version 155 seems to be
* a baseline for some of the VBT documentation. When adding new fields, please
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8fc77a852b5..e3c7de286226 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -34,7 +34,6 @@
#include <linux/pm_qos.h>
-#include <drm/drm_connector.h>
#include <drm/ttm/ttm_device.h>
#include "display/intel_display.h"
@@ -90,15 +89,6 @@ struct vlv_s0ix_state;
I915_GEM_DOMAIN_INSTRUCTION | \
I915_GEM_DOMAIN_VERTEX)
-struct sdvo_device_mapping {
- u8 initialized;
- u8 dvo_port;
- u8 slave_addr;
- u8 dvo_wiring;
- u8 i2c_pin;
- u8 ddc_pin;
-};
-
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
@@ -200,32 +190,6 @@ i915_fence_timeout(const struct drm_i915_private *i915)
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-struct intel_vbt_data {
- /* bdb version */
- u16 version;
-
- /* Feature bits */
- unsigned int int_tv_support:1;
- unsigned int int_crt_support:1;
- unsigned int lvds_use_ssc:1;
- unsigned int int_lvds_support:1;
- unsigned int display_clock_mode:1;
- unsigned int fdi_rx_polarity_inverted:1;
- int lvds_ssc_freq;
- enum drm_panel_orientation orientation;
-
- bool override_afc_startup;
- u8 override_afc_startup_val;
-
- int crt_ddc_pin;
-
- struct list_head display_devices;
- struct list_head bdb_blocks;
-
- struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
- struct sdvo_device_mapping sdvo_mappings[2];
-};
-
struct i915_frontbuffer_tracking {
spinlock_t lock;
@@ -323,7 +287,6 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct intel_fbc *fbc[I915_MAX_FBCS];
- struct intel_vbt_data vbt;
bool preserve_bios_swizzle;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a7bfa063447c..b8187c8d39f1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7463,7 +7463,7 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
- if (dev_priv->vbt.fdi_rx_polarity_inverted)
+ if (dev_priv->display.vbt.fdi_rx_polarity_inverted)
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 08/18] drm/i915: move fbc to display.fbc
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (6 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 07/18] drm/i915: move vbt to display.vbt Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 09/18] drm/i915: move and group power related members under display.power Jani Nikula
` (14 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display FBC related members under drm_i915_private display
sub-struct.
Pointers and arrays of pointers to structs that we defined are fine
without a sub-struct wrapping.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +++---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ---
5 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 0f35f2facdfc..5afbe3e98ee8 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
- return dev_priv->fbc[INTEL_FBC_A];
+ return dev_priv->display.fbc[INTEL_FBC_A];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 4eeb6a8caf67..be40d4a12434 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -18,6 +18,7 @@
#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
+#include "intel_fbc.h"
#include "intel_global_state.h"
#include "intel_gmbus.h"
#include "intel_opregion.h"
@@ -345,6 +346,7 @@ struct intel_display {
struct intel_audio audio;
struct intel_dmc dmc;
struct intel_dpll dpll;
+ struct intel_fbc *fbc[I915_MAX_FBCS];
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 0ece995ae766..f38175304928 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -59,7 +59,7 @@
#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
for_each_fbc_id((__dev_priv), (__fbc_id)) \
- for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
+ for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
struct intel_fbc_funcs {
void (*activate)(struct intel_fbc *fbc);
@@ -1720,7 +1720,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
i915->params.enable_fbc);
for_each_fbc_id(i915, fbc_id)
- i915->fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
+ i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
}
/**
@@ -1840,7 +1840,7 @@ void intel_fbc_debugfs_register(struct drm_i915_private *i915)
struct drm_minor *minor = i915->drm.primary;
struct intel_fbc *fbc;
- fbc = i915->fbc[INTEL_FBC_A];
+ fbc = i915->display.fbc[INTEL_FBC_A];
if (fbc)
intel_fbc_debugfs_add(fbc, minor->debugfs_root);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index bcfde81e4d08..8f22a2739d1d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1940,7 +1940,7 @@ static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
- return dev_priv->fbc[fbc_id];
+ return dev_priv->display.fbc[fbc_id];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e3c7de286226..43e73f6d7ef3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -40,7 +40,6 @@
#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
#include "display/intel_dsb.h"
-#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_context_types.h"
@@ -286,8 +285,6 @@ struct drm_i915_private {
};
u32 pipestat_irq_mask[I915_MAX_PIPES];
- struct intel_fbc *fbc[I915_MAX_FBCS];
-
bool preserve_bios_swizzle;
unsigned int fsb_freq, mem_freq, is_ddr3;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 09/18] drm/i915: move and group power related members under display.power
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (7 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 08/18] drm/i915: move fbc to display.fbc Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 10/18] drm/i915: move and group fdi members under display.fdi Jani Nikula
` (13 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display power related members under drm_i915_private display
sub-struct.
Arguably chv_phy_control and chv_phy_assert could be placed in a phy
substruct, but they are only used in the power code.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 11 ++
.../drm/i915/display/intel_display_power.c | 114 +++++++++---------
.../i915/display/intel_display_power_map.c | 4 +-
.../i915/display/intel_display_power_well.c | 56 ++++-----
.../i915/display/intel_display_power_well.h | 12 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 20 +--
8 files changed, 111 insertions(+), 110 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index be40d4a12434..1f25e22496db 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
#include "intel_cdclk.h"
#include "intel_display.h"
+#include "intel_display_power.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
#include "intel_fbc.h"
@@ -324,6 +325,16 @@ struct intel_display {
struct mutex comp_mutex;
} hdcp;
+ struct {
+ struct i915_power_domains domains;
+
+ /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
+ u32 chv_phy_control;
+
+ /* perform PHY state sanity checks? */
+ bool chv_phy_assert[2];
+ } power;
+
struct {
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 438a368ba358..b64aec60c36c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -244,7 +244,7 @@ bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains;
bool ret;
- power_domains = &dev_priv->power_domains;
+ power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
ret = __intel_display_power_is_enabled(dev_priv, domain);
@@ -292,7 +292,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
{
struct i915_power_well *power_well;
bool dc_off_enabled;
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
@@ -340,7 +340,7 @@ assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
return !drm_WARN_ON(&i915->drm,
bitmap_intersects(power_domains->async_put_domains[0].bits,
@@ -353,7 +353,7 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
struct intel_power_domain_mask async_put_mask;
enum intel_display_power_domain domain;
bool err = false;
@@ -376,7 +376,7 @@ static void print_power_domains(struct i915_power_domains *power_domains,
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
enum intel_display_power_domain domain;
drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
@@ -391,7 +391,7 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
drm_dbg(&i915->drm, "async_put_wakeref %u\n",
power_domains->async_put_wakeref);
@@ -446,7 +446,7 @@ static bool
intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct intel_power_domain_mask async_put_mask;
bool ret = false;
@@ -475,7 +475,7 @@ static void
__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *power_well;
if (intel_display_power_grab_async_put_ref(dev_priv, domain))
@@ -502,7 +502,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&power_domains->lock);
@@ -528,7 +528,7 @@ intel_wakeref_t
intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
intel_wakeref_t wakeref;
bool is_enabled;
@@ -564,7 +564,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
const char *name = intel_display_power_domain_str(domain);
struct intel_power_domain_mask async_put_mask;
- power_domains = &dev_priv->power_domains;
+ power_domains = &dev_priv->display.power.domains;
drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
"Use count on domain %s is already zero\n",
@@ -584,7 +584,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
static void __intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
__intel_display_power_put_domain(dev_priv, domain);
@@ -597,7 +597,7 @@ queue_async_put_domains_work(struct i915_power_domains *power_domains,
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
power_domains->async_put_wakeref = wakeref;
drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
@@ -611,7 +611,7 @@ release_async_put_domains(struct i915_power_domains *power_domains,
{
struct drm_i915_private *dev_priv =
container_of(power_domains, struct drm_i915_private,
- power_domains);
+ display.power.domains);
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
enum intel_display_power_domain domain;
intel_wakeref_t wakeref;
@@ -638,8 +638,8 @@ intel_display_power_put_async_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
- power_domains.async_put_work.work);
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ display.power.domains.async_put_work.work);
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
intel_wakeref_t old_work_wakeref = 0;
@@ -699,7 +699,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
enum intel_display_power_domain domain,
intel_wakeref_t wakeref)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
@@ -747,7 +747,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
*/
void intel_display_power_flush_work(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct intel_power_domain_mask async_put_mask;
intel_wakeref_t work_wakeref;
@@ -780,7 +780,7 @@ void intel_display_power_flush_work(struct drm_i915_private *i915)
static void
intel_display_power_flush_work_sync(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
intel_display_power_flush_work(i915);
cancel_delayed_work_sync(&power_domains->async_put_work);
@@ -977,7 +977,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
*/
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
@@ -1004,12 +1004,12 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
*/
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
{
- intel_display_power_map_cleanup(&dev_priv->power_domains);
+ intel_display_power_map_cleanup(&dev_priv->display.power.domains);
}
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
@@ -1038,7 +1038,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
enum dbuf_slice slice;
@@ -1398,7 +1398,7 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -1430,7 +1430,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1464,7 +1464,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -1498,7 +1498,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1607,7 +1607,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
static void icl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
u32 val;
@@ -1674,7 +1674,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1719,7 +1719,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* power well state and lane status to reconstruct the
* expected initial value.
*/
- dev_priv->chv_phy_control =
+ dev_priv->display.power.chv_phy_control =
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
@@ -1741,27 +1741,27 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
mask = (status & DPLL_PORTC_READY_MASK) >> 4;
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
+ dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
- dev_priv->chv_phy_assert[DPIO_PHY0] = false;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false;
} else {
- dev_priv->chv_phy_assert[DPIO_PHY0] = true;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
}
if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
@@ -1773,21 +1773,21 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
+ dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
- dev_priv->chv_phy_assert[DPIO_PHY1] = false;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false;
} else {
- dev_priv->chv_phy_assert[DPIO_PHY1] = true;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true;
}
drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
/* Defer application of initial phy_control to enabling the powerwell */
}
@@ -1871,7 +1871,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
*/
void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
power_domains->initializing = true;
@@ -1912,8 +1912,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
/* Disable power support if the user asked so. */
if (!i915->params.disable_power_well) {
drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
- i915->power_domains.disable_wakeref = intel_display_power_get(i915,
- POWER_DOMAIN_INIT);
+ i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
+ POWER_DOMAIN_INIT);
}
intel_power_domains_sync_hw(i915);
@@ -1934,12 +1934,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
void intel_power_domains_driver_remove(struct drm_i915_private *i915)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&i915->power_domains.init_wakeref);
+ fetch_and_zero(&i915->display.power.domains.init_wakeref);
/* Remove the refcount we took to keep power well support disabled. */
if (!i915->params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
- fetch_and_zero(&i915->power_domains.disable_wakeref));
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
intel_display_power_flush_work_sync(i915);
@@ -1961,7 +1961,7 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915)
*/
void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
@@ -1995,7 +1995,7 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
void intel_power_domains_enable(struct drm_i915_private *i915)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&i915->power_domains.init_wakeref);
+ fetch_and_zero(&i915->display.power.domains.init_wakeref);
intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
intel_power_domains_verify_state(i915);
@@ -2010,7 +2010,7 @@ void intel_power_domains_enable(struct drm_i915_private *i915)
*/
void intel_power_domains_disable(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
power_domains->init_wakeref =
@@ -2033,7 +2033,7 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
void intel_power_domains_suspend(struct drm_i915_private *i915,
enum i915_drm_suspend_mode suspend_mode)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
intel_wakeref_t wakeref __maybe_unused =
fetch_and_zero(&power_domains->init_wakeref);
@@ -2060,7 +2060,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
*/
if (!i915->params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
- fetch_and_zero(&i915->power_domains.disable_wakeref));
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
@@ -2087,7 +2087,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
*/
void intel_power_domains_resume(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
if (power_domains->display_core_suspended) {
intel_power_domains_init_hw(i915, true);
@@ -2105,7 +2105,7 @@ void intel_power_domains_resume(struct drm_i915_private *i915)
static void intel_power_domains_dump_info(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
for_each_power_well(i915, power_well) {
@@ -2133,7 +2133,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
*/
static void intel_power_domains_verify_state(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
bool dump_domain_info;
@@ -2259,7 +2259,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
int i;
mutex_lock(&power_domains->lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 97b367f39f35..5ddd1b93751c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1388,7 +1388,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
u64 power_well_ids = 0;
const struct i915_power_well_desc_list *desc_list;
const struct i915_power_well_desc *desc;
@@ -1447,7 +1447,7 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
/*
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 7482580f62fe..a358ce9e4bcd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -85,7 +85,7 @@ lookup_power_well(struct drm_i915_private *i915,
drm_WARN(&i915->drm, 1,
"Power well %d not defined for this platform\n",
power_well_id);
- return &i915->power_domains.power_wells[0];
+ return &i915->display.power.domains.power_wells[0];
}
void intel_power_well_enable(struct drm_i915_private *i915,
@@ -1208,7 +1208,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
* During driver initialization/resume we can avoid restoring the
* part of the HW/SW state that will be inited anyway explicitly.
*/
- if (dev_priv->power_domains.initializing)
+ if (dev_priv->display.power.domains.initializing)
return;
intel_hpd_init(dev_priv);
@@ -1303,7 +1303,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
- u32 phy_control = dev_priv->chv_phy_control;
+ u32 phy_control = dev_priv->display.power.chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1314,7 +1314,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->chv_phy_assert[DPIO_PHY0])
+ if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
@@ -1322,7 +1322,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
- if (!dev_priv->chv_phy_assert[DPIO_PHY1])
+ if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
@@ -1398,7 +1398,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
drm_err(&dev_priv->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
- phy_status, dev_priv->chv_phy_control);
+ phy_status, dev_priv->display.power.chv_phy_control);
}
#undef BITS_SET
@@ -1458,13 +1458,13 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_dpio_put(dev_priv);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
+ dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ phy, dev_priv->display.power.chv_phy_control);
assert_chv_phy_status(dev_priv);
}
@@ -1488,18 +1488,18 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
assert_pll_disabled(dev_priv, PIPE_C);
}
- dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
+ dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
vlv_set_power_well(dev_priv, power_well, false);
drm_dbg_kms(&dev_priv->drm,
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ phy, dev_priv->display.power.chv_phy_control);
/* PHY is fully reset now, so we can enable the PHY state asserts */
- dev_priv->chv_phy_assert[phy] = true;
+ dev_priv->display.power.chv_phy_assert[phy] = true;
assert_chv_phy_status(dev_priv);
}
@@ -1517,7 +1517,7 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->chv_phy_assert[phy])
+ if (!dev_priv->display.power.chv_phy_assert[phy])
return;
if (ch == DPIO_CH0)
@@ -1571,27 +1571,27 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
bool was_override;
mutex_lock(&power_domains->lock);
- was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
if (override == was_override)
goto out;
if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
- phy, ch, dev_priv->chv_phy_control);
+ phy, ch, dev_priv->display.power.chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -1605,26 +1605,26 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
mutex_lock(&power_domains->lock);
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
+ dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
+ dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
- phy, ch, mask, dev_priv->chv_phy_control);
+ phy, ch, mask, dev_priv->display.power.chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -1702,7 +1702,7 @@ static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
}
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index d0624642dcb6..31a898176ebb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -14,15 +14,15 @@ struct drm_i915_private;
struct i915_power_well;
#define for_each_power_well(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
- (__power_well) - (__dev_priv)->power_domains.power_wells < \
- (__dev_priv)->power_domains.power_well_count; \
+ for ((__power_well) = (__dev_priv)->display.power.domains.power_wells; \
+ (__power_well) - (__dev_priv)->display.power.domains.power_wells < \
+ (__dev_priv)->display.power.domains.power_well_count; \
(__power_well)++)
#define for_each_power_well_reverse(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
- (__dev_priv)->power_domains.power_well_count - 1; \
- (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ for ((__power_well) = (__dev_priv)->display.power.domains.power_wells + \
+ (__dev_priv)->display.power.domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->display.power.domains.power_wells >= 0; \
(__power_well)--)
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index cc6abe761f5e..8732b8722ed7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -484,7 +484,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
bool was_enabled;
- lockdep_assert_held(&dev_priv->power_domains.lock);
+ lockdep_assert_held(&dev_priv->display.power.domains.lock);
was_enabled = true;
if (rcomp_phy != -1)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 63fd18732db3..3e99a6a88c3a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -492,7 +492,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused)
seq_puts(m, "Runtime power management not supported\n");
seq_printf(m, "Runtime power status: %s\n",
- str_enabled_disabled(!dev_priv->power_domains.init_wakeref));
+ str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref));
seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake));
seq_printf(m, "IRQs disabled: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43e73f6d7ef3..074679320056 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -38,7 +38,6 @@
#include "display/intel_display.h"
#include "display/intel_display_core.h"
-#include "display/intel_display_power.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
@@ -360,8 +359,6 @@ struct drm_i915_private {
*/
u32 edram_size_mb;
- struct i915_power_domains power_domains;
-
struct i915_gpu_error gpu_error;
struct drm_property *broadcast_rgb_property;
@@ -369,8 +366,6 @@ struct drm_i915_private {
u32 fdi_rx_config;
- /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
- u32 chv_phy_control;
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working in the presence hardware
@@ -439,16 +434,11 @@ struct drm_i915_private {
bool irq_enabled;
- union {
- /* perform PHY state sanity checks? */
- bool chv_phy_assert[2];
-
- /*
- * DG2: Mask of PHYs that were not calibrated by the firmware
- * and should not be used.
- */
- u8 snps_phy_failed_calibration;
- };
+ /*
+ * DG2: Mask of PHYs that were not calibrated by the firmware
+ * and should not be used.
+ */
+ u8 snps_phy_failed_calibration;
bool ipc_enabled;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 10/18] drm/i915: move and group fdi members under display.fdi
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (8 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 09/18] drm/i915: move and group power related members under display.power Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 11/18] drm/i915: move fb_tracking under display sub-struct Jani Nikula
` (12 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display fdi related members under drm_i915_private display
sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_core.h | 5 +++++
drivers/gpu/drm/i915/display/intel_fdi.c | 10 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 3 ---
4 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 760b5788eb43..6c555555b7bf 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1110,8 +1110,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
- dev_priv->fdi_rx_config = intel_de_read(dev_priv,
- FDI_RX_CTL(PIPE_A)) & fdi_config;
+ dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
+ FDI_RX_CTL(PIPE_A)) & fdi_config;
}
intel_crt_reset(&crt->base.base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 1f25e22496db..0aeebf169ba6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -299,6 +299,11 @@ struct intel_display {
struct work_struct suspend_work;
} fbdev;
+ struct {
+ unsigned int pll_freq;
+ u32 rx_config;
+ } fdi;
+
struct {
/*
* Base address of where the gmbus and gpio blocks are located
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 03ad5f5c8417..f67dd4f05bab 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -210,14 +210,14 @@ void intel_fdi_pll_freq_update(struct drm_i915_private *i915)
u32 fdi_pll_clk =
intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
- i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
+ i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 10000;
} else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
- i915->fdi_pll_freq = 270000;
+ i915->display.fdi.pll_freq = 270000;
} else {
return;
}
- drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
+ drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq);
}
int intel_fdi_link_freq(struct drm_i915_private *i915,
@@ -226,7 +226,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
if (HAS_DDI(i915))
return pipe_config->port_clock; /* SPLL */
else
- return i915->fdi_pll_freq;
+ return i915->display.fdi.pll_freq;
}
int ilk_fdi_compute_config(struct intel_crtc *crtc,
@@ -789,7 +789,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
/* Enable the PCH Receiver FDI PLL */
- rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
+ rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
FDI_RX_PLL_ENABLE |
FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 074679320056..a03b8e676a22 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -291,7 +291,6 @@ struct drm_i915_private {
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
- unsigned int fdi_pll_freq;
unsigned int czclk_freq;
struct {
@@ -364,8 +363,6 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
- u32 fdi_rx_config;
-
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working in the presence hardware
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 11/18] drm/i915: move fb_tracking under display sub-struct
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (9 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 10/18] drm/i915: move and group fdi members under display.fdi Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 12/18] drm/i915: move dbuf " Jani Nikula
` (11 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display frontbuffer tracking related members under drm_i915_private
display sub-struct.
Rename struct i915_frontbuffer_tracking to intel_frontbuffer_tracking
while at it.
FIXME: fb_tracking.lock mutex init should be moved away from
i915_gem_init_early().
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 12 +++++
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../gpu/drm/i915/display/intel_frontbuffer.c | 54 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 14 -----
drivers/gpu/drm/i915/i915_gem.c | 2 +-
5 files changed, 42 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 0aeebf169ba6..3d2e1b14e186 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -120,6 +120,17 @@ struct intel_dpll {
} ref_clks;
};
+struct intel_frontbuffer_tracking {
+ spinlock_t lock;
+
+ /*
+ * Tracking bits for delayed frontbuffer flushing du to gpu activity or
+ * scheduled flips.
+ */
+ unsigned busy_bits;
+ unsigned flip_bits;
+};
+
struct intel_hotplug {
struct delayed_work hotplug_work;
@@ -363,6 +374,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_fbc *fbc[I915_MAX_FBCS];
+ struct intel_frontbuffer_tracking fb_tracking;
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 619523f85a18..5dc364e9db49 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -37,10 +37,10 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
seq_printf(m, "FB tracking busy bits: 0x%08x\n",
- dev_priv->fb_tracking.busy_bits);
+ dev_priv->display.fb_tracking.busy_bits);
seq_printf(m, "FB tracking flip bits: 0x%08x\n",
- dev_priv->fb_tracking.flip_bits);
+ dev_priv->display.fb_tracking.flip_bits);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 1463493824b8..d80e3e8a9b01 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -81,9 +81,9 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
enum fb_op_origin origin)
{
/* Delay flushing when rings are still busy.*/
- spin_lock(&i915->fb_tracking.lock);
- frontbuffer_bits &= ~i915->fb_tracking.busy_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
+ frontbuffer_bits &= ~i915->display.fb_tracking.busy_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
if (!frontbuffer_bits)
return;
@@ -111,11 +111,11 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
- i915->fb_tracking.flip_bits |= frontbuffer_bits;
+ spin_lock(&i915->display.fb_tracking.lock);
+ i915->display.fb_tracking.flip_bits |= frontbuffer_bits;
/* Remove stale busy bits due to the old buffer. */
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
}
/**
@@ -131,11 +131,11 @@ void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
/* Mask any cancelled flips. */
- frontbuffer_bits &= i915->fb_tracking.flip_bits;
- i915->fb_tracking.flip_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ frontbuffer_bits &= i915->display.fb_tracking.flip_bits;
+ i915->display.fb_tracking.flip_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
if (frontbuffer_bits)
frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP);
@@ -155,10 +155,10 @@ void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
void intel_frontbuffer_flip(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
/* Remove stale busy bits due to the old buffer. */
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP);
}
@@ -170,10 +170,10 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
struct drm_i915_private *i915 = to_i915(front->obj->base.dev);
if (origin == ORIGIN_CS) {
- spin_lock(&i915->fb_tracking.lock);
- i915->fb_tracking.busy_bits |= frontbuffer_bits;
- i915->fb_tracking.flip_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
+ i915->display.fb_tracking.busy_bits |= frontbuffer_bits;
+ i915->display.fb_tracking.flip_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
}
trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin);
@@ -191,11 +191,11 @@ void __intel_fb_flush(struct intel_frontbuffer *front,
struct drm_i915_private *i915 = to_i915(front->obj->base.dev);
if (origin == ORIGIN_CS) {
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
/* Filter out new bits since rendering started. */
- frontbuffer_bits &= i915->fb_tracking.busy_bits;
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ frontbuffer_bits &= i915->display.fb_tracking.busy_bits;
+ i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
}
if (frontbuffer_bits)
@@ -221,7 +221,7 @@ static void frontbuffer_retire(struct i915_active *ref)
}
static void frontbuffer_release(struct kref *ref)
- __releases(&to_i915(front->obj->base.dev)->fb_tracking.lock)
+ __releases(&to_i915(front->obj->base.dev)->display.fb_tracking.lock)
{
struct intel_frontbuffer *front =
container_of(ref, typeof(*front), ref);
@@ -238,7 +238,7 @@ static void frontbuffer_release(struct kref *ref)
spin_unlock(&obj->vma.lock);
RCU_INIT_POINTER(obj->frontbuffer, NULL);
- spin_unlock(&to_i915(obj->base.dev)->fb_tracking.lock);
+ spin_unlock(&to_i915(obj->base.dev)->display.fb_tracking.lock);
i915_active_fini(&front->write);
@@ -268,7 +268,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)
frontbuffer_retire,
I915_ACTIVE_RETIRE_SLEEPS);
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
if (rcu_access_pointer(obj->frontbuffer)) {
kfree(front);
front = rcu_dereference_protected(obj->frontbuffer, true);
@@ -277,7 +277,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)
i915_gem_object_get(obj);
rcu_assign_pointer(obj->frontbuffer, front);
}
- spin_unlock(&i915->fb_tracking.lock);
+ spin_unlock(&i915->display.fb_tracking.lock);
return front;
}
@@ -286,7 +286,7 @@ void intel_frontbuffer_put(struct intel_frontbuffer *front)
{
kref_put_lock(&front->ref,
frontbuffer_release,
- &to_i915(front->obj->base.dev)->fb_tracking.lock);
+ &to_i915(front->obj->base.dev)->display.fb_tracking.lock);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a03b8e676a22..c950867153b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -39,7 +39,6 @@
#include "display/intel_display.h"
#include "display/intel_display_core.h"
#include "display/intel_dsb.h"
-#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_context_types.h"
#include "gem/i915_gem_lmem.h"
@@ -188,17 +187,6 @@ i915_fence_timeout(const struct drm_i915_private *i915)
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-struct i915_frontbuffer_tracking {
- spinlock_t lock;
-
- /*
- * Tracking bits for delayed frontbuffer flushing du to gpu activity or
- * scheduled flips.
- */
- unsigned busy_bits;
- unsigned flip_bits;
-};
-
struct i915_virtual_gpu {
struct mutex lock; /* serialises sending of g2v_notify command pkts */
bool active;
@@ -333,8 +321,6 @@ struct drm_i915_private {
struct list_head global_obj_list;
- struct i915_frontbuffer_tracking fb_tracking;
-
struct intel_atomic_helper {
struct llist_head free_list;
struct work_struct free_work;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 32f0b5c443c8..c2d6172ba4bb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1212,7 +1212,7 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
i915_gem_init__mm(dev_priv);
i915_gem_init__contexts(dev_priv);
- spin_lock_init(&dev_priv->fb_tracking.lock);
+ spin_lock_init(&dev_priv->display.fb_tracking.lock);
}
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 12/18] drm/i915: move dbuf under display sub-struct
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (10 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 11/18] drm/i915: move fb_tracking under display sub-struct Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 13/18] drm/i915: move and group modeset_wq and flip_wq under display.wq Jani Nikula
` (10 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display dbuf related members under drm_i915_private display
sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 7 +++++++
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
.../drm/i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 7 -------
drivers/gpu/drm/i915/intel_pm.c | 14 +++++++-------
drivers/gpu/drm/i915/intel_pm.h | 4 ++--
7 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 3d2e1b14e186..b061deb21df1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -299,6 +299,13 @@ struct intel_display {
unsigned int max_cdclk_freq;
} cdclk;
+ struct {
+ /* The current hardware dbuf configuration */
+ u8 enabled_slices;
+
+ struct intel_global_obj obj;
+ } dbuf;
+
struct {
/* VLV/CHV/BXT/GLK DSI MMIO register base address */
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b64aec60c36c..1af1705d730d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1061,14 +1061,14 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
for_each_dbuf_slice(dev_priv, slice)
gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
- dev_priv->dbuf.enabled_slices = req_slices;
+ dev_priv->display.dbuf.enabled_slices = req_slices;
mutex_unlock(&power_domains->lock);
}
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
- dev_priv->dbuf.enabled_slices =
+ dev_priv->display.dbuf.enabled_slices =
intel_enabled_dbuf_slices_mask(dev_priv);
/*
@@ -1076,7 +1076,7 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
* figure out later which slices we have and what we need.
*/
gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
- dev_priv->dbuf.enabled_slices);
+ dev_priv->display.dbuf.enabled_slices);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a358ce9e4bcd..c8b741dd05ba 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -946,7 +946,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
{
u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
- u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
+ u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
drm_WARN(&dev_priv->drm,
hw_enabled_dbuf_slices != enabled_dbuf_slices,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index def782794184..aed386dce96a 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -34,7 +34,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
@@ -417,7 +417,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c950867153b6..1a494933dd92 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -281,13 +281,6 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int czclk_freq;
- struct {
- /* The current hardware dbuf configuration */
- u8 enabled_slices;
-
- struct intel_global_obj obj;
- } dbuf;
-
/**
* wq - Driver workqueue for GEM.
*
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b8187c8d39f1..cbf46d25a0df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6568,7 +6568,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+ to_intel_dbuf_state(dev_priv->display.dbuf.obj.state);
struct intel_crtc *crtc;
if (HAS_MBUS_JOINING(dev_priv))
@@ -6630,13 +6630,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
str_yes_no(dbuf_state->joined_mbus));
}
- dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
+ dbuf_state->enabled_slices = dev_priv->display.dbuf.enabled_slices;
}
static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915)
{
const struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
struct intel_crtc *crtc;
@@ -7222,10 +7222,10 @@ void intel_wm_state_verify(struct intel_crtc *crtc,
hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
if (DISPLAY_VER(dev_priv) >= 11 &&
- hw_enabled_slices != dev_priv->dbuf.enabled_slices)
+ hw_enabled_slices != dev_priv->display.dbuf.enabled_slices)
drm_err(&dev_priv->drm,
"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
- dev_priv->dbuf.enabled_slices,
+ dev_priv->display.dbuf.enabled_slices,
hw_enabled_slices);
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
@@ -8342,7 +8342,7 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *dbuf_state;
- dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->dbuf.obj);
+ dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.dbuf.obj);
if (IS_ERR(dbuf_state))
return ERR_CAST(dbuf_state);
@@ -8357,7 +8357,7 @@ int intel_dbuf_init(struct drm_i915_private *dev_priv)
if (!dbuf_state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->dbuf.obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display.dbuf.obj,
&dbuf_state->base, &intel_dbuf_funcs);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 945503ae493e..3ee71831d1a4 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -77,9 +77,9 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
#define intel_atomic_get_old_dbuf_state(state) \
- to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
+ to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
#define intel_atomic_get_new_dbuf_state(state) \
- to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
+ to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
int intel_dbuf_init(struct drm_i915_private *dev_priv);
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 13/18] drm/i915: move and group modeset_wq and flip_wq under display.wq
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (11 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 12/18] drm/i915: move dbuf " Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 14/18] drm/i915/quirks: abstract checking for display quirks Jani Nikula
` (9 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display workqueue related members under drm_i915_private display
sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 8 ++++++++
drivers/gpu/drm/i915/i915_drv.h | 5 -----
3 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b347165ac2cf..5fb027ff5246 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7812,12 +7812,12 @@ static int intel_atomic_commit(struct drm_device *dev,
i915_sw_fence_commit(&state->commit_ready);
if (nonblock && state->modeset) {
- queue_work(dev_priv->modeset_wq, &state->base.commit_work);
+ queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
} else if (nonblock) {
- queue_work(dev_priv->flip_wq, &state->base.commit_work);
+ queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
} else {
if (state->modeset)
- flush_workqueue(dev_priv->modeset_wq);
+ flush_workqueue(dev_priv->display.wq.modeset);
intel_atomic_commit_tail(state);
}
@@ -8686,9 +8686,9 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
intel_dmc_ucode_init(i915);
- i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
- i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
- WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
+ i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
+ i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
+ WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
intel_mode_config_init(i915);
@@ -8995,8 +8995,8 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- flush_workqueue(i915->flip_wq);
- flush_workqueue(i915->modeset_wq);
+ flush_workqueue(i915->display.wq.flip);
+ flush_workqueue(i915->display.wq.modeset);
flush_work(&i915->atomic_helper.free_work);
drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
@@ -9037,8 +9037,8 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
intel_gmbus_teardown(i915);
- destroy_workqueue(i915->flip_wq);
- destroy_workqueue(i915->modeset_wq);
+ destroy_workqueue(i915->display.wq.flip);
+ destroy_workqueue(i915->display.wq.modeset);
intel_fbc_cleanup(i915);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index b061deb21df1..31fd05a04bff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -376,6 +376,14 @@ struct intel_display {
u32 block_time_us;
} sagv;
+ struct {
+ /* ordered wq for modesets */
+ struct workqueue_struct *modeset;
+
+ /* unbound hipri wq for page flips/plane updates */
+ struct workqueue_struct *flip;
+ } wq;
+
/* Grouping using named structs. Keep sorted. */
struct intel_audio audio;
struct intel_dmc dmc;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a494933dd92..5aac06da3cc7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -290,11 +290,6 @@ struct drm_i915_private {
*/
struct workqueue_struct *wq;
- /* ordered wq for modesets */
- struct workqueue_struct *modeset_wq;
- /* unbound hipri wq for page flips/plane updates */
- struct workqueue_struct *flip_wq;
-
/* pm private clock gating functions */
const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 14/18] drm/i915/quirks: abstract checking for display quirks
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (12 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 13/18] drm/i915: move and group modeset_wq and flip_wq under display.wq Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 15/18] drm/i915/quirks: abstract quirks further by making quirk ids an enum Jani Nikula
` (8 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Add intel_has_quirk() for checking if a display quirk is present. Avoid
accessing i915->quirks all over the place.
v2: Rebase
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_backlight.c | 9 +++++----
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_panel.c | 5 +++--
drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
drivers/gpu/drm/i915/display/intel_quirks.c | 5 +++++
drivers/gpu/drm/i915/display/intel_quirks.h | 5 ++++-
6 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index f20f3c06ca96..11a1342d6d37 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -18,6 +18,7 @@
#include "intel_panel.h"
#include "intel_pci_config.h"
#include "intel_pps.h"
+#include "intel_quirks.h"
/**
* scale - scale values from one range to another
@@ -88,7 +89,7 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 val)
return val;
if (dev_priv->params.invert_brightness > 0 ||
- dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
+ intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)) {
return panel->backlight.pwm_level_max - val + panel->backlight.pwm_level_min;
}
@@ -128,7 +129,7 @@ u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val)
panel->backlight.max == 0 || panel->backlight.pwm_level_max == 0);
if (dev_priv->params.invert_brightness > 0 ||
- (dev_priv->params.invert_brightness == 0 && dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS))
+ (dev_priv->params.invert_brightness == 0 && intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)))
val = panel->backlight.pwm_level_max - (val - panel->backlight.pwm_level_min);
return scale(val, panel->backlight.pwm_level_min, panel->backlight.pwm_level_max,
@@ -1605,7 +1606,7 @@ int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
int ret;
if (!connector->panel.vbt.backlight.present) {
- if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
+ if (intel_has_quirk(dev_priv, QUIRK_BACKLIGHT_PRESENT)) {
drm_dbg_kms(&dev_priv->drm,
"no backlight present per VBT, but present per quirk\n");
} else {
@@ -1777,7 +1778,7 @@ void intel_backlight_init_funcs(struct intel_panel *panel)
if (intel_dp_aux_init_backlight_funcs(connector) == 0)
return;
- if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
+ if (!intel_has_quirk(dev_priv, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
connector->panel.backlight.power = intel_pps_backlight_power;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b7702c4581aa..f5416433826d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -57,6 +57,7 @@
#include "intel_lspcon.h"
#include "intel_pps.h"
#include "intel_psr.h"
+#include "intel_quirks.h"
#include "intel_snps_phy.h"
#include "intel_sprite.h"
#include "intel_tc.h"
@@ -631,7 +632,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
- if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
+ if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
drm_dbg_kms(&dev_priv->drm,
"Quirk Increase DDI disabled time\n");
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 43dbc5a3ec37..a1b4ef1ad917 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -37,13 +37,14 @@
#include "intel_display_types.h"
#include "intel_drrs.h"
#include "intel_panel.h"
+#include "intel_quirks.h"
bool intel_panel_use_ssc(struct drm_i915_private *i915)
{
if (i915->params.panel_use_ssc >= 0)
return i915->params.panel_use_ssc != 0;
- return i915->display.vbt.lvds_use_ssc
- && !(i915->quirks & QUIRK_LVDS_SSC_DISABLE);
+ return i915->display.vbt.lvds_use_ssc &&
+ !intel_has_quirk(i915, QUIRK_LVDS_SSC_DISABLE);
}
const struct drm_display_mode *
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 9a66e03aa2d6..21944f5bf3a8 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -12,6 +12,7 @@
#include "intel_dpll.h"
#include "intel_lvds.h"
#include "intel_pps.h"
+#include "intel_quirks.h"
static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
enum pipe pipe);
@@ -1202,7 +1203,7 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp,
* just fails to power back on. Increasing the delay to 800ms
* seems sufficient to avoid this problem.
*/
- if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
+ if (intel_has_quirk(dev_priv, QUIRK_INCREASE_T12_DELAY)) {
vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10);
drm_dbg_kms(&dev_priv->drm,
"Increasing T12 panel delay as per the quirk to %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index e415cd7c0b84..edc82d115434 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -216,3 +216,8 @@ void intel_init_quirks(struct drm_i915_private *i915)
intel_dmi_quirks[i].hook(i915);
}
}
+
+bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk)
+{
+ return i915->quirks & quirk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h
index b0fcff142a56..f5e399a6e7d3 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.h
+++ b/drivers/gpu/drm/i915/display/intel_quirks.h
@@ -6,8 +6,11 @@
#ifndef __INTEL_QUIRKS_H__
#define __INTEL_QUIRKS_H__
+#include <linux/types.h>
+
struct drm_i915_private;
-void intel_init_quirks(struct drm_i915_private *dev_priv);
+void intel_init_quirks(struct drm_i915_private *i915);
+bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk);
#endif /* __INTEL_QUIRKS_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 15/18] drm/i915/quirks: abstract quirks further by making quirk ids an enum
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (13 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 14/18] drm/i915/quirks: abstract checking for display quirks Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 16/18] drm/i915: move quirks under display sub-struct Jani Nikula
` (7 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Turn the quirk ids to enums instead of bits, and hide the masking inside
intel_quirks.c. Define the enums in intel_quirks.h to declutter
i915_drv.h while at it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_quirks.c | 21 +++++++++++++--------
drivers/gpu/drm/i915/display/intel_quirks.h | 11 ++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 7 -------
3 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index edc82d115434..41caeda795cb 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -9,12 +9,17 @@
#include "intel_display_types.h"
#include "intel_quirks.h"
+static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
+{
+ i915->quirks |= BIT(quirk);
+}
+
/*
* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
*/
static void quirk_ssc_force_disable(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_LVDS_SSC_DISABLE;
+ intel_set_quirk(i915, QUIRK_LVDS_SSC_DISABLE);
drm_info(&i915->drm, "applying lvds SSC disable quirk\n");
}
@@ -24,14 +29,14 @@ static void quirk_ssc_force_disable(struct drm_i915_private *i915)
*/
static void quirk_invert_brightness(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INVERT_BRIGHTNESS;
+ intel_set_quirk(i915, QUIRK_INVERT_BRIGHTNESS);
drm_info(&i915->drm, "applying inverted panel brightness quirk\n");
}
/* Some VBT's incorrectly indicate no backlight is present */
static void quirk_backlight_present(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_BACKLIGHT_PRESENT;
+ intel_set_quirk(i915, QUIRK_BACKLIGHT_PRESENT);
drm_info(&i915->drm, "applying backlight present quirk\n");
}
@@ -40,7 +45,7 @@ static void quirk_backlight_present(struct drm_i915_private *i915)
*/
static void quirk_increase_t12_delay(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INCREASE_T12_DELAY;
+ intel_set_quirk(i915, QUIRK_INCREASE_T12_DELAY);
drm_info(&i915->drm, "Applying T12 delay quirk\n");
}
@@ -50,13 +55,13 @@ static void quirk_increase_t12_delay(struct drm_i915_private *i915)
*/
static void quirk_increase_ddi_disabled_time(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+ intel_set_quirk(i915, QUIRK_INCREASE_DDI_DISABLED_TIME);
drm_info(&i915->drm, "Applying Increase DDI Disabled quirk\n");
}
static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK;
+ intel_set_quirk(i915, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK);
drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
}
@@ -217,7 +222,7 @@ void intel_init_quirks(struct drm_i915_private *i915)
}
}
-bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk)
+bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- return i915->quirks & quirk;
+ return i915->quirks & BIT(quirk);
}
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h
index f5e399a6e7d3..10a4d163149f 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.h
+++ b/drivers/gpu/drm/i915/display/intel_quirks.h
@@ -10,7 +10,16 @@
struct drm_i915_private;
+enum intel_quirk_id {
+ QUIRK_BACKLIGHT_PRESENT,
+ QUIRK_INCREASE_DDI_DISABLED_TIME,
+ QUIRK_INCREASE_T12_DELAY,
+ QUIRK_INVERT_BRIGHTNESS,
+ QUIRK_LVDS_SSC_DISABLE,
+ QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
+};
+
void intel_init_quirks(struct drm_i915_private *i915);
-bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk);
+bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk);
#endif /* __INTEL_QUIRKS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5aac06da3cc7..c486a1dcfb07 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -90,13 +90,6 @@ struct vlv_s0ix_state;
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
-#define QUIRK_LVDS_SSC_DISABLE (1<<1)
-#define QUIRK_INVERT_BRIGHTNESS (1<<2)
-#define QUIRK_BACKLIGHT_PRESENT (1<<3)
-#define QUIRK_INCREASE_T12_DELAY (1<<6)
-#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
-#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
-
struct i915_suspend_saved_registers {
u32 saveDSPARB;
u32 saveSWF0[16];
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 16/18] drm/i915: move quirks under display sub-struct
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (14 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 15/18] drm/i915/quirks: abstract quirks further by making quirk ids an enum Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 17/18] drm/i915: move atomic_helper " Jani Nikula
` (6 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display quirk related members under drm_i915_private display
sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4 ++++
drivers/gpu/drm/i915/display/intel_quirks.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 -
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 31fd05a04bff..577ab7765fa9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -365,6 +365,10 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ unsigned long mask;
+ } quirks;
+
struct {
enum {
I915_SAGV_UNKNOWN = 0,
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index 41caeda795cb..6e48d3bcdfec 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -11,7 +11,7 @@
static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- i915->quirks |= BIT(quirk);
+ i915->display.quirks.mask |= BIT(quirk);
}
/*
@@ -224,5 +224,5 @@ void intel_init_quirks(struct drm_i915_private *i915)
bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- return i915->quirks & BIT(quirk);
+ return i915->display.quirks.mask & BIT(quirk);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c486a1dcfb07..47f2629da226 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -291,7 +291,6 @@ struct drm_i915_private {
unsigned short pch_id;
unsigned long gem_quirks;
- unsigned long quirks;
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 17/18] drm/i915: move atomic_helper under display sub-struct
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (15 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 16/18] drm/i915: move quirks under display sub-struct Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 18/18] drm/i915: move and group properties under display.properties Jani Nikula
` (5 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display atomic helper related members under drm_i915_private
display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
drivers/gpu/drm/i915/display/intel_display_core.h | 6 ++++++
drivers/gpu/drm/i915/i915_drv.h | 5 -----
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5fb027ff5246..be7cff722196 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7408,7 +7408,7 @@ static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
struct intel_atomic_state *state, *next;
struct llist_node *freed;
- freed = llist_del_all(&dev_priv->atomic_helper.free_list);
+ freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
llist_for_each_entry_safe(state, next, freed, freed)
drm_atomic_state_put(&state->base);
}
@@ -7416,7 +7416,7 @@ static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
static void intel_atomic_helper_free_state_worker(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), atomic_helper.free_work);
+ container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
intel_atomic_helper_free_state(dev_priv);
}
@@ -7709,7 +7709,7 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
case FENCE_FREE:
{
struct intel_atomic_helper *helper =
- &to_i915(state->base.dev)->atomic_helper;
+ &to_i915(state->base.dev)->display.atomic_helper;
if (llist_add(&state->freed, &helper->free_list))
schedule_work(&helper->free_work);
@@ -8704,8 +8704,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
- init_llist_head(&i915->atomic_helper.free_list);
- INIT_WORK(&i915->atomic_helper.free_work,
+ init_llist_head(&i915->display.atomic_helper.free_list);
+ INIT_WORK(&i915->display.atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
intel_init_quirks(i915);
@@ -8998,8 +8998,8 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
flush_workqueue(i915->display.wq.flip);
flush_workqueue(i915->display.wq.modeset);
- flush_work(&i915->atomic_helper.free_work);
- drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
+ flush_work(&i915->display.atomic_helper.free_work);
+ drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list));
}
/* part #2: call after irq uninstall */
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 577ab7765fa9..bf78b0fcbd11 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -7,6 +7,7 @@
#define __INTEL_DISPLAY_CORE_H__
#include <linux/list.h>
+#include <linux/llist.h>
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/wait.h>
@@ -268,6 +269,11 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct intel_atomic_helper {
+ struct llist_head free_list;
+ struct work_struct free_work;
+ } atomic_helper;
+
struct {
/* backlight registers and fields in struct intel_panel */
struct mutex lock;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 47f2629da226..9dc1f2b19702 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -301,11 +301,6 @@ struct drm_i915_private {
struct list_head global_obj_list;
- struct intel_atomic_helper {
- struct llist_head free_list;
- struct work_struct free_work;
- } atomic_helper;
-
bool mchbar_need_disable;
struct intel_l3_parity l3_parity;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH v3 18/18] drm/i915: move and group properties under display.properties
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (16 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 17/18] drm/i915: move atomic_helper " Jani Nikula
@ 2022-08-29 13:18 ` Jani Nikula
2022-08-29 18:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display sub-struct to drm_i915_private (rev3) Patchwork
` (4 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-29 13:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi
Move display property related members under drm_i915_private display
sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_connector.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_display_core.h | 6 ++++++
drivers/gpu/drm/i915/i915_drv.h | 3 ---
4 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index b94973b5633f..18f0a5ae3bac 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -62,9 +62,9 @@ int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property)
+ if (property == dev_priv->display.properties.force_audio)
*val = intel_conn_state->force_audio;
- else if (property == dev_priv->broadcast_rgb_property)
+ else if (property == dev_priv->display.properties.broadcast_rgb)
*val = intel_conn_state->broadcast_rgb;
else {
drm_dbg_atomic(&dev_priv->drm,
@@ -95,12 +95,12 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property) {
+ if (property == dev_priv->display.properties.force_audio) {
intel_conn_state->force_audio = val;
return 0;
}
- if (property == dev_priv->broadcast_rgb_property) {
+ if (property == dev_priv->display.properties.broadcast_rgb) {
intel_conn_state->broadcast_rgb = val;
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c
index 1dcc268927a2..6d5cbeb8df4d 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -229,7 +229,7 @@ intel_attach_force_audio_property(struct drm_connector *connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->force_audio_property;
+ prop = dev_priv->display.properties.force_audio;
if (prop == NULL) {
prop = drm_property_create_enum(dev, 0,
"audio",
@@ -238,7 +238,7 @@ intel_attach_force_audio_property(struct drm_connector *connector)
if (prop == NULL)
return;
- dev_priv->force_audio_property = prop;
+ dev_priv->display.properties.force_audio = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
}
@@ -256,7 +256,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->broadcast_rgb_property;
+ prop = dev_priv->display.properties.broadcast_rgb;
if (prop == NULL) {
prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
"Broadcast RGB",
@@ -265,7 +265,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector)
if (prop == NULL)
return;
- dev_priv->broadcast_rgb_property = prop;
+ dev_priv->display.properties.broadcast_rgb = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index bf78b0fcbd11..9086a612365e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -27,6 +27,7 @@
#include "intel_pm_types.h"
struct drm_i915_private;
+struct drm_property;
struct i915_audio_component;
struct i915_hdcp_comp_master;
struct intel_atomic_state;
@@ -371,6 +372,11 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ struct drm_property *broadcast_rgb;
+ struct drm_property *force_audio;
+ } properties;
+
struct {
unsigned long mask;
} quirks;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9dc1f2b19702..5eb6a5cd0c8c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -321,9 +321,6 @@ struct drm_i915_private {
struct i915_gpu_error gpu_error;
- struct drm_property *broadcast_rgb_property;
- struct drm_property *force_audio_property;
-
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working in the presence hardware
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display sub-struct to drm_i915_private (rev3)
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (17 preceding siblings ...)
2022-08-29 13:18 ` [Intel-gfx] [PATCH v3 18/18] drm/i915: move and group properties under display.properties Jani Nikula
@ 2022-08-29 18:17 ` Patchwork
2022-08-29 18:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-08-29 18:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private (rev3)
URL : https://patchwork.freedesktop.org/series/107170/
State : warning
== Summary ==
Error: dim checkpatch failed
b9427de47e84 drm/i915: move and group hdcp under display.hdcp
38c5ef38c07f drm/i915: move and group max_bw and bw_obj under display.bw
188be8254ff5 drm/i915: move opregion to display.opregion
4a5d9830abcd drm/i915: move and group cdclk under display.cdclk
-:43: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/intel_audio.c:974:
+ get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);
-:704: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#704: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:80:
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
-:707: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#707: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:82:
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
-:735: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#735: FILE: drivers/gpu/drm/i915/display/intel_display.c:8401:
+ cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
total: 0 errors, 3 warnings, 1 checks, 815 lines checked
dc34d78592ca drm/i915: move backlight to display.backlight
0f8dc6218ed1 drm/i915: move mipi_mmio_base to display.dsi
5b04974fa687 drm/i915: move vbt to display.vbt
-:124: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#124: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1157:
+ i915->display.vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7;
-:931: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#931: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2773:
+ pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
total: 0 errors, 2 warnings, 0 checks, 1031 lines checked
dde24b693f2b drm/i915: move fbc to display.fbc
ee6883528cb3 drm/i915: move and group power related members under display.power
-:388: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#388: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:1916:
+ POWER_DOMAIN_INIT);
-:403: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#403: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:1942:
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
-:448: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#448: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:2063:
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
total: 0 errors, 3 warnings, 0 checks, 685 lines checked
a10ed581da9a drm/i915: move and group fdi members under display.fdi
9ac4a6704fb4 drm/i915: move fb_tracking under display sub-struct
-:27: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#27: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:124:
+ spinlock_t lock;
-:33: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#33: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:130:
+ unsigned busy_bits;
-:34: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#34: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:131:
+ unsigned flip_bits;
total: 0 errors, 2 warnings, 1 checks, 200 lines checked
cee54e8c5f62 drm/i915: move dbuf under display sub-struct
-:182: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#182: FILE: drivers/gpu/drm/i915/intel_pm.h:80:
+ to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
-:185: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#185: FILE: drivers/gpu/drm/i915/intel_pm.h:82:
+ to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
total: 0 errors, 2 warnings, 0 checks, 136 lines checked
d01d1ea53004 drm/i915: move and group modeset_wq and flip_wq under display.wq
649d16ff4f98 drm/i915/quirks: abstract checking for display quirks
-:40: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_backlight.c:132:
+ (dev_priv->params.invert_brightness == 0 && intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)))
total: 0 errors, 1 warnings, 0 checks, 105 lines checked
18f3f330cd08 drm/i915/quirks: abstract quirks further by making quirk ids an enum
9cb21285a019 drm/i915: move quirks under display sub-struct
0b5f46827012 drm/i915: move atomic_helper under display sub-struct
69ef45caaf55 drm/i915: move and group properties under display.properties
^ permalink raw reply [flat|nested] 24+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add display sub-struct to drm_i915_private (rev3)
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (18 preceding siblings ...)
2022-08-29 18:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display sub-struct to drm_i915_private (rev3) Patchwork
@ 2022-08-29 18:17 ` Patchwork
2022-08-29 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-08-29 18:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private (rev3)
URL : https://patchwork.freedesktop.org/series/107170/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 24+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add display sub-struct to drm_i915_private (rev3)
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (19 preceding siblings ...)
2022-08-29 18:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-08-29 18:45 ` Patchwork
2022-08-31 9:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-08-31 14:49 ` [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
22 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-08-29 18:45 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6375 bytes --]
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private (rev3)
URL : https://patchwork.freedesktop.org/series/107170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12044 -> Patchwork_107170v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/index.html
Participating hosts (40 -> 37)
------------------------------
Missing (3): fi-ctg-p8600 fi-bdw-samus fi-hsw-4200u
Known issues
------------
Here are the changes found in Patchwork_107170v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][1] -> [INCOMPLETE][2] ([i915#4785])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/fi-pnv-d510/igt@i915_selftest@live@requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/fi-bdw-5557u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#4312] / [i915#5594] / [i915#6246])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][7] ([i915#2867]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@gt_pm:
- bat-adlp-4: [DMESG-FAIL][9] ([i915#3987]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/bat-adlp-4/igt@i915_selftest@live@gt_pm.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/bat-adlp-4/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [INCOMPLETE][11] ([i915#146] / [i915#6598]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][13] ([i915#4957]) -> [DMESG-FAIL][14] ([i915#4494] / [i915#4957])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6380]: https://gitlab.freedesktop.org/drm/intel/issues/6380
[i915#6523]: https://gitlab.freedesktop.org/drm/intel/issues/6523
[i915#6530]: https://gitlab.freedesktop.org/drm/intel/issues/6530
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
Build changes
-------------
* Linux: CI_DRM_12044 -> Patchwork_107170v3
CI-20190529: 20190529
CI_DRM_12044: 287ad23d60ce7aa8befbe8dd1fea6fb705bd08ac @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6637: a23e8aed0b54018339647d0817267431bd2b7075 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107170v3: 287ad23d60ce7aa8befbe8dd1fea6fb705bd08ac @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
22e9f90bcecb drm/i915: move and group properties under display.properties
621bf44c068b drm/i915: move atomic_helper under display sub-struct
2dfb695bf25e drm/i915: move quirks under display sub-struct
90fbf5710ced drm/i915/quirks: abstract quirks further by making quirk ids an enum
93552b56060b drm/i915/quirks: abstract checking for display quirks
8e0d53f40741 drm/i915: move and group modeset_wq and flip_wq under display.wq
550ac6eb8df2 drm/i915: move dbuf under display sub-struct
49b22bed8e09 drm/i915: move fb_tracking under display sub-struct
8808c1cfd81b drm/i915: move and group fdi members under display.fdi
55d08a273f6d drm/i915: move and group power related members under display.power
4351ce867a46 drm/i915: move fbc to display.fbc
3b2c5a5781f6 drm/i915: move vbt to display.vbt
39d2b0cf99db drm/i915: move mipi_mmio_base to display.dsi
116a206d1c53 drm/i915: move backlight to display.backlight
0f9748559959 drm/i915: move and group cdclk under display.cdclk
4203b8947165 drm/i915: move opregion to display.opregion
94a7c1652a0d drm/i915: move and group max_bw and bw_obj under display.bw
b2750dd9319b drm/i915: move and group hdcp under display.hdcp
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/index.html
[-- Attachment #2: Type: text/html, Size: 7126 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add display sub-struct to drm_i915_private (rev3)
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (20 preceding siblings ...)
2022-08-29 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-08-31 9:29 ` Patchwork
2022-08-31 14:49 ` [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
22 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-08-31 9:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 24860 bytes --]
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private (rev3)
URL : https://patchwork.freedesktop.org/series/107170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12044_full -> Patchwork_107170v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_107170v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb2/igt@gem_exec_balancer@parallel.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb7/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][3] ([i915#2846])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_userptr_blits@huge-split:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#3376])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl1/igt@gem_userptr_blits@huge-split.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl4/igt@gem_userptr_blits@huge-split.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#454])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886]) +9 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#3886])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl1/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@vga-frame-dump:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][14] -> [FAIL][15] ([i915#4767])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [PASS][16] -> [FAIL][17] ([i915#79])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl8/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl7/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#3555]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2672]) +5 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][20] ([i915#265])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][21] ([fdo#108145] / [i915#265]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-dp-1:
- shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271]) +93 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-dp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][23] -> [SKIP][24] ([i915#5235]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#658]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][26] -> [SKIP][27] ([fdo#109441]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#2437]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_writeback@writeback-pixel-formats.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#2994]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@sysfs_clients@fair-7.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][32] ([i915#6268]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-tglu-6/igt@gem_ctx_exec@basic-nohangcheck.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-tglu-1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [TIMEOUT][34] ([i915#3070]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb8/igt@gem_eio@in-flight-contexts-10ms.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][36] ([i915#4525]) -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][38] ([i915#2842]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [FAIL][40] ([i915#2842]) -> [PASS][41] +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][42] ([i915#5566] / [i915#716]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl2/igt@gen9_exec_parse@allowed-single.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
- shard-apl: [DMESG-WARN][44] ([i915#180]) -> [PASS][45] +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl2/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl8/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-kbl: [FAIL][46] ([i915#1188]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl1/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][48] ([fdo#109441]) -> [PASS][49] +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb1/igt@kms_psr@psr2_primary_blt.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][50] ([i915#180]) -> [PASS][51] +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@perf@polling-parameterized:
- shard-apl: [FAIL][52] ([i915#5639]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl3/igt@perf@polling-parameterized.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl2/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][54] ([i915#588]) -> [SKIP][55] ([i915#658])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [FAIL][56] ([i915#4767]) -> [INCOMPLETE][57] ([i915#180] / [i915#4939] / [i915#6598])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][58] ([i915#658]) -> [SKIP][59] ([i915#2920]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][60] ([i915#2920]) -> [SKIP][61] ([i915#658]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb7/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: [SKIP][62] ([fdo#111068] / [i915#658]) -> [SKIP][63] ([i915#2920])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-iclb1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][64], [FAIL][65], [FAIL][66], [FAIL][67], [FAIL][68], [FAIL][69]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][70], [FAIL][71]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl7/igt@runner@aborted.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl2/igt@runner@aborted.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl7/igt@runner@aborted.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl2/igt@runner@aborted.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl2/igt@runner@aborted.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-apl6/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl6/igt@runner@aborted.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-apl7/igt@runner@aborted.html
- shard-kbl: ([FAIL][72], [FAIL][73], [FAIL][74], [FAIL][75], [FAIL][76], [FAIL][77]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][78], [FAIL][79], [FAIL][80], [FAIL][81], [FAIL][82], [FAIL][83], [FAIL][84], [FAIL][85], [FAIL][86]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl7/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl7/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl7/igt@runner@aborted.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl4/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl7/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12044/shard-kbl7/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl7/igt@runner@aborted.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl7/igt@runner@aborted.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl4/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl1/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl7/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl4/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl4/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl7/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/shard-kbl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* Linux: CI_DRM_12044 -> Patchwork_107170v3
CI-20190529: 20190529
CI_DRM_12044: 287ad23d60ce7aa8befbe8dd1fea6fb705bd08ac @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6637: a23e8aed0b54018339647d0817267431bd2b7075 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107170v3: 287ad23d60ce7aa8befbe8dd1fea6fb705bd08ac @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v3/index.html
[-- Attachment #2: Type: text/html, Size: 24050 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private
2022-08-29 13:18 [Intel-gfx] [PATCH v3 00/18] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (21 preceding siblings ...)
2022-08-31 9:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-08-31 14:49 ` Jani Nikula
22 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2022-08-31 14:49 UTC (permalink / raw)
To: intel-gfx
On Mon, 29 Aug 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> v3 of https://patchwork.freedesktop.org/series/107170/
>
> Dropped already merged patches, rebased the rest.
And pushed the lot to drm-intel-next. Thanks for the review.
BR,
Jani.
>
> Jani Nikula (18):
> drm/i915: move and group hdcp under display.hdcp
> drm/i915: move and group max_bw and bw_obj under display.bw
> drm/i915: move opregion to display.opregion
> drm/i915: move and group cdclk under display.cdclk
> drm/i915: move backlight to display.backlight
> drm/i915: move mipi_mmio_base to display.dsi
> drm/i915: move vbt to display.vbt
> drm/i915: move fbc to display.fbc
> drm/i915: move and group power related members under display.power
> drm/i915: move and group fdi members under display.fdi
> drm/i915: move fb_tracking under display sub-struct
> drm/i915: move dbuf under display sub-struct
> drm/i915: move and group modeset_wq and flip_wq under display.wq
> drm/i915/quirks: abstract checking for display quirks
> drm/i915/quirks: abstract quirks further by making quirk ids an enum
> drm/i915: move quirks under display sub-struct
> drm/i915: move atomic_helper under display sub-struct
> drm/i915: move and group properties under display.properties
>
> drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
> drivers/gpu/drm/i915/display/intel_atomic.c | 8 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 6 +-
> .../gpu/drm/i915/display/intel_backlight.c | 41 ++--
> drivers/gpu/drm/i915/display/intel_bios.c | 216 +++++++++---------
> drivers/gpu/drm/i915/display/intel_bw.c | 42 ++--
> drivers/gpu/drm/i915/display/intel_cdclk.c | 206 ++++++++---------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 4 +-
> .../gpu/drm/i915/display/intel_connector.c | 8 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 8 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 56 ++---
> .../gpu/drm/i915/display/intel_display_core.h | 155 +++++++++++++
> .../drm/i915/display/intel_display_debugfs.c | 10 +-
> .../drm/i915/display/intel_display_power.c | 122 +++++-----
> .../i915/display/intel_display_power_map.c | 4 +-
> .../i915/display/intel_display_power_well.c | 60 ++---
> .../i915/display/intel_display_power_well.h | 12 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 14 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 +-
> drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 10 +-
> .../gpu/drm/i915/display/intel_frontbuffer.c | 54 ++---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +++++------
> drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
> .../drm/i915/display/intel_modeset_setup.c | 12 +-
> drivers/gpu/drm/i915/display/intel_opregion.c | 42 ++--
> drivers/gpu/drm/i915/display/intel_panel.c | 5 +-
> .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 3 +-
> drivers/gpu/drm/i915/display/intel_quirks.c | 22 +-
> drivers/gpu/drm/i915/display/intel_quirks.h | 14 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 18 +-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 +-
> .../drm/i915/display/skl_universal_plane.c | 2 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 188 +++++++--------
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_driver.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 153 +------------
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 16 +-
> drivers/gpu/drm/i915/intel_pm.h | 4 +-
> 50 files changed, 885 insertions(+), 843 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
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