* [PATCH 0/2] Add some missing dt bindings for Hikey970 @ 2020-08-19 9:52 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 9+ messages in thread From: Mauro Carvalho Chehab @ 2020-08-19 9:52 UTC (permalink / raw) To: Rob Herring Cc: linuxarm, mauro.chehab, Mauro Carvalho Chehab, John Stultz, Manivannan Sadhasivam, linux-kernel, Wei Xu, devicetree, linux-arm-kernel Currently, the DT bindings for Kirin 970 and Hikey 970 are incomplete: they're missing the I2C buses and several pinctrl. Add those, as they'll be needed by upcoming drivers for DRM and USB. Mauro Carvalho Chehab (2): dts: hisilicon: hi3670.dtsi: add I2C settings dts: hikey970-pinctrl.dtsi: add missing pinctrl settings arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++ .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 548 +++++++++++++++++- 2 files changed, 608 insertions(+), 11 deletions(-) -- 2.26.2 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/2] Add some missing dt bindings for Hikey970 @ 2020-08-19 9:52 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 9+ messages in thread From: Mauro Carvalho Chehab @ 2020-08-19 9:52 UTC (permalink / raw) To: Rob Herring Cc: devicetree, Manivannan Sadhasivam, Mauro Carvalho Chehab, linuxarm, Wei Xu, linux-kernel, John Stultz, mauro.chehab, linux-arm-kernel Currently, the DT bindings for Kirin 970 and Hikey 970 are incomplete: they're missing the I2C buses and several pinctrl. Add those, as they'll be needed by upcoming drivers for DRM and USB. Mauro Carvalho Chehab (2): dts: hisilicon: hi3670.dtsi: add I2C settings dts: hikey970-pinctrl.dtsi: add missing pinctrl settings arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++ .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 548 +++++++++++++++++- 2 files changed, 608 insertions(+), 11 deletions(-) -- 2.26.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] dts: hisilicon: hi3670.dtsi: add I2C settings 2020-08-19 9:52 ` Mauro Carvalho Chehab @ 2020-08-19 9:52 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 9+ messages in thread From: Mauro Carvalho Chehab @ 2020-08-19 9:52 UTC (permalink / raw) To: Rob Herring Cc: linuxarm, mauro.chehab, Mauro Carvalho Chehab, John Stultz, Manivannan Sadhasivam, Wei Xu, linux-arm-kernel, devicetree, linux-kernel The I2C buses are not declared at the device tree. As this will be needed by further patches, add them, keeping all in disabled state. Per-board settings can override it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index b1acb4fb1d1c..416f69c782d7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -723,5 +723,76 @@ dwmmc2: dwmmc2@fc183000 { card-detect-delay = <200>; status = "disabled"; }; + + /* I2C */ + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c2: i2c@ffd73000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd73000 0x0 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C2>; + resets = <&iomcu_rst 0x20 5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c4: i2c@fdf0d000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0d000 0x0 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>; + resets = <&crg_rst 0x78 27>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>; + status = "disabled"; + }; }; }; -- 2.26.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/2] dts: hisilicon: hi3670.dtsi: add I2C settings @ 2020-08-19 9:52 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 9+ messages in thread From: Mauro Carvalho Chehab @ 2020-08-19 9:52 UTC (permalink / raw) To: Rob Herring Cc: devicetree, Manivannan Sadhasivam, Mauro Carvalho Chehab, linuxarm, Wei Xu, linux-kernel, John Stultz, mauro.chehab, linux-arm-kernel The I2C buses are not declared at the device tree. As this will be needed by further patches, add them, keeping all in disabled state. Per-board settings can override it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index b1acb4fb1d1c..416f69c782d7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -723,5 +723,76 @@ dwmmc2: dwmmc2@fc183000 { card-detect-delay = <200>; status = "disabled"; }; + + /* I2C */ + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c2: i2c@ffd73000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd73000 0x0 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C2>; + resets = <&iomcu_rst 0x20 5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c4: i2c@fdf0d000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0d000 0x0 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>; + resets = <&crg_rst 0x78 27>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>; + status = "disabled"; + }; }; }; -- 2.26.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] dts: hisilicon: hi3670.dtsi: add I2C settings 2020-08-19 9:52 ` Mauro Carvalho Chehab (?) @ 2020-08-19 18:27 ` kernel test robot -1 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2020-08-19 18:27 UTC (permalink / raw) To: Mauro Carvalho Chehab, Rob Herring Cc: kbuild-all, clang-built-linux, linux-media, linuxarm, mauro.chehab, Mauro Carvalho Chehab, John Stultz, Manivannan Sadhasivam, Wei Xu, linux-arm-kernel, devicetree [-- Attachment #1: Type: text/plain, Size: 1455 bytes --] Hi Mauro, I love your patch! Yet something to improve: [auto build test ERROR on robh/for-next] [also build test ERROR on v5.9-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Mauro-Carvalho-Chehab/Add-some-missing-dt-bindings-for-Hikey970/20200819-175403 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arm64-randconfig-r034-20200818 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project b34b1e38381fa4d1b1d9751a6b5233b68e734cfe) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> ERROR: Input tree has errors, aborting (use -f to force output) --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 35684 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] dts: hisilicon: hi3670.dtsi: add I2C settings @ 2020-08-19 18:27 ` kernel test robot 0 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2020-08-19 18:27 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 1489 bytes --] Hi Mauro, I love your patch! Yet something to improve: [auto build test ERROR on robh/for-next] [also build test ERROR on v5.9-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Mauro-Carvalho-Chehab/Add-some-missing-dt-bindings-for-Hikey970/20200819-175403 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arm64-randconfig-r034-20200818 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project b34b1e38381fa4d1b1d9751a6b5233b68e734cfe) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> ERROR: Input tree has errors, aborting (use -f to force output) --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org [-- Attachment #2: config.gz --] [-- Type: application/gzip, Size: 35684 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] dts: hisilicon: hi3670.dtsi: add I2C settings @ 2020-08-19 18:27 ` kernel test robot 0 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2020-08-19 18:27 UTC (permalink / raw) To: Mauro Carvalho Chehab, Rob Herring Cc: devicetree, kbuild-all, Manivannan Sadhasivam, linuxarm, Wei Xu, clang-built-linux, John Stultz, mauro.chehab, Mauro Carvalho Chehab, linux-arm-kernel, linux-media [-- Attachment #1: Type: text/plain, Size: 1455 bytes --] Hi Mauro, I love your patch! Yet something to improve: [auto build test ERROR on robh/for-next] [also build test ERROR on v5.9-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Mauro-Carvalho-Chehab/Add-some-missing-dt-bindings-for-Hikey970/20200819-175403 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arm64-randconfig-r034-20200818 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project b34b1e38381fa4d1b1d9751a6b5233b68e734cfe) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> ERROR: Input tree has errors, aborting (use -f to force output) --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 35684 bytes --] [-- Attachment #3: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] dts: hikey970-pinctrl.dtsi: add missing pinctrl settings 2020-08-19 9:52 ` Mauro Carvalho Chehab @ 2020-08-19 9:52 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 9+ messages in thread From: Mauro Carvalho Chehab @ 2020-08-19 9:52 UTC (permalink / raw) To: Rob Herring Cc: linuxarm, mauro.chehab, Mauro Carvalho Chehab, John Stultz, Manivannan Sadhasivam, Wei Xu, linux-arm-kernel, devicetree, linux-kernel There are several pinctrl settings that are missing at this DT file. Also, the entries are out of order. Add the missing bits, as they'll be required by the DRM driver - and probably by other drivers not upstreamed yet. Reorder the entres, adding the missing bits. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 548 +++++++++++++++++- 1 file changed, 537 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index d456b0aa6f58..75723a1ad5ab 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -61,6 +61,153 @@ uart6_pmx_func: uart6_pmx_func { 0x060 MUX_M1 /* UART6_TXD */ >; }; + + i2c3_pmx_func: i2c3_pmx_func { + pinctrl-single,pins = < + 0x010 MUX_M1 /* I2C3_SCL */ + 0x014 MUX_M1 /* I2C3_SDA */ + >; + }; + + i2c4_pmx_func: i2c4_pmx_func { + pinctrl-single,pins = < + 0x03c MUX_M1 /* I2C4_SCL */ + 0x040 MUX_M1 /* I2C4_SDA */ + >; + }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x714 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x048 MUX_M0 /* CAM1_RST */ + >; + }; + + cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x098 MUX_M0 /* CAM0_PWD_N */ + >; + }; + + cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CAM1_PWD_N */ + >; + }; + + isp0_pmx_func: isp0_pmx_func { + pinctrl-single,pins = < + 0x018 MUX_M1 /* ISP_CLK0 */ + 0x024 MUX_M1 /* ISP_SCL0 */ + 0x028 MUX_M1 /* ISP_SDA0 */ + >; + }; + + isp1_pmx_func: isp1_pmx_func { + pinctrl-single,pins = < + 0x01c MUX_M1 /* ISP_CLK1 */ + 0x02c MUX_M1 /* ISP_SCL1 */ + 0x030 MUX_M1 /* ISP_SDA1 */ + >; + }; + }; + + pmx1: pinmux@fff11000 { + compatible = "pinctrl-single"; + reg = <0x0 0xfff11000 0x0 0x73c>; + #gpio-range-cells = <0x3>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 46 0>; + + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x064 MUX_M0 /* GPIO_203 */ + >; + }; + + pd_pmx_func: pd_pmx_func{ + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_221 */ + >; + }; + + i2s2_pmx_func: i2s2_pmx_func { + pinctrl-single,pins = < + 0x050 MUX_M1 /* I2S2_DI */ + 0x054 MUX_M1 /* I2S2_DO */ + 0x058 MUX_M1 /* I2S2_XCLK */ + 0x05c MUX_M1 /* I2S2_XFS */ + >; + }; + + spi0_pmx_func: spi0_pmx_func { + pinctrl-single,pins = < + 0x094 MUX_M1 /* SPI0_CLK */ + 0x098 MUX_M1 /* SPI0_DI */ + 0x09c MUX_M1 /* SPI0_DO */ + 0x0a0 MUX_M1 /* SPI0_CS0_N */ + >; + }; + + spi2_pmx_func: spi2_pmx_func { + pinctrl-single,pins = < + 0x710 MUX_M1 /* SPI2_CLK */ + 0x714 MUX_M1 /* SPI2_DI */ + 0x718 MUX_M1 /* SPI2_DO */ + 0x71c MUX_M1 /* SPI2_CS0_N */ + >; + }; + + spi3_pmx_func: spi3_pmx_func { + pinctrl-single,pins = < + 0x72c MUX_M1 /* SPI3_CLK */ + 0x730 MUX_M1 /* SPI3_DI */ + 0x734 MUX_M1 /* SPI3_DO */ + 0x738 MUX_M1 /* SPI3_CS0_N */ + >; + }; + + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0x020 MUX_M1 /* I2C0_SCL */ + 0x024 MUX_M1 /* I2C0_SDA */ + >; + }; + + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0x028 MUX_M1 /* I2C1_SCL */ + 0x02c MUX_M1 /* I2C1_SDA */ + >; + }; + i2c2_pmx_func: i2c2_pmx_func { + pinctrl-single,pins = < + 0x030 MUX_M1 /* I2C2_SCL */ + 0x034 MUX_M1 /* I2C2_SDA */ + >; + }; + + pcie_clkreq_pmx_func: pcie_clkreq_pmx_func { + pinctrl-single,pins = < + 0x084 MUX_M1 /* PCIE0_CLKREQ_N */ + >; + }; + + gpio185_pmx_func: gpio185_pmx_func { + pinctrl-single,pins = <0x01C 0x1>; + }; + + gpio185_pmx_idle: gpio185_pmx_idle { + pinctrl-single,pins = <0x01C 0x0>; + }; }; pmx2: pinmux@e896c800 { @@ -184,6 +331,108 @@ PULL_UP DRIVE7_02MA DRIVE6_MASK >; }; + + i2c3_cfg_func: i2c3_cfg_func { + pinctrl-single,pins = < + 0x014 0x0 /* I2C3_SCL */ + 0x018 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c4_cfg_func: i2c4_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2C4_SCL */ + 0x044 0x0 /* I2C4_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x714 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x04C 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x09C 0x0 /* CAM0_PWD_N */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x048 0x0 /* CAM1_PWD_N */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x01C 0x0 /* ISP_CLK0 */ + 0x028 0x0 /* ISP_SCL0 */ + 0x02C 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + isp1_cfg_func: isp1_cfg_func { + pinctrl-single,pins = < + 0x020 0x0 /* ISP_CLK1 */ + 0x030 0x0 /* ISP_SCL1 */ + 0x034 0x0 /* ISP_SDA1 */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; }; pmx5: pinmux@fc182000 { @@ -338,22 +587,299 @@ DRIVE6_MASK }; }; - pmx1: pinmux@fff11000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfff11000 0x0 0x73c>; - #gpio-range-cells = <0x3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 46 0>; - }; - pmx16: pinmux@fff11800 { compatible = "pinconf-single"; reg = <0x0 0xfff11800 0x0 0x73c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; + + pwr_key_cfg_func: pwr_key_cfg_func { + pinctrl-single,pins = < + 0x090 0x0 /* GPIO_203 */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0AC 0x0 /* GPIO_221 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi0_cfg_func: spi0_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* SPI0_DI */ + 0x0cc 0x0 /* SPI0_DO */ + 0x0d0 0x0 /* SPI0_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x714 0x0 /* SPI2_DI */ + 0x718 0x0 /* SPI2_DO */ + 0x71c 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x730 0x0 /* SPI3_DI */ + 0x734 0x0 /* SPI3_DO */ + 0x738 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi0_clk_cfg_func: spi0_clk_cfg_func { + pinctrl-single,pins = < + 0x0c4 0x0 /* SPI0_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + spi2_clk_cfg_func: spi2_clk_cfg_func { + pinctrl-single,pins = < + 0x710 0x0 /* SPI2_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + spi3_clk_cfg_func: spi3_clk_cfg_func { + pinctrl-single,pins = < + 0x72c 0x0 /* SPI3_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x04c 0x0 /* I2C0_SCL */ + 0x050 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x054 0x0 /* I2C1_SCL */ + 0x058 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c2_cfg_func: i2c2_cfg_func { + pinctrl-single,pins = < + 0x05c 0x0 /* I2C2_SCL */ + 0x060 0x0 /* I2C2_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + pcie_clkreq_cfg_func: pcie_clkreq_cfg_func { + pinctrl-single,pins = < + 0x0b0 0x0 + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x07c 0x0 /* I2S2_DI */ + 0x080 0x0 /* I2S2_DO */ + 0x084 0x0 /* I2S2_XCLK */ + 0x088 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + gpio185_cfg_func: gpio185_cfg_func { + pinctrl-single,pins = <0x048 0>; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x00 0x70>; + pinctrl-single,slew-rate = <0x0 0x80>; + }; + + gpio185_cfg_idle: gpio185_cfg_idle { + pinctrl-single,pins = <0x048 0>; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x00 0x70>; + pinctrl-single,slew-rate = <0x0 0x80>; + }; }; }; }; -- 2.26.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] dts: hikey970-pinctrl.dtsi: add missing pinctrl settings @ 2020-08-19 9:52 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 9+ messages in thread From: Mauro Carvalho Chehab @ 2020-08-19 9:52 UTC (permalink / raw) To: Rob Herring Cc: devicetree, Manivannan Sadhasivam, Mauro Carvalho Chehab, linuxarm, Wei Xu, linux-kernel, John Stultz, mauro.chehab, linux-arm-kernel There are several pinctrl settings that are missing at this DT file. Also, the entries are out of order. Add the missing bits, as they'll be required by the DRM driver - and probably by other drivers not upstreamed yet. Reorder the entres, adding the missing bits. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 548 +++++++++++++++++- 1 file changed, 537 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index d456b0aa6f58..75723a1ad5ab 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -61,6 +61,153 @@ uart6_pmx_func: uart6_pmx_func { 0x060 MUX_M1 /* UART6_TXD */ >; }; + + i2c3_pmx_func: i2c3_pmx_func { + pinctrl-single,pins = < + 0x010 MUX_M1 /* I2C3_SCL */ + 0x014 MUX_M1 /* I2C3_SDA */ + >; + }; + + i2c4_pmx_func: i2c4_pmx_func { + pinctrl-single,pins = < + 0x03c MUX_M1 /* I2C4_SCL */ + 0x040 MUX_M1 /* I2C4_SDA */ + >; + }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x714 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x048 MUX_M0 /* CAM1_RST */ + >; + }; + + cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x098 MUX_M0 /* CAM0_PWD_N */ + >; + }; + + cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CAM1_PWD_N */ + >; + }; + + isp0_pmx_func: isp0_pmx_func { + pinctrl-single,pins = < + 0x018 MUX_M1 /* ISP_CLK0 */ + 0x024 MUX_M1 /* ISP_SCL0 */ + 0x028 MUX_M1 /* ISP_SDA0 */ + >; + }; + + isp1_pmx_func: isp1_pmx_func { + pinctrl-single,pins = < + 0x01c MUX_M1 /* ISP_CLK1 */ + 0x02c MUX_M1 /* ISP_SCL1 */ + 0x030 MUX_M1 /* ISP_SDA1 */ + >; + }; + }; + + pmx1: pinmux@fff11000 { + compatible = "pinctrl-single"; + reg = <0x0 0xfff11000 0x0 0x73c>; + #gpio-range-cells = <0x3>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 46 0>; + + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x064 MUX_M0 /* GPIO_203 */ + >; + }; + + pd_pmx_func: pd_pmx_func{ + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_221 */ + >; + }; + + i2s2_pmx_func: i2s2_pmx_func { + pinctrl-single,pins = < + 0x050 MUX_M1 /* I2S2_DI */ + 0x054 MUX_M1 /* I2S2_DO */ + 0x058 MUX_M1 /* I2S2_XCLK */ + 0x05c MUX_M1 /* I2S2_XFS */ + >; + }; + + spi0_pmx_func: spi0_pmx_func { + pinctrl-single,pins = < + 0x094 MUX_M1 /* SPI0_CLK */ + 0x098 MUX_M1 /* SPI0_DI */ + 0x09c MUX_M1 /* SPI0_DO */ + 0x0a0 MUX_M1 /* SPI0_CS0_N */ + >; + }; + + spi2_pmx_func: spi2_pmx_func { + pinctrl-single,pins = < + 0x710 MUX_M1 /* SPI2_CLK */ + 0x714 MUX_M1 /* SPI2_DI */ + 0x718 MUX_M1 /* SPI2_DO */ + 0x71c MUX_M1 /* SPI2_CS0_N */ + >; + }; + + spi3_pmx_func: spi3_pmx_func { + pinctrl-single,pins = < + 0x72c MUX_M1 /* SPI3_CLK */ + 0x730 MUX_M1 /* SPI3_DI */ + 0x734 MUX_M1 /* SPI3_DO */ + 0x738 MUX_M1 /* SPI3_CS0_N */ + >; + }; + + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0x020 MUX_M1 /* I2C0_SCL */ + 0x024 MUX_M1 /* I2C0_SDA */ + >; + }; + + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0x028 MUX_M1 /* I2C1_SCL */ + 0x02c MUX_M1 /* I2C1_SDA */ + >; + }; + i2c2_pmx_func: i2c2_pmx_func { + pinctrl-single,pins = < + 0x030 MUX_M1 /* I2C2_SCL */ + 0x034 MUX_M1 /* I2C2_SDA */ + >; + }; + + pcie_clkreq_pmx_func: pcie_clkreq_pmx_func { + pinctrl-single,pins = < + 0x084 MUX_M1 /* PCIE0_CLKREQ_N */ + >; + }; + + gpio185_pmx_func: gpio185_pmx_func { + pinctrl-single,pins = <0x01C 0x1>; + }; + + gpio185_pmx_idle: gpio185_pmx_idle { + pinctrl-single,pins = <0x01C 0x0>; + }; }; pmx2: pinmux@e896c800 { @@ -184,6 +331,108 @@ PULL_UP DRIVE7_02MA DRIVE6_MASK >; }; + + i2c3_cfg_func: i2c3_cfg_func { + pinctrl-single,pins = < + 0x014 0x0 /* I2C3_SCL */ + 0x018 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c4_cfg_func: i2c4_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2C4_SCL */ + 0x044 0x0 /* I2C4_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x714 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x04C 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x09C 0x0 /* CAM0_PWD_N */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x048 0x0 /* CAM1_PWD_N */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x01C 0x0 /* ISP_CLK0 */ + 0x028 0x0 /* ISP_SCL0 */ + 0x02C 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; + + isp1_cfg_func: isp1_cfg_func { + pinctrl-single,pins = < + 0x020 0x0 /* ISP_CLK1 */ + 0x030 0x0 /* ISP_SCL1 */ + 0x034 0x0 /* ISP_SDA1 */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_04MA DRIVE6_MASK>; + }; }; pmx5: pinmux@fc182000 { @@ -338,22 +587,299 @@ DRIVE6_MASK }; }; - pmx1: pinmux@fff11000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfff11000 0x0 0x73c>; - #gpio-range-cells = <0x3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 46 0>; - }; - pmx16: pinmux@fff11800 { compatible = "pinconf-single"; reg = <0x0 0xfff11800 0x0 0x73c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; + + pwr_key_cfg_func: pwr_key_cfg_func { + pinctrl-single,pins = < + 0x090 0x0 /* GPIO_203 */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0AC 0x0 /* GPIO_221 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi0_cfg_func: spi0_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* SPI0_DI */ + 0x0cc 0x0 /* SPI0_DO */ + 0x0d0 0x0 /* SPI0_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x714 0x0 /* SPI2_DI */ + 0x718 0x0 /* SPI2_DO */ + 0x71c 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x730 0x0 /* SPI3_DI */ + 0x734 0x0 /* SPI3_DO */ + 0x738 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi0_clk_cfg_func: spi0_clk_cfg_func { + pinctrl-single,pins = < + 0x0c4 0x0 /* SPI0_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + spi2_clk_cfg_func: spi2_clk_cfg_func { + pinctrl-single,pins = < + 0x710 0x0 /* SPI2_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + spi3_clk_cfg_func: spi3_clk_cfg_func { + pinctrl-single,pins = < + 0x72c 0x0 /* SPI3_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x04c 0x0 /* I2C0_SCL */ + 0x050 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x054 0x0 /* I2C1_SCL */ + 0x058 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c2_cfg_func: i2c2_cfg_func { + pinctrl-single,pins = < + 0x05c 0x0 /* I2C2_SCL */ + 0x060 0x0 /* I2C2_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + pcie_clkreq_cfg_func: pcie_clkreq_cfg_func { + pinctrl-single,pins = < + 0x0b0 0x0 + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x07c 0x0 /* I2S2_DI */ + 0x080 0x0 /* I2S2_DO */ + 0x084 0x0 /* I2S2_XCLK */ + 0x088 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + gpio185_cfg_func: gpio185_cfg_func { + pinctrl-single,pins = <0x048 0>; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x00 0x70>; + pinctrl-single,slew-rate = <0x0 0x80>; + }; + + gpio185_cfg_idle: gpio185_cfg_idle { + pinctrl-single,pins = <0x048 0>; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x00 0x70>; + pinctrl-single,slew-rate = <0x0 0x80>; + }; }; }; }; -- 2.26.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-08-19 18:49 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-19 9:52 [PATCH 0/2] Add some missing dt bindings for Hikey970 Mauro Carvalho Chehab 2020-08-19 9:52 ` Mauro Carvalho Chehab 2020-08-19 9:52 ` [PATCH 1/2] dts: hisilicon: hi3670.dtsi: add I2C settings Mauro Carvalho Chehab 2020-08-19 9:52 ` Mauro Carvalho Chehab 2020-08-19 18:27 ` kernel test robot 2020-08-19 18:27 ` kernel test robot 2020-08-19 18:27 ` kernel test robot 2020-08-19 9:52 ` [PATCH 2/2] dts: hikey970-pinctrl.dtsi: add missing pinctrl settings Mauro Carvalho Chehab 2020-08-19 9:52 ` Mauro Carvalho Chehab
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