[PATCH v1 0/3] ARM: imx6sx: add enet support

[PATCH v1 0/3] ARM: imx6sx: add enet support

[Fugang Duan]

The three patches just to enable enet1 and enet2 for imx6sx-sdb boards.


Fugang Duan (3):
  ARM: imx6sx: add imx6sx iomux-gpr field define
  ARM: imx: add enet init for i.mx6sx
  ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

 arch/arm/boot/dts/imx6sx-sdb.dts            |   28 +++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi               |    2 +-
 arch/arm/mach-imx/mach-imx6sx.c             |   51 +++++++++++++++++++++++++++
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |   39 ++++++++++++++++++++
 4 files changed, 119 insertions(+), 1 deletions(-)

-- 
1.7.8

[PATCH v1 1/3] ARM: imx6sx: add imx6sx iomux-gpr field define

[Fugang Duan]

Add imx6sx iomux-gpr register field define in "imx6q-iomuxc-gpr.h" header
file, which is not fully define all iomux-gpr registers and fields, only
align with freescale internal tree related GPR macro define.

Signed-off-by: Fugang Duan <B38611@freescale.com>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |   39 +++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..c877cad 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -395,4 +395,43 @@
 #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
 #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
 
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR1_VDEC_SW_RST_MASK			(0x1 << 20)
+#define IMX6SX_GPR1_VDEC_SW_RST_RESET			(0x1 << 20)
+#define IMX6SX_GPR1_VDEC_SW_RST_RELEASE			(0x0 << 20)
+#define IMX6SX_GPR1_VADC_SW_RST_MASK			(0x1 << 19)
+#define IMX6SX_GPR1_VADC_SW_RST_RESET			(0x1 << 19)
+#define IMX6SX_GPR1_VADC_SW_RST_RELEASE			(0x0 << 19)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK		(0x3 << 13)
+#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK		(0x3 << 17)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT		(0x3 << 13)
+
+#define IMX6SX_GPR4_FEC_ENET1_STOP_REQ			(0x1 << 3)
+#define IMX6SX_GPR4_FEC_ENET2_STOP_REQ			(0x1 << 4)
+
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK		(0x1 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1		(0x0 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2		(0x1 << 3)
+
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK			(0x3 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN		(0x0 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD			(0x1 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI		(0x2 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_GND			(0x3 << 27)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK		(0x1 << 26)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE	(0x1 << 26)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE	(0x0 << 26)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN		(0x0 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD			(0x1 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI		(0x2 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND			(0x3 << 4)
+
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2		(0x0 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS			(0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK			(0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1		(0x0 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS			(0x1 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK			(0x1 << 1)
+
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.7.8

[PATCH v1 2/3] ARM: imx: add enet init for i.mx6sx

[Fugang Duan]

Add enet init for i.mx6sx:
- Add phy ar8031 fixup
- Set enet clock source from internal PLL

Signed-off-by: Fugang Duan <B38611@freescale.com>
---
 arch/arm/mach-imx/mach-imx6sx.c |   51 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 3de3b73..9822249 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -8,12 +8,62 @@
 
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
 #include "cpuidle.h"
 
+static int ar8031_phy_fixup(struct phy_device *dev)
+{
+	u16 val;
+
+	/* Set RGMII IO voltage to 1.8V */
+	phy_write(dev, 0x1d, 0x1f);
+	phy_write(dev, 0x1e, 0x8);
+
+	/* introduce tx clock delay */
+	phy_write(dev, 0x1d, 0x5);
+	val = phy_read(dev, 0x1e);
+	val |= 0x0100;
+	phy_write(dev, 0x1e, val);
+
+	return 0;
+}
+
+#define PHY_ID_AR8031   0x004dd074
+static void __init imx6sx_enet_phy_init(void)
+{
+	if (IS_BUILTIN(CONFIG_PHYLIB))
+		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
+					   ar8031_phy_fixup);
+}
+
+static void __init imx6sx_enet_clk_sel(void)
+{
+	struct regmap *gpr;
+
+	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
+	if (!IS_ERR(gpr)) {
+		regmap_update_bits(gpr, IOMUXC_GPR1,
+				   IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
+		regmap_update_bits(gpr, IOMUXC_GPR1,
+				   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
+	} else {
+		pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
+	}
+}
+
+static inline void imx6sx_enet_init(void)
+{
+	imx6sx_enet_phy_init();
+	imx6sx_enet_clk_sel();
+}
+
 static void __init imx6sx_init_machine(void)
 {
 	struct device *parent;
@@ -26,6 +76,7 @@ static void __init imx6sx_init_machine(void)
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 
+	imx6sx_enet_init();
 	imx_anatop_init();
 	imx6sx_pm_init();
 }
-- 
1.7.8

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[Fugang Duan]

Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
compatible for fec2 node to be compatible with the old version.

Signed-off-by: Fugang Duan <B38611@freescale.com>
---
 arch/arm/boot/dts/imx6sx-sdb.dts |   28 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi    |    2 +-
 2 files changed, 29 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 82d6b34..06e0977 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -133,6 +133,14 @@
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
+	pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6 GPIO_ACTIVE_LOW>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
 	phy-mode = "rgmii";
 	status = "okay";
 };
@@ -394,6 +402,26 @@
 				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
 				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
 				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
+				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000
+				MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19	0x80000000
+				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
+				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
+				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
+				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
+				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
+				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
+				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
+				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
+				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
+				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
+				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
+				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
 			>;
 		};
 
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 888dd76..5a36053 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -875,7 +875,7 @@
 			};
 
 			fec2: ethernet at 021b4000 {
-				compatible = "fsl,imx6sx-fec";
+				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 				reg = <0x021b4000 0x4000>;
 				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-- 
1.7.8

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[Shawn Guo]

On Wed, Sep 24, 2014 at 10:11:20AM +0800, Fugang Duan wrote:
> Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
> compatible for fec2 node to be compatible with the old version.
> 
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> ---
>  arch/arm/boot/dts/imx6sx-sdb.dts |   28 ++++++++++++++++++++++++++++
>  arch/arm/boot/dts/imx6sx.dtsi    |    2 +-
>  2 files changed, 29 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
> index 82d6b34..06e0977 100644
> --- a/arch/arm/boot/dts/imx6sx-sdb.dts
> +++ b/arch/arm/boot/dts/imx6sx-sdb.dts
> @@ -133,6 +133,14 @@
>  &fec1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_enet1>;
> +	pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6 GPIO_ACTIVE_LOW>;

I do not think this property is supported by upstream kernel.

> +	phy-mode = "rgmii";
> +	status = "okay";
> +};
> +
> +&fec2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet2>;
>  	phy-mode = "rgmii";
>  	status = "okay";
>  };
> @@ -394,6 +402,26 @@
>  				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
>  				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
>  				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
> +				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000
> +				MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19	0x80000000
> +				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
> +			>;
> +		};
> +
> +		pinctrl_enet2: enet2grp {
> +			fsl,pins = <
> +				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
> +				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
> +				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
> +				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
> +				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
> +				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
> +				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
> +				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
> +				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
> +				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
> +				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
> +				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
>  			>;
>  		};
>  
> diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> index 888dd76..5a36053 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -875,7 +875,7 @@
>  			};
>  
>  			fec2: ethernet at 021b4000 {
> -				compatible = "fsl,imx6sx-fec";
> +				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";

Why is this change is necessary?  If "fsl,imx6sx-fec" is supported by
driver, it can be matched.

Shawn

>  				reg = <0x021b4000 0x4000>;
>  				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>  					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> -- 
> 1.7.8
> 

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[fugang.duan at freescale.com]

From: Guo Shawn-R65073 Sent: Sunday, September 28, 2014 11:29 AM + 0800
>To: Duan Fugang-B38611
>Cc: linux-arm-kernel at lists.infradead.org; b20596 at solarflare.com;
>shawn.guo at linaro.org; kernel at pengutronix.de
>Subject: Re: [PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-
>sdb board
>
>On Wed, Sep 24, 2014 at 10:11:20AM +0800, Fugang Duan wrote:
>> Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
>> compatible for fec2 node to be compatible with the old version.
>>
>> Signed-off-by: Fugang Duan <B38611@freescale.com>
>> ---
>>  arch/arm/boot/dts/imx6sx-sdb.dts |   28 ++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/imx6sx.dtsi    |    2 +-
>>  2 files changed, 29 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts
>> b/arch/arm/boot/dts/imx6sx-sdb.dts
>> index 82d6b34..06e0977 100644
>> --- a/arch/arm/boot/dts/imx6sx-sdb.dts
>> +++ b/arch/arm/boot/dts/imx6sx-sdb.dts
>> @@ -133,6 +133,14 @@
>>  &fec1 {
>>  	pinctrl-names = "default";
>>  	pinctrl-0 = <&pinctrl_enet1>;
>> +	pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6
>> +GPIO_ACTIVE_LOW>;
>
>I do not think this property is supported by upstream kernel.
The upstream kernel how to handle it ?

>
>> +	phy-mode = "rgmii";
>> +	status = "okay";
>> +};
>> +
>> +&fec2 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_enet2>;
>>  	phy-mode = "rgmii";
>>  	status = "okay";
>>  };
>> @@ -394,6 +402,26 @@
>>  				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
>>  				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
>>  				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
>> +				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000
>> +				MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19	0x80000000
>> +				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
>> +			>;
>> +		};
>> +
>> +		pinctrl_enet2: enet2grp {
>> +			fsl,pins = <
>> +				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
>> +				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
>> +				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
>> +				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
>> +				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
>> +				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
>> +				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
>> +				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
>> +				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
>> +				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
>> +				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
>> +				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
>>  			>;
>>  		};
>>
>> diff --git a/arch/arm/boot/dts/imx6sx.dtsi
>> b/arch/arm/boot/dts/imx6sx.dtsi index 888dd76..5a36053 100644
>> --- a/arch/arm/boot/dts/imx6sx.dtsi
>> +++ b/arch/arm/boot/dts/imx6sx.dtsi
>> @@ -875,7 +875,7 @@
>>  			};
>>
>>  			fec2: ethernet at 021b4000 {
>> -				compatible = "fsl,imx6sx-fec";
>> +				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
>
>Why is this change is necessary?  If "fsl,imx6sx-fec" is supported by
>driver, it can be matched.
>
>Shawn
- I want to let it align with fec1 compatible
- Your tree still have no imx6sx enet patch, so fec2 will don't work at your tree. But the ip
  Is compatible with imx6q-fec, so add the compatible.

>
>>  				reg = <0x021b4000 0x4000>;
>>  				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>>  					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
>> --
>> 1.7.8
>>

Thanks,
Andy

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[Shawn Guo]

On Sun, Sep 28, 2014 at 11:34:39AM +0800, Duan Fugang-B38611 wrote:
> From: Guo Shawn-R65073 Sent: Sunday, September 28, 2014 11:29 AM + 0800
> >To: Duan Fugang-B38611
> >Cc: linux-arm-kernel at lists.infradead.org; b20596 at solarflare.com;
> >shawn.guo at linaro.org; kernel at pengutronix.de
> >Subject: Re: [PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-
> >sdb board
> >
> >On Wed, Sep 24, 2014 at 10:11:20AM +0800, Fugang Duan wrote:
> >> Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
> >> compatible for fec2 node to be compatible with the old version.
> >>
> >> Signed-off-by: Fugang Duan <B38611@freescale.com>
> >> ---
> >>  arch/arm/boot/dts/imx6sx-sdb.dts |   28 ++++++++++++++++++++++++++++
> >>  arch/arm/boot/dts/imx6sx.dtsi    |    2 +-
> >>  2 files changed, 29 insertions(+), 1 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts
> >> b/arch/arm/boot/dts/imx6sx-sdb.dts
> >> index 82d6b34..06e0977 100644
> >> --- a/arch/arm/boot/dts/imx6sx-sdb.dts
> >> +++ b/arch/arm/boot/dts/imx6sx-sdb.dts
> >> @@ -133,6 +133,14 @@
> >>  &fec1 {
> >>  	pinctrl-names = "default";
> >>  	pinctrl-0 = <&pinctrl_enet1>;
> >> +	pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6
> >> +GPIO_ACTIVE_LOW>;
> >
> >I do not think this property is supported by upstream kernel.
> The upstream kernel how to handle it ?

What are the purpose of these two GPIOs?

> 
> >
> >> +	phy-mode = "rgmii";
> >> +	status = "okay";
> >> +};
> >> +
> >> +&fec2 {
> >> +	pinctrl-names = "default";
> >> +	pinctrl-0 = <&pinctrl_enet2>;
> >>  	phy-mode = "rgmii";
> >>  	status = "okay";
> >>  };
> >> @@ -394,6 +402,26 @@
> >>  				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
> >>  				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
> >>  				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
> >> +				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000
> >> +				MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19	0x80000000
> >> +				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
> >> +			>;
> >> +		};
> >> +
> >> +		pinctrl_enet2: enet2grp {
> >> +			fsl,pins = <
> >> +				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
> >> +				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
> >> +				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
> >> +				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
> >> +				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
> >> +				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
> >> +				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
> >> +				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
> >> +				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
> >> +				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
> >> +				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
> >> +				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
> >>  			>;
> >>  		};
> >>
> >> diff --git a/arch/arm/boot/dts/imx6sx.dtsi
> >> b/arch/arm/boot/dts/imx6sx.dtsi index 888dd76..5a36053 100644
> >> --- a/arch/arm/boot/dts/imx6sx.dtsi
> >> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> >> @@ -875,7 +875,7 @@
> >>  			};
> >>
> >>  			fec2: ethernet at 021b4000 {
> >> -				compatible = "fsl,imx6sx-fec";
> >> +				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
> >
> >Why is this change is necessary?  If "fsl,imx6sx-fec" is supported by
> >driver, it can be matched.
> >
> >Shawn
> - I want to let it align with fec1 compatible
> - Your tree still have no imx6sx enet patch, so fec2 will don't work at your tree. But the ip
>   Is compatible with imx6q-fec, so add the compatible.

Okay.

Shawn

> 
> >
> >>  				reg = <0x021b4000 0x4000>;
> >>  				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> >>  					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> >> --
> >> 1.7.8
> >>
> 
> Thanks,
> Andy

[PATCH v1 0/3] ARM: imx6sx: add enet support

[Shawn Guo]

On Wed, Sep 24, 2014 at 10:11:17AM +0800, Fugang Duan wrote:
> The three patches just to enable enet1 and enet2 for imx6sx-sdb boards.
> 
> 
> Fugang Duan (3):
>   ARM: imx6sx: add imx6sx iomux-gpr field define
>   ARM: imx: add enet init for i.mx6sx

Applied these two.

>   ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[fugang.duan at freescale.com]

From: Guo Shawn-R65073 Sent: Sunday, September 28, 2014 11:42 AM + 0800
>To: Duan Fugang-B38611
>Cc: linux-arm-kernel at lists.infradead.org; b20596 at solarflare.com;
>shawn.guo at linaro.org; kernel at pengutronix.de
>Subject: Re: [PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-
>sdb board
>
>On Sun, Sep 28, 2014 at 11:34:39AM +0800, Duan Fugang-B38611 wrote:
>> From: Guo Shawn-R65073 Sent: Sunday, September 28, 2014 11:29 AM +
>> 0800
>> >To: Duan Fugang-B38611
>> >Cc: linux-arm-kernel at lists.infradead.org; b20596 at solarflare.com;
>> >shawn.guo at linaro.org; kernel at pengutronix.de
>> >Subject: Re: [PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for
>> >imx6sx- sdb board
>> >
>> >On Wed, Sep 24, 2014 at 10:11:20AM +0800, Fugang Duan wrote:
>> >> Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
>> >> compatible for fec2 node to be compatible with the old version.
>> >>
>> >> Signed-off-by: Fugang Duan <B38611@freescale.com>
>> >> ---
>> >>  arch/arm/boot/dts/imx6sx-sdb.dts |   28 ++++++++++++++++++++++++++++
>> >>  arch/arm/boot/dts/imx6sx.dtsi    |    2 +-
>> >>  2 files changed, 29 insertions(+), 1 deletions(-)
>> >>
>> >> diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts
>> >> b/arch/arm/boot/dts/imx6sx-sdb.dts
>> >> index 82d6b34..06e0977 100644
>> >> --- a/arch/arm/boot/dts/imx6sx-sdb.dts
>> >> +++ b/arch/arm/boot/dts/imx6sx-sdb.dts
>> >> @@ -133,6 +133,14 @@
>> >>  &fec1 {
>> >>  	pinctrl-names = "default";
>> >>  	pinctrl-0 = <&pinctrl_enet1>;
>> >> +	pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6
>> >> +GPIO_ACTIVE_LOW>;
>> >
>> >I do not think this property is supported by upstream kernel.
>> The upstream kernel how to handle it ?
>
>What are the purpose of these two GPIOs?

MX6SX_PAD_ENET2_COL__GPIO2_IO_6: it is a switch which enable ENET_3V3 and 25Mhz clock for phy.
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16: it is a switch which enable PERI_3V3 that supply power for some modules including enet MAC and phy.

Regards,
Andy

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[Shawn Guo]

On Sun, Sep 28, 2014 at 01:20:16PM +0800, Duan Fugang-B38611 wrote:
> MX6SX_PAD_ENET2_COL__GPIO2_IO_6: it is a switch which enable ENET_3V3 and 25Mhz clock for phy.
> MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16: it is a switch which enable PERI_3V3 that supply power for some modules including enet MAC and phy.
> 

So it sounds like they can be handled with fixed regulators?

Shawn

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[fugang.duan at freescale.com]

From: Guo Shawn-R65073 Sent: Sunday, September 28, 2014 1:32 PM + 0800
>To: Duan Fugang-B38611
>Cc: linux-arm-kernel at lists.infradead.org; b20596 at solarflare.com;
>shawn.guo at linaro.org; kernel at pengutronix.de
>Subject: Re: [PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-
>sdb board
>
>On Sun, Sep 28, 2014 at 01:20:16PM +0800, Duan Fugang-B38611 wrote:
>> MX6SX_PAD_ENET2_COL__GPIO2_IO_6: it is a switch which enable ENET_3V3
>and 25Mhz clock for phy.
>> MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16: it is a switch which enable
>PERI_3V3 that supply power for some modules including enet MAC and phy.
>>
>
>So it sounds like they can be handled with fixed regulators?
>
>Shawn

It make sense that it use fixed regulators.  I change it for next version.

Thanks,
Andy

[PATCH v1 3/3] ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board

[Fugang Duan]

Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
compatible for fec2 node to be compatible with the old version.

Signed-off-by: Fugang Duan <B38611@freescale.com>
---
 arch/arm/boot/dts/imx6sx-sdb.dts |   28 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi    |    2 +-
 2 files changed, 29 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 82d6b34..06e0977 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -133,6 +133,14 @@
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
+	pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6 GPIO_ACTIVE_LOW>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
 	phy-mode = "rgmii";
 	status = "okay";
 };
@@ -394,6 +402,26 @@
 				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
 				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
 				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
+				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000
+				MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19	0x80000000
+				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
+				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
+				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
+				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
+				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
+				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
+				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
+				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
+				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
+				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
+				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
+				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
 			>;
 		};
 
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 888dd76..5a36053 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -875,7 +875,7 @@
 			};
 
 			fec2: ethernet at 021b4000 {
-				compatible = "fsl,imx6sx-fec";
+				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 				reg = <0x021b4000 0x4000>;
 				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-- 
1.7.8