[PATCH v3 0/3] add the reset controller to the Meson8b clkc

[PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Martin Blumenstingl]

This registers the known (soft) reset lines provided by the clock
controller's registers.

This is the first preparation step for SMP and CPU hotplug support on
Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
requires asserting and de-asserting a reset line (one for each CPU
core). These reset lines are provided by the clock controller.

The reset controller part of the meson8b clock controller has to be
registered early (which I did through CLK_OF_DECLARE_DRIVER), because
the secondary cores are started *very* early in the boot process (and
meson8b_clkc_probe is invoked long after we need the reset controller
to be available for booting the secondary CPU cores).

The user of the reset-controller (= the patches which enable SMP and
CPU hotplug support) will follow in the next days. I decided to split
this because the SMP series will probably consist of 6 patches alone
(and may need to go through two separate trees).

Changes since v2 at [3]:
- move the reset line preprocessor defines into a separate file
  (affects patch #1 as this header file is part of the dt-binding)
- rename the reset line preprocessor macros from RESETID_ to
  CLKC_RESET_ to clearly indicate that these are provided by the
  clock controller (unlike the preprocessor macros for the reset
  lines in the standlone reset controller, which start with RESET_)
- updated patch #2 due to the changes mentioned above
- added Neil's Reviewed-by to all patches

Changes since v1 at [0]:
- updated cover letter description as we are now registering more than
  four reset lines
- split patch #1 into a dt-binding and clk driver patch
- slightly reworded the dt-binding documentation so it's now clear that
  the reset identifiers are preprocessor macros in
  dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
  macros at all)
- patch #2 (previously part of patch #1) now registers all known reset
  lines (see [1] and [2] for the results of my detective work)
- patch #3 is untouched


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html


Martin Blumenstingl (3):
  dt-bindings: clock: meson8b: describe the embedded reset controller
  clk: meson: meson8b: register the built-in reset controller
  ARM: dts: meson: mark the clock controller also as reset controller

 .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
 arch/arm/boot/dts/meson8.dtsi                      |   1 +
 arch/arm/boot/dts/meson8b.dtsi                     |   1 +
 drivers/clk/meson/Kconfig                          |   1 +
 drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++--
 drivers/clk/meson/meson8b.h                        |   9 +-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
 7 files changed, 193 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

-- 
2.13.3

[PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Martin Blumenstingl]

This registers the known (soft) reset lines provided by the clock
controller's registers.

This is the first preparation step for SMP and CPU hotplug support on
Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
requires asserting and de-asserting a reset line (one for each CPU
core). These reset lines are provided by the clock controller.

The reset controller part of the meson8b clock controller has to be
registered early (which I did through CLK_OF_DECLARE_DRIVER), because
the secondary cores are started *very* early in the boot process (and
meson8b_clkc_probe is invoked long after we need the reset controller
to be available for booting the secondary CPU cores).

The user of the reset-controller (= the patches which enable SMP and
CPU hotplug support) will follow in the next days. I decided to split
this because the SMP series will probably consist of 6 patches alone
(and may need to go through two separate trees).

Changes since v2 at [3]:
- move the reset line preprocessor defines into a separate file
  (affects patch #1 as this header file is part of the dt-binding)
- rename the reset line preprocessor macros from RESETID_ to
  CLKC_RESET_ to clearly indicate that these are provided by the
  clock controller (unlike the preprocessor macros for the reset
  lines in the standlone reset controller, which start with RESET_)
- updated patch #2 due to the changes mentioned above
- added Neil's Reviewed-by to all patches

Changes since v1 at [0]:
- updated cover letter description as we are now registering more than
  four reset lines
- split patch #1 into a dt-binding and clk driver patch
- slightly reworded the dt-binding documentation so it's now clear that
  the reset identifiers are preprocessor macros in
  dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
  macros at all)
- patch #2 (previously part of patch #1) now registers all known reset
  lines (see [1] and [2] for the results of my detective work)
- patch #3 is untouched


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html


Martin Blumenstingl (3):
  dt-bindings: clock: meson8b: describe the embedded reset controller
  clk: meson: meson8b: register the built-in reset controller
  ARM: dts: meson: mark the clock controller also as reset controller

 .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
 arch/arm/boot/dts/meson8.dtsi                      |   1 +
 arch/arm/boot/dts/meson8b.dtsi                     |   1 +
 drivers/clk/meson/Kconfig                          |   1 +
 drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++--
 drivers/clk/meson/meson8b.h                        |   9 +-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
 7 files changed, 193 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

-- 
2.13.3

[PATCH v3 1/3] dt-bindings: clock: meson8b: describe the embedded reset controller

[Martin Blumenstingl]

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.

This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 .../bindings/clock/amlogic,meson8b-clkc.txt        |  9 +++++++-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h | 27 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 606da38c0959..c858fd64f680 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -16,18 +16,25 @@ Required Properties:
 	   mapped region.
 
 - #clock-cells: should be 1.
+- #reset-cells: should be 1.
 
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
 used in device tree sources.
 
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
 Example: Clock controller node:
 
 	clkc: clock-controller@c1104000 {
-		#clock-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 
diff --git a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
new file mode 100644
index 000000000000..1f1b56e57346
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+
+#define CLKC_RESET_L2_CACHE_SOFT_RESET				0
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
+#define CLKC_RESET_SCU_SOFT_RESET				2
+#define CLKC_RESET_CPU0_SOFT_RESET				3
+#define CLKC_RESET_CPU1_SOFT_RESET				4
+#define CLKC_RESET_CPU2_SOFT_RESET				5
+#define CLKC_RESET_CPU3_SOFT_RESET				6
+#define CLKC_RESET_A5_GLOBAL_RESET				7
+#define CLKC_RESET_A5_AXI_SOFT_RESET				8
+#define CLKC_RESET_A5_ABP_SOFT_RESET				9
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET		10
+#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET			11
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST		12
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE		13
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST		14
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE			15
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
-- 
2.13.3

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[PATCH v3 1/3] dt-bindings: clock: meson8b: describe the embedded reset controller

[Martin Blumenstingl]

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.

This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 .../bindings/clock/amlogic,meson8b-clkc.txt        |  9 +++++++-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h | 27 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 606da38c0959..c858fd64f680 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -16,18 +16,25 @@ Required Properties:
 	   mapped region.
 
 - #clock-cells: should be 1.
+- #reset-cells: should be 1.
 
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
 used in device tree sources.
 
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
 Example: Clock controller node:
 
 	clkc: clock-controller@c1104000 {
-		#clock-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 
diff --git a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
new file mode 100644
index 000000000000..1f1b56e57346
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+
+#define CLKC_RESET_L2_CACHE_SOFT_RESET				0
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
+#define CLKC_RESET_SCU_SOFT_RESET				2
+#define CLKC_RESET_CPU0_SOFT_RESET				3
+#define CLKC_RESET_CPU1_SOFT_RESET				4
+#define CLKC_RESET_CPU2_SOFT_RESET				5
+#define CLKC_RESET_CPU3_SOFT_RESET				6
+#define CLKC_RESET_A5_GLOBAL_RESET				7
+#define CLKC_RESET_A5_AXI_SOFT_RESET				8
+#define CLKC_RESET_A5_ABP_SOFT_RESET				9
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET		10
+#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET			11
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST		12
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE		13
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST		14
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE			15
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
-- 
2.13.3

[PATCH v3 1/3] dt-bindings: clock: meson8b: describe the embedded reset controller

[Martin Blumenstingl]

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.

This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 .../bindings/clock/amlogic,meson8b-clkc.txt        |  9 +++++++-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h | 27 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 606da38c0959..c858fd64f680 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -16,18 +16,25 @@ Required Properties:
 	   mapped region.
 
 - #clock-cells: should be 1.
+- #reset-cells: should be 1.
 
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
 used in device tree sources.
 
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
 Example: Clock controller node:
 
 	clkc: clock-controller at c1104000 {
-		#clock-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 
diff --git a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
new file mode 100644
index 000000000000..1f1b56e57346
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+
+#define CLKC_RESET_L2_CACHE_SOFT_RESET				0
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
+#define CLKC_RESET_SCU_SOFT_RESET				2
+#define CLKC_RESET_CPU0_SOFT_RESET				3
+#define CLKC_RESET_CPU1_SOFT_RESET				4
+#define CLKC_RESET_CPU2_SOFT_RESET				5
+#define CLKC_RESET_CPU3_SOFT_RESET				6
+#define CLKC_RESET_A5_GLOBAL_RESET				7
+#define CLKC_RESET_A5_AXI_SOFT_RESET				8
+#define CLKC_RESET_A5_ABP_SOFT_RESET				9
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET		10
+#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET			11
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST		12
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE		13
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST		14
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE			15
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
-- 
2.13.3

[PATCH v3 2/3] clk: meson: meson8b: register the built-in reset controller

[Martin Blumenstingl]

The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).

According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET

All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.

Suggested-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 drivers/clk/meson/Kconfig   |   1 +
 drivers/clk/meson/meson8b.c | 159 ++++++++++++++++++++++++++++++++++++++++----
 drivers/clk/meson/meson8b.h |   9 ++-
 3 files changed, 156 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 5588f75a8414..d2d0174a6eca 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -6,6 +6,7 @@ config COMMON_CLK_AMLOGIC
 config COMMON_CLK_MESON8B
 	bool
 	depends on COMMON_CLK_AMLOGIC
+	select RESET_CONTROLLER
 	help
 	  Support for the clock controller on AmLogic S802 (Meson8),
 	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index bb3f1de876b1..0c330d54392f 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -25,6 +25,8 @@
 #include <linux/clk-provider.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 
 #include "clkc.h"
@@ -32,6 +34,13 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
+static void __iomem *clk_base;
+
+struct meson8b_clk_reset {
+	struct reset_controller_dev reset;
+	void __iomem *base;
+};
+
 static const struct pll_rate_table sys_pll_rate_table[] = {
 	PLL_RATE(312000000, 52, 1, 2),
 	PLL_RATE(336000000, 56, 1, 2),
@@ -690,20 +699,114 @@ static struct clk_divider *const meson8b_clk_dividers[] = {
 	&meson8b_mpeg_clk_div,
 };
 
+static const struct meson8b_clk_reset_line {
+	u32 reg;
+	u8 bit_idx;
+} meson8b_clk_reset_bits[] = {
+	[CLKC_RESET_L2_CACHE_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
+	},
+	[CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
+	},
+	[CLKC_RESET_SCU_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
+	},
+	[CLKC_RESET_CPU3_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
+	},
+	[CLKC_RESET_CPU2_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
+	},
+	[CLKC_RESET_CPU1_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
+	},
+	[CLKC_RESET_CPU0_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
+	},
+	[CLKC_RESET_A5_GLOBAL_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
+	},
+	[CLKC_RESET_A5_AXI_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
+	},
+	[CLKC_RESET_A5_ABP_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
+	},
+	[CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
+	},
+	[CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
+		.reg = HHI_VID_CLK_CNTL, .bit_idx = 15
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
+	},
+};
+
+static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
+				    unsigned long id, bool assert)
+{
+	struct meson8b_clk_reset *meson8b_clk_reset =
+		container_of(rcdev, struct meson8b_clk_reset, reset);
+	unsigned long flags;
+	const struct meson8b_clk_reset_line *reset;
+	u32 val;
+
+	if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
+		return -EINVAL;
+
+	reset = &meson8b_clk_reset_bits[id];
+
+	spin_lock_irqsave(&clk_lock, flags);
+
+	val = readl(meson8b_clk_reset->base + reset->reg);
+	if (assert)
+		val |= BIT(reset->bit_idx);
+	else
+		val &= ~BIT(reset->bit_idx);
+	writel(val, meson8b_clk_reset->base + reset->reg);
+
+	spin_unlock_irqrestore(&clk_lock, flags);
+
+	return 0;
+}
+
+static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
+				     unsigned long id)
+{
+	return meson8b_clk_reset_update(rcdev, id, true);
+}
+
+static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
+				       unsigned long id)
+{
+	return meson8b_clk_reset_update(rcdev, id, false);
+}
+
+static const struct reset_control_ops meson8b_clk_reset_ops = {
+	.assert = meson8b_clk_reset_assert,
+	.deassert = meson8b_clk_reset_deassert,
+};
+
 static int meson8b_clkc_probe(struct platform_device *pdev)
 {
-	void __iomem *clk_base;
 	int ret, clkid, i;
 	struct clk_hw *parent_hw;
 	struct clk *parent_clk;
 	struct device *dev = &pdev->dev;
 
-	/*  Generic clocks and PLLs */
-	clk_base = of_iomap(dev->of_node, 1);
-	if (!clk_base) {
-		pr_err("%s: Unable to map clk base\n", __func__);
+	if (!clk_base)
 		return -ENXIO;
-	}
 
 	/* Populate base address for PLLs */
 	for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
@@ -743,7 +846,7 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 		/* FIXME convert to devm_clk_register */
 		ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
 		if (ret)
-			goto iounmap;
+			return ret;
 	}
 
 	/*
@@ -766,15 +869,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 	if (ret) {
 		pr_err("%s: failed to register clock notifier for cpu_clk\n",
 				__func__);
-		goto iounmap;
+		return ret;
 	}
 
 	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 			&meson8b_hw_onecell_data);
-
-iounmap:
-	iounmap(clk_base);
-	return ret;
 }
 
 static const struct of_device_id meson8b_clkc_match_table[] = {
@@ -793,3 +892,39 @@ static struct platform_driver meson8b_driver = {
 };
 
 builtin_platform_driver(meson8b_driver);
+
+static void __init meson8b_clkc_reset_init(struct device_node *np)
+{
+	struct meson8b_clk_reset *rstc;
+	int ret;
+
+	/* Generic clocks, PLLs and some of the reset-bits */
+	clk_base = of_iomap(np, 1);
+	if (!clk_base) {
+		pr_err("%s: Unable to map clk base\n", __func__);
+		return;
+	}
+
+	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return;
+
+	/* Reset Controller */
+	rstc->base = clk_base;
+	rstc->reset.ops = &meson8b_clk_reset_ops;
+	rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
+	rstc->reset.of_node = np;
+	ret = reset_controller_register(&rstc->reset);
+	if (ret) {
+		pr_err("%s: Failed to register clkc reset controller: %d\n",
+		       __func__, ret);
+		return;
+	}
+}
+
+CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
+		      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
+		      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
+		      meson8b_clkc_reset_init);
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index a687e02547dc..9e4c597d8a79 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -37,6 +37,9 @@
 #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
 #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
+#define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
+#define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
@@ -163,7 +166,11 @@
 
 #define CLK_NR_CLKS		96
 
-/* include the CLKIDs that have been made part of the stable DT binding */
+/*
+ * include the CLKID and RESETID that have
+ * been made part of the stable DT binding
+ */
 #include <dt-bindings/clock/meson8b-clkc.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 
 #endif /* __MESON8B_H */
-- 
2.13.3

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[PATCH v3 2/3] clk: meson: meson8b: register the built-in reset controller

[Martin Blumenstingl]

The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).

According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET

All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.

Suggested-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/meson/Kconfig   |   1 +
 drivers/clk/meson/meson8b.c | 159 ++++++++++++++++++++++++++++++++++++++++----
 drivers/clk/meson/meson8b.h |   9 ++-
 3 files changed, 156 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 5588f75a8414..d2d0174a6eca 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -6,6 +6,7 @@ config COMMON_CLK_AMLOGIC
 config COMMON_CLK_MESON8B
 	bool
 	depends on COMMON_CLK_AMLOGIC
+	select RESET_CONTROLLER
 	help
 	  Support for the clock controller on AmLogic S802 (Meson8),
 	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index bb3f1de876b1..0c330d54392f 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -25,6 +25,8 @@
 #include <linux/clk-provider.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 
 #include "clkc.h"
@@ -32,6 +34,13 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
+static void __iomem *clk_base;
+
+struct meson8b_clk_reset {
+	struct reset_controller_dev reset;
+	void __iomem *base;
+};
+
 static const struct pll_rate_table sys_pll_rate_table[] = {
 	PLL_RATE(312000000, 52, 1, 2),
 	PLL_RATE(336000000, 56, 1, 2),
@@ -690,20 +699,114 @@ static struct clk_divider *const meson8b_clk_dividers[] = {
 	&meson8b_mpeg_clk_div,
 };
 
+static const struct meson8b_clk_reset_line {
+	u32 reg;
+	u8 bit_idx;
+} meson8b_clk_reset_bits[] = {
+	[CLKC_RESET_L2_CACHE_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
+	},
+	[CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
+	},
+	[CLKC_RESET_SCU_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
+	},
+	[CLKC_RESET_CPU3_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
+	},
+	[CLKC_RESET_CPU2_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
+	},
+	[CLKC_RESET_CPU1_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
+	},
+	[CLKC_RESET_CPU0_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
+	},
+	[CLKC_RESET_A5_GLOBAL_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
+	},
+	[CLKC_RESET_A5_AXI_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
+	},
+	[CLKC_RESET_A5_ABP_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
+	},
+	[CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
+	},
+	[CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
+		.reg = HHI_VID_CLK_CNTL, .bit_idx = 15
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
+	},
+};
+
+static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
+				    unsigned long id, bool assert)
+{
+	struct meson8b_clk_reset *meson8b_clk_reset =
+		container_of(rcdev, struct meson8b_clk_reset, reset);
+	unsigned long flags;
+	const struct meson8b_clk_reset_line *reset;
+	u32 val;
+
+	if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
+		return -EINVAL;
+
+	reset = &meson8b_clk_reset_bits[id];
+
+	spin_lock_irqsave(&clk_lock, flags);
+
+	val = readl(meson8b_clk_reset->base + reset->reg);
+	if (assert)
+		val |= BIT(reset->bit_idx);
+	else
+		val &= ~BIT(reset->bit_idx);
+	writel(val, meson8b_clk_reset->base + reset->reg);
+
+	spin_unlock_irqrestore(&clk_lock, flags);
+
+	return 0;
+}
+
+static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
+				     unsigned long id)
+{
+	return meson8b_clk_reset_update(rcdev, id, true);
+}
+
+static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
+				       unsigned long id)
+{
+	return meson8b_clk_reset_update(rcdev, id, false);
+}
+
+static const struct reset_control_ops meson8b_clk_reset_ops = {
+	.assert = meson8b_clk_reset_assert,
+	.deassert = meson8b_clk_reset_deassert,
+};
+
 static int meson8b_clkc_probe(struct platform_device *pdev)
 {
-	void __iomem *clk_base;
 	int ret, clkid, i;
 	struct clk_hw *parent_hw;
 	struct clk *parent_clk;
 	struct device *dev = &pdev->dev;
 
-	/*  Generic clocks and PLLs */
-	clk_base = of_iomap(dev->of_node, 1);
-	if (!clk_base) {
-		pr_err("%s: Unable to map clk base\n", __func__);
+	if (!clk_base)
 		return -ENXIO;
-	}
 
 	/* Populate base address for PLLs */
 	for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
@@ -743,7 +846,7 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 		/* FIXME convert to devm_clk_register */
 		ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
 		if (ret)
-			goto iounmap;
+			return ret;
 	}
 
 	/*
@@ -766,15 +869,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 	if (ret) {
 		pr_err("%s: failed to register clock notifier for cpu_clk\n",
 				__func__);
-		goto iounmap;
+		return ret;
 	}
 
 	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 			&meson8b_hw_onecell_data);
-
-iounmap:
-	iounmap(clk_base);
-	return ret;
 }
 
 static const struct of_device_id meson8b_clkc_match_table[] = {
@@ -793,3 +892,39 @@ static struct platform_driver meson8b_driver = {
 };
 
 builtin_platform_driver(meson8b_driver);
+
+static void __init meson8b_clkc_reset_init(struct device_node *np)
+{
+	struct meson8b_clk_reset *rstc;
+	int ret;
+
+	/* Generic clocks, PLLs and some of the reset-bits */
+	clk_base = of_iomap(np, 1);
+	if (!clk_base) {
+		pr_err("%s: Unable to map clk base\n", __func__);
+		return;
+	}
+
+	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return;
+
+	/* Reset Controller */
+	rstc->base = clk_base;
+	rstc->reset.ops = &meson8b_clk_reset_ops;
+	rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
+	rstc->reset.of_node = np;
+	ret = reset_controller_register(&rstc->reset);
+	if (ret) {
+		pr_err("%s: Failed to register clkc reset controller: %d\n",
+		       __func__, ret);
+		return;
+	}
+}
+
+CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
+		      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
+		      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
+		      meson8b_clkc_reset_init);
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index a687e02547dc..9e4c597d8a79 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -37,6 +37,9 @@
 #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
 #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
+#define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
+#define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
@@ -163,7 +166,11 @@
 
 #define CLK_NR_CLKS		96
 
-/* include the CLKIDs that have been made part of the stable DT binding */
+/*
+ * include the CLKID and RESETID that have
+ * been made part of the stable DT binding
+ */
 #include <dt-bindings/clock/meson8b-clkc.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 
 #endif /* __MESON8B_H */
-- 
2.13.3

[PATCH v3 2/3] clk: meson: meson8b: register the built-in reset controller

[Martin Blumenstingl]

The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).

According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET

All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.

Suggested-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/meson/Kconfig   |   1 +
 drivers/clk/meson/meson8b.c | 159 ++++++++++++++++++++++++++++++++++++++++----
 drivers/clk/meson/meson8b.h |   9 ++-
 3 files changed, 156 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 5588f75a8414..d2d0174a6eca 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -6,6 +6,7 @@ config COMMON_CLK_AMLOGIC
 config COMMON_CLK_MESON8B
 	bool
 	depends on COMMON_CLK_AMLOGIC
+	select RESET_CONTROLLER
 	help
 	  Support for the clock controller on AmLogic S802 (Meson8),
 	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index bb3f1de876b1..0c330d54392f 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -25,6 +25,8 @@
 #include <linux/clk-provider.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 
 #include "clkc.h"
@@ -32,6 +34,13 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
+static void __iomem *clk_base;
+
+struct meson8b_clk_reset {
+	struct reset_controller_dev reset;
+	void __iomem *base;
+};
+
 static const struct pll_rate_table sys_pll_rate_table[] = {
 	PLL_RATE(312000000, 52, 1, 2),
 	PLL_RATE(336000000, 56, 1, 2),
@@ -690,20 +699,114 @@ static struct clk_divider *const meson8b_clk_dividers[] = {
 	&meson8b_mpeg_clk_div,
 };
 
+static const struct meson8b_clk_reset_line {
+	u32 reg;
+	u8 bit_idx;
+} meson8b_clk_reset_bits[] = {
+	[CLKC_RESET_L2_CACHE_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
+	},
+	[CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
+	},
+	[CLKC_RESET_SCU_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
+	},
+	[CLKC_RESET_CPU3_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
+	},
+	[CLKC_RESET_CPU2_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
+	},
+	[CLKC_RESET_CPU1_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
+	},
+	[CLKC_RESET_CPU0_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
+	},
+	[CLKC_RESET_A5_GLOBAL_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
+	},
+	[CLKC_RESET_A5_AXI_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
+	},
+	[CLKC_RESET_A5_ABP_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
+	},
+	[CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
+		.reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
+	},
+	[CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
+		.reg = HHI_VID_CLK_CNTL, .bit_idx = 15
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
+	},
+	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
+		.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
+	},
+};
+
+static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
+				    unsigned long id, bool assert)
+{
+	struct meson8b_clk_reset *meson8b_clk_reset =
+		container_of(rcdev, struct meson8b_clk_reset, reset);
+	unsigned long flags;
+	const struct meson8b_clk_reset_line *reset;
+	u32 val;
+
+	if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
+		return -EINVAL;
+
+	reset = &meson8b_clk_reset_bits[id];
+
+	spin_lock_irqsave(&clk_lock, flags);
+
+	val = readl(meson8b_clk_reset->base + reset->reg);
+	if (assert)
+		val |= BIT(reset->bit_idx);
+	else
+		val &= ~BIT(reset->bit_idx);
+	writel(val, meson8b_clk_reset->base + reset->reg);
+
+	spin_unlock_irqrestore(&clk_lock, flags);
+
+	return 0;
+}
+
+static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
+				     unsigned long id)
+{
+	return meson8b_clk_reset_update(rcdev, id, true);
+}
+
+static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
+				       unsigned long id)
+{
+	return meson8b_clk_reset_update(rcdev, id, false);
+}
+
+static const struct reset_control_ops meson8b_clk_reset_ops = {
+	.assert = meson8b_clk_reset_assert,
+	.deassert = meson8b_clk_reset_deassert,
+};
+
 static int meson8b_clkc_probe(struct platform_device *pdev)
 {
-	void __iomem *clk_base;
 	int ret, clkid, i;
 	struct clk_hw *parent_hw;
 	struct clk *parent_clk;
 	struct device *dev = &pdev->dev;
 
-	/*  Generic clocks and PLLs */
-	clk_base = of_iomap(dev->of_node, 1);
-	if (!clk_base) {
-		pr_err("%s: Unable to map clk base\n", __func__);
+	if (!clk_base)
 		return -ENXIO;
-	}
 
 	/* Populate base address for PLLs */
 	for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
@@ -743,7 +846,7 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 		/* FIXME convert to devm_clk_register */
 		ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
 		if (ret)
-			goto iounmap;
+			return ret;
 	}
 
 	/*
@@ -766,15 +869,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 	if (ret) {
 		pr_err("%s: failed to register clock notifier for cpu_clk\n",
 				__func__);
-		goto iounmap;
+		return ret;
 	}
 
 	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 			&meson8b_hw_onecell_data);
-
-iounmap:
-	iounmap(clk_base);
-	return ret;
 }
 
 static const struct of_device_id meson8b_clkc_match_table[] = {
@@ -793,3 +892,39 @@ static struct platform_driver meson8b_driver = {
 };
 
 builtin_platform_driver(meson8b_driver);
+
+static void __init meson8b_clkc_reset_init(struct device_node *np)
+{
+	struct meson8b_clk_reset *rstc;
+	int ret;
+
+	/* Generic clocks, PLLs and some of the reset-bits */
+	clk_base = of_iomap(np, 1);
+	if (!clk_base) {
+		pr_err("%s: Unable to map clk base\n", __func__);
+		return;
+	}
+
+	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return;
+
+	/* Reset Controller */
+	rstc->base = clk_base;
+	rstc->reset.ops = &meson8b_clk_reset_ops;
+	rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
+	rstc->reset.of_node = np;
+	ret = reset_controller_register(&rstc->reset);
+	if (ret) {
+		pr_err("%s: Failed to register clkc reset controller: %d\n",
+		       __func__, ret);
+		return;
+	}
+}
+
+CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
+		      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
+		      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
+		      meson8b_clkc_reset_init);
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index a687e02547dc..9e4c597d8a79 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -37,6 +37,9 @@
 #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
 #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
+#define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
+#define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
@@ -163,7 +166,11 @@
 
 #define CLK_NR_CLKS		96
 
-/* include the CLKIDs that have been made part of the stable DT binding */
+/*
+ * include the CLKID and RESETID that have
+ * been made part of the stable DT binding
+ */
 #include <dt-bindings/clock/meson8b-clkc.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 
 #endif /* __MESON8B_H */
-- 
2.13.3

[PATCH v3 3/3] ARM: dts: meson: mark the clock controller also as reset controller

[Martin Blumenstingl]

The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi  | 1 +
 arch/arm/boot/dts/meson8b.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6fe6a159e960..b98d44fde6b6 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -168,6 +168,7 @@
 &cbus {
 	clkc: clock-controller@4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8fce13844b0c..bc278da7df0d 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -119,6 +119,7 @@
 &cbus {
 	clkc: clock-controller@4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};
-- 
2.13.3

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[PATCH v3 3/3] ARM: dts: meson: mark the clock controller also as reset controller

[Martin Blumenstingl]

The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson8.dtsi  | 1 +
 arch/arm/boot/dts/meson8b.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6fe6a159e960..b98d44fde6b6 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -168,6 +168,7 @@
 &cbus {
 	clkc: clock-controller@4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8fce13844b0c..bc278da7df0d 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -119,6 +119,7 @@
 &cbus {
 	clkc: clock-controller@4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};
-- 
2.13.3

[PATCH v3 3/3] ARM: dts: meson: mark the clock controller also as reset controller

[Martin Blumenstingl]

The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson8.dtsi  | 1 +
 arch/arm/boot/dts/meson8b.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6fe6a159e960..b98d44fde6b6 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -168,6 +168,7 @@
 &cbus {
 	clkc: clock-controller at 4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8fce13844b0c..bc278da7df0d 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -119,6 +119,7 @@
 &cbus {
 	clkc: clock-controller at 4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};
-- 
2.13.3

Re: [PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Jerome Brunet]

On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
> This registers the known (soft) reset lines provided by the clock
> controller's registers.
> 
> This is the first preparation step for SMP and CPU hotplug support on
> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
> requires asserting and de-asserting a reset line (one for each CPU
> core). These reset lines are provided by the clock controller.
> 
> The reset controller part of the meson8b clock controller has to be
> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
> the secondary cores are started *very* early in the boot process (and
> meson8b_clkc_probe is invoked long after we need the reset controller
> to be available for booting the secondary CPU cores).
> 
> The user of the reset-controller (= the patches which enable SMP and
> CPU hotplug support) will follow in the next days. I decided to split
> this because the SMP series will probably consist of 6 patches alone
> (and may need to go through two separate trees).
> 
> Changes since v2 at [3]:
> - move the reset line preprocessor defines into a separate file
>   (affects patch #1 as this header file is part of the dt-binding)
> - rename the reset line preprocessor macros from RESETID_ to
>   CLKC_RESET_ to clearly indicate that these are provided by the
>   clock controller (unlike the preprocessor macros for the reset
>   lines in the standlone reset controller, which start with RESET_)
> - updated patch #2 due to the changes mentioned above
> - added Neil's Reviewed-by to all patches
> 
> Changes since v1 at [0]:
> - updated cover letter description as we are now registering more than
>   four reset lines
> - split patch #1 into a dt-binding and clk driver patch
> - slightly reworded the dt-binding documentation so it's now clear that
>   the reset identifiers are preprocessor macros in
>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>   macros at all)
> - patch #2 (previously part of patch #1) now registers all known reset
>   lines (see [1] and [2] for the results of my detective work)
> - patch #3 is untouched
> 
> 
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
> 
> 
> Martin Blumenstingl (3):
>   dt-bindings: clock: meson8b: describe the embedded reset controller
>   clk: meson: meson8b: register the built-in reset controller
>   ARM: dts: meson: mark the clock controller also as reset controller
> 
>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>  drivers/clk/meson/Kconfig                          |   1 +
>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
> -
>  drivers/clk/meson/meson8b.h                        |   9 +-
>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>  7 files changed, 193 insertions(+), 14 deletions(-)
>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
> 

Series looks good to me overall.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

Just one thing, which is not an issue really, I wonder if the dt-bindings
documentation and the bindings them-self should be in separate patches ? 

[PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Jerome Brunet]

On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
> This registers the known (soft) reset lines provided by the clock
> controller's registers.
> 
> This is the first preparation step for SMP and CPU hotplug support on
> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
> requires asserting and de-asserting a reset line (one for each CPU
> core). These reset lines are provided by the clock controller.
> 
> The reset controller part of the meson8b clock controller has to be
> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
> the secondary cores are started *very* early in the boot process (and
> meson8b_clkc_probe is invoked long after we need the reset controller
> to be available for booting the secondary CPU cores).
> 
> The user of the reset-controller (= the patches which enable SMP and
> CPU hotplug support) will follow in the next days. I decided to split
> this because the SMP series will probably consist of 6 patches alone
> (and may need to go through two separate trees).
> 
> Changes since v2 at [3]:
> - move the reset line preprocessor defines into a separate file
> ? (affects patch #1 as this header file is part of the dt-binding)
> - rename the reset line preprocessor macros from RESETID_ to
> ? CLKC_RESET_ to clearly indicate that these are provided by the
> ? clock controller (unlike the preprocessor macros for the reset
> ? lines in the standlone reset controller, which start with RESET_)
> - updated patch #2 due to the changes mentioned above
> - added Neil's Reviewed-by to all patches
> 
> Changes since v1 at [0]:
> - updated cover letter description as we are now registering more than
> ? four reset lines
> - split patch #1 into a dt-binding and clk driver patch
> - slightly reworded the dt-binding documentation so it's now clear that
> ? the reset identifiers are preprocessor macros in
> ? dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
> ? macros at all)
> - patch #2 (previously part of patch #1) now registers all known reset
> ? lines (see [1] and [2] for the results of my detective work)
> - patch #3 is untouched
> 
> 
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
> 
> 
> Martin Blumenstingl (3):
> ? dt-bindings: clock: meson8b: describe the embedded reset controller
> ? clk: meson: meson8b: register the built-in reset controller
> ? ARM: dts: meson: mark the clock controller also as reset controller
> 
> ?.../bindings/clock/amlogic,meson8b-clkc.txt????????|???9 +-
> ?arch/arm/boot/dts/meson8.dtsi??????????????????????|???1 +
> ?arch/arm/boot/dts/meson8b.dtsi?????????????????????|???1 +
> ?drivers/clk/meson/Kconfig??????????????????????????|???1 +
> ?drivers/clk/meson/meson8b.c????????????????????????| 159 +++++++++++++++++++-
> -
> ?drivers/clk/meson/meson8b.h????????????????????????|???9 +-
> ?.../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |??27 ++++
> ?7 files changed, 193 insertions(+), 14 deletions(-)
> ?create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
> 

Series looks good to me overall.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

Just one thing, which is not an issue really, I wonder if the dt-bindings
documentation and the bindings them-self should be in separate patches ? 

Re: [PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Neil Armstrong]

On 07/31/2017 10:27 AM, Jerome Brunet wrote:
> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>> This registers the known (soft) reset lines provided by the clock
>> controller's registers.
>>
>> This is the first preparation step for SMP and CPU hotplug support on
>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>> requires asserting and de-asserting a reset line (one for each CPU
>> core). These reset lines are provided by the clock controller.
>>
>> The reset controller part of the meson8b clock controller has to be
>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>> the secondary cores are started *very* early in the boot process (and
>> meson8b_clkc_probe is invoked long after we need the reset controller
>> to be available for booting the secondary CPU cores).
>>
>> The user of the reset-controller (= the patches which enable SMP and
>> CPU hotplug support) will follow in the next days. I decided to split
>> this because the SMP series will probably consist of 6 patches alone
>> (and may need to go through two separate trees).
>>
>> Changes since v2 at [3]:
>> - move the reset line preprocessor defines into a separate file
>>   (affects patch #1 as this header file is part of the dt-binding)
>> - rename the reset line preprocessor macros from RESETID_ to
>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>   clock controller (unlike the preprocessor macros for the reset
>>   lines in the standlone reset controller, which start with RESET_)
>> - updated patch #2 due to the changes mentioned above
>> - added Neil's Reviewed-by to all patches
>>
>> Changes since v1 at [0]:
>> - updated cover letter description as we are now registering more than
>>   four reset lines
>> - split patch #1 into a dt-binding and clk driver patch
>> - slightly reworded the dt-binding documentation so it's now clear that
>>   the reset identifiers are preprocessor macros in
>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>   macros at all)
>> - patch #2 (previously part of patch #1) now registers all known reset
>>   lines (see [1] and [2] for the results of my detective work)
>> - patch #3 is untouched
>>
>>
>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>
>>
>> Martin Blumenstingl (3):
>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>   clk: meson: meson8b: register the built-in reset controller
>>   ARM: dts: meson: mark the clock controller also as reset controller
>>
>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>  drivers/clk/meson/Kconfig                          |   1 +
>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>> -
>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>
> 
> Series looks good to me overall.
> 
> Acked-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> 
> Just one thing, which is not an issue really, I wonder if the dt-bindings
> documentation and the bindings them-self should be in separate patches ? 
> 

Hi Martin,

Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.

Kevin, patch 3 is all yours !

Thanks,
Neil
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Re: [PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Neil Armstrong]

On 07/31/2017 10:27 AM, Jerome Brunet wrote:
> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>> This registers the known (soft) reset lines provided by the clock
>> controller's registers.
>>
>> This is the first preparation step for SMP and CPU hotplug support on
>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>> requires asserting and de-asserting a reset line (one for each CPU
>> core). These reset lines are provided by the clock controller.
>>
>> The reset controller part of the meson8b clock controller has to be
>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>> the secondary cores are started *very* early in the boot process (and
>> meson8b_clkc_probe is invoked long after we need the reset controller
>> to be available for booting the secondary CPU cores).
>>
>> The user of the reset-controller (= the patches which enable SMP and
>> CPU hotplug support) will follow in the next days. I decided to split
>> this because the SMP series will probably consist of 6 patches alone
>> (and may need to go through two separate trees).
>>
>> Changes since v2 at [3]:
>> - move the reset line preprocessor defines into a separate file
>>   (affects patch #1 as this header file is part of the dt-binding)
>> - rename the reset line preprocessor macros from RESETID_ to
>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>   clock controller (unlike the preprocessor macros for the reset
>>   lines in the standlone reset controller, which start with RESET_)
>> - updated patch #2 due to the changes mentioned above
>> - added Neil's Reviewed-by to all patches
>>
>> Changes since v1 at [0]:
>> - updated cover letter description as we are now registering more than
>>   four reset lines
>> - split patch #1 into a dt-binding and clk driver patch
>> - slightly reworded the dt-binding documentation so it's now clear that
>>   the reset identifiers are preprocessor macros in
>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>   macros at all)
>> - patch #2 (previously part of patch #1) now registers all known reset
>>   lines (see [1] and [2] for the results of my detective work)
>> - patch #3 is untouched
>>
>>
>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>
>>
>> Martin Blumenstingl (3):
>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>   clk: meson: meson8b: register the built-in reset controller
>>   ARM: dts: meson: mark the clock controller also as reset controller
>>
>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>  drivers/clk/meson/Kconfig                          |   1 +
>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>> -
>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>
> 
> Series looks good to me overall.
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 
> Just one thing, which is not an issue really, I wonder if the dt-bindings
> documentation and the bindings them-self should be in separate patches ? 
> 

Hi Martin,

Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.

Kevin, patch 3 is all yours !

Thanks,
Neil

[PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Neil Armstrong]

On 07/31/2017 10:27 AM, Jerome Brunet wrote:
> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>> This registers the known (soft) reset lines provided by the clock
>> controller's registers.
>>
>> This is the first preparation step for SMP and CPU hotplug support on
>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>> requires asserting and de-asserting a reset line (one for each CPU
>> core). These reset lines are provided by the clock controller.
>>
>> The reset controller part of the meson8b clock controller has to be
>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>> the secondary cores are started *very* early in the boot process (and
>> meson8b_clkc_probe is invoked long after we need the reset controller
>> to be available for booting the secondary CPU cores).
>>
>> The user of the reset-controller (= the patches which enable SMP and
>> CPU hotplug support) will follow in the next days. I decided to split
>> this because the SMP series will probably consist of 6 patches alone
>> (and may need to go through two separate trees).
>>
>> Changes since v2 at [3]:
>> - move the reset line preprocessor defines into a separate file
>>   (affects patch #1 as this header file is part of the dt-binding)
>> - rename the reset line preprocessor macros from RESETID_ to
>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>   clock controller (unlike the preprocessor macros for the reset
>>   lines in the standlone reset controller, which start with RESET_)
>> - updated patch #2 due to the changes mentioned above
>> - added Neil's Reviewed-by to all patches
>>
>> Changes since v1 at [0]:
>> - updated cover letter description as we are now registering more than
>>   four reset lines
>> - split patch #1 into a dt-binding and clk driver patch
>> - slightly reworded the dt-binding documentation so it's now clear that
>>   the reset identifiers are preprocessor macros in
>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>   macros at all)
>> - patch #2 (previously part of patch #1) now registers all known reset
>>   lines (see [1] and [2] for the results of my detective work)
>> - patch #3 is untouched
>>
>>
>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>
>>
>> Martin Blumenstingl (3):
>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>   clk: meson: meson8b: register the built-in reset controller
>>   ARM: dts: meson: mark the clock controller also as reset controller
>>
>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>  drivers/clk/meson/Kconfig                          |   1 +
>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>> -
>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>
> 
> Series looks good to me overall.
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 
> Just one thing, which is not an issue really, I wonder if the dt-bindings
> documentation and the bindings them-self should be in separate patches ? 
> 

Hi Martin,

Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.

Kevin, patch 3 is all yours !

Thanks,
Neil

Re: [PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Martin Blumenstingl]

Hi Neil,

On Mon, Jul 31, 2017 at 1:59 PM, Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
> On 07/31/2017 10:27 AM, Jerome Brunet wrote:
>> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>>> This registers the known (soft) reset lines provided by the clock
>>> controller's registers.
>>>
>>> This is the first preparation step for SMP and CPU hotplug support on
>>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>>> requires asserting and de-asserting a reset line (one for each CPU
>>> core). These reset lines are provided by the clock controller.
>>>
>>> The reset controller part of the meson8b clock controller has to be
>>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>>> the secondary cores are started *very* early in the boot process (and
>>> meson8b_clkc_probe is invoked long after we need the reset controller
>>> to be available for booting the secondary CPU cores).
>>>
>>> The user of the reset-controller (= the patches which enable SMP and
>>> CPU hotplug support) will follow in the next days. I decided to split
>>> this because the SMP series will probably consist of 6 patches alone
>>> (and may need to go through two separate trees).
>>>
>>> Changes since v2 at [3]:
>>> - move the reset line preprocessor defines into a separate file
>>>   (affects patch #1 as this header file is part of the dt-binding)
>>> - rename the reset line preprocessor macros from RESETID_ to
>>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>>   clock controller (unlike the preprocessor macros for the reset
>>>   lines in the standlone reset controller, which start with RESET_)
>>> - updated patch #2 due to the changes mentioned above
>>> - added Neil's Reviewed-by to all patches
>>>
>>> Changes since v1 at [0]:
>>> - updated cover letter description as we are now registering more than
>>>   four reset lines
>>> - split patch #1 into a dt-binding and clk driver patch
>>> - slightly reworded the dt-binding documentation so it's now clear that
>>>   the reset identifiers are preprocessor macros in
>>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>>   macros at all)
>>> - patch #2 (previously part of patch #1) now registers all known reset
>>>   lines (see [1] and [2] for the results of my detective work)
>>> - patch #3 is untouched
>>>
>>>
>>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>>
>>>
>>> Martin Blumenstingl (3):
>>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>>   clk: meson: meson8b: register the built-in reset controller
>>>   ARM: dts: meson: mark the clock controller also as reset controller
>>>
>>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>>  drivers/clk/meson/Kconfig                          |   1 +
>>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>>> -
>>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>>
>>
>> Series looks good to me overall.
>>
>> Acked-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>>
>> Just one thing, which is not an issue really, I wonder if the dt-bindings
>> documentation and the bindings them-self should be in separate patches ?
>>
>
> Hi Martin,
>
> Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.
thank you!
I'm also fine with either way - I chose to include it in the
dt-bindings patch due to two reasons:
- my SMP series depends on this header file
- we typically send header updates with a dt-bindings patch (see your
AO CEC clock for example)
with these I thought it makes sense to combine the documentation and
the header in the dt-bindings patch - if it's an issue I can simply
change it

may be the DT-maintainers can comment on this?

anyway, thanks for taking care!

> Kevin, patch 3 is all yours !
>
> Thanks,
> Neil


Martin
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Re: [PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Martin Blumenstingl]

Hi Neil,

On Mon, Jul 31, 2017 at 1:59 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
> On 07/31/2017 10:27 AM, Jerome Brunet wrote:
>> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>>> This registers the known (soft) reset lines provided by the clock
>>> controller's registers.
>>>
>>> This is the first preparation step for SMP and CPU hotplug support on
>>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>>> requires asserting and de-asserting a reset line (one for each CPU
>>> core). These reset lines are provided by the clock controller.
>>>
>>> The reset controller part of the meson8b clock controller has to be
>>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>>> the secondary cores are started *very* early in the boot process (and
>>> meson8b_clkc_probe is invoked long after we need the reset controller
>>> to be available for booting the secondary CPU cores).
>>>
>>> The user of the reset-controller (= the patches which enable SMP and
>>> CPU hotplug support) will follow in the next days. I decided to split
>>> this because the SMP series will probably consist of 6 patches alone
>>> (and may need to go through two separate trees).
>>>
>>> Changes since v2 at [3]:
>>> - move the reset line preprocessor defines into a separate file
>>>   (affects patch #1 as this header file is part of the dt-binding)
>>> - rename the reset line preprocessor macros from RESETID_ to
>>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>>   clock controller (unlike the preprocessor macros for the reset
>>>   lines in the standlone reset controller, which start with RESET_)
>>> - updated patch #2 due to the changes mentioned above
>>> - added Neil's Reviewed-by to all patches
>>>
>>> Changes since v1 at [0]:
>>> - updated cover letter description as we are now registering more than
>>>   four reset lines
>>> - split patch #1 into a dt-binding and clk driver patch
>>> - slightly reworded the dt-binding documentation so it's now clear that
>>>   the reset identifiers are preprocessor macros in
>>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>>   macros at all)
>>> - patch #2 (previously part of patch #1) now registers all known reset
>>>   lines (see [1] and [2] for the results of my detective work)
>>> - patch #3 is untouched
>>>
>>>
>>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>>
>>>
>>> Martin Blumenstingl (3):
>>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>>   clk: meson: meson8b: register the built-in reset controller
>>>   ARM: dts: meson: mark the clock controller also as reset controller
>>>
>>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>>  drivers/clk/meson/Kconfig                          |   1 +
>>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>>> -
>>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>>
>>
>> Series looks good to me overall.
>>
>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>>
>> Just one thing, which is not an issue really, I wonder if the dt-bindings
>> documentation and the bindings them-self should be in separate patches ?
>>
>
> Hi Martin,
>
> Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.
thank you!
I'm also fine with either way - I chose to include it in the
dt-bindings patch due to two reasons:
- my SMP series depends on this header file
- we typically send header updates with a dt-bindings patch (see your
AO CEC clock for example)
with these I thought it makes sense to combine the documentation and
the header in the dt-bindings patch - if it's an issue I can simply
change it

may be the DT-maintainers can comment on this?

anyway, thanks for taking care!

> Kevin, patch 3 is all yours !
>
> Thanks,
> Neil


Martin

[PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Martin Blumenstingl]

Hi Neil,

On Mon, Jul 31, 2017 at 1:59 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
> On 07/31/2017 10:27 AM, Jerome Brunet wrote:
>> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>>> This registers the known (soft) reset lines provided by the clock
>>> controller's registers.
>>>
>>> This is the first preparation step for SMP and CPU hotplug support on
>>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>>> requires asserting and de-asserting a reset line (one for each CPU
>>> core). These reset lines are provided by the clock controller.
>>>
>>> The reset controller part of the meson8b clock controller has to be
>>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>>> the secondary cores are started *very* early in the boot process (and
>>> meson8b_clkc_probe is invoked long after we need the reset controller
>>> to be available for booting the secondary CPU cores).
>>>
>>> The user of the reset-controller (= the patches which enable SMP and
>>> CPU hotplug support) will follow in the next days. I decided to split
>>> this because the SMP series will probably consist of 6 patches alone
>>> (and may need to go through two separate trees).
>>>
>>> Changes since v2 at [3]:
>>> - move the reset line preprocessor defines into a separate file
>>>   (affects patch #1 as this header file is part of the dt-binding)
>>> - rename the reset line preprocessor macros from RESETID_ to
>>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>>   clock controller (unlike the preprocessor macros for the reset
>>>   lines in the standlone reset controller, which start with RESET_)
>>> - updated patch #2 due to the changes mentioned above
>>> - added Neil's Reviewed-by to all patches
>>>
>>> Changes since v1 at [0]:
>>> - updated cover letter description as we are now registering more than
>>>   four reset lines
>>> - split patch #1 into a dt-binding and clk driver patch
>>> - slightly reworded the dt-binding documentation so it's now clear that
>>>   the reset identifiers are preprocessor macros in
>>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>>   macros at all)
>>> - patch #2 (previously part of patch #1) now registers all known reset
>>>   lines (see [1] and [2] for the results of my detective work)
>>> - patch #3 is untouched
>>>
>>>
>>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>>
>>>
>>> Martin Blumenstingl (3):
>>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>>   clk: meson: meson8b: register the built-in reset controller
>>>   ARM: dts: meson: mark the clock controller also as reset controller
>>>
>>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>>  drivers/clk/meson/Kconfig                          |   1 +
>>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>>> -
>>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>>
>>
>> Series looks good to me overall.
>>
>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>>
>> Just one thing, which is not an issue really, I wonder if the dt-bindings
>> documentation and the bindings them-self should be in separate patches ?
>>
>
> Hi Martin,
>
> Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.
thank you!
I'm also fine with either way - I chose to include it in the
dt-bindings patch due to two reasons:
- my SMP series depends on this header file
- we typically send header updates with a dt-bindings patch (see your
AO CEC clock for example)
with these I thought it makes sense to combine the documentation and
the header in the dt-bindings patch - if it's an issue I can simply
change it

may be the DT-maintainers can comment on this?

anyway, thanks for taking care!

> Kevin, patch 3 is all yours !
>
> Thanks,
> Neil


Martin

Re: [PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> Hi Neil,
>
> On Mon, Jul 31, 2017 at 1:59 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
>> On 07/31/2017 10:27 AM, Jerome Brunet wrote:
>>> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>>>> This registers the known (soft) reset lines provided by the clock
>>>> controller's registers.
>>>>
>>>> This is the first preparation step for SMP and CPU hotplug support on
>>>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>>>> requires asserting and de-asserting a reset line (one for each CPU
>>>> core). These reset lines are provided by the clock controller.
>>>>
>>>> The reset controller part of the meson8b clock controller has to be
>>>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>>>> the secondary cores are started *very* early in the boot process (and
>>>> meson8b_clkc_probe is invoked long after we need the reset controller
>>>> to be available for booting the secondary CPU cores).
>>>>
>>>> The user of the reset-controller (= the patches which enable SMP and
>>>> CPU hotplug support) will follow in the next days. I decided to split
>>>> this because the SMP series will probably consist of 6 patches alone
>>>> (and may need to go through two separate trees).
>>>>
>>>> Changes since v2 at [3]:
>>>> - move the reset line preprocessor defines into a separate file
>>>>   (affects patch #1 as this header file is part of the dt-binding)
>>>> - rename the reset line preprocessor macros from RESETID_ to
>>>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>>>   clock controller (unlike the preprocessor macros for the reset
>>>>   lines in the standlone reset controller, which start with RESET_)
>>>> - updated patch #2 due to the changes mentioned above
>>>> - added Neil's Reviewed-by to all patches
>>>>
>>>> Changes since v1 at [0]:
>>>> - updated cover letter description as we are now registering more than
>>>>   four reset lines
>>>> - split patch #1 into a dt-binding and clk driver patch
>>>> - slightly reworded the dt-binding documentation so it's now clear that
>>>>   the reset identifiers are preprocessor macros in
>>>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>>>   macros at all)
>>>> - patch #2 (previously part of patch #1) now registers all known reset
>>>>   lines (see [1] and [2] for the results of my detective work)
>>>> - patch #3 is untouched
>>>>
>>>>
>>>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>>>
>>>>
>>>> Martin Blumenstingl (3):
>>>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>>>   clk: meson: meson8b: register the built-in reset controller
>>>>   ARM: dts: meson: mark the clock controller also as reset controller
>>>>
>>>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>>>  drivers/clk/meson/Kconfig                          |   1 +
>>>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>>>> -
>>>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>>>
>>>
>>> Series looks good to me overall.
>>>
>>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>>>
>>> Just one thing, which is not an issue really, I wonder if the dt-bindings
>>> documentation and the bindings them-self should be in separate patches ?
>>>
>>
>> Hi Martin,
>>
>> Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.
> thank you!
> I'm also fine with either way - I chose to include it in the
> dt-bindings patch due to two reasons:
> - my SMP series depends on this header file
> - we typically send header updates with a dt-bindings patch (see your
> AO CEC clock for example)
> with these I thought it makes sense to combine the documentation and
> the header in the dt-bindings patch - if it's an issue I can simply
> change it
>
> may be the DT-maintainers can comment on this?

If it was a new binding, or significant change, it would be better to
send bindings as a separate patch, but in this case, it should be fine.

>> Kevin, patch 3 is all yours !

Applied to v4.14/dt,

Thanks,

Kevin

Re: [PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> Hi Neil,
>
> On Mon, Jul 31, 2017 at 1:59 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
>> On 07/31/2017 10:27 AM, Jerome Brunet wrote:
>>> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>>>> This registers the known (soft) reset lines provided by the clock
>>>> controller's registers.
>>>>
>>>> This is the first preparation step for SMP and CPU hotplug support on
>>>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>>>> requires asserting and de-asserting a reset line (one for each CPU
>>>> core). These reset lines are provided by the clock controller.
>>>>
>>>> The reset controller part of the meson8b clock controller has to be
>>>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>>>> the secondary cores are started *very* early in the boot process (and
>>>> meson8b_clkc_probe is invoked long after we need the reset controller
>>>> to be available for booting the secondary CPU cores).
>>>>
>>>> The user of the reset-controller (= the patches which enable SMP and
>>>> CPU hotplug support) will follow in the next days. I decided to split
>>>> this because the SMP series will probably consist of 6 patches alone
>>>> (and may need to go through two separate trees).
>>>>
>>>> Changes since v2 at [3]:
>>>> - move the reset line preprocessor defines into a separate file
>>>>   (affects patch #1 as this header file is part of the dt-binding)
>>>> - rename the reset line preprocessor macros from RESETID_ to
>>>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>>>   clock controller (unlike the preprocessor macros for the reset
>>>>   lines in the standlone reset controller, which start with RESET_)
>>>> - updated patch #2 due to the changes mentioned above
>>>> - added Neil's Reviewed-by to all patches
>>>>
>>>> Changes since v1 at [0]:
>>>> - updated cover letter description as we are now registering more than
>>>>   four reset lines
>>>> - split patch #1 into a dt-binding and clk driver patch
>>>> - slightly reworded the dt-binding documentation so it's now clear that
>>>>   the reset identifiers are preprocessor macros in
>>>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>>>   macros at all)
>>>> - patch #2 (previously part of patch #1) now registers all known reset
>>>>   lines (see [1] and [2] for the results of my detective work)
>>>> - patch #3 is untouched
>>>>
>>>>
>>>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>>>
>>>>
>>>> Martin Blumenstingl (3):
>>>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>>>   clk: meson: meson8b: register the built-in reset controller
>>>>   ARM: dts: meson: mark the clock controller also as reset controller
>>>>
>>>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>>>  drivers/clk/meson/Kconfig                          |   1 +
>>>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>>>> -
>>>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>>>
>>>
>>> Series looks good to me overall.
>>>
>>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>>>
>>> Just one thing, which is not an issue really, I wonder if the dt-bindings
>>> documentation and the bindings them-self should be in separate patches ?
>>>
>>
>> Hi Martin,
>>
>> Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.
> thank you!
> I'm also fine with either way - I chose to include it in the
> dt-bindings patch due to two reasons:
> - my SMP series depends on this header file
> - we typically send header updates with a dt-bindings patch (see your
> AO CEC clock for example)
> with these I thought it makes sense to combine the documentation and
> the header in the dt-bindings patch - if it's an issue I can simply
> change it
>
> may be the DT-maintainers can comment on this?

If it was a new binding, or significant change, it would be better to
send bindings as a separate patch, but in this case, it should be fine.

>> Kevin, patch 3 is all yours !

Applied to v4.14/dt,

Thanks,

Kevin

[PATCH v3 0/3] add the reset controller to the Meson8b clkc

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> Hi Neil,
>
> On Mon, Jul 31, 2017 at 1:59 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
>> On 07/31/2017 10:27 AM, Jerome Brunet wrote:
>>> On Fri, 2017-07-28 at 23:13 +0200, Martin Blumenstingl wrote:
>>>> This registers the known (soft) reset lines provided by the clock
>>>> controller's registers.
>>>>
>>>> This is the first preparation step for SMP and CPU hotplug support on
>>>> Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs
>>>> requires asserting and de-asserting a reset line (one for each CPU
>>>> core). These reset lines are provided by the clock controller.
>>>>
>>>> The reset controller part of the meson8b clock controller has to be
>>>> registered early (which I did through CLK_OF_DECLARE_DRIVER), because
>>>> the secondary cores are started *very* early in the boot process (and
>>>> meson8b_clkc_probe is invoked long after we need the reset controller
>>>> to be available for booting the secondary CPU cores).
>>>>
>>>> The user of the reset-controller (= the patches which enable SMP and
>>>> CPU hotplug support) will follow in the next days. I decided to split
>>>> this because the SMP series will probably consist of 6 patches alone
>>>> (and may need to go through two separate trees).
>>>>
>>>> Changes since v2 at [3]:
>>>> - move the reset line preprocessor defines into a separate file
>>>>   (affects patch #1 as this header file is part of the dt-binding)
>>>> - rename the reset line preprocessor macros from RESETID_ to
>>>>   CLKC_RESET_ to clearly indicate that these are provided by the
>>>>   clock controller (unlike the preprocessor macros for the reset
>>>>   lines in the standlone reset controller, which start with RESET_)
>>>> - updated patch #2 due to the changes mentioned above
>>>> - added Neil's Reviewed-by to all patches
>>>>
>>>> Changes since v1 at [0]:
>>>> - updated cover letter description as we are now registering more than
>>>>   four reset lines
>>>> - split patch #1 into a dt-binding and clk driver patch
>>>> - slightly reworded the dt-binding documentation so it's now clear that
>>>>   the reset identifiers are preprocessor macros in
>>>>   dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these
>>>>   macros at all)
>>>> - patch #2 (previously part of patch #1) now registers all known reset
>>>>   lines (see [1] and [2] for the results of my detective work)
>>>> - patch #3 is untouched
>>>>
>>>>
>>>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
>>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
>>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
>>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
>>>>
>>>>
>>>> Martin Blumenstingl (3):
>>>>   dt-bindings: clock: meson8b: describe the embedded reset controller
>>>>   clk: meson: meson8b: register the built-in reset controller
>>>>   ARM: dts: meson: mark the clock controller also as reset controller
>>>>
>>>>  .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
>>>>  arch/arm/boot/dts/meson8.dtsi                      |   1 +
>>>>  arch/arm/boot/dts/meson8b.dtsi                     |   1 +
>>>>  drivers/clk/meson/Kconfig                          |   1 +
>>>>  drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
>>>> -
>>>>  drivers/clk/meson/meson8b.h                        |   9 +-
>>>>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
>>>>  7 files changed, 193 insertions(+), 14 deletions(-)
>>>>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
>>>>
>>>
>>> Series looks good to me overall.
>>>
>>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>>>
>>> Just one thing, which is not an issue really, I wonder if the dt-bindings
>>> documentation and the bindings them-self should be in separate patches ?
>>>
>>
>> Hi Martin,
>>
>> Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.
> thank you!
> I'm also fine with either way - I chose to include it in the
> dt-bindings patch due to two reasons:
> - my SMP series depends on this header file
> - we typically send header updates with a dt-bindings patch (see your
> AO CEC clock for example)
> with these I thought it makes sense to combine the documentation and
> the header in the dt-bindings patch - if it's an issue I can simply
> change it
>
> may be the DT-maintainers can comment on this?

If it was a new binding, or significant change, it would be better to
send bindings as a separate patch, but in this case, it should be fine.

>> Kevin, patch 3 is all yours !

Applied to v4.14/dt,

Thanks,

Kevin

Re: [PATCH v3 1/3] dt-bindings: clock: meson8b: describe the embedded reset controller

[Rob Herring]

On Fri, Jul 28, 2017 at 11:13:11PM +0200, Martin Blumenstingl wrote:
> The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
> lines. These are used for example to boot the secondary CPU cores.
> 
> This patch describes the reset controller which is embedded into the
> clock controller on these SoCs.
> A header file is provided which provides preprocessor macros for each
> reset line (to make the .dts files easier to read).
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
>  .../bindings/clock/amlogic,meson8b-clkc.txt        |  9 +++++++-
>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h | 27 ++++++++++++++++++++++
>  2 files changed, 35 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v3 1/3] dt-bindings: clock: meson8b: describe the embedded reset controller

[Rob Herring]

On Fri, Jul 28, 2017 at 11:13:11PM +0200, Martin Blumenstingl wrote:
> The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
> lines. These are used for example to boot the secondary CPU cores.
> 
> This patch describes the reset controller which is embedded into the
> clock controller on these SoCs.
> A header file is provided which provides preprocessor macros for each
> reset line (to make the .dts files easier to read).
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
>  .../bindings/clock/amlogic,meson8b-clkc.txt        |  9 +++++++-
>  .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h | 27 ++++++++++++++++++++++
>  2 files changed, 35 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

Acked-by: Rob Herring <robh@kernel.org>