* [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b
@ 2018-04-22 10:45 Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 1/2] ARM: dts: meson8: add the cortex-a9-pmu compatible PMU Martin Blumenstingl
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Martin Blumenstingl @ 2018-04-22 10:45 UTC (permalink / raw)
To: linus-amlogic
Meson8 uses Cortex-A9 cores and Meson8b uses Cortex-A5 cores. As most
Cortex-A5/A9 implementation these Amlogic SoCs also come with a
built-in PMU for counting cpu and cache events like cache misses and
hits.
Testing was done with:
# perf stat -a stress --cpu 4
(wait for ~8 seconds, then CTRL+C)
stress: info: [347] dispatching hogs: 4 cpu, 0 io, 0 vm, 0 hdd
stress: Interrupt
Performance counter stats for 'system wide':
33096.764000 cpu-clock (msec) # 4.000 CPUs utilized
587 context-switches # 0.018 K/sec
6 cpu-migrations # 0.000 K/sec
146 page-faults # 0.004 K/sec
39601836695 cycles # 1.197 GHz
28734941189 instructions # 0.73 insn per cycle
3326006882 branches # 100.493 M/sec
12294901 branch-misses # 0.37% of all branches
8.274358000 seconds time elapsed
# grep arm-pmu /proc/interrupts
29: 7 0 0 0 GIC-0 169 Level arm-pmu
30: 0 7 0 0 GIC-0 170 Level arm-pmu
31: 0 0 7 0 GIC-0 185 Level arm-pmu
32: 0 0 0 7 GIC-0 186 Level arm-pmu
Martin Blumenstingl (2):
ARM: dts: meson8: add the cortex-a9-pmu compatible PMU
ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU
arch/arm/boot/dts/meson8.dtsi | 17 +++++++++++++----
arch/arm/boot/dts/meson8b.dtsi | 17 +++++++++++++----
2 files changed, 26 insertions(+), 8 deletions(-)
--
2.17.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] ARM: dts: meson8: add the cortex-a9-pmu compatible PMU
2018-04-22 10:45 [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Martin Blumenstingl
@ 2018-04-22 10:45 ` Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 2/2] ARM: dts: meson8b: add the cortex-a5-pmu " Martin Blumenstingl
2018-04-27 19:08 ` [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Kevin Hilman
2 siblings, 0 replies; 4+ messages in thread
From: Martin Blumenstingl @ 2018-04-22 10:45 UTC (permalink / raw)
To: linus-amlogic
Enable the performance monitor unit on Meson8.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index dcc9292d2ffa..7b16ea61e914 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -57,7 +57,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu at 200 {
+ cpu0: cpu at 200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@@ -66,7 +66,7 @@
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
- cpu at 201 {
+ cpu1: cpu at 201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@@ -75,7 +75,7 @@
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
- cpu at 202 {
+ cpu2: cpu at 202 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@@ -84,7 +84,7 @@
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
- cpu at 203 {
+ cpu3: cpu at 203 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@@ -94,6 +94,15 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
--
2.17.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU
2018-04-22 10:45 [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 1/2] ARM: dts: meson8: add the cortex-a9-pmu compatible PMU Martin Blumenstingl
@ 2018-04-22 10:45 ` Martin Blumenstingl
2018-04-27 19:08 ` [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Kevin Hilman
2 siblings, 0 replies; 4+ messages in thread
From: Martin Blumenstingl @ 2018-04-22 10:45 UTC (permalink / raw)
To: linus-amlogic
Enable the performance monitor unit on Meson8b.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8b.dtsi | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 553b82174604..6cfd7e225cee 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -55,7 +55,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu at 200 {
+ cpu0: cpu at 200 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -64,7 +64,7 @@
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
- cpu at 201 {
+ cpu1: cpu at 201 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -73,7 +73,7 @@
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
- cpu at 202 {
+ cpu2: cpu at 202 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -82,7 +82,7 @@
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
- cpu at 203 {
+ cpu3: cpu at 203 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -92,6 +92,15 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a5-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
--
2.17.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b
2018-04-22 10:45 [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 1/2] ARM: dts: meson8: add the cortex-a9-pmu compatible PMU Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 2/2] ARM: dts: meson8b: add the cortex-a5-pmu " Martin Blumenstingl
@ 2018-04-27 19:08 ` Kevin Hilman
2 siblings, 0 replies; 4+ messages in thread
From: Kevin Hilman @ 2018-04-27 19:08 UTC (permalink / raw)
To: linus-amlogic
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> Meson8 uses Cortex-A9 cores and Meson8b uses Cortex-A5 cores. As most
> Cortex-A5/A9 implementation these Amlogic SoCs also come with a
> built-in PMU for counting cpu and cache events like cache misses and
> hits.
Applied to v4.18/dt,
Thanks,
Kevin
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-04-27 19:08 UTC | newest]
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2018-04-22 10:45 [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 1/2] ARM: dts: meson8: add the cortex-a9-pmu compatible PMU Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 2/2] ARM: dts: meson8b: add the cortex-a5-pmu " Martin Blumenstingl
2018-04-27 19:08 ` [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Kevin Hilman
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