[PATCH v4] Mediatek SCPSYS power domain support

[PATCH v4] Mediatek SCPSYS power domain support

[Sascha Hauer]

This series adds support for the MediaTek SCPSYS unit.

The SCPSYS unit handles several power management related tasks such
as thermal measurement, DVFS, interrupt filter and low level sleep
control.

The initial support only contains the generic power domain handling.
This is needed to turn on power to the different power domains.

The driver is quite straight forward now. Due to the lack of a better
place I have put it to drivers/soc/mediatek. As the SCPSYS unit has
several other tasks that also do not fit into some specific subsystem
this probably is a good place for this driver.

Patch 5/5 currently has a dependency on the patch adding the clocks
to the MT8173 dtsi file, the rest should be mergable as is.

Please review, any input welcome.

Sascha

Changes since v3:
- Drop unnecessary MODULE_* macros for builtin code
- introduce scpsys_domain_is_on() function instead of open coding this
  twice
- Drop unnecessary initialisation of power_o[ff|n]_latencies. The kernel
  updates them with the measured values anyway.

changes since v2:
- Add missing include/linux/soc/mediatek/infracfg.h file
- rename VDE -> VDEC, VEN -> VENC, DIS -> DISP and VEN2 -> VENC_LT
  to make the abbreviatons more clear
- make of_device_id const
- remove double loop
- fix hunk in wrong patch
- Fix order of domains. Some domains depend on other domains. Reorder
  the domains so that all domains can be turned on in order when
  CONFIG_PM is disabled. Also fixes earlier mixups in the domain array
- Do not allow compilation as modules. pm_domains cannot be removed, so
  compilation as module is not that useful
- reorder Kconfig items alphabetically
- reorder #includes alphabetically
- select MTK_INFRACFG instead of depending on it
- Use only two clocks as dependencies for the domains. The previously
  used 5 clocks are not necessary as confirmed by the hardware designers
- use 'genpd' as variable name for struct generic_pm_domain like done in
  other pm code

changes since v1:
- make MFG_ASYNC a subdomain of MFG_2D and MFG_2D a subdomain of MFG
- Add (now hopefully properly) infracfg register handling again
- Add clock handling
- Fix on/off mixup in error message
- Make readonly data const
- Fix MODULE_LICENSE to GPL v2

changes since RFC:

- add a commit log to driver patch
- drop manipulating infracfg registers for now, can be added (properly)
  later
- Add warning messages when errors occur
- add NULL pointer check for kmalloc

----------------------------------------------------------------
Sascha Hauer (5):
      soc: mediatek: Add infracfg misc driver support
      dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit
      soc: Mediatek: Add SCPSYS power domain driver
      ARM64: MediaTek: Add generic pm domain support
      ARM64: MediaTek MT8173: Add SCPSYS device node

 .../devicetree/bindings/soc/mediatek/scpsys.txt    |  34 ++
 arch/arm64/Kconfig                                 |   1 +
 arch/arm64/boot/dts/mediatek/mt8173.dtsi           |  10 +
 drivers/soc/mediatek/Kconfig                       |  18 +
 drivers/soc/mediatek/Makefile                      |   2 +
 drivers/soc/mediatek/mtk-infracfg.c                |  91 ++++
 drivers/soc/mediatek/mtk-scpsys.c                  | 490 +++++++++++++++++++++
 include/dt-bindings/power/mt8173-power.h           |  15 +
 include/linux/soc/mediatek/infracfg.h              |  26 ++
 9 files changed, 687 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
 create mode 100644 drivers/soc/mediatek/mtk-infracfg.c
 create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
 create mode 100644 include/dt-bindings/power/mt8173-power.h
 create mode 100644 include/linux/soc/mediatek/infracfg.h

[PATCH v4] Mediatek SCPSYS power domain support

[Sascha Hauer]

This series adds support for the MediaTek SCPSYS unit.

The SCPSYS unit handles several power management related tasks such
as thermal measurement, DVFS, interrupt filter and low level sleep
control.

The initial support only contains the generic power domain handling.
This is needed to turn on power to the different power domains.

The driver is quite straight forward now. Due to the lack of a better
place I have put it to drivers/soc/mediatek. As the SCPSYS unit has
several other tasks that also do not fit into some specific subsystem
this probably is a good place for this driver.

Patch 5/5 currently has a dependency on the patch adding the clocks
to the MT8173 dtsi file, the rest should be mergable as is.

Please review, any input welcome.

Sascha

Changes since v3:
- Drop unnecessary MODULE_* macros for builtin code
- introduce scpsys_domain_is_on() function instead of open coding this
  twice
- Drop unnecessary initialisation of power_o[ff|n]_latencies. The kernel
  updates them with the measured values anyway.

changes since v2:
- Add missing include/linux/soc/mediatek/infracfg.h file
- rename VDE -> VDEC, VEN -> VENC, DIS -> DISP and VEN2 -> VENC_LT
  to make the abbreviatons more clear
- make of_device_id const
- remove double loop
- fix hunk in wrong patch
- Fix order of domains. Some domains depend on other domains. Reorder
  the domains so that all domains can be turned on in order when
  CONFIG_PM is disabled. Also fixes earlier mixups in the domain array
- Do not allow compilation as modules. pm_domains cannot be removed, so
  compilation as module is not that useful
- reorder Kconfig items alphabetically
- reorder #includes alphabetically
- select MTK_INFRACFG instead of depending on it
- Use only two clocks as dependencies for the domains. The previously
  used 5 clocks are not necessary as confirmed by the hardware designers
- use 'genpd' as variable name for struct generic_pm_domain like done in
  other pm code

changes since v1:
- make MFG_ASYNC a subdomain of MFG_2D and MFG_2D a subdomain of MFG
- Add (now hopefully properly) infracfg register handling again
- Add clock handling
- Fix on/off mixup in error message
- Make readonly data const
- Fix MODULE_LICENSE to GPL v2

changes since RFC:

- add a commit log to driver patch
- drop manipulating infracfg registers for now, can be added (properly)
  later
- Add warning messages when errors occur
- add NULL pointer check for kmalloc

----------------------------------------------------------------
Sascha Hauer (5):
      soc: mediatek: Add infracfg misc driver support
      dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit
      soc: Mediatek: Add SCPSYS power domain driver
      ARM64: MediaTek: Add generic pm domain support
      ARM64: MediaTek MT8173: Add SCPSYS device node

 .../devicetree/bindings/soc/mediatek/scpsys.txt    |  34 ++
 arch/arm64/Kconfig                                 |   1 +
 arch/arm64/boot/dts/mediatek/mt8173.dtsi           |  10 +
 drivers/soc/mediatek/Kconfig                       |  18 +
 drivers/soc/mediatek/Makefile                      |   2 +
 drivers/soc/mediatek/mtk-infracfg.c                |  91 ++++
 drivers/soc/mediatek/mtk-scpsys.c                  | 490 +++++++++++++++++++++
 include/dt-bindings/power/mt8173-power.h           |  15 +
 include/linux/soc/mediatek/infracfg.h              |  26 ++
 9 files changed, 687 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
 create mode 100644 drivers/soc/mediatek/mtk-infracfg.c
 create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
 create mode 100644 include/dt-bindings/power/mt8173-power.h
 create mode 100644 include/linux/soc/mediatek/infracfg.h

[PATCH 1/5] soc: mediatek: Add infracfg misc driver support

[Sascha Hauer]

This adds support for some miscellaneous bits of the infracfg controller.
The mtk_infracfg_set/clear_bus_protection functions are necessary for
the scpsys power domain driver to handle the bus protection bits which
are contained in the infacfg register space.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/soc/mediatek/Kconfig          |  9 ++++
 drivers/soc/mediatek/Makefile         |  1 +
 drivers/soc/mediatek/mtk-infracfg.c   | 91 +++++++++++++++++++++++++++++++++++
 include/linux/soc/mediatek/infracfg.h | 26 ++++++++++
 4 files changed, 127 insertions(+)
 create mode 100644 drivers/soc/mediatek/mtk-infracfg.c
 create mode 100644 include/linux/soc/mediatek/infracfg.h

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index bcdb22d..e4f37a3 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -1,6 +1,15 @@
 #
 # MediaTek SoC drivers
 #
+config MTK_INFRACFG
+	bool "MediaTek INFRACFG Support"
+	depends on ARCH_MEDIATEK
+	select REGMAP
+	help
+	  Say yes here to add support for the MediaTek INFRACFG controller. The
+	  INFRACFG controller contains various infrastructure registers not
+	  directly associated to any device.
+
 config MTK_PMIC_WRAP
 	tristate "MediaTek PMIC Wrapper Support"
 	depends on ARCH_MEDIATEK
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index ecaf4de..3fa940f 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
new file mode 100644
index 0000000..ca786e0
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-infracfg.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/export.h>
+#include <linux/jiffies.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/infracfg.h>
+#include <asm/processor.h>
+
+#define INFRA_TOPAXI_PROTECTEN		0x0220
+#define INFRA_TOPAXI_PROTECTSTA1	0x0228
+
+/**
+ * mtk_infracfg_set_bus_protection - enable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be enabled.
+ *
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hanf when some unit accesses the
+ * bus while in power down.
+ */
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
+{
+	unsigned long expired;
+	u32 val;
+	int ret;
+
+	regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask);
+
+	expired = jiffies + HZ;
+
+	while (1) {
+		ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+		if (ret)
+			return ret;
+
+		if ((val & mask) == mask)
+			break;
+
+		cpu_relax();
+		if (time_after(jiffies, expired))
+			return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * mtk_infracfg_clear_bus_protection - disable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be disabled.
+ *
+ * This function disables the bus protection bits previously enabled with
+ * mtk_infracfg_set_bus_protection.
+ */
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask)
+{
+	unsigned long expired;
+	int ret;
+
+	regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
+
+	expired = jiffies + HZ;
+
+	while (1) {
+		u32 val;
+
+		ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+		if (ret)
+			return ret;
+
+		if (!(val & mask))
+			break;
+
+		cpu_relax();
+		if (time_after(jiffies, expired))
+			return -EIO;
+	}
+
+	return 0;
+}
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
new file mode 100644
index 0000000..a5714e9
--- /dev/null
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -0,0 +1,26 @@
+#ifndef __SOC_MEDIATEK_INFRACFG_H
+#define __SOC_MEDIATEK_INFRACFG_H
+
+#define MT8173_TOP_AXI_PROT_EN_MCI_M2		BIT(0)
+#define MT8173_TOP_AXI_PROT_EN_MM_M0		BIT(1)
+#define MT8173_TOP_AXI_PROT_EN_MM_M1		BIT(2)
+#define MT8173_TOP_AXI_PROT_EN_MMAPB_S		BIT(6)
+#define MT8173_TOP_AXI_PROT_EN_L2C_M2		BIT(9)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI		BIT(11)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD		BIT(12)
+#define MT8173_TOP_AXI_PROT_EN_CCI_M2		BIT(13)
+#define MT8173_TOP_AXI_PROT_EN_MFG_S		BIT(14)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M0		BIT(15)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M1		BIT(16)
+#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS		BIT(17)
+#define MT8173_TOP_AXI_PROT_EN_CQ_DMA		BIT(18)
+#define MT8173_TOP_AXI_PROT_EN_GCPU		BIT(19)
+#define MT8173_TOP_AXI_PROT_EN_IOMMU		BIT(20)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M0		BIT(21)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
+#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
+
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
+
+#endif /* __SOC_MEDIATEK_INFRACFG_H */
-- 
2.1.4

[PATCH 1/5] soc: mediatek: Add infracfg misc driver support

[Sascha Hauer]

This adds support for some miscellaneous bits of the infracfg controller.
The mtk_infracfg_set/clear_bus_protection functions are necessary for
the scpsys power domain driver to handle the bus protection bits which
are contained in the infacfg register space.

Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 drivers/soc/mediatek/Kconfig          |  9 ++++
 drivers/soc/mediatek/Makefile         |  1 +
 drivers/soc/mediatek/mtk-infracfg.c   | 91 +++++++++++++++++++++++++++++++++++
 include/linux/soc/mediatek/infracfg.h | 26 ++++++++++
 4 files changed, 127 insertions(+)
 create mode 100644 drivers/soc/mediatek/mtk-infracfg.c
 create mode 100644 include/linux/soc/mediatek/infracfg.h

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index bcdb22d..e4f37a3 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -1,6 +1,15 @@
 #
 # MediaTek SoC drivers
 #
+config MTK_INFRACFG
+	bool "MediaTek INFRACFG Support"
+	depends on ARCH_MEDIATEK
+	select REGMAP
+	help
+	  Say yes here to add support for the MediaTek INFRACFG controller. The
+	  INFRACFG controller contains various infrastructure registers not
+	  directly associated to any device.
+
 config MTK_PMIC_WRAP
 	tristate "MediaTek PMIC Wrapper Support"
 	depends on ARCH_MEDIATEK
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index ecaf4de..3fa940f 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
new file mode 100644
index 0000000..ca786e0
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-infracfg.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/export.h>
+#include <linux/jiffies.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/infracfg.h>
+#include <asm/processor.h>
+
+#define INFRA_TOPAXI_PROTECTEN		0x0220
+#define INFRA_TOPAXI_PROTECTSTA1	0x0228
+
+/**
+ * mtk_infracfg_set_bus_protection - enable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be enabled.
+ *
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hanf when some unit accesses the
+ * bus while in power down.
+ */
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
+{
+	unsigned long expired;
+	u32 val;
+	int ret;
+
+	regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask);
+
+	expired = jiffies + HZ;
+
+	while (1) {
+		ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+		if (ret)
+			return ret;
+
+		if ((val & mask) == mask)
+			break;
+
+		cpu_relax();
+		if (time_after(jiffies, expired))
+			return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * mtk_infracfg_clear_bus_protection - disable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be disabled.
+ *
+ * This function disables the bus protection bits previously enabled with
+ * mtk_infracfg_set_bus_protection.
+ */
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask)
+{
+	unsigned long expired;
+	int ret;
+
+	regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
+
+	expired = jiffies + HZ;
+
+	while (1) {
+		u32 val;
+
+		ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+		if (ret)
+			return ret;
+
+		if (!(val & mask))
+			break;
+
+		cpu_relax();
+		if (time_after(jiffies, expired))
+			return -EIO;
+	}
+
+	return 0;
+}
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
new file mode 100644
index 0000000..a5714e9
--- /dev/null
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -0,0 +1,26 @@
+#ifndef __SOC_MEDIATEK_INFRACFG_H
+#define __SOC_MEDIATEK_INFRACFG_H
+
+#define MT8173_TOP_AXI_PROT_EN_MCI_M2		BIT(0)
+#define MT8173_TOP_AXI_PROT_EN_MM_M0		BIT(1)
+#define MT8173_TOP_AXI_PROT_EN_MM_M1		BIT(2)
+#define MT8173_TOP_AXI_PROT_EN_MMAPB_S		BIT(6)
+#define MT8173_TOP_AXI_PROT_EN_L2C_M2		BIT(9)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI		BIT(11)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD		BIT(12)
+#define MT8173_TOP_AXI_PROT_EN_CCI_M2		BIT(13)
+#define MT8173_TOP_AXI_PROT_EN_MFG_S		BIT(14)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M0		BIT(15)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M1		BIT(16)
+#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS		BIT(17)
+#define MT8173_TOP_AXI_PROT_EN_CQ_DMA		BIT(18)
+#define MT8173_TOP_AXI_PROT_EN_GCPU		BIT(19)
+#define MT8173_TOP_AXI_PROT_EN_IOMMU		BIT(20)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M0		BIT(21)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
+#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
+
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
+
+#endif /* __SOC_MEDIATEK_INFRACFG_H */
-- 
2.1.4

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[PATCH 1/5] soc: mediatek: Add infracfg misc driver support

[Sascha Hauer]

This adds support for some miscellaneous bits of the infracfg controller.
The mtk_infracfg_set/clear_bus_protection functions are necessary for
the scpsys power domain driver to handle the bus protection bits which
are contained in the infacfg register space.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/soc/mediatek/Kconfig          |  9 ++++
 drivers/soc/mediatek/Makefile         |  1 +
 drivers/soc/mediatek/mtk-infracfg.c   | 91 +++++++++++++++++++++++++++++++++++
 include/linux/soc/mediatek/infracfg.h | 26 ++++++++++
 4 files changed, 127 insertions(+)
 create mode 100644 drivers/soc/mediatek/mtk-infracfg.c
 create mode 100644 include/linux/soc/mediatek/infracfg.h

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index bcdb22d..e4f37a3 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -1,6 +1,15 @@
 #
 # MediaTek SoC drivers
 #
+config MTK_INFRACFG
+	bool "MediaTek INFRACFG Support"
+	depends on ARCH_MEDIATEK
+	select REGMAP
+	help
+	  Say yes here to add support for the MediaTek INFRACFG controller. The
+	  INFRACFG controller contains various infrastructure registers not
+	  directly associated to any device.
+
 config MTK_PMIC_WRAP
 	tristate "MediaTek PMIC Wrapper Support"
 	depends on ARCH_MEDIATEK
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index ecaf4de..3fa940f 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
new file mode 100644
index 0000000..ca786e0
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-infracfg.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/export.h>
+#include <linux/jiffies.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/infracfg.h>
+#include <asm/processor.h>
+
+#define INFRA_TOPAXI_PROTECTEN		0x0220
+#define INFRA_TOPAXI_PROTECTSTA1	0x0228
+
+/**
+ * mtk_infracfg_set_bus_protection - enable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be enabled.
+ *
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hanf when some unit accesses the
+ * bus while in power down.
+ */
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
+{
+	unsigned long expired;
+	u32 val;
+	int ret;
+
+	regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask);
+
+	expired = jiffies + HZ;
+
+	while (1) {
+		ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+		if (ret)
+			return ret;
+
+		if ((val & mask) == mask)
+			break;
+
+		cpu_relax();
+		if (time_after(jiffies, expired))
+			return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * mtk_infracfg_clear_bus_protection - disable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be disabled.
+ *
+ * This function disables the bus protection bits previously enabled with
+ * mtk_infracfg_set_bus_protection.
+ */
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask)
+{
+	unsigned long expired;
+	int ret;
+
+	regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
+
+	expired = jiffies + HZ;
+
+	while (1) {
+		u32 val;
+
+		ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+		if (ret)
+			return ret;
+
+		if (!(val & mask))
+			break;
+
+		cpu_relax();
+		if (time_after(jiffies, expired))
+			return -EIO;
+	}
+
+	return 0;
+}
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
new file mode 100644
index 0000000..a5714e9
--- /dev/null
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -0,0 +1,26 @@
+#ifndef __SOC_MEDIATEK_INFRACFG_H
+#define __SOC_MEDIATEK_INFRACFG_H
+
+#define MT8173_TOP_AXI_PROT_EN_MCI_M2		BIT(0)
+#define MT8173_TOP_AXI_PROT_EN_MM_M0		BIT(1)
+#define MT8173_TOP_AXI_PROT_EN_MM_M1		BIT(2)
+#define MT8173_TOP_AXI_PROT_EN_MMAPB_S		BIT(6)
+#define MT8173_TOP_AXI_PROT_EN_L2C_M2		BIT(9)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI		BIT(11)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD		BIT(12)
+#define MT8173_TOP_AXI_PROT_EN_CCI_M2		BIT(13)
+#define MT8173_TOP_AXI_PROT_EN_MFG_S		BIT(14)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M0		BIT(15)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M1		BIT(16)
+#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS		BIT(17)
+#define MT8173_TOP_AXI_PROT_EN_CQ_DMA		BIT(18)
+#define MT8173_TOP_AXI_PROT_EN_GCPU		BIT(19)
+#define MT8173_TOP_AXI_PROT_EN_IOMMU		BIT(20)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M0		BIT(21)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
+#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
+
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
+
+#endif /* __SOC_MEDIATEK_INFRACFG_H */
-- 
2.1.4

[PATCH 2/5] dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit

[Sascha Hauer]

This adds documentation for the MediaTek SCPSYS unit found in MT8173 SoCs.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt    | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
new file mode 100644
index 0000000..87f2091
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -0,0 +1,34 @@
+MediaTek SCPSYS
+===============
+
+The System Control Processor System (SCPSYS) has several power management
+related tasks in the system. The tasks include thermal measurement, dynamic
+voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
+The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
+domain control.
+
+The driver implements the Generic PM domain bindings described in
+power/power_domain.txt. It provides the power domains defined in
+include/dt-bindings/power/mt8173-power.h.
+
+Required properties:
+- compatible: Must be "mediatek,mt8173-scpsys"
+- #power-domain-cells: Must be 1
+- reg: Address range of the SCPSYS unit
+- infracfg: must contain a phandle to the infracfg controller
+
+Example:
+
+	scpsys: scpsys@10006000 {
+		#power-domain-cells = <1>;
+		compatible = "mediatek,mt8173-scpsys";
+		reg = <0 0x10006000 0 0x1000>;
+		infracfg = <&infracfg>;
+	};
+
+Example consumer:
+
+	afe: mt8173-afe-pcm@11220000 {
+		compatible = "mediatek,mt8173-afe-pcm";
+		power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+	};
-- 
2.1.4

[PATCH 2/5] dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit

[Sascha Hauer]

This adds documentation for the MediaTek SCPSYS unit found in MT8173 SoCs.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt    | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
new file mode 100644
index 0000000..87f2091
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -0,0 +1,34 @@
+MediaTek SCPSYS
+===============
+
+The System Control Processor System (SCPSYS) has several power management
+related tasks in the system. The tasks include thermal measurement, dynamic
+voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
+The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
+domain control.
+
+The driver implements the Generic PM domain bindings described in
+power/power_domain.txt. It provides the power domains defined in
+include/dt-bindings/power/mt8173-power.h.
+
+Required properties:
+- compatible: Must be "mediatek,mt8173-scpsys"
+- #power-domain-cells: Must be 1
+- reg: Address range of the SCPSYS unit
+- infracfg: must contain a phandle to the infracfg controller
+
+Example:
+
+	scpsys: scpsys at 10006000 {
+		#power-domain-cells = <1>;
+		compatible = "mediatek,mt8173-scpsys";
+		reg = <0 0x10006000 0 0x1000>;
+		infracfg = <&infracfg>;
+	};
+
+Example consumer:
+
+	afe: mt8173-afe-pcm at 11220000 {
+		compatible = "mediatek,mt8173-afe-pcm";
+		power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+	};
-- 
2.1.4

[PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Sascha Hauer]

This adds a power domain driver for the Mediatek SCPSYS unit.

The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.

For now this driver only adds power domain support, the more
advanced features are not yet supported. The driver implements
the generic PM domain device tree bindings, the first user will
most likely be the Mediatek AFE audio driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/soc/mediatek/Kconfig             |   9 +
 drivers/soc/mediatek/Makefile            |   1 +
 drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
 include/dt-bindings/power/mt8173-power.h |  15 +
 4 files changed, 515 insertions(+)
 create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
 create mode 100644 include/dt-bindings/power/mt8173-power.h

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index e4f37a3..9a61b54 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
 	  Say yes here to add support for MediaTek PMIC Wrapper found
 	  on different MediaTek SoCs. The PMIC wrapper is a proprietary
 	  hardware to connect the PMIC.
+
+config MTK_SCPSYS
+	bool "MediaTek SCPSYS Support"
+	depends on ARCH_MEDIATEK || COMPILE_TEST
+	select REGMAP
+	select MTK_INFRACFG
+	help
+	  Say yes here to add support for the MediaTek SCPSYS power domain
+	  driver.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 3fa940f..12998b0 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
+obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
new file mode 100644
index 0000000..b9eed37
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/infracfg.h>
+#include <dt-bindings/power/mt8173-power.h>
+
+#define SPM_VDE_PWR_CON			0x0210
+#define SPM_MFG_PWR_CON			0x0214
+#define SPM_VEN_PWR_CON			0x0230
+#define SPM_ISP_PWR_CON			0x0238
+#define SPM_DIS_PWR_CON			0x023c
+#define SPM_VEN2_PWR_CON		0x0298
+#define SPM_AUDIO_PWR_CON		0x029c
+#define SPM_MFG_2D_PWR_CON		0x02c0
+#define SPM_MFG_ASYNC_PWR_CON		0x02c4
+#define SPM_USB_PWR_CON			0x02cc
+#define SPM_PWR_STATUS			0x060c
+#define SPM_PWR_STATUS_2ND		0x0610
+
+#define PWR_RST_B_BIT			BIT(0)
+#define PWR_ISO_BIT			BIT(1)
+#define PWR_ON_BIT			BIT(2)
+#define PWR_ON_2ND_BIT			BIT(3)
+#define PWR_CLK_DIS_BIT			BIT(4)
+
+#define PWR_STATUS_DISP			BIT(3)
+#define PWR_STATUS_MFG			BIT(4)
+#define PWR_STATUS_ISP			BIT(5)
+#define PWR_STATUS_VDEC			BIT(7)
+#define PWR_STATUS_VENC_LT		BIT(20)
+#define PWR_STATUS_VENC			BIT(21)
+#define PWR_STATUS_MFG_2D		BIT(22)
+#define PWR_STATUS_MFG_ASYNC		BIT(23)
+#define PWR_STATUS_AUDIO		BIT(24)
+#define PWR_STATUS_USB			BIT(25)
+
+enum clk_id {
+	MT8173_CLK_NONE,
+	MT8173_CLK_MM,
+	MT8173_CLK_MFG,
+	MT8173_CLK_MAX = MT8173_CLK_MFG,
+};
+
+struct scp_domain_data {
+	const char *name;
+	u32 sta_mask;
+	int ctl_offs;
+	u32 sram_pdn_bits;
+	u32 sram_pdn_ack_bits;
+	u32 bus_prot_mask;
+	enum clk_id clk_id;
+};
+
+static const struct scp_domain_data scp_domain_data[] __initconst = {
+	[MT8173_POWER_DOMAIN_VDEC] = {
+		.name = "vdec",
+		.sta_mask = PWR_STATUS_VDEC,
+		.ctl_offs = SPM_VDE_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(12, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_VENC] = {
+		.name = "venc",
+		.sta_mask = PWR_STATUS_VENC,
+		.ctl_offs = SPM_VEN_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_ISP] = {
+		.name = "isp",
+		.sta_mask = PWR_STATUS_ISP,
+		.ctl_offs = SPM_ISP_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(13, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_MM] = {
+		.name = "mm",
+		.sta_mask = PWR_STATUS_DISP,
+		.ctl_offs = SPM_DIS_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(12, 12),
+		.clk_id = MT8173_CLK_MM,
+		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
+			MT8173_TOP_AXI_PROT_EN_MM_M1,
+	},
+	[MT8173_POWER_DOMAIN_VENC_LT] = {
+		.name = "venc_lt",
+		.sta_mask = PWR_STATUS_VENC_LT,
+		.ctl_offs = SPM_VEN2_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_AUDIO] = {
+		.name = "audio",
+		.sta_mask = PWR_STATUS_AUDIO,
+		.ctl_offs = SPM_AUDIO_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_NONE,
+	},
+	[MT8173_POWER_DOMAIN_USB] = {
+		.name = "usb",
+		.sta_mask = PWR_STATUS_USB,
+		.ctl_offs = SPM_USB_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_NONE,
+	},
+	[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
+		.name = "mfg_async",
+		.sta_mask = PWR_STATUS_MFG_ASYNC,
+		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = 0,
+		.clk_id = MT8173_CLK_MFG,
+	},
+	[MT8173_POWER_DOMAIN_MFG_2D] = {
+		.name = "mfg_2d",
+		.sta_mask = PWR_STATUS_MFG_2D,
+		.ctl_offs = SPM_MFG_2D_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(13, 12),
+		.clk_id = MT8173_CLK_NONE,
+	},
+	[MT8173_POWER_DOMAIN_MFG] = {
+		.name = "mfg",
+		.sta_mask = PWR_STATUS_MFG,
+		.ctl_offs = SPM_MFG_PWR_CON,
+		.sram_pdn_bits = GENMASK(13, 8),
+		.sram_pdn_ack_bits = GENMASK(21, 16),
+		.clk_id = MT8173_CLK_NONE,
+		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
+			MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+			MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+			MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
+	},
+};
+
+#define NUM_DOMAINS	ARRAY_SIZE(scp_domain_data)
+
+struct scp;
+
+struct scp_domain {
+	struct generic_pm_domain genpd;
+	struct scp *scp;
+	struct clk *clk;
+	u32 sta_mask;
+	void __iomem *ctl_addr;
+	u32 sram_pdn_bits;
+	u32 sram_pdn_ack_bits;
+	u32 bus_prot_mask;
+};
+
+struct scp {
+	struct scp_domain domains[NUM_DOMAINS];
+	struct genpd_onecell_data pd_data;
+	struct device *dev;
+	void __iomem *base;
+	struct regmap *infracfg;
+	struct clk *clk[MT8173_CLK_MAX];
+};
+
+static int scpsys_domain_is_on(struct scp_domain *scpd)
+{
+	struct scp *scp = scpd->scp;
+
+	u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
+	u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
+
+	/*
+	 * A domain is on when both status bits are set. If only one is set
+	 * return an error. This happens while powering up a domain
+	 */
+
+	if (status && status2)
+		return true;
+	if (!status && !status2)
+		return false;
+
+	return -EINVAL;
+}
+
+static int scpsys_power_on(struct generic_pm_domain *genpd)
+{
+	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+	struct scp *scp = scpd->scp;
+	unsigned long timeout;
+	bool expired;
+	void __iomem *ctl_addr = scpd->ctl_addr;
+	u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
+	u32 val;
+	int ret;
+
+	if (scpd->clk) {
+		ret = clk_prepare_enable(scpd->clk);
+		if (ret)
+			return ret;
+	}
+
+	val = readl(ctl_addr);
+	val |= PWR_ON_BIT;
+	writel(val, ctl_addr);
+	val |= PWR_ON_2ND_BIT;
+	writel(val, ctl_addr);
+
+	/* wait until PWR_ACK = 1 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (1) {
+		ret = scpsys_domain_is_on(scpd);
+		if (ret > 0)
+			break;
+
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	val &= ~PWR_CLK_DIS_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_ISO_BIT;
+	writel(val, ctl_addr);
+
+	val |= PWR_RST_B_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~scpd->sram_pdn_bits;
+	writel(val, ctl_addr);
+
+	/* wait until SRAM_PDN_ACK all 0 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
+
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	if (scpd->bus_prot_mask) {
+		ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
+				scpd->bus_prot_mask);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+out:
+	dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
+
+	return ret;
+}
+
+static int scpsys_power_off(struct generic_pm_domain *genpd)
+{
+	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+	struct scp *scp = scpd->scp;
+	unsigned long timeout;
+	bool expired;
+	void __iomem *ctl_addr = scpd->ctl_addr;
+	u32 pdn_ack = scpd->sram_pdn_ack_bits;
+	u32 val;
+	int ret;
+
+	if (scpd->bus_prot_mask) {
+		ret = mtk_infracfg_set_bus_protection(scp->infracfg,
+				scpd->bus_prot_mask);
+		if (ret)
+			return ret;
+	}
+
+	val = readl(ctl_addr);
+	val |= scpd->sram_pdn_bits;
+	writel(val, ctl_addr);
+
+	/* wait until SRAM_PDN_ACK all 1 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	val |= PWR_ISO_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_RST_B_BIT;
+	writel(val, ctl_addr);
+
+	val |= PWR_CLK_DIS_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_ON_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_ON_2ND_BIT;
+	writel(val, ctl_addr);
+
+	/* wait until PWR_ACK = 0 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (1) {
+		ret = scpsys_domain_is_on(scpd);
+		if (ret == 0)
+			break;
+
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	if (scpd->clk)
+		clk_disable_unprepare(scpd->clk);
+
+	return 0;
+
+out:
+	dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
+
+	return ret;
+}
+
+static int __init scpsys_probe(struct platform_device *pdev)
+{
+	struct genpd_onecell_data *pd_data;
+	struct resource *res;
+	int i, ret;
+	struct scp *scp;
+
+	scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
+	if (!scp)
+		return -ENOMEM;
+
+	scp->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	scp->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(scp->base))
+		return PTR_ERR(scp->base);
+
+	pd_data = &scp->pd_data;
+
+	pd_data->domains = devm_kzalloc(&pdev->dev,
+			sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
+	if (!pd_data->domains)
+		return -ENOMEM;
+
+	scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
+	if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
+		dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
+				PTR_ERR(scp->clk[MT8173_CLK_MM]));
+		return PTR_ERR(scp->clk[MT8173_CLK_MM]);
+	}
+
+	scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
+	if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
+		dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
+				PTR_ERR(scp->clk[MT8173_CLK_MFG]));
+		return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
+	}
+
+	scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+			"infracfg");
+	if (IS_ERR(scp->infracfg)) {
+		dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
+				PTR_ERR(scp->infracfg));
+		return PTR_ERR(scp->infracfg);
+	}
+
+	pd_data->num_domains = NUM_DOMAINS;
+
+	for (i = 0; i < NUM_DOMAINS; i++) {
+		struct scp_domain *scpd = &scp->domains[i];
+		struct generic_pm_domain *genpd = &scpd->genpd;
+		const struct scp_domain_data *data = &scp_domain_data[i];
+
+		pd_data->domains[i] = genpd;
+		scpd->scp = scp;
+
+		scpd->sta_mask = data->sta_mask;
+		scpd->ctl_addr = scp->base + data->ctl_offs;
+		scpd->sram_pdn_bits = data->sram_pdn_bits;
+		scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
+		scpd->bus_prot_mask = data->bus_prot_mask;
+		if (data->clk_id != MT8173_CLK_NONE)
+			scpd->clk = scp->clk[data->clk_id];
+
+		genpd->name = data->name;
+		genpd->power_off = scpsys_power_off;
+		genpd->power_on = scpsys_power_on;
+
+		/*
+		 * Initially turn on all domains to make the domains usable
+		 * with !CONFIG_PM and to get the hardware in sync with the
+		 * software.  The unused domains will be switched off during
+		 * late_init time.
+		 */
+		genpd->power_on(genpd);
+
+		pm_genpd_init(genpd, NULL, false);
+	}
+
+	/*
+	 * We are not allowed to fail here since there is no way to unregister
+	 * a power domain. Once registered above we have to keep the domains
+	 * valid.
+	 */
+
+	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
+		pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
+	if (ret && IS_ENABLED(CONFIG_PM))
+		dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
+
+	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
+		pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
+	if (ret && IS_ENABLED(CONFIG_PM))
+		dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
+
+	ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
+	if (ret)
+		dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
+
+	return 0;
+}
+
+static const struct of_device_id of_scpsys_match_tbl[] = {
+	{
+		.compatible = "mediatek,mt8173-scpsys",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver scpsys_drv = {
+	.driver = {
+		.name = "mtk-scpsys",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(of_scpsys_match_tbl),
+	},
+};
+
+module_platform_driver_probe(scpsys_drv, scpsys_probe);
diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h
new file mode 100644
index 0000000..b34cee9
--- /dev/null
+++ b/include/dt-bindings/power/mt8173-power.h
@@ -0,0 +1,15 @@
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8173_POWER_DOMAIN_VDEC	0
+#define MT8173_POWER_DOMAIN_VENC	1
+#define MT8173_POWER_DOMAIN_ISP		2
+#define MT8173_POWER_DOMAIN_MM		3
+#define MT8173_POWER_DOMAIN_VENC_LT	4
+#define MT8173_POWER_DOMAIN_AUDIO	5
+#define MT8173_POWER_DOMAIN_USB		6
+#define MT8173_POWER_DOMAIN_MFG_ASYNC	7
+#define MT8173_POWER_DOMAIN_MFG_2D	8
+#define MT8173_POWER_DOMAIN_MFG		9
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
-- 
2.1.4

[PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Sascha Hauer]

This adds a power domain driver for the Mediatek SCPSYS unit.

The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.

For now this driver only adds power domain support, the more
advanced features are not yet supported. The driver implements
the generic PM domain device tree bindings, the first user will
most likely be the Mediatek AFE audio driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/soc/mediatek/Kconfig             |   9 +
 drivers/soc/mediatek/Makefile            |   1 +
 drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
 include/dt-bindings/power/mt8173-power.h |  15 +
 4 files changed, 515 insertions(+)
 create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
 create mode 100644 include/dt-bindings/power/mt8173-power.h

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index e4f37a3..9a61b54 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
 	  Say yes here to add support for MediaTek PMIC Wrapper found
 	  on different MediaTek SoCs. The PMIC wrapper is a proprietary
 	  hardware to connect the PMIC.
+
+config MTK_SCPSYS
+	bool "MediaTek SCPSYS Support"
+	depends on ARCH_MEDIATEK || COMPILE_TEST
+	select REGMAP
+	select MTK_INFRACFG
+	help
+	  Say yes here to add support for the MediaTek SCPSYS power domain
+	  driver.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 3fa940f..12998b0 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
+obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
new file mode 100644
index 0000000..b9eed37
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/infracfg.h>
+#include <dt-bindings/power/mt8173-power.h>
+
+#define SPM_VDE_PWR_CON			0x0210
+#define SPM_MFG_PWR_CON			0x0214
+#define SPM_VEN_PWR_CON			0x0230
+#define SPM_ISP_PWR_CON			0x0238
+#define SPM_DIS_PWR_CON			0x023c
+#define SPM_VEN2_PWR_CON		0x0298
+#define SPM_AUDIO_PWR_CON		0x029c
+#define SPM_MFG_2D_PWR_CON		0x02c0
+#define SPM_MFG_ASYNC_PWR_CON		0x02c4
+#define SPM_USB_PWR_CON			0x02cc
+#define SPM_PWR_STATUS			0x060c
+#define SPM_PWR_STATUS_2ND		0x0610
+
+#define PWR_RST_B_BIT			BIT(0)
+#define PWR_ISO_BIT			BIT(1)
+#define PWR_ON_BIT			BIT(2)
+#define PWR_ON_2ND_BIT			BIT(3)
+#define PWR_CLK_DIS_BIT			BIT(4)
+
+#define PWR_STATUS_DISP			BIT(3)
+#define PWR_STATUS_MFG			BIT(4)
+#define PWR_STATUS_ISP			BIT(5)
+#define PWR_STATUS_VDEC			BIT(7)
+#define PWR_STATUS_VENC_LT		BIT(20)
+#define PWR_STATUS_VENC			BIT(21)
+#define PWR_STATUS_MFG_2D		BIT(22)
+#define PWR_STATUS_MFG_ASYNC		BIT(23)
+#define PWR_STATUS_AUDIO		BIT(24)
+#define PWR_STATUS_USB			BIT(25)
+
+enum clk_id {
+	MT8173_CLK_NONE,
+	MT8173_CLK_MM,
+	MT8173_CLK_MFG,
+	MT8173_CLK_MAX = MT8173_CLK_MFG,
+};
+
+struct scp_domain_data {
+	const char *name;
+	u32 sta_mask;
+	int ctl_offs;
+	u32 sram_pdn_bits;
+	u32 sram_pdn_ack_bits;
+	u32 bus_prot_mask;
+	enum clk_id clk_id;
+};
+
+static const struct scp_domain_data scp_domain_data[] __initconst = {
+	[MT8173_POWER_DOMAIN_VDEC] = {
+		.name = "vdec",
+		.sta_mask = PWR_STATUS_VDEC,
+		.ctl_offs = SPM_VDE_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(12, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_VENC] = {
+		.name = "venc",
+		.sta_mask = PWR_STATUS_VENC,
+		.ctl_offs = SPM_VEN_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_ISP] = {
+		.name = "isp",
+		.sta_mask = PWR_STATUS_ISP,
+		.ctl_offs = SPM_ISP_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(13, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_MM] = {
+		.name = "mm",
+		.sta_mask = PWR_STATUS_DISP,
+		.ctl_offs = SPM_DIS_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(12, 12),
+		.clk_id = MT8173_CLK_MM,
+		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
+			MT8173_TOP_AXI_PROT_EN_MM_M1,
+	},
+	[MT8173_POWER_DOMAIN_VENC_LT] = {
+		.name = "venc_lt",
+		.sta_mask = PWR_STATUS_VENC_LT,
+		.ctl_offs = SPM_VEN2_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_MM,
+	},
+	[MT8173_POWER_DOMAIN_AUDIO] = {
+		.name = "audio",
+		.sta_mask = PWR_STATUS_AUDIO,
+		.ctl_offs = SPM_AUDIO_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_NONE,
+	},
+	[MT8173_POWER_DOMAIN_USB] = {
+		.name = "usb",
+		.sta_mask = PWR_STATUS_USB,
+		.ctl_offs = SPM_USB_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.clk_id = MT8173_CLK_NONE,
+	},
+	[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
+		.name = "mfg_async",
+		.sta_mask = PWR_STATUS_MFG_ASYNC,
+		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = 0,
+		.clk_id = MT8173_CLK_MFG,
+	},
+	[MT8173_POWER_DOMAIN_MFG_2D] = {
+		.name = "mfg_2d",
+		.sta_mask = PWR_STATUS_MFG_2D,
+		.ctl_offs = SPM_MFG_2D_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(13, 12),
+		.clk_id = MT8173_CLK_NONE,
+	},
+	[MT8173_POWER_DOMAIN_MFG] = {
+		.name = "mfg",
+		.sta_mask = PWR_STATUS_MFG,
+		.ctl_offs = SPM_MFG_PWR_CON,
+		.sram_pdn_bits = GENMASK(13, 8),
+		.sram_pdn_ack_bits = GENMASK(21, 16),
+		.clk_id = MT8173_CLK_NONE,
+		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
+			MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+			MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+			MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
+	},
+};
+
+#define NUM_DOMAINS	ARRAY_SIZE(scp_domain_data)
+
+struct scp;
+
+struct scp_domain {
+	struct generic_pm_domain genpd;
+	struct scp *scp;
+	struct clk *clk;
+	u32 sta_mask;
+	void __iomem *ctl_addr;
+	u32 sram_pdn_bits;
+	u32 sram_pdn_ack_bits;
+	u32 bus_prot_mask;
+};
+
+struct scp {
+	struct scp_domain domains[NUM_DOMAINS];
+	struct genpd_onecell_data pd_data;
+	struct device *dev;
+	void __iomem *base;
+	struct regmap *infracfg;
+	struct clk *clk[MT8173_CLK_MAX];
+};
+
+static int scpsys_domain_is_on(struct scp_domain *scpd)
+{
+	struct scp *scp = scpd->scp;
+
+	u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
+	u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
+
+	/*
+	 * A domain is on when both status bits are set. If only one is set
+	 * return an error. This happens while powering up a domain
+	 */
+
+	if (status && status2)
+		return true;
+	if (!status && !status2)
+		return false;
+
+	return -EINVAL;
+}
+
+static int scpsys_power_on(struct generic_pm_domain *genpd)
+{
+	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+	struct scp *scp = scpd->scp;
+	unsigned long timeout;
+	bool expired;
+	void __iomem *ctl_addr = scpd->ctl_addr;
+	u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
+	u32 val;
+	int ret;
+
+	if (scpd->clk) {
+		ret = clk_prepare_enable(scpd->clk);
+		if (ret)
+			return ret;
+	}
+
+	val = readl(ctl_addr);
+	val |= PWR_ON_BIT;
+	writel(val, ctl_addr);
+	val |= PWR_ON_2ND_BIT;
+	writel(val, ctl_addr);
+
+	/* wait until PWR_ACK = 1 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (1) {
+		ret = scpsys_domain_is_on(scpd);
+		if (ret > 0)
+			break;
+
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	val &= ~PWR_CLK_DIS_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_ISO_BIT;
+	writel(val, ctl_addr);
+
+	val |= PWR_RST_B_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~scpd->sram_pdn_bits;
+	writel(val, ctl_addr);
+
+	/* wait until SRAM_PDN_ACK all 0 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
+
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	if (scpd->bus_prot_mask) {
+		ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
+				scpd->bus_prot_mask);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+out:
+	dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
+
+	return ret;
+}
+
+static int scpsys_power_off(struct generic_pm_domain *genpd)
+{
+	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+	struct scp *scp = scpd->scp;
+	unsigned long timeout;
+	bool expired;
+	void __iomem *ctl_addr = scpd->ctl_addr;
+	u32 pdn_ack = scpd->sram_pdn_ack_bits;
+	u32 val;
+	int ret;
+
+	if (scpd->bus_prot_mask) {
+		ret = mtk_infracfg_set_bus_protection(scp->infracfg,
+				scpd->bus_prot_mask);
+		if (ret)
+			return ret;
+	}
+
+	val = readl(ctl_addr);
+	val |= scpd->sram_pdn_bits;
+	writel(val, ctl_addr);
+
+	/* wait until SRAM_PDN_ACK all 1 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	val |= PWR_ISO_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_RST_B_BIT;
+	writel(val, ctl_addr);
+
+	val |= PWR_CLK_DIS_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_ON_BIT;
+	writel(val, ctl_addr);
+
+	val &= ~PWR_ON_2ND_BIT;
+	writel(val, ctl_addr);
+
+	/* wait until PWR_ACK = 0 */
+	timeout = jiffies + HZ;
+	expired = false;
+	while (1) {
+		ret = scpsys_domain_is_on(scpd);
+		if (ret == 0)
+			break;
+
+		if (expired) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		cpu_relax();
+
+		if (time_after(jiffies, timeout))
+			expired = true;
+	}
+
+	if (scpd->clk)
+		clk_disable_unprepare(scpd->clk);
+
+	return 0;
+
+out:
+	dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
+
+	return ret;
+}
+
+static int __init scpsys_probe(struct platform_device *pdev)
+{
+	struct genpd_onecell_data *pd_data;
+	struct resource *res;
+	int i, ret;
+	struct scp *scp;
+
+	scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
+	if (!scp)
+		return -ENOMEM;
+
+	scp->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	scp->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(scp->base))
+		return PTR_ERR(scp->base);
+
+	pd_data = &scp->pd_data;
+
+	pd_data->domains = devm_kzalloc(&pdev->dev,
+			sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
+	if (!pd_data->domains)
+		return -ENOMEM;
+
+	scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
+	if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
+		dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
+				PTR_ERR(scp->clk[MT8173_CLK_MM]));
+		return PTR_ERR(scp->clk[MT8173_CLK_MM]);
+	}
+
+	scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
+	if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
+		dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
+				PTR_ERR(scp->clk[MT8173_CLK_MFG]));
+		return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
+	}
+
+	scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+			"infracfg");
+	if (IS_ERR(scp->infracfg)) {
+		dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
+				PTR_ERR(scp->infracfg));
+		return PTR_ERR(scp->infracfg);
+	}
+
+	pd_data->num_domains = NUM_DOMAINS;
+
+	for (i = 0; i < NUM_DOMAINS; i++) {
+		struct scp_domain *scpd = &scp->domains[i];
+		struct generic_pm_domain *genpd = &scpd->genpd;
+		const struct scp_domain_data *data = &scp_domain_data[i];
+
+		pd_data->domains[i] = genpd;
+		scpd->scp = scp;
+
+		scpd->sta_mask = data->sta_mask;
+		scpd->ctl_addr = scp->base + data->ctl_offs;
+		scpd->sram_pdn_bits = data->sram_pdn_bits;
+		scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
+		scpd->bus_prot_mask = data->bus_prot_mask;
+		if (data->clk_id != MT8173_CLK_NONE)
+			scpd->clk = scp->clk[data->clk_id];
+
+		genpd->name = data->name;
+		genpd->power_off = scpsys_power_off;
+		genpd->power_on = scpsys_power_on;
+
+		/*
+		 * Initially turn on all domains to make the domains usable
+		 * with !CONFIG_PM and to get the hardware in sync with the
+		 * software.  The unused domains will be switched off during
+		 * late_init time.
+		 */
+		genpd->power_on(genpd);
+
+		pm_genpd_init(genpd, NULL, false);
+	}
+
+	/*
+	 * We are not allowed to fail here since there is no way to unregister
+	 * a power domain. Once registered above we have to keep the domains
+	 * valid.
+	 */
+
+	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
+		pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
+	if (ret && IS_ENABLED(CONFIG_PM))
+		dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
+
+	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
+		pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
+	if (ret && IS_ENABLED(CONFIG_PM))
+		dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
+
+	ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
+	if (ret)
+		dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
+
+	return 0;
+}
+
+static const struct of_device_id of_scpsys_match_tbl[] = {
+	{
+		.compatible = "mediatek,mt8173-scpsys",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver scpsys_drv = {
+	.driver = {
+		.name = "mtk-scpsys",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(of_scpsys_match_tbl),
+	},
+};
+
+module_platform_driver_probe(scpsys_drv, scpsys_probe);
diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h
new file mode 100644
index 0000000..b34cee9
--- /dev/null
+++ b/include/dt-bindings/power/mt8173-power.h
@@ -0,0 +1,15 @@
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8173_POWER_DOMAIN_VDEC	0
+#define MT8173_POWER_DOMAIN_VENC	1
+#define MT8173_POWER_DOMAIN_ISP		2
+#define MT8173_POWER_DOMAIN_MM		3
+#define MT8173_POWER_DOMAIN_VENC_LT	4
+#define MT8173_POWER_DOMAIN_AUDIO	5
+#define MT8173_POWER_DOMAIN_USB		6
+#define MT8173_POWER_DOMAIN_MFG_ASYNC	7
+#define MT8173_POWER_DOMAIN_MFG_2D	8
+#define MT8173_POWER_DOMAIN_MFG		9
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
-- 
2.1.4

[PATCH 4/5] ARM64: MediaTek: Add generic pm domain support

[Sascha Hauer]

Enable support for generic power domains in the config.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7796af4..ba8469c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -185,6 +185,7 @@ config ARCH_MEDIATEK
 	bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
 	select ARM_GIC
 	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM
 	help
 	  Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
 
-- 
2.1.4

[PATCH 4/5] ARM64: MediaTek: Add generic pm domain support

[Sascha Hauer]

Enable support for generic power domains in the config.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7796af4..ba8469c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -185,6 +185,7 @@ config ARCH_MEDIATEK
 	bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
 	select ARM_GIC
 	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM
 	help
 	  Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
 
-- 
2.1.4

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

This adds the SCPSYS device node to the MT8173 dtsi file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..12430f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,16 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		scpsys: scpsys@10006000 {
+			compatible = "mediatek,mt8173-scpsys";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&clk26m>,
+				 <&topckgen CLK_TOP_MM_SEL>;
+			clock-names = "mfg", "mm";
+			infracfg = <&infracfg>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
2.1.4

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

This adds the SCPSYS device node to the MT8173 dtsi file.

Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..12430f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,16 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		scpsys: scpsys@10006000 {
+			compatible = "mediatek,mt8173-scpsys";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&clk26m>,
+				 <&topckgen CLK_TOP_MM_SEL>;
+			clock-names = "mfg", "mm";
+			infracfg = <&infracfg>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
2.1.4

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[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

This adds the SCPSYS device node to the MT8173 dtsi file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..12430f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,16 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		scpsys: scpsys at 10006000 {
+			compatible = "mediatek,mt8173-scpsys";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&clk26m>,
+				 <&topckgen CLK_TOP_MM_SEL>;
+			clock-names = "mfg", "mm";
+			infracfg = <&infracfg>;
+		};
+
 		sysirq: intpol-controller at 10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
2.1.4

Re: [PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Matthias Brugger]

2015-06-09 10:47 GMT+02:00 Sascha Hauer <s.hauer@pengutronix.de>:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency scaling (DVFS), interrupt
> filter and lowlevel sleep control. The System Power Manager (SPM)
> inside the SCPSYS is for the MTCMOS power domain control.
>
> For now this driver only adds power domain support, the more
> advanced features are not yet supported. The driver implements
> the generic PM domain device tree bindings, the first user will
> most likely be the Mediatek AFE audio driver.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/soc/mediatek/Kconfig             |   9 +
>  drivers/soc/mediatek/Makefile            |   1 +
>  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
>  include/dt-bindings/power/mt8173-power.h |  15 +
>  4 files changed, 515 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
>  create mode 100644 include/dt-bindings/power/mt8173-power.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index e4f37a3..9a61b54 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
>           Say yes here to add support for MediaTek PMIC Wrapper found
>           on different MediaTek SoCs. The PMIC wrapper is a proprietary
>           hardware to connect the PMIC.
> +
> +config MTK_SCPSYS
> +       bool "MediaTek SCPSYS Support"
> +       depends on ARCH_MEDIATEK || COMPILE_TEST
> +       select REGMAP
> +       select MTK_INFRACFG
> +       help
> +         Say yes here to add support for the MediaTek SCPSYS power domain
> +         driver.
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 3fa940f..12998b0 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> new file mode 100644
> index 0000000..b9eed37
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -0,0 +1,490 @@
> +/*
> + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/mediatek/infracfg.h>
> +#include <dt-bindings/power/mt8173-power.h>
> +
> +#define SPM_VDE_PWR_CON                        0x0210
> +#define SPM_MFG_PWR_CON                        0x0214
> +#define SPM_VEN_PWR_CON                        0x0230
> +#define SPM_ISP_PWR_CON                        0x0238
> +#define SPM_DIS_PWR_CON                        0x023c
> +#define SPM_VEN2_PWR_CON               0x0298
> +#define SPM_AUDIO_PWR_CON              0x029c
> +#define SPM_MFG_2D_PWR_CON             0x02c0
> +#define SPM_MFG_ASYNC_PWR_CON          0x02c4
> +#define SPM_USB_PWR_CON                        0x02cc
> +#define SPM_PWR_STATUS                 0x060c
> +#define SPM_PWR_STATUS_2ND             0x0610
> +
> +#define PWR_RST_B_BIT                  BIT(0)
> +#define PWR_ISO_BIT                    BIT(1)
> +#define PWR_ON_BIT                     BIT(2)
> +#define PWR_ON_2ND_BIT                 BIT(3)
> +#define PWR_CLK_DIS_BIT                        BIT(4)
> +
> +#define PWR_STATUS_DISP                        BIT(3)
> +#define PWR_STATUS_MFG                 BIT(4)
> +#define PWR_STATUS_ISP                 BIT(5)
> +#define PWR_STATUS_VDEC                        BIT(7)
> +#define PWR_STATUS_VENC_LT             BIT(20)
> +#define PWR_STATUS_VENC                        BIT(21)
> +#define PWR_STATUS_MFG_2D              BIT(22)
> +#define PWR_STATUS_MFG_ASYNC           BIT(23)
> +#define PWR_STATUS_AUDIO               BIT(24)
> +#define PWR_STATUS_USB                 BIT(25)
> +
> +enum clk_id {
> +       MT8173_CLK_NONE,
> +       MT8173_CLK_MM,
> +       MT8173_CLK_MFG,
> +       MT8173_CLK_MAX = MT8173_CLK_MFG,
> +};
> +
> +struct scp_domain_data {
> +       const char *name;
> +       u32 sta_mask;
> +       int ctl_offs;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +       enum clk_id clk_id;
> +};
> +
> +static const struct scp_domain_data scp_domain_data[] __initconst = {
> +       [MT8173_POWER_DOMAIN_VDEC] = {
> +               .name = "vdec",
> +               .sta_mask = PWR_STATUS_VDEC,
> +               .ctl_offs = SPM_VDE_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC] = {
> +               .name = "venc",
> +               .sta_mask = PWR_STATUS_VENC,
> +               .ctl_offs = SPM_VEN_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_ISP] = {
> +               .name = "isp",
> +               .sta_mask = PWR_STATUS_ISP,
> +               .ctl_offs = SPM_ISP_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_MM] = {
> +               .name = "mm",
> +               .sta_mask = PWR_STATUS_DISP,
> +               .ctl_offs = SPM_DIS_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MM_M1,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC_LT] = {
> +               .name = "venc_lt",
> +               .sta_mask = PWR_STATUS_VENC_LT,
> +               .ctl_offs = SPM_VEN2_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_AUDIO] = {
> +               .name = "audio",
> +               .sta_mask = PWR_STATUS_AUDIO,
> +               .ctl_offs = SPM_AUDIO_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_USB] = {
> +               .name = "usb",
> +               .sta_mask = PWR_STATUS_USB,
> +               .ctl_offs = SPM_USB_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> +               .name = "mfg_async",
> +               .sta_mask = PWR_STATUS_MFG_ASYNC,
> +               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = 0,
> +               .clk_id = MT8173_CLK_MFG,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_2D] = {
> +               .name = "mfg_2d",
> +               .sta_mask = PWR_STATUS_MFG_2D,
> +               .ctl_offs = SPM_MFG_2D_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG] = {
> +               .name = "mfg",
> +               .sta_mask = PWR_STATUS_MFG,
> +               .ctl_offs = SPM_MFG_PWR_CON,
> +               .sram_pdn_bits = GENMASK(13, 8),
> +               .sram_pdn_ack_bits = GENMASK(21, 16),
> +               .clk_id = MT8173_CLK_NONE,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> +       },
> +};
> +
> +#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
> +
> +struct scp;
> +
> +struct scp_domain {
> +       struct generic_pm_domain genpd;
> +       struct scp *scp;
> +       struct clk *clk;
> +       u32 sta_mask;
> +       void __iomem *ctl_addr;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +};
> +
> +struct scp {
> +       struct scp_domain domains[NUM_DOMAINS];
> +       struct genpd_onecell_data pd_data;
> +       struct device *dev;
> +       void __iomem *base;
> +       struct regmap *infracfg;
> +       struct clk *clk[MT8173_CLK_MAX];
> +};
> +
> +static int scpsys_domain_is_on(struct scp_domain *scpd)
> +{
> +       struct scp *scp = scpd->scp;
> +
> +       u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
> +       u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
> +
> +       /*
> +        * A domain is on when both status bits are set. If only one is set
> +        * return an error. This happens while powering up a domain
> +        */
> +
> +       if (status && status2)
> +               return true;
> +       if (!status && !status2)
> +               return false;
> +
> +       return -EINVAL;
> +}
> +
> +static int scpsys_power_on(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->clk) {
> +               ret = clk_prepare_enable(scpd->clk);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +       val |= PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret > 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val &= ~PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +out:
> +       dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int scpsys_power_off(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val |= PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret == 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->clk)
> +               clk_disable_unprepare(scpd->clk);
> +
> +       return 0;
> +
> +out:
> +       dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int __init scpsys_probe(struct platform_device *pdev)
> +{
> +       struct genpd_onecell_data *pd_data;
> +       struct resource *res;
> +       int i, ret;
> +       struct scp *scp;
> +
> +       scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> +       if (!scp)
> +               return -ENOMEM;
> +
> +       scp->dev = &pdev->dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       scp->base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(scp->base))
> +               return PTR_ERR(scp->base);
> +
> +       pd_data = &scp->pd_data;
> +
> +       pd_data->domains = devm_kzalloc(&pdev->dev,
> +                       sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
> +       if (!pd_data->domains)
> +               return -ENOMEM;
> +
> +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));
> +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> +       }
> +
> +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));
> +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> +       }
> +
> +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +                       "infracfg");
> +       if (IS_ERR(scp->infracfg)) {
> +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> +                               PTR_ERR(scp->infracfg));
> +               return PTR_ERR(scp->infracfg);
> +       }
> +
> +       pd_data->num_domains = NUM_DOMAINS;
> +
> +       for (i = 0; i < NUM_DOMAINS; i++) {
> +               struct scp_domain *scpd = &scp->domains[i];
> +               struct generic_pm_domain *genpd = &scpd->genpd;
> +               const struct scp_domain_data *data = &scp_domain_data[i];
> +
> +               pd_data->domains[i] = genpd;
> +               scpd->scp = scp;
> +
> +               scpd->sta_mask = data->sta_mask;
> +               scpd->ctl_addr = scp->base + data->ctl_offs;
> +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> +               scpd->bus_prot_mask = data->bus_prot_mask;
> +               if (data->clk_id != MT8173_CLK_NONE)
> +                       scpd->clk = scp->clk[data->clk_id];
> +
> +               genpd->name = data->name;
> +               genpd->power_off = scpsys_power_off;
> +               genpd->power_on = scpsys_power_on;
> +
> +               /*
> +                * Initially turn on all domains to make the domains usable
> +                * with !CONFIG_PM and to get the hardware in sync with the
> +                * software.  The unused domains will be switched off during
> +                * late_init time.
> +                */
> +               genpd->power_on(genpd);
> +
> +               pm_genpd_init(genpd, NULL, false);
> +       }
> +
> +       /*
> +        * We are not allowed to fail here since there is no way to unregister
> +        * a power domain. Once registered above we have to keep the domains
> +        * valid.
> +        */
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
> +       if (ret)
> +               dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id of_scpsys_match_tbl[] = {
> +       {
> +               .compatible = "mediatek,mt8173-scpsys",
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver scpsys_drv = {
> +       .driver = {
> +               .name = "mtk-scpsys",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> +       },
> +};
> +
> +module_platform_driver_probe(scpsys_drv, scpsys_probe);

I saw builtin_platform_driver_probe() is in linux-next, so I suppose
it is fine to change this.
Apart from that the series look good to me.

Thanks,
Matthias

Re: [PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Matthias Brugger]

2015-06-09 10:47 GMT+02:00 Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency scaling (DVFS), interrupt
> filter and lowlevel sleep control. The System Power Manager (SPM)
> inside the SCPSYS is for the MTCMOS power domain control.
>
> For now this driver only adds power domain support, the more
> advanced features are not yet supported. The driver implements
> the generic PM domain device tree bindings, the first user will
> most likely be the Mediatek AFE audio driver.
>
> Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
>  drivers/soc/mediatek/Kconfig             |   9 +
>  drivers/soc/mediatek/Makefile            |   1 +
>  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
>  include/dt-bindings/power/mt8173-power.h |  15 +
>  4 files changed, 515 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
>  create mode 100644 include/dt-bindings/power/mt8173-power.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index e4f37a3..9a61b54 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
>           Say yes here to add support for MediaTek PMIC Wrapper found
>           on different MediaTek SoCs. The PMIC wrapper is a proprietary
>           hardware to connect the PMIC.
> +
> +config MTK_SCPSYS
> +       bool "MediaTek SCPSYS Support"
> +       depends on ARCH_MEDIATEK || COMPILE_TEST
> +       select REGMAP
> +       select MTK_INFRACFG
> +       help
> +         Say yes here to add support for the MediaTek SCPSYS power domain
> +         driver.
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 3fa940f..12998b0 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> new file mode 100644
> index 0000000..b9eed37
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -0,0 +1,490 @@
> +/*
> + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/mediatek/infracfg.h>
> +#include <dt-bindings/power/mt8173-power.h>
> +
> +#define SPM_VDE_PWR_CON                        0x0210
> +#define SPM_MFG_PWR_CON                        0x0214
> +#define SPM_VEN_PWR_CON                        0x0230
> +#define SPM_ISP_PWR_CON                        0x0238
> +#define SPM_DIS_PWR_CON                        0x023c
> +#define SPM_VEN2_PWR_CON               0x0298
> +#define SPM_AUDIO_PWR_CON              0x029c
> +#define SPM_MFG_2D_PWR_CON             0x02c0
> +#define SPM_MFG_ASYNC_PWR_CON          0x02c4
> +#define SPM_USB_PWR_CON                        0x02cc
> +#define SPM_PWR_STATUS                 0x060c
> +#define SPM_PWR_STATUS_2ND             0x0610
> +
> +#define PWR_RST_B_BIT                  BIT(0)
> +#define PWR_ISO_BIT                    BIT(1)
> +#define PWR_ON_BIT                     BIT(2)
> +#define PWR_ON_2ND_BIT                 BIT(3)
> +#define PWR_CLK_DIS_BIT                        BIT(4)
> +
> +#define PWR_STATUS_DISP                        BIT(3)
> +#define PWR_STATUS_MFG                 BIT(4)
> +#define PWR_STATUS_ISP                 BIT(5)
> +#define PWR_STATUS_VDEC                        BIT(7)
> +#define PWR_STATUS_VENC_LT             BIT(20)
> +#define PWR_STATUS_VENC                        BIT(21)
> +#define PWR_STATUS_MFG_2D              BIT(22)
> +#define PWR_STATUS_MFG_ASYNC           BIT(23)
> +#define PWR_STATUS_AUDIO               BIT(24)
> +#define PWR_STATUS_USB                 BIT(25)
> +
> +enum clk_id {
> +       MT8173_CLK_NONE,
> +       MT8173_CLK_MM,
> +       MT8173_CLK_MFG,
> +       MT8173_CLK_MAX = MT8173_CLK_MFG,
> +};
> +
> +struct scp_domain_data {
> +       const char *name;
> +       u32 sta_mask;
> +       int ctl_offs;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +       enum clk_id clk_id;
> +};
> +
> +static const struct scp_domain_data scp_domain_data[] __initconst = {
> +       [MT8173_POWER_DOMAIN_VDEC] = {
> +               .name = "vdec",
> +               .sta_mask = PWR_STATUS_VDEC,
> +               .ctl_offs = SPM_VDE_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC] = {
> +               .name = "venc",
> +               .sta_mask = PWR_STATUS_VENC,
> +               .ctl_offs = SPM_VEN_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_ISP] = {
> +               .name = "isp",
> +               .sta_mask = PWR_STATUS_ISP,
> +               .ctl_offs = SPM_ISP_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_MM] = {
> +               .name = "mm",
> +               .sta_mask = PWR_STATUS_DISP,
> +               .ctl_offs = SPM_DIS_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MM_M1,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC_LT] = {
> +               .name = "venc_lt",
> +               .sta_mask = PWR_STATUS_VENC_LT,
> +               .ctl_offs = SPM_VEN2_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_AUDIO] = {
> +               .name = "audio",
> +               .sta_mask = PWR_STATUS_AUDIO,
> +               .ctl_offs = SPM_AUDIO_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_USB] = {
> +               .name = "usb",
> +               .sta_mask = PWR_STATUS_USB,
> +               .ctl_offs = SPM_USB_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> +               .name = "mfg_async",
> +               .sta_mask = PWR_STATUS_MFG_ASYNC,
> +               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = 0,
> +               .clk_id = MT8173_CLK_MFG,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_2D] = {
> +               .name = "mfg_2d",
> +               .sta_mask = PWR_STATUS_MFG_2D,
> +               .ctl_offs = SPM_MFG_2D_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG] = {
> +               .name = "mfg",
> +               .sta_mask = PWR_STATUS_MFG,
> +               .ctl_offs = SPM_MFG_PWR_CON,
> +               .sram_pdn_bits = GENMASK(13, 8),
> +               .sram_pdn_ack_bits = GENMASK(21, 16),
> +               .clk_id = MT8173_CLK_NONE,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> +       },
> +};
> +
> +#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
> +
> +struct scp;
> +
> +struct scp_domain {
> +       struct generic_pm_domain genpd;
> +       struct scp *scp;
> +       struct clk *clk;
> +       u32 sta_mask;
> +       void __iomem *ctl_addr;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +};
> +
> +struct scp {
> +       struct scp_domain domains[NUM_DOMAINS];
> +       struct genpd_onecell_data pd_data;
> +       struct device *dev;
> +       void __iomem *base;
> +       struct regmap *infracfg;
> +       struct clk *clk[MT8173_CLK_MAX];
> +};
> +
> +static int scpsys_domain_is_on(struct scp_domain *scpd)
> +{
> +       struct scp *scp = scpd->scp;
> +
> +       u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
> +       u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
> +
> +       /*
> +        * A domain is on when both status bits are set. If only one is set
> +        * return an error. This happens while powering up a domain
> +        */
> +
> +       if (status && status2)
> +               return true;
> +       if (!status && !status2)
> +               return false;
> +
> +       return -EINVAL;
> +}
> +
> +static int scpsys_power_on(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->clk) {
> +               ret = clk_prepare_enable(scpd->clk);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +       val |= PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret > 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val &= ~PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +out:
> +       dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int scpsys_power_off(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val |= PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret == 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->clk)
> +               clk_disable_unprepare(scpd->clk);
> +
> +       return 0;
> +
> +out:
> +       dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int __init scpsys_probe(struct platform_device *pdev)
> +{
> +       struct genpd_onecell_data *pd_data;
> +       struct resource *res;
> +       int i, ret;
> +       struct scp *scp;
> +
> +       scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> +       if (!scp)
> +               return -ENOMEM;
> +
> +       scp->dev = &pdev->dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       scp->base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(scp->base))
> +               return PTR_ERR(scp->base);
> +
> +       pd_data = &scp->pd_data;
> +
> +       pd_data->domains = devm_kzalloc(&pdev->dev,
> +                       sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
> +       if (!pd_data->domains)
> +               return -ENOMEM;
> +
> +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));
> +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> +       }
> +
> +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));
> +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> +       }
> +
> +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +                       "infracfg");
> +       if (IS_ERR(scp->infracfg)) {
> +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> +                               PTR_ERR(scp->infracfg));
> +               return PTR_ERR(scp->infracfg);
> +       }
> +
> +       pd_data->num_domains = NUM_DOMAINS;
> +
> +       for (i = 0; i < NUM_DOMAINS; i++) {
> +               struct scp_domain *scpd = &scp->domains[i];
> +               struct generic_pm_domain *genpd = &scpd->genpd;
> +               const struct scp_domain_data *data = &scp_domain_data[i];
> +
> +               pd_data->domains[i] = genpd;
> +               scpd->scp = scp;
> +
> +               scpd->sta_mask = data->sta_mask;
> +               scpd->ctl_addr = scp->base + data->ctl_offs;
> +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> +               scpd->bus_prot_mask = data->bus_prot_mask;
> +               if (data->clk_id != MT8173_CLK_NONE)
> +                       scpd->clk = scp->clk[data->clk_id];
> +
> +               genpd->name = data->name;
> +               genpd->power_off = scpsys_power_off;
> +               genpd->power_on = scpsys_power_on;
> +
> +               /*
> +                * Initially turn on all domains to make the domains usable
> +                * with !CONFIG_PM and to get the hardware in sync with the
> +                * software.  The unused domains will be switched off during
> +                * late_init time.
> +                */
> +               genpd->power_on(genpd);
> +
> +               pm_genpd_init(genpd, NULL, false);
> +       }
> +
> +       /*
> +        * We are not allowed to fail here since there is no way to unregister
> +        * a power domain. Once registered above we have to keep the domains
> +        * valid.
> +        */
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
> +       if (ret)
> +               dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id of_scpsys_match_tbl[] = {
> +       {
> +               .compatible = "mediatek,mt8173-scpsys",
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver scpsys_drv = {
> +       .driver = {
> +               .name = "mtk-scpsys",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> +       },
> +};
> +
> +module_platform_driver_probe(scpsys_drv, scpsys_probe);

I saw builtin_platform_driver_probe() is in linux-next, so I suppose
it is fine to change this.
Apart from that the series look good to me.

Thanks,
Matthias
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[PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Matthias Brugger]

2015-06-09 10:47 GMT+02:00 Sascha Hauer <s.hauer@pengutronix.de>:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency scaling (DVFS), interrupt
> filter and lowlevel sleep control. The System Power Manager (SPM)
> inside the SCPSYS is for the MTCMOS power domain control.
>
> For now this driver only adds power domain support, the more
> advanced features are not yet supported. The driver implements
> the generic PM domain device tree bindings, the first user will
> most likely be the Mediatek AFE audio driver.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/soc/mediatek/Kconfig             |   9 +
>  drivers/soc/mediatek/Makefile            |   1 +
>  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
>  include/dt-bindings/power/mt8173-power.h |  15 +
>  4 files changed, 515 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
>  create mode 100644 include/dt-bindings/power/mt8173-power.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index e4f37a3..9a61b54 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
>           Say yes here to add support for MediaTek PMIC Wrapper found
>           on different MediaTek SoCs. The PMIC wrapper is a proprietary
>           hardware to connect the PMIC.
> +
> +config MTK_SCPSYS
> +       bool "MediaTek SCPSYS Support"
> +       depends on ARCH_MEDIATEK || COMPILE_TEST
> +       select REGMAP
> +       select MTK_INFRACFG
> +       help
> +         Say yes here to add support for the MediaTek SCPSYS power domain
> +         driver.
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 3fa940f..12998b0 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> new file mode 100644
> index 0000000..b9eed37
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -0,0 +1,490 @@
> +/*
> + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/mediatek/infracfg.h>
> +#include <dt-bindings/power/mt8173-power.h>
> +
> +#define SPM_VDE_PWR_CON                        0x0210
> +#define SPM_MFG_PWR_CON                        0x0214
> +#define SPM_VEN_PWR_CON                        0x0230
> +#define SPM_ISP_PWR_CON                        0x0238
> +#define SPM_DIS_PWR_CON                        0x023c
> +#define SPM_VEN2_PWR_CON               0x0298
> +#define SPM_AUDIO_PWR_CON              0x029c
> +#define SPM_MFG_2D_PWR_CON             0x02c0
> +#define SPM_MFG_ASYNC_PWR_CON          0x02c4
> +#define SPM_USB_PWR_CON                        0x02cc
> +#define SPM_PWR_STATUS                 0x060c
> +#define SPM_PWR_STATUS_2ND             0x0610
> +
> +#define PWR_RST_B_BIT                  BIT(0)
> +#define PWR_ISO_BIT                    BIT(1)
> +#define PWR_ON_BIT                     BIT(2)
> +#define PWR_ON_2ND_BIT                 BIT(3)
> +#define PWR_CLK_DIS_BIT                        BIT(4)
> +
> +#define PWR_STATUS_DISP                        BIT(3)
> +#define PWR_STATUS_MFG                 BIT(4)
> +#define PWR_STATUS_ISP                 BIT(5)
> +#define PWR_STATUS_VDEC                        BIT(7)
> +#define PWR_STATUS_VENC_LT             BIT(20)
> +#define PWR_STATUS_VENC                        BIT(21)
> +#define PWR_STATUS_MFG_2D              BIT(22)
> +#define PWR_STATUS_MFG_ASYNC           BIT(23)
> +#define PWR_STATUS_AUDIO               BIT(24)
> +#define PWR_STATUS_USB                 BIT(25)
> +
> +enum clk_id {
> +       MT8173_CLK_NONE,
> +       MT8173_CLK_MM,
> +       MT8173_CLK_MFG,
> +       MT8173_CLK_MAX = MT8173_CLK_MFG,
> +};
> +
> +struct scp_domain_data {
> +       const char *name;
> +       u32 sta_mask;
> +       int ctl_offs;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +       enum clk_id clk_id;
> +};
> +
> +static const struct scp_domain_data scp_domain_data[] __initconst = {
> +       [MT8173_POWER_DOMAIN_VDEC] = {
> +               .name = "vdec",
> +               .sta_mask = PWR_STATUS_VDEC,
> +               .ctl_offs = SPM_VDE_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC] = {
> +               .name = "venc",
> +               .sta_mask = PWR_STATUS_VENC,
> +               .ctl_offs = SPM_VEN_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_ISP] = {
> +               .name = "isp",
> +               .sta_mask = PWR_STATUS_ISP,
> +               .ctl_offs = SPM_ISP_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_MM] = {
> +               .name = "mm",
> +               .sta_mask = PWR_STATUS_DISP,
> +               .ctl_offs = SPM_DIS_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MM_M1,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC_LT] = {
> +               .name = "venc_lt",
> +               .sta_mask = PWR_STATUS_VENC_LT,
> +               .ctl_offs = SPM_VEN2_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_AUDIO] = {
> +               .name = "audio",
> +               .sta_mask = PWR_STATUS_AUDIO,
> +               .ctl_offs = SPM_AUDIO_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_USB] = {
> +               .name = "usb",
> +               .sta_mask = PWR_STATUS_USB,
> +               .ctl_offs = SPM_USB_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> +               .name = "mfg_async",
> +               .sta_mask = PWR_STATUS_MFG_ASYNC,
> +               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = 0,
> +               .clk_id = MT8173_CLK_MFG,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_2D] = {
> +               .name = "mfg_2d",
> +               .sta_mask = PWR_STATUS_MFG_2D,
> +               .ctl_offs = SPM_MFG_2D_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG] = {
> +               .name = "mfg",
> +               .sta_mask = PWR_STATUS_MFG,
> +               .ctl_offs = SPM_MFG_PWR_CON,
> +               .sram_pdn_bits = GENMASK(13, 8),
> +               .sram_pdn_ack_bits = GENMASK(21, 16),
> +               .clk_id = MT8173_CLK_NONE,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> +       },
> +};
> +
> +#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
> +
> +struct scp;
> +
> +struct scp_domain {
> +       struct generic_pm_domain genpd;
> +       struct scp *scp;
> +       struct clk *clk;
> +       u32 sta_mask;
> +       void __iomem *ctl_addr;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +};
> +
> +struct scp {
> +       struct scp_domain domains[NUM_DOMAINS];
> +       struct genpd_onecell_data pd_data;
> +       struct device *dev;
> +       void __iomem *base;
> +       struct regmap *infracfg;
> +       struct clk *clk[MT8173_CLK_MAX];
> +};
> +
> +static int scpsys_domain_is_on(struct scp_domain *scpd)
> +{
> +       struct scp *scp = scpd->scp;
> +
> +       u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
> +       u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
> +
> +       /*
> +        * A domain is on when both status bits are set. If only one is set
> +        * return an error. This happens while powering up a domain
> +        */
> +
> +       if (status && status2)
> +               return true;
> +       if (!status && !status2)
> +               return false;
> +
> +       return -EINVAL;
> +}
> +
> +static int scpsys_power_on(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->clk) {
> +               ret = clk_prepare_enable(scpd->clk);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +       val |= PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret > 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val &= ~PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +out:
> +       dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int scpsys_power_off(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val |= PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret == 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->clk)
> +               clk_disable_unprepare(scpd->clk);
> +
> +       return 0;
> +
> +out:
> +       dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int __init scpsys_probe(struct platform_device *pdev)
> +{
> +       struct genpd_onecell_data *pd_data;
> +       struct resource *res;
> +       int i, ret;
> +       struct scp *scp;
> +
> +       scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> +       if (!scp)
> +               return -ENOMEM;
> +
> +       scp->dev = &pdev->dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       scp->base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(scp->base))
> +               return PTR_ERR(scp->base);
> +
> +       pd_data = &scp->pd_data;
> +
> +       pd_data->domains = devm_kzalloc(&pdev->dev,
> +                       sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
> +       if (!pd_data->domains)
> +               return -ENOMEM;
> +
> +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));
> +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> +       }
> +
> +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));
> +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> +       }
> +
> +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +                       "infracfg");
> +       if (IS_ERR(scp->infracfg)) {
> +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> +                               PTR_ERR(scp->infracfg));
> +               return PTR_ERR(scp->infracfg);
> +       }
> +
> +       pd_data->num_domains = NUM_DOMAINS;
> +
> +       for (i = 0; i < NUM_DOMAINS; i++) {
> +               struct scp_domain *scpd = &scp->domains[i];
> +               struct generic_pm_domain *genpd = &scpd->genpd;
> +               const struct scp_domain_data *data = &scp_domain_data[i];
> +
> +               pd_data->domains[i] = genpd;
> +               scpd->scp = scp;
> +
> +               scpd->sta_mask = data->sta_mask;
> +               scpd->ctl_addr = scp->base + data->ctl_offs;
> +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> +               scpd->bus_prot_mask = data->bus_prot_mask;
> +               if (data->clk_id != MT8173_CLK_NONE)
> +                       scpd->clk = scp->clk[data->clk_id];
> +
> +               genpd->name = data->name;
> +               genpd->power_off = scpsys_power_off;
> +               genpd->power_on = scpsys_power_on;
> +
> +               /*
> +                * Initially turn on all domains to make the domains usable
> +                * with !CONFIG_PM and to get the hardware in sync with the
> +                * software.  The unused domains will be switched off during
> +                * late_init time.
> +                */
> +               genpd->power_on(genpd);
> +
> +               pm_genpd_init(genpd, NULL, false);
> +       }
> +
> +       /*
> +        * We are not allowed to fail here since there is no way to unregister
> +        * a power domain. Once registered above we have to keep the domains
> +        * valid.
> +        */
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
> +       if (ret)
> +               dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id of_scpsys_match_tbl[] = {
> +       {
> +               .compatible = "mediatek,mt8173-scpsys",
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver scpsys_drv = {
> +       .driver = {
> +               .name = "mtk-scpsys",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> +       },
> +};
> +
> +module_platform_driver_probe(scpsys_drv, scpsys_probe);

I saw builtin_platform_driver_probe() is in linux-next, so I suppose
it is fine to change this.
Apart from that the series look good to me.

Thanks,
Matthias

Re: [PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Ulf Hansson]

On 9 June 2015 at 10:47, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency scaling (DVFS), interrupt
> filter and lowlevel sleep control. The System Power Manager (SPM)
> inside the SCPSYS is for the MTCMOS power domain control.
>
> For now this driver only adds power domain support, the more
> advanced features are not yet supported. The driver implements
> the generic PM domain device tree bindings, the first user will
> most likely be the Mediatek AFE audio driver.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/soc/mediatek/Kconfig             |   9 +
>  drivers/soc/mediatek/Makefile            |   1 +
>  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
>  include/dt-bindings/power/mt8173-power.h |  15 +
>  4 files changed, 515 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
>  create mode 100644 include/dt-bindings/power/mt8173-power.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index e4f37a3..9a61b54 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
>           Say yes here to add support for MediaTek PMIC Wrapper found
>           on different MediaTek SoCs. The PMIC wrapper is a proprietary
>           hardware to connect the PMIC.
> +
> +config MTK_SCPSYS
> +       bool "MediaTek SCPSYS Support"
> +       depends on ARCH_MEDIATEK || COMPILE_TEST

How about also depending on "PM" and selecting PM_GENERIC_DOMAINS,
would that work?

> +       select REGMAP
> +       select MTK_INFRACFG
> +       help
> +         Say yes here to add support for the MediaTek SCPSYS power domain
> +         driver.
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 3fa940f..12998b0 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> new file mode 100644
> index 0000000..b9eed37
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -0,0 +1,490 @@
> +/*
> + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/mediatek/infracfg.h>
> +#include <dt-bindings/power/mt8173-power.h>
> +
> +#define SPM_VDE_PWR_CON                        0x0210
> +#define SPM_MFG_PWR_CON                        0x0214
> +#define SPM_VEN_PWR_CON                        0x0230
> +#define SPM_ISP_PWR_CON                        0x0238
> +#define SPM_DIS_PWR_CON                        0x023c
> +#define SPM_VEN2_PWR_CON               0x0298
> +#define SPM_AUDIO_PWR_CON              0x029c
> +#define SPM_MFG_2D_PWR_CON             0x02c0
> +#define SPM_MFG_ASYNC_PWR_CON          0x02c4
> +#define SPM_USB_PWR_CON                        0x02cc
> +#define SPM_PWR_STATUS                 0x060c
> +#define SPM_PWR_STATUS_2ND             0x0610
> +
> +#define PWR_RST_B_BIT                  BIT(0)
> +#define PWR_ISO_BIT                    BIT(1)
> +#define PWR_ON_BIT                     BIT(2)
> +#define PWR_ON_2ND_BIT                 BIT(3)
> +#define PWR_CLK_DIS_BIT                        BIT(4)
> +
> +#define PWR_STATUS_DISP                        BIT(3)
> +#define PWR_STATUS_MFG                 BIT(4)
> +#define PWR_STATUS_ISP                 BIT(5)
> +#define PWR_STATUS_VDEC                        BIT(7)
> +#define PWR_STATUS_VENC_LT             BIT(20)
> +#define PWR_STATUS_VENC                        BIT(21)
> +#define PWR_STATUS_MFG_2D              BIT(22)
> +#define PWR_STATUS_MFG_ASYNC           BIT(23)
> +#define PWR_STATUS_AUDIO               BIT(24)
> +#define PWR_STATUS_USB                 BIT(25)
> +
> +enum clk_id {
> +       MT8173_CLK_NONE,
> +       MT8173_CLK_MM,
> +       MT8173_CLK_MFG,
> +       MT8173_CLK_MAX = MT8173_CLK_MFG,
> +};
> +
> +struct scp_domain_data {
> +       const char *name;
> +       u32 sta_mask;
> +       int ctl_offs;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +       enum clk_id clk_id;
> +};
> +
> +static const struct scp_domain_data scp_domain_data[] __initconst = {
> +       [MT8173_POWER_DOMAIN_VDEC] = {
> +               .name = "vdec",
> +               .sta_mask = PWR_STATUS_VDEC,
> +               .ctl_offs = SPM_VDE_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC] = {
> +               .name = "venc",
> +               .sta_mask = PWR_STATUS_VENC,
> +               .ctl_offs = SPM_VEN_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_ISP] = {
> +               .name = "isp",
> +               .sta_mask = PWR_STATUS_ISP,
> +               .ctl_offs = SPM_ISP_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_MM] = {
> +               .name = "mm",
> +               .sta_mask = PWR_STATUS_DISP,
> +               .ctl_offs = SPM_DIS_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MM_M1,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC_LT] = {
> +               .name = "venc_lt",
> +               .sta_mask = PWR_STATUS_VENC_LT,
> +               .ctl_offs = SPM_VEN2_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_AUDIO] = {
> +               .name = "audio",
> +               .sta_mask = PWR_STATUS_AUDIO,
> +               .ctl_offs = SPM_AUDIO_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_USB] = {
> +               .name = "usb",
> +               .sta_mask = PWR_STATUS_USB,
> +               .ctl_offs = SPM_USB_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> +               .name = "mfg_async",
> +               .sta_mask = PWR_STATUS_MFG_ASYNC,
> +               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = 0,
> +               .clk_id = MT8173_CLK_MFG,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_2D] = {
> +               .name = "mfg_2d",
> +               .sta_mask = PWR_STATUS_MFG_2D,
> +               .ctl_offs = SPM_MFG_2D_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG] = {
> +               .name = "mfg",
> +               .sta_mask = PWR_STATUS_MFG,
> +               .ctl_offs = SPM_MFG_PWR_CON,
> +               .sram_pdn_bits = GENMASK(13, 8),
> +               .sram_pdn_ack_bits = GENMASK(21, 16),
> +               .clk_id = MT8173_CLK_NONE,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> +       },
> +};
> +
> +#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
> +
> +struct scp;
> +
> +struct scp_domain {
> +       struct generic_pm_domain genpd;
> +       struct scp *scp;
> +       struct clk *clk;
> +       u32 sta_mask;
> +       void __iomem *ctl_addr;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +};
> +
> +struct scp {
> +       struct scp_domain domains[NUM_DOMAINS];
> +       struct genpd_onecell_data pd_data;
> +       struct device *dev;
> +       void __iomem *base;
> +       struct regmap *infracfg;
> +       struct clk *clk[MT8173_CLK_MAX];
> +};
> +
> +static int scpsys_domain_is_on(struct scp_domain *scpd)
> +{
> +       struct scp *scp = scpd->scp;
> +
> +       u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
> +       u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
> +
> +       /*
> +        * A domain is on when both status bits are set. If only one is set
> +        * return an error. This happens while powering up a domain
> +        */
> +
> +       if (status && status2)
> +               return true;
> +       if (!status && !status2)
> +               return false;
> +
> +       return -EINVAL;
> +}
> +
> +static int scpsys_power_on(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->clk) {

Shouldn't you check for !IS_ERR(scpd->clk) instead?

> +               ret = clk_prepare_enable(scpd->clk);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +       val |= PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret > 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val &= ~PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +out:

There are no error handling. Especially the clock should be gated.

> +       dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int scpsys_power_off(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val |= PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret == 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->clk)

Shouldn't you check for !IS_ERR(scpd->clk) instead?

> +               clk_disable_unprepare(scpd->clk);
> +
> +       return 0;
> +
> +out:

There are no error handling, isn't that needed?

> +       dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int __init scpsys_probe(struct platform_device *pdev)
> +{
> +       struct genpd_onecell_data *pd_data;
> +       struct resource *res;
> +       int i, ret;
> +       struct scp *scp;
> +
> +       scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> +       if (!scp)
> +               return -ENOMEM;
> +
> +       scp->dev = &pdev->dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       scp->base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(scp->base))
> +               return PTR_ERR(scp->base);
> +
> +       pd_data = &scp->pd_data;
> +
> +       pd_data->domains = devm_kzalloc(&pdev->dev,
> +                       sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
> +       if (!pd_data->domains)
> +               return -ENOMEM;
> +
> +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));

I think a similar error message is already printed by the common clk framework!?

> +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> +       }
> +
> +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));

I think a similar error message is already printed by the common clk framework!?

> +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> +       }
> +
> +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +                       "infracfg");
> +       if (IS_ERR(scp->infracfg)) {
> +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> +                               PTR_ERR(scp->infracfg));
> +               return PTR_ERR(scp->infracfg);
> +       }
> +
> +       pd_data->num_domains = NUM_DOMAINS;
> +
> +       for (i = 0; i < NUM_DOMAINS; i++) {
> +               struct scp_domain *scpd = &scp->domains[i];
> +               struct generic_pm_domain *genpd = &scpd->genpd;
> +               const struct scp_domain_data *data = &scp_domain_data[i];
> +
> +               pd_data->domains[i] = genpd;
> +               scpd->scp = scp;
> +
> +               scpd->sta_mask = data->sta_mask;
> +               scpd->ctl_addr = scp->base + data->ctl_offs;
> +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> +               scpd->bus_prot_mask = data->bus_prot_mask;
> +               if (data->clk_id != MT8173_CLK_NONE)
> +                       scpd->clk = scp->clk[data->clk_id];

This seems odd. Why do you need to have an array of clocks to deal
with this assignment?

I don't find that the struct scp->clk pointer is used but from this
place. Couldn't you just fetch a reference to the clock to a local
struct *clk, without caching it in the struct scp->clk?

> +
> +               genpd->name = data->name;
> +               genpd->power_off = scpsys_power_off;
> +               genpd->power_on = scpsys_power_on;
> +
> +               /*
> +                * Initially turn on all domains to make the domains usable
> +                * with !CONFIG_PM and to get the hardware in sync with the
> +                * software.  The unused domains will be switched off during
> +                * late_init time.
> +                */
> +               genpd->power_on(genpd);
> +
> +               pm_genpd_init(genpd, NULL, false);
> +       }
> +
> +       /*
> +        * We are not allowed to fail here since there is no way to unregister
> +        * a power domain. Once registered above we have to keep the domains
> +        * valid.
> +        */
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
> +       if (ret)
> +               dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id of_scpsys_match_tbl[] = {
> +       {
> +               .compatible = "mediatek,mt8173-scpsys",
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver scpsys_drv = {
> +       .driver = {
> +               .name = "mtk-scpsys",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> +       },
> +};
> +
> +module_platform_driver_probe(scpsys_drv, scpsys_probe);
> diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h
> new file mode 100644
> index 0000000..b34cee9
> --- /dev/null
> +++ b/include/dt-bindings/power/mt8173-power.h
> @@ -0,0 +1,15 @@
> +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
> +#define _DT_BINDINGS_POWER_MT8183_POWER_H
> +
> +#define MT8173_POWER_DOMAIN_VDEC       0
> +#define MT8173_POWER_DOMAIN_VENC       1
> +#define MT8173_POWER_DOMAIN_ISP                2
> +#define MT8173_POWER_DOMAIN_MM         3
> +#define MT8173_POWER_DOMAIN_VENC_LT    4
> +#define MT8173_POWER_DOMAIN_AUDIO      5
> +#define MT8173_POWER_DOMAIN_USB                6
> +#define MT8173_POWER_DOMAIN_MFG_ASYNC  7
> +#define MT8173_POWER_DOMAIN_MFG_2D     8
> +#define MT8173_POWER_DOMAIN_MFG                9
> +
> +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
> --
> 2.1.4

Kind regards
Uffe

Re: [PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Ulf Hansson]

On 9 June 2015 at 10:47, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency scaling (DVFS), interrupt
> filter and lowlevel sleep control. The System Power Manager (SPM)
> inside the SCPSYS is for the MTCMOS power domain control.
>
> For now this driver only adds power domain support, the more
> advanced features are not yet supported. The driver implements
> the generic PM domain device tree bindings, the first user will
> most likely be the Mediatek AFE audio driver.
>
> Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
>  drivers/soc/mediatek/Kconfig             |   9 +
>  drivers/soc/mediatek/Makefile            |   1 +
>  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
>  include/dt-bindings/power/mt8173-power.h |  15 +
>  4 files changed, 515 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
>  create mode 100644 include/dt-bindings/power/mt8173-power.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index e4f37a3..9a61b54 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
>           Say yes here to add support for MediaTek PMIC Wrapper found
>           on different MediaTek SoCs. The PMIC wrapper is a proprietary
>           hardware to connect the PMIC.
> +
> +config MTK_SCPSYS
> +       bool "MediaTek SCPSYS Support"
> +       depends on ARCH_MEDIATEK || COMPILE_TEST

How about also depending on "PM" and selecting PM_GENERIC_DOMAINS,
would that work?

> +       select REGMAP
> +       select MTK_INFRACFG
> +       help
> +         Say yes here to add support for the MediaTek SCPSYS power domain
> +         driver.
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 3fa940f..12998b0 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> new file mode 100644
> index 0000000..b9eed37
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -0,0 +1,490 @@
> +/*
> + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/mediatek/infracfg.h>
> +#include <dt-bindings/power/mt8173-power.h>
> +
> +#define SPM_VDE_PWR_CON                        0x0210
> +#define SPM_MFG_PWR_CON                        0x0214
> +#define SPM_VEN_PWR_CON                        0x0230
> +#define SPM_ISP_PWR_CON                        0x0238
> +#define SPM_DIS_PWR_CON                        0x023c
> +#define SPM_VEN2_PWR_CON               0x0298
> +#define SPM_AUDIO_PWR_CON              0x029c
> +#define SPM_MFG_2D_PWR_CON             0x02c0
> +#define SPM_MFG_ASYNC_PWR_CON          0x02c4
> +#define SPM_USB_PWR_CON                        0x02cc
> +#define SPM_PWR_STATUS                 0x060c
> +#define SPM_PWR_STATUS_2ND             0x0610
> +
> +#define PWR_RST_B_BIT                  BIT(0)
> +#define PWR_ISO_BIT                    BIT(1)
> +#define PWR_ON_BIT                     BIT(2)
> +#define PWR_ON_2ND_BIT                 BIT(3)
> +#define PWR_CLK_DIS_BIT                        BIT(4)
> +
> +#define PWR_STATUS_DISP                        BIT(3)
> +#define PWR_STATUS_MFG                 BIT(4)
> +#define PWR_STATUS_ISP                 BIT(5)
> +#define PWR_STATUS_VDEC                        BIT(7)
> +#define PWR_STATUS_VENC_LT             BIT(20)
> +#define PWR_STATUS_VENC                        BIT(21)
> +#define PWR_STATUS_MFG_2D              BIT(22)
> +#define PWR_STATUS_MFG_ASYNC           BIT(23)
> +#define PWR_STATUS_AUDIO               BIT(24)
> +#define PWR_STATUS_USB                 BIT(25)
> +
> +enum clk_id {
> +       MT8173_CLK_NONE,
> +       MT8173_CLK_MM,
> +       MT8173_CLK_MFG,
> +       MT8173_CLK_MAX = MT8173_CLK_MFG,
> +};
> +
> +struct scp_domain_data {
> +       const char *name;
> +       u32 sta_mask;
> +       int ctl_offs;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +       enum clk_id clk_id;
> +};
> +
> +static const struct scp_domain_data scp_domain_data[] __initconst = {
> +       [MT8173_POWER_DOMAIN_VDEC] = {
> +               .name = "vdec",
> +               .sta_mask = PWR_STATUS_VDEC,
> +               .ctl_offs = SPM_VDE_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC] = {
> +               .name = "venc",
> +               .sta_mask = PWR_STATUS_VENC,
> +               .ctl_offs = SPM_VEN_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_ISP] = {
> +               .name = "isp",
> +               .sta_mask = PWR_STATUS_ISP,
> +               .ctl_offs = SPM_ISP_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_MM] = {
> +               .name = "mm",
> +               .sta_mask = PWR_STATUS_DISP,
> +               .ctl_offs = SPM_DIS_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MM_M1,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC_LT] = {
> +               .name = "venc_lt",
> +               .sta_mask = PWR_STATUS_VENC_LT,
> +               .ctl_offs = SPM_VEN2_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_AUDIO] = {
> +               .name = "audio",
> +               .sta_mask = PWR_STATUS_AUDIO,
> +               .ctl_offs = SPM_AUDIO_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_USB] = {
> +               .name = "usb",
> +               .sta_mask = PWR_STATUS_USB,
> +               .ctl_offs = SPM_USB_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> +               .name = "mfg_async",
> +               .sta_mask = PWR_STATUS_MFG_ASYNC,
> +               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = 0,
> +               .clk_id = MT8173_CLK_MFG,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_2D] = {
> +               .name = "mfg_2d",
> +               .sta_mask = PWR_STATUS_MFG_2D,
> +               .ctl_offs = SPM_MFG_2D_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG] = {
> +               .name = "mfg",
> +               .sta_mask = PWR_STATUS_MFG,
> +               .ctl_offs = SPM_MFG_PWR_CON,
> +               .sram_pdn_bits = GENMASK(13, 8),
> +               .sram_pdn_ack_bits = GENMASK(21, 16),
> +               .clk_id = MT8173_CLK_NONE,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> +       },
> +};
> +
> +#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
> +
> +struct scp;
> +
> +struct scp_domain {
> +       struct generic_pm_domain genpd;
> +       struct scp *scp;
> +       struct clk *clk;
> +       u32 sta_mask;
> +       void __iomem *ctl_addr;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +};
> +
> +struct scp {
> +       struct scp_domain domains[NUM_DOMAINS];
> +       struct genpd_onecell_data pd_data;
> +       struct device *dev;
> +       void __iomem *base;
> +       struct regmap *infracfg;
> +       struct clk *clk[MT8173_CLK_MAX];
> +};
> +
> +static int scpsys_domain_is_on(struct scp_domain *scpd)
> +{
> +       struct scp *scp = scpd->scp;
> +
> +       u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
> +       u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
> +
> +       /*
> +        * A domain is on when both status bits are set. If only one is set
> +        * return an error. This happens while powering up a domain
> +        */
> +
> +       if (status && status2)
> +               return true;
> +       if (!status && !status2)
> +               return false;
> +
> +       return -EINVAL;
> +}
> +
> +static int scpsys_power_on(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->clk) {

Shouldn't you check for !IS_ERR(scpd->clk) instead?

> +               ret = clk_prepare_enable(scpd->clk);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +       val |= PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret > 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val &= ~PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +out:

There are no error handling. Especially the clock should be gated.

> +       dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int scpsys_power_off(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val |= PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret == 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->clk)

Shouldn't you check for !IS_ERR(scpd->clk) instead?

> +               clk_disable_unprepare(scpd->clk);
> +
> +       return 0;
> +
> +out:

There are no error handling, isn't that needed?

> +       dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int __init scpsys_probe(struct platform_device *pdev)
> +{
> +       struct genpd_onecell_data *pd_data;
> +       struct resource *res;
> +       int i, ret;
> +       struct scp *scp;
> +
> +       scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> +       if (!scp)
> +               return -ENOMEM;
> +
> +       scp->dev = &pdev->dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       scp->base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(scp->base))
> +               return PTR_ERR(scp->base);
> +
> +       pd_data = &scp->pd_data;
> +
> +       pd_data->domains = devm_kzalloc(&pdev->dev,
> +                       sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
> +       if (!pd_data->domains)
> +               return -ENOMEM;
> +
> +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));

I think a similar error message is already printed by the common clk framework!?

> +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> +       }
> +
> +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));

I think a similar error message is already printed by the common clk framework!?

> +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> +       }
> +
> +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +                       "infracfg");
> +       if (IS_ERR(scp->infracfg)) {
> +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> +                               PTR_ERR(scp->infracfg));
> +               return PTR_ERR(scp->infracfg);
> +       }
> +
> +       pd_data->num_domains = NUM_DOMAINS;
> +
> +       for (i = 0; i < NUM_DOMAINS; i++) {
> +               struct scp_domain *scpd = &scp->domains[i];
> +               struct generic_pm_domain *genpd = &scpd->genpd;
> +               const struct scp_domain_data *data = &scp_domain_data[i];
> +
> +               pd_data->domains[i] = genpd;
> +               scpd->scp = scp;
> +
> +               scpd->sta_mask = data->sta_mask;
> +               scpd->ctl_addr = scp->base + data->ctl_offs;
> +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> +               scpd->bus_prot_mask = data->bus_prot_mask;
> +               if (data->clk_id != MT8173_CLK_NONE)
> +                       scpd->clk = scp->clk[data->clk_id];

This seems odd. Why do you need to have an array of clocks to deal
with this assignment?

I don't find that the struct scp->clk pointer is used but from this
place. Couldn't you just fetch a reference to the clock to a local
struct *clk, without caching it in the struct scp->clk?

> +
> +               genpd->name = data->name;
> +               genpd->power_off = scpsys_power_off;
> +               genpd->power_on = scpsys_power_on;
> +
> +               /*
> +                * Initially turn on all domains to make the domains usable
> +                * with !CONFIG_PM and to get the hardware in sync with the
> +                * software.  The unused domains will be switched off during
> +                * late_init time.
> +                */
> +               genpd->power_on(genpd);
> +
> +               pm_genpd_init(genpd, NULL, false);
> +       }
> +
> +       /*
> +        * We are not allowed to fail here since there is no way to unregister
> +        * a power domain. Once registered above we have to keep the domains
> +        * valid.
> +        */
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
> +       if (ret)
> +               dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id of_scpsys_match_tbl[] = {
> +       {
> +               .compatible = "mediatek,mt8173-scpsys",
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver scpsys_drv = {
> +       .driver = {
> +               .name = "mtk-scpsys",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> +       },
> +};
> +
> +module_platform_driver_probe(scpsys_drv, scpsys_probe);
> diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h
> new file mode 100644
> index 0000000..b34cee9
> --- /dev/null
> +++ b/include/dt-bindings/power/mt8173-power.h
> @@ -0,0 +1,15 @@
> +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
> +#define _DT_BINDINGS_POWER_MT8183_POWER_H
> +
> +#define MT8173_POWER_DOMAIN_VDEC       0
> +#define MT8173_POWER_DOMAIN_VENC       1
> +#define MT8173_POWER_DOMAIN_ISP                2
> +#define MT8173_POWER_DOMAIN_MM         3
> +#define MT8173_POWER_DOMAIN_VENC_LT    4
> +#define MT8173_POWER_DOMAIN_AUDIO      5
> +#define MT8173_POWER_DOMAIN_USB                6
> +#define MT8173_POWER_DOMAIN_MFG_ASYNC  7
> +#define MT8173_POWER_DOMAIN_MFG_2D     8
> +#define MT8173_POWER_DOMAIN_MFG                9
> +
> +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
> --
> 2.1.4

Kind regards
Uffe
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[PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Ulf Hansson]

On 9 June 2015 at 10:47, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency scaling (DVFS), interrupt
> filter and lowlevel sleep control. The System Power Manager (SPM)
> inside the SCPSYS is for the MTCMOS power domain control.
>
> For now this driver only adds power domain support, the more
> advanced features are not yet supported. The driver implements
> the generic PM domain device tree bindings, the first user will
> most likely be the Mediatek AFE audio driver.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/soc/mediatek/Kconfig             |   9 +
>  drivers/soc/mediatek/Makefile            |   1 +
>  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
>  include/dt-bindings/power/mt8173-power.h |  15 +
>  4 files changed, 515 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
>  create mode 100644 include/dt-bindings/power/mt8173-power.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index e4f37a3..9a61b54 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
>           Say yes here to add support for MediaTek PMIC Wrapper found
>           on different MediaTek SoCs. The PMIC wrapper is a proprietary
>           hardware to connect the PMIC.
> +
> +config MTK_SCPSYS
> +       bool "MediaTek SCPSYS Support"
> +       depends on ARCH_MEDIATEK || COMPILE_TEST

How about also depending on "PM" and selecting PM_GENERIC_DOMAINS,
would that work?

> +       select REGMAP
> +       select MTK_INFRACFG
> +       help
> +         Say yes here to add support for the MediaTek SCPSYS power domain
> +         driver.
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 3fa940f..12998b0 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> new file mode 100644
> index 0000000..b9eed37
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -0,0 +1,490 @@
> +/*
> + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/mediatek/infracfg.h>
> +#include <dt-bindings/power/mt8173-power.h>
> +
> +#define SPM_VDE_PWR_CON                        0x0210
> +#define SPM_MFG_PWR_CON                        0x0214
> +#define SPM_VEN_PWR_CON                        0x0230
> +#define SPM_ISP_PWR_CON                        0x0238
> +#define SPM_DIS_PWR_CON                        0x023c
> +#define SPM_VEN2_PWR_CON               0x0298
> +#define SPM_AUDIO_PWR_CON              0x029c
> +#define SPM_MFG_2D_PWR_CON             0x02c0
> +#define SPM_MFG_ASYNC_PWR_CON          0x02c4
> +#define SPM_USB_PWR_CON                        0x02cc
> +#define SPM_PWR_STATUS                 0x060c
> +#define SPM_PWR_STATUS_2ND             0x0610
> +
> +#define PWR_RST_B_BIT                  BIT(0)
> +#define PWR_ISO_BIT                    BIT(1)
> +#define PWR_ON_BIT                     BIT(2)
> +#define PWR_ON_2ND_BIT                 BIT(3)
> +#define PWR_CLK_DIS_BIT                        BIT(4)
> +
> +#define PWR_STATUS_DISP                        BIT(3)
> +#define PWR_STATUS_MFG                 BIT(4)
> +#define PWR_STATUS_ISP                 BIT(5)
> +#define PWR_STATUS_VDEC                        BIT(7)
> +#define PWR_STATUS_VENC_LT             BIT(20)
> +#define PWR_STATUS_VENC                        BIT(21)
> +#define PWR_STATUS_MFG_2D              BIT(22)
> +#define PWR_STATUS_MFG_ASYNC           BIT(23)
> +#define PWR_STATUS_AUDIO               BIT(24)
> +#define PWR_STATUS_USB                 BIT(25)
> +
> +enum clk_id {
> +       MT8173_CLK_NONE,
> +       MT8173_CLK_MM,
> +       MT8173_CLK_MFG,
> +       MT8173_CLK_MAX = MT8173_CLK_MFG,
> +};
> +
> +struct scp_domain_data {
> +       const char *name;
> +       u32 sta_mask;
> +       int ctl_offs;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +       enum clk_id clk_id;
> +};
> +
> +static const struct scp_domain_data scp_domain_data[] __initconst = {
> +       [MT8173_POWER_DOMAIN_VDEC] = {
> +               .name = "vdec",
> +               .sta_mask = PWR_STATUS_VDEC,
> +               .ctl_offs = SPM_VDE_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC] = {
> +               .name = "venc",
> +               .sta_mask = PWR_STATUS_VENC,
> +               .ctl_offs = SPM_VEN_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_ISP] = {
> +               .name = "isp",
> +               .sta_mask = PWR_STATUS_ISP,
> +               .ctl_offs = SPM_ISP_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_MM] = {
> +               .name = "mm",
> +               .sta_mask = PWR_STATUS_DISP,
> +               .ctl_offs = SPM_DIS_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(12, 12),
> +               .clk_id = MT8173_CLK_MM,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MM_M1,
> +       },
> +       [MT8173_POWER_DOMAIN_VENC_LT] = {
> +               .name = "venc_lt",
> +               .sta_mask = PWR_STATUS_VENC_LT,
> +               .ctl_offs = SPM_VEN2_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_MM,
> +       },
> +       [MT8173_POWER_DOMAIN_AUDIO] = {
> +               .name = "audio",
> +               .sta_mask = PWR_STATUS_AUDIO,
> +               .ctl_offs = SPM_AUDIO_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_USB] = {
> +               .name = "usb",
> +               .sta_mask = PWR_STATUS_USB,
> +               .ctl_offs = SPM_USB_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(15, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> +               .name = "mfg_async",
> +               .sta_mask = PWR_STATUS_MFG_ASYNC,
> +               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = 0,
> +               .clk_id = MT8173_CLK_MFG,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG_2D] = {
> +               .name = "mfg_2d",
> +               .sta_mask = PWR_STATUS_MFG_2D,
> +               .ctl_offs = SPM_MFG_2D_PWR_CON,
> +               .sram_pdn_bits = GENMASK(11, 8),
> +               .sram_pdn_ack_bits = GENMASK(13, 12),
> +               .clk_id = MT8173_CLK_NONE,
> +       },
> +       [MT8173_POWER_DOMAIN_MFG] = {
> +               .name = "mfg",
> +               .sta_mask = PWR_STATUS_MFG,
> +               .ctl_offs = SPM_MFG_PWR_CON,
> +               .sram_pdn_bits = GENMASK(13, 8),
> +               .sram_pdn_ack_bits = GENMASK(21, 16),
> +               .clk_id = MT8173_CLK_NONE,
> +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> +                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> +       },
> +};
> +
> +#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
> +
> +struct scp;
> +
> +struct scp_domain {
> +       struct generic_pm_domain genpd;
> +       struct scp *scp;
> +       struct clk *clk;
> +       u32 sta_mask;
> +       void __iomem *ctl_addr;
> +       u32 sram_pdn_bits;
> +       u32 sram_pdn_ack_bits;
> +       u32 bus_prot_mask;
> +};
> +
> +struct scp {
> +       struct scp_domain domains[NUM_DOMAINS];
> +       struct genpd_onecell_data pd_data;
> +       struct device *dev;
> +       void __iomem *base;
> +       struct regmap *infracfg;
> +       struct clk *clk[MT8173_CLK_MAX];
> +};
> +
> +static int scpsys_domain_is_on(struct scp_domain *scpd)
> +{
> +       struct scp *scp = scpd->scp;
> +
> +       u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
> +       u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
> +
> +       /*
> +        * A domain is on when both status bits are set. If only one is set
> +        * return an error. This happens while powering up a domain
> +        */
> +
> +       if (status && status2)
> +               return true;
> +       if (!status && !status2)
> +               return false;
> +
> +       return -EINVAL;
> +}
> +
> +static int scpsys_power_on(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->clk) {

Shouldn't you check for !IS_ERR(scpd->clk) instead?

> +               ret = clk_prepare_enable(scpd->clk);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +       val |= PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret > 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val &= ~PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +out:

There are no error handling. Especially the clock should be gated.

> +       dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int scpsys_power_off(struct generic_pm_domain *genpd)
> +{
> +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> +       struct scp *scp = scpd->scp;
> +       unsigned long timeout;
> +       bool expired;
> +       void __iomem *ctl_addr = scpd->ctl_addr;
> +       u32 pdn_ack = scpd->sram_pdn_ack_bits;
> +       u32 val;
> +       int ret;
> +
> +       if (scpd->bus_prot_mask) {
> +               ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> +                               scpd->bus_prot_mask);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       val = readl(ctl_addr);
> +       val |= scpd->sram_pdn_bits;
> +       writel(val, ctl_addr);
> +
> +       /* wait until SRAM_PDN_ACK all 1 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       val |= PWR_ISO_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_RST_B_BIT;
> +       writel(val, ctl_addr);
> +
> +       val |= PWR_CLK_DIS_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_BIT;
> +       writel(val, ctl_addr);
> +
> +       val &= ~PWR_ON_2ND_BIT;
> +       writel(val, ctl_addr);
> +
> +       /* wait until PWR_ACK = 0 */
> +       timeout = jiffies + HZ;
> +       expired = false;
> +       while (1) {
> +               ret = scpsys_domain_is_on(scpd);
> +               if (ret == 0)
> +                       break;
> +
> +               if (expired) {
> +                       ret = -ETIMEDOUT;
> +                       goto out;
> +               }
> +
> +               cpu_relax();
> +
> +               if (time_after(jiffies, timeout))
> +                       expired = true;
> +       }
> +
> +       if (scpd->clk)

Shouldn't you check for !IS_ERR(scpd->clk) instead?

> +               clk_disable_unprepare(scpd->clk);
> +
> +       return 0;
> +
> +out:

There are no error handling, isn't that needed?

> +       dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
> +
> +       return ret;
> +}
> +
> +static int __init scpsys_probe(struct platform_device *pdev)
> +{
> +       struct genpd_onecell_data *pd_data;
> +       struct resource *res;
> +       int i, ret;
> +       struct scp *scp;
> +
> +       scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> +       if (!scp)
> +               return -ENOMEM;
> +
> +       scp->dev = &pdev->dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       scp->base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(scp->base))
> +               return PTR_ERR(scp->base);
> +
> +       pd_data = &scp->pd_data;
> +
> +       pd_data->domains = devm_kzalloc(&pdev->dev,
> +                       sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
> +       if (!pd_data->domains)
> +               return -ENOMEM;
> +
> +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));

I think a similar error message is already printed by the common clk framework!?

> +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> +       }
> +
> +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));

I think a similar error message is already printed by the common clk framework!?

> +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> +       }
> +
> +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +                       "infracfg");
> +       if (IS_ERR(scp->infracfg)) {
> +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> +                               PTR_ERR(scp->infracfg));
> +               return PTR_ERR(scp->infracfg);
> +       }
> +
> +       pd_data->num_domains = NUM_DOMAINS;
> +
> +       for (i = 0; i < NUM_DOMAINS; i++) {
> +               struct scp_domain *scpd = &scp->domains[i];
> +               struct generic_pm_domain *genpd = &scpd->genpd;
> +               const struct scp_domain_data *data = &scp_domain_data[i];
> +
> +               pd_data->domains[i] = genpd;
> +               scpd->scp = scp;
> +
> +               scpd->sta_mask = data->sta_mask;
> +               scpd->ctl_addr = scp->base + data->ctl_offs;
> +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> +               scpd->bus_prot_mask = data->bus_prot_mask;
> +               if (data->clk_id != MT8173_CLK_NONE)
> +                       scpd->clk = scp->clk[data->clk_id];

This seems odd. Why do you need to have an array of clocks to deal
with this assignment?

I don't find that the struct scp->clk pointer is used but from this
place. Couldn't you just fetch a reference to the clock to a local
struct *clk, without caching it in the struct scp->clk?

> +
> +               genpd->name = data->name;
> +               genpd->power_off = scpsys_power_off;
> +               genpd->power_on = scpsys_power_on;
> +
> +               /*
> +                * Initially turn on all domains to make the domains usable
> +                * with !CONFIG_PM and to get the hardware in sync with the
> +                * software.  The unused domains will be switched off during
> +                * late_init time.
> +                */
> +               genpd->power_on(genpd);
> +
> +               pm_genpd_init(genpd, NULL, false);
> +       }
> +
> +       /*
> +        * We are not allowed to fail here since there is no way to unregister
> +        * a power domain. Once registered above we have to keep the domains
> +        * valid.
> +        */
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
> +               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
> +       if (ret && IS_ENABLED(CONFIG_PM))
> +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
> +
> +       ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
> +       if (ret)
> +               dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id of_scpsys_match_tbl[] = {
> +       {
> +               .compatible = "mediatek,mt8173-scpsys",
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver scpsys_drv = {
> +       .driver = {
> +               .name = "mtk-scpsys",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> +       },
> +};
> +
> +module_platform_driver_probe(scpsys_drv, scpsys_probe);
> diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h
> new file mode 100644
> index 0000000..b34cee9
> --- /dev/null
> +++ b/include/dt-bindings/power/mt8173-power.h
> @@ -0,0 +1,15 @@
> +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
> +#define _DT_BINDINGS_POWER_MT8183_POWER_H
> +
> +#define MT8173_POWER_DOMAIN_VDEC       0
> +#define MT8173_POWER_DOMAIN_VENC       1
> +#define MT8173_POWER_DOMAIN_ISP                2
> +#define MT8173_POWER_DOMAIN_MM         3
> +#define MT8173_POWER_DOMAIN_VENC_LT    4
> +#define MT8173_POWER_DOMAIN_AUDIO      5
> +#define MT8173_POWER_DOMAIN_USB                6
> +#define MT8173_POWER_DOMAIN_MFG_ASYNC  7
> +#define MT8173_POWER_DOMAIN_MFG_2D     8
> +#define MT8173_POWER_DOMAIN_MFG                9
> +
> +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
> --
> 2.1.4

Kind regards
Uffe

Re: [PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Sascha Hauer]

Hi Ulf,

On Wed, Jun 10, 2015 at 04:47:01PM +0200, Ulf Hansson wrote:
> On 9 June 2015 at 10:47, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > This adds a power domain driver for the Mediatek SCPSYS unit.
> >
> > The System Control Processor System (SCPSYS) has several power
> > management related tasks in the system. The tasks include thermal
> > measurement, dynamic voltage frequency scaling (DVFS), interrupt
> > filter and lowlevel sleep control. The System Power Manager (SPM)
> > inside the SCPSYS is for the MTCMOS power domain control.
> >
> > For now this driver only adds power domain support, the more
> > advanced features are not yet supported. The driver implements
> > the generic PM domain device tree bindings, the first user will
> > most likely be the Mediatek AFE audio driver.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  drivers/soc/mediatek/Kconfig             |   9 +
> >  drivers/soc/mediatek/Makefile            |   1 +
> >  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
> >  include/dt-bindings/power/mt8173-power.h |  15 +
> >  4 files changed, 515 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
> >  create mode 100644 include/dt-bindings/power/mt8173-power.h
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index e4f37a3..9a61b54 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
> >           Say yes here to add support for MediaTek PMIC Wrapper found
> >           on different MediaTek SoCs. The PMIC wrapper is a proprietary
> >           hardware to connect the PMIC.
> > +
> > +config MTK_SCPSYS
> > +       bool "MediaTek SCPSYS Support"
> > +       depends on ARCH_MEDIATEK || COMPILE_TEST
> 
> How about also depending on "PM" and selecting PM_GENERIC_DOMAINS,
> would that work?

That's what patch 4/5 does. So far all drivers have this in
arch/arm/mach-*/Kconfig and so did I. However, they probably have it
under arch/ to have it next to the driver. I'll move it here and drop
4/5.

> > +static int scpsys_power_on(struct generic_pm_domain *genpd)
> > +{
> > +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> > +       struct scp *scp = scpd->scp;
> > +       unsigned long timeout;
> > +       bool expired;
> > +       void __iomem *ctl_addr = scpd->ctl_addr;
> > +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> > +       u32 val;
> > +       int ret;
> > +
> > +       if (scpd->clk) {
> 
> Shouldn't you check for !IS_ERR(scpd->clk) instead?

No. scpd->clk is initialized like this:

		if (data->clk_id != MT8173_CLK_NONE)
			scpd->clk = scp->clk[data->clk_id];

So scpd->clk will never be an ERR_PTR but always NULL if unset.

> 
> > +               ret = clk_prepare_enable(scpd->clk);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
> > +       val = readl(ctl_addr);
> > +       val |= PWR_ON_BIT;
> > +       writel(val, ctl_addr);
> > +       val |= PWR_ON_2ND_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until PWR_ACK = 1 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (1) {
> > +               ret = scpsys_domain_is_on(scpd);
> > +               if (ret > 0)
> > +                       break;
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       val &= ~PWR_CLK_DIS_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val &= ~PWR_ISO_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val |= PWR_RST_B_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val &= ~scpd->sram_pdn_bits;
> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until SRAM_PDN_ACK all 0 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       if (scpd->bus_prot_mask) {
> > +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> > +                               scpd->bus_prot_mask);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
> > +       return 0;
> > +out:
> 
> There are no error handling. Especially the clock should be gated.

I'll disable the clock in the error path for the next round. Apart from
that I think I cannot implement a proper error handling without knowing
what actually went wrong. I mean I ask the hardware to do something
and then poll for a bit to get the ack from the hardware. If that ack
doesn't come I don't know what to do to recover from this state. A I2C
controller or such could probably be resetted in this situation, but a
power domain controller?

> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until PWR_ACK = 0 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (1) {
> > +               ret = scpsys_domain_is_on(scpd);
> > +               if (ret == 0)
> > +                       break;
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       if (scpd->clk)
> 
> Shouldn't you check for !IS_ERR(scpd->clk) instead?

No, as above.

> > +               return -ENOMEM;
> > +
> > +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> > +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> > +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> > +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));
> 
> I think a similar error message is already printed by the common clk framework!?
> 
> > +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> > +       }
> > +
> > +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> > +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> > +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> > +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));
> 
> I think a similar error message is already printed by the common clk framework!?

Yes, will drop these messages.

> 
> > +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> > +       }
> > +
> > +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> > +                       "infracfg");
> > +       if (IS_ERR(scp->infracfg)) {
> > +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> > +                               PTR_ERR(scp->infracfg));
> > +               return PTR_ERR(scp->infracfg);
> > +       }
> > +
> > +       pd_data->num_domains = NUM_DOMAINS;
> > +
> > +       for (i = 0; i < NUM_DOMAINS; i++) {
> > +               struct scp_domain *scpd = &scp->domains[i];
> > +               struct generic_pm_domain *genpd = &scpd->genpd;
> > +               const struct scp_domain_data *data = &scp_domain_data[i];
> > +
> > +               pd_data->domains[i] = genpd;
> > +               scpd->scp = scp;
> > +
> > +               scpd->sta_mask = data->sta_mask;
> > +               scpd->ctl_addr = scp->base + data->ctl_offs;
> > +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> > +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> > +               scpd->bus_prot_mask = data->bus_prot_mask;
> > +               if (data->clk_id != MT8173_CLK_NONE)
> > +                       scpd->clk = scp->clk[data->clk_id];
> 
> This seems odd. Why do you need to have an array of clocks to deal
> with this assignment?
> 
> I don't find that the struct scp->clk pointer is used but from this
> place. Couldn't you just fetch a reference to the clock to a local
> struct *clk, without caching it in the struct scp->clk?

Yes, will change.

Thanks for reviewing.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Sascha Hauer]

Hi Ulf,

On Wed, Jun 10, 2015 at 04:47:01PM +0200, Ulf Hansson wrote:
> On 9 June 2015 at 10:47, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > This adds a power domain driver for the Mediatek SCPSYS unit.
> >
> > The System Control Processor System (SCPSYS) has several power
> > management related tasks in the system. The tasks include thermal
> > measurement, dynamic voltage frequency scaling (DVFS), interrupt
> > filter and lowlevel sleep control. The System Power Manager (SPM)
> > inside the SCPSYS is for the MTCMOS power domain control.
> >
> > For now this driver only adds power domain support, the more
> > advanced features are not yet supported. The driver implements
> > the generic PM domain device tree bindings, the first user will
> > most likely be the Mediatek AFE audio driver.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  drivers/soc/mediatek/Kconfig             |   9 +
> >  drivers/soc/mediatek/Makefile            |   1 +
> >  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
> >  include/dt-bindings/power/mt8173-power.h |  15 +
> >  4 files changed, 515 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
> >  create mode 100644 include/dt-bindings/power/mt8173-power.h
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index e4f37a3..9a61b54 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
> >           Say yes here to add support for MediaTek PMIC Wrapper found
> >           on different MediaTek SoCs. The PMIC wrapper is a proprietary
> >           hardware to connect the PMIC.
> > +
> > +config MTK_SCPSYS
> > +       bool "MediaTek SCPSYS Support"
> > +       depends on ARCH_MEDIATEK || COMPILE_TEST
> 
> How about also depending on "PM" and selecting PM_GENERIC_DOMAINS,
> would that work?

That's what patch 4/5 does. So far all drivers have this in
arch/arm/mach-*/Kconfig and so did I. However, they probably have it
under arch/ to have it next to the driver. I'll move it here and drop
4/5.

> > +static int scpsys_power_on(struct generic_pm_domain *genpd)
> > +{
> > +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> > +       struct scp *scp = scpd->scp;
> > +       unsigned long timeout;
> > +       bool expired;
> > +       void __iomem *ctl_addr = scpd->ctl_addr;
> > +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> > +       u32 val;
> > +       int ret;
> > +
> > +       if (scpd->clk) {
> 
> Shouldn't you check for !IS_ERR(scpd->clk) instead?

No. scpd->clk is initialized like this:

		if (data->clk_id != MT8173_CLK_NONE)
			scpd->clk = scp->clk[data->clk_id];

So scpd->clk will never be an ERR_PTR but always NULL if unset.

> 
> > +               ret = clk_prepare_enable(scpd->clk);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
> > +       val = readl(ctl_addr);
> > +       val |= PWR_ON_BIT;
> > +       writel(val, ctl_addr);
> > +       val |= PWR_ON_2ND_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until PWR_ACK = 1 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (1) {
> > +               ret = scpsys_domain_is_on(scpd);
> > +               if (ret > 0)
> > +                       break;
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       val &= ~PWR_CLK_DIS_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val &= ~PWR_ISO_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val |= PWR_RST_B_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val &= ~scpd->sram_pdn_bits;
> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until SRAM_PDN_ACK all 0 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       if (scpd->bus_prot_mask) {
> > +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> > +                               scpd->bus_prot_mask);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
> > +       return 0;
> > +out:
> 
> There are no error handling. Especially the clock should be gated.

I'll disable the clock in the error path for the next round. Apart from
that I think I cannot implement a proper error handling without knowing
what actually went wrong. I mean I ask the hardware to do something
and then poll for a bit to get the ack from the hardware. If that ack
doesn't come I don't know what to do to recover from this state. A I2C
controller or such could probably be resetted in this situation, but a
power domain controller?

> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until PWR_ACK = 0 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (1) {
> > +               ret = scpsys_domain_is_on(scpd);
> > +               if (ret == 0)
> > +                       break;
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       if (scpd->clk)
> 
> Shouldn't you check for !IS_ERR(scpd->clk) instead?

No, as above.

> > +               return -ENOMEM;
> > +
> > +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> > +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> > +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> > +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));
> 
> I think a similar error message is already printed by the common clk framework!?
> 
> > +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> > +       }
> > +
> > +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> > +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> > +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> > +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));
> 
> I think a similar error message is already printed by the common clk framework!?

Yes, will drop these messages.

> 
> > +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> > +       }
> > +
> > +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> > +                       "infracfg");
> > +       if (IS_ERR(scp->infracfg)) {
> > +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> > +                               PTR_ERR(scp->infracfg));
> > +               return PTR_ERR(scp->infracfg);
> > +       }
> > +
> > +       pd_data->num_domains = NUM_DOMAINS;
> > +
> > +       for (i = 0; i < NUM_DOMAINS; i++) {
> > +               struct scp_domain *scpd = &scp->domains[i];
> > +               struct generic_pm_domain *genpd = &scpd->genpd;
> > +               const struct scp_domain_data *data = &scp_domain_data[i];
> > +
> > +               pd_data->domains[i] = genpd;
> > +               scpd->scp = scp;
> > +
> > +               scpd->sta_mask = data->sta_mask;
> > +               scpd->ctl_addr = scp->base + data->ctl_offs;
> > +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> > +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> > +               scpd->bus_prot_mask = data->bus_prot_mask;
> > +               if (data->clk_id != MT8173_CLK_NONE)
> > +                       scpd->clk = scp->clk[data->clk_id];
> 
> This seems odd. Why do you need to have an array of clocks to deal
> with this assignment?
> 
> I don't find that the struct scp->clk pointer is used but from this
> place. Couldn't you just fetch a reference to the clock to a local
> struct *clk, without caching it in the struct scp->clk?

Yes, will change.

Thanks for reviewing.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 3/5] soc: Mediatek: Add SCPSYS power domain driver

[Sascha Hauer]

Hi Ulf,

On Wed, Jun 10, 2015 at 04:47:01PM +0200, Ulf Hansson wrote:
> On 9 June 2015 at 10:47, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > This adds a power domain driver for the Mediatek SCPSYS unit.
> >
> > The System Control Processor System (SCPSYS) has several power
> > management related tasks in the system. The tasks include thermal
> > measurement, dynamic voltage frequency scaling (DVFS), interrupt
> > filter and lowlevel sleep control. The System Power Manager (SPM)
> > inside the SCPSYS is for the MTCMOS power domain control.
> >
> > For now this driver only adds power domain support, the more
> > advanced features are not yet supported. The driver implements
> > the generic PM domain device tree bindings, the first user will
> > most likely be the Mediatek AFE audio driver.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  drivers/soc/mediatek/Kconfig             |   9 +
> >  drivers/soc/mediatek/Makefile            |   1 +
> >  drivers/soc/mediatek/mtk-scpsys.c        | 490 +++++++++++++++++++++++++++++++
> >  include/dt-bindings/power/mt8173-power.h |  15 +
> >  4 files changed, 515 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
> >  create mode 100644 include/dt-bindings/power/mt8173-power.h
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index e4f37a3..9a61b54 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -18,3 +18,12 @@ config MTK_PMIC_WRAP
> >           Say yes here to add support for MediaTek PMIC Wrapper found
> >           on different MediaTek SoCs. The PMIC wrapper is a proprietary
> >           hardware to connect the PMIC.
> > +
> > +config MTK_SCPSYS
> > +       bool "MediaTek SCPSYS Support"
> > +       depends on ARCH_MEDIATEK || COMPILE_TEST
> 
> How about also depending on "PM" and selecting PM_GENERIC_DOMAINS,
> would that work?

That's what patch 4/5 does. So far all drivers have this in
arch/arm/mach-*/Kconfig and so did I. However, they probably have it
under arch/ to have it next to the driver. I'll move it here and drop
4/5.

> > +static int scpsys_power_on(struct generic_pm_domain *genpd)
> > +{
> > +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> > +       struct scp *scp = scpd->scp;
> > +       unsigned long timeout;
> > +       bool expired;
> > +       void __iomem *ctl_addr = scpd->ctl_addr;
> > +       u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
> > +       u32 val;
> > +       int ret;
> > +
> > +       if (scpd->clk) {
> 
> Shouldn't you check for !IS_ERR(scpd->clk) instead?

No. scpd->clk is initialized like this:

		if (data->clk_id != MT8173_CLK_NONE)
			scpd->clk = scp->clk[data->clk_id];

So scpd->clk will never be an ERR_PTR but always NULL if unset.

> 
> > +               ret = clk_prepare_enable(scpd->clk);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
> > +       val = readl(ctl_addr);
> > +       val |= PWR_ON_BIT;
> > +       writel(val, ctl_addr);
> > +       val |= PWR_ON_2ND_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until PWR_ACK = 1 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (1) {
> > +               ret = scpsys_domain_is_on(scpd);
> > +               if (ret > 0)
> > +                       break;
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       val &= ~PWR_CLK_DIS_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val &= ~PWR_ISO_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val |= PWR_RST_B_BIT;
> > +       writel(val, ctl_addr);
> > +
> > +       val &= ~scpd->sram_pdn_bits;
> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until SRAM_PDN_ACK all 0 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       if (scpd->bus_prot_mask) {
> > +               ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> > +                               scpd->bus_prot_mask);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
> > +       return 0;
> > +out:
> 
> There are no error handling. Especially the clock should be gated.

I'll disable the clock in the error path for the next round. Apart from
that I think I cannot implement a proper error handling without knowing
what actually went wrong. I mean I ask the hardware to do something
and then poll for a bit to get the ack from the hardware. If that ack
doesn't come I don't know what to do to recover from this state. A I2C
controller or such could probably be resetted in this situation, but a
power domain controller?

> > +       writel(val, ctl_addr);
> > +
> > +       /* wait until PWR_ACK = 0 */
> > +       timeout = jiffies + HZ;
> > +       expired = false;
> > +       while (1) {
> > +               ret = scpsys_domain_is_on(scpd);
> > +               if (ret == 0)
> > +                       break;
> > +
> > +               if (expired) {
> > +                       ret = -ETIMEDOUT;
> > +                       goto out;
> > +               }
> > +
> > +               cpu_relax();
> > +
> > +               if (time_after(jiffies, timeout))
> > +                       expired = true;
> > +       }
> > +
> > +       if (scpd->clk)
> 
> Shouldn't you check for !IS_ERR(scpd->clk) instead?

No, as above.

> > +               return -ENOMEM;
> > +
> > +       scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
> > +       if (IS_ERR(scp->clk[MT8173_CLK_MM])) {
> > +               dev_err(&pdev->dev, "Failed to get mm clk: %ld\n",
> > +                               PTR_ERR(scp->clk[MT8173_CLK_MM]));
> 
> I think a similar error message is already printed by the common clk framework!?
> 
> > +               return PTR_ERR(scp->clk[MT8173_CLK_MM]);
> > +       }
> > +
> > +       scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
> > +       if (IS_ERR(scp->clk[MT8173_CLK_MFG])) {
> > +               dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n",
> > +                               PTR_ERR(scp->clk[MT8173_CLK_MFG]));
> 
> I think a similar error message is already printed by the common clk framework!?

Yes, will drop these messages.

> 
> > +               return PTR_ERR(scp->clk[MT8173_CLK_MFG]);
> > +       }
> > +
> > +       scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> > +                       "infracfg");
> > +       if (IS_ERR(scp->infracfg)) {
> > +               dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
> > +                               PTR_ERR(scp->infracfg));
> > +               return PTR_ERR(scp->infracfg);
> > +       }
> > +
> > +       pd_data->num_domains = NUM_DOMAINS;
> > +
> > +       for (i = 0; i < NUM_DOMAINS; i++) {
> > +               struct scp_domain *scpd = &scp->domains[i];
> > +               struct generic_pm_domain *genpd = &scpd->genpd;
> > +               const struct scp_domain_data *data = &scp_domain_data[i];
> > +
> > +               pd_data->domains[i] = genpd;
> > +               scpd->scp = scp;
> > +
> > +               scpd->sta_mask = data->sta_mask;
> > +               scpd->ctl_addr = scp->base + data->ctl_offs;
> > +               scpd->sram_pdn_bits = data->sram_pdn_bits;
> > +               scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
> > +               scpd->bus_prot_mask = data->bus_prot_mask;
> > +               if (data->clk_id != MT8173_CLK_NONE)
> > +                       scpd->clk = scp->clk[data->clk_id];
> 
> This seems odd. Why do you need to have an array of clocks to deal
> with this assignment?
> 
> I don't find that the struct scp->clk pointer is used but from this
> place. Couldn't you just fetch a reference to the clock to a local
> struct *clk, without caching it in the struct scp->clk?

Yes, will change.

Thanks for reviewing.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Kevin Hilman]

Sascha Hauer <s.hauer@pengutronix.de> writes:

> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 924fdb6..12430f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -125,6 +125,16 @@
>  						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		scpsys: scpsys@10006000 {
> +			compatible = "mediatek,mt8173-scpsys";
> +			#power-domain-cells = <1>;
> +			reg = <0 0x10006000 0 0x1000>;
> +			clocks = <&clk26m>,
> +				 <&topckgen CLK_TOP_MM_SEL>;

Neither your binding doc (nor the generic one) mentions these clock
properties or what they are used for.  They appear to define a clock
that must be enabled in order to for the power domain to be on.

Also the order here seems rather important and probably needs
documenting in the binding (e.g. the clk_id order is hard-coded in the
driver.)

Kevin

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Kevin Hilman]

Sascha Hauer <s.hauer@pengutronix.de> writes:

> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 924fdb6..12430f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -125,6 +125,16 @@
>  						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		scpsys: scpsys at 10006000 {
> +			compatible = "mediatek,mt8173-scpsys";
> +			#power-domain-cells = <1>;
> +			reg = <0 0x10006000 0 0x1000>;
> +			clocks = <&clk26m>,
> +				 <&topckgen CLK_TOP_MM_SEL>;

Neither your binding doc (nor the generic one) mentions these clock
properties or what they are used for.  They appear to define a clock
that must be enabled in order to for the power domain to be on.

Also the order here seems rather important and probably needs
documenting in the binding (e.g. the clk_id order is hard-coded in the
driver.)

Kevin

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

On Tue, Jun 16, 2015 at 11:17:53AM -0700, Kevin Hilman wrote:
> Sascha Hauer <s.hauer@pengutronix.de> writes:
> 
> > This adds the SCPSYS device node to the MT8173 dtsi file.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 924fdb6..12430f0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -125,6 +125,16 @@
> >  						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> >  		};
> >  
> > +		scpsys: scpsys@10006000 {
> > +			compatible = "mediatek,mt8173-scpsys";
> > +			#power-domain-cells = <1>;
> > +			reg = <0 0x10006000 0 0x1000>;
> > +			clocks = <&clk26m>,
> > +				 <&topckgen CLK_TOP_MM_SEL>;
> 
> Neither your binding doc (nor the generic one) mentions these clock
> properties or what they are used for.  They appear to define a clock
> that must be enabled in order to for the power domain to be on.

Ok, will add documentation for this.

> 
> Also the order here seems rather important and probably needs
> documenting in the binding (e.g. the clk_id order is hard-coded in the
> driver.)

The order is not important, the clock-names property defines which clock
is which.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

On Tue, Jun 16, 2015 at 11:17:53AM -0700, Kevin Hilman wrote:
> Sascha Hauer <s.hauer@pengutronix.de> writes:
> 
> > This adds the SCPSYS device node to the MT8173 dtsi file.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 924fdb6..12430f0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -125,6 +125,16 @@
> >  						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> >  		};
> >  
> > +		scpsys: scpsys at 10006000 {
> > +			compatible = "mediatek,mt8173-scpsys";
> > +			#power-domain-cells = <1>;
> > +			reg = <0 0x10006000 0 0x1000>;
> > +			clocks = <&clk26m>,
> > +				 <&topckgen CLK_TOP_MM_SEL>;
> 
> Neither your binding doc (nor the generic one) mentions these clock
> properties or what they are used for.  They appear to define a clock
> that must be enabled in order to for the power domain to be on.

Ok, will add documentation for this.

> 
> Also the order here seems rather important and probably needs
> documenting in the binding (e.g. the clk_id order is hard-coded in the
> driver.)

The order is not important, the clock-names property defines which clock
is which.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

Hi James,

On Fri, May 22, 2015 at 1:40 PM, James Liao <jamesjj.liao@mediatek.com> wrote:
> Hi Daniel,
>
> On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
>> On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao@mediatek.com> wrote:
>> >
>> > Sascha is right. I had confirmed with our designer that MFG on MT8173
>> > uses clk26m to check state. I also tested MFG domain power on/off with
>> > CLK_TOP_MFG_SEL off and it worked correctly.
>>
>> Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
>> Now I am even more confused.
>> Which is the correct clock to use for the mfg power domains?
>
> I tested MFG domain power on/off with MFG_SEL "OFF". If MFG domain use
> MFG_SEL as its bus clock, it will be timeout while waiting SRAM ACK. But
> in my test, MFG power domain can power on/off without MFG_SEL. That
> means it doesn't need MFG_SEL while power on/off MFG domains.
>
>> >
>> > My patch set yesterday add subsystem clocks, which are not needed by
>> > power domain on/off. So I think these 2 patch set are independent.
>>
>> In other versions of the SCPSYS patch set, the scpsys node has
>> additional "subsystem bus clocks".
>
> That's my fault because I provided wrong information to Sascha. So in
> his early version of mtk-scpsys driver, the clocks setting of power
> domains are incorrect. The correct clock setting for each power domain
> should be:
>
> POWER_DOMAIN_MFG:     clk26m (no need to enable topckgen clocks)
> POWER_DOMAIN_DISP:    mm_sel
> POWER_DOMAIN_VDEC:    mm_sel
> POWER_DOMAIN_VENC:    mm_sel
> POWER_DOMAIN_VENC_LT: mm_sel
> POWER_DOMAIN_ISP:     mm_sel
>
>> So will we need additional patches later to add back these additional
>> clocks which have been removed from the current version of this pach?
>
> No. Clocks provided by topckgen are enough for scpsys driver. Please see
> my comments below.
>
>> In other words, will there be a follow up patch like below, plus
>> another patch to add these clocks to "enum clk_id":
>>
>> @@ -163,9 +163,12 @@
>>   compatible = "mediatek,mt8173-scpsys";
>>   #power-domain-cells = <1>;
>>   reg = <0 0x10006000 0 0x1000>;
>> - clocks = <&clk26m>,
>> - <&topckgen CLK_TOP_MM_SEL>;
>> - clock-names = "mfg", "mm";
>> + clocks = <&topckgen CLK_TOP_MFG_SEL>,
>> + <&topckgen CLK_TOP_MM_SEL>,
>> + <&topckgen CLK_TOP_VDEC_SEL>,
>> + <&topckgen CLK_TOP_VENC_SEL>,
>> + <&topckgen CLK_TOP_VENC_LT_SEL>;
>> + clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
>>   infracfg = <&infracfg>;
>>   };
>
> These clocks come from topckgen. In our term, they are "top clocks".
> Subsystem clocks which mentioned in my patch set are provided by
> subsystems such as mmsys, vdecsys, vencsys and so on.


This is all great news!
Thanks for the detailed update.

Best Regards,
-Daniel

>
>
> Best regards,
>
> James
>

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

Hi James,

On Fri, May 22, 2015 at 1:40 PM, James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> Hi Daniel,
>
> On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
>> On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
>> >
>> > Sascha is right. I had confirmed with our designer that MFG on MT8173
>> > uses clk26m to check state. I also tested MFG domain power on/off with
>> > CLK_TOP_MFG_SEL off and it worked correctly.
>>
>> Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
>> Now I am even more confused.
>> Which is the correct clock to use for the mfg power domains?
>
> I tested MFG domain power on/off with MFG_SEL "OFF". If MFG domain use
> MFG_SEL as its bus clock, it will be timeout while waiting SRAM ACK. But
> in my test, MFG power domain can power on/off without MFG_SEL. That
> means it doesn't need MFG_SEL while power on/off MFG domains.
>
>> >
>> > My patch set yesterday add subsystem clocks, which are not needed by
>> > power domain on/off. So I think these 2 patch set are independent.
>>
>> In other versions of the SCPSYS patch set, the scpsys node has
>> additional "subsystem bus clocks".
>
> That's my fault because I provided wrong information to Sascha. So in
> his early version of mtk-scpsys driver, the clocks setting of power
> domains are incorrect. The correct clock setting for each power domain
> should be:
>
> POWER_DOMAIN_MFG:     clk26m (no need to enable topckgen clocks)
> POWER_DOMAIN_DISP:    mm_sel
> POWER_DOMAIN_VDEC:    mm_sel
> POWER_DOMAIN_VENC:    mm_sel
> POWER_DOMAIN_VENC_LT: mm_sel
> POWER_DOMAIN_ISP:     mm_sel
>
>> So will we need additional patches later to add back these additional
>> clocks which have been removed from the current version of this pach?
>
> No. Clocks provided by topckgen are enough for scpsys driver. Please see
> my comments below.
>
>> In other words, will there be a follow up patch like below, plus
>> another patch to add these clocks to "enum clk_id":
>>
>> @@ -163,9 +163,12 @@
>>   compatible = "mediatek,mt8173-scpsys";
>>   #power-domain-cells = <1>;
>>   reg = <0 0x10006000 0 0x1000>;
>> - clocks = <&clk26m>,
>> - <&topckgen CLK_TOP_MM_SEL>;
>> - clock-names = "mfg", "mm";
>> + clocks = <&topckgen CLK_TOP_MFG_SEL>,
>> + <&topckgen CLK_TOP_MM_SEL>,
>> + <&topckgen CLK_TOP_VDEC_SEL>,
>> + <&topckgen CLK_TOP_VENC_SEL>,
>> + <&topckgen CLK_TOP_VENC_LT_SEL>;
>> + clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
>>   infracfg = <&infracfg>;
>>   };
>
> These clocks come from topckgen. In our term, they are "top clocks".
> Subsystem clocks which mentioned in my patch set are provided by
> subsystems such as mmsys, vdecsys, vencsys and so on.


This is all great news!
Thanks for the detailed update.

Best Regards,
-Daniel

>
>
> Best regards,
>
> James
>
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[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

Hi James,

On Fri, May 22, 2015 at 1:40 PM, James Liao <jamesjj.liao@mediatek.com> wrote:
> Hi Daniel,
>
> On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
>> On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao@mediatek.com> wrote:
>> >
>> > Sascha is right. I had confirmed with our designer that MFG on MT8173
>> > uses clk26m to check state. I also tested MFG domain power on/off with
>> > CLK_TOP_MFG_SEL off and it worked correctly.
>>
>> Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
>> Now I am even more confused.
>> Which is the correct clock to use for the mfg power domains?
>
> I tested MFG domain power on/off with MFG_SEL "OFF". If MFG domain use
> MFG_SEL as its bus clock, it will be timeout while waiting SRAM ACK. But
> in my test, MFG power domain can power on/off without MFG_SEL. That
> means it doesn't need MFG_SEL while power on/off MFG domains.
>
>> >
>> > My patch set yesterday add subsystem clocks, which are not needed by
>> > power domain on/off. So I think these 2 patch set are independent.
>>
>> In other versions of the SCPSYS patch set, the scpsys node has
>> additional "subsystem bus clocks".
>
> That's my fault because I provided wrong information to Sascha. So in
> his early version of mtk-scpsys driver, the clocks setting of power
> domains are incorrect. The correct clock setting for each power domain
> should be:
>
> POWER_DOMAIN_MFG:     clk26m (no need to enable topckgen clocks)
> POWER_DOMAIN_DISP:    mm_sel
> POWER_DOMAIN_VDEC:    mm_sel
> POWER_DOMAIN_VENC:    mm_sel
> POWER_DOMAIN_VENC_LT: mm_sel
> POWER_DOMAIN_ISP:     mm_sel
>
>> So will we need additional patches later to add back these additional
>> clocks which have been removed from the current version of this pach?
>
> No. Clocks provided by topckgen are enough for scpsys driver. Please see
> my comments below.
>
>> In other words, will there be a follow up patch like below, plus
>> another patch to add these clocks to "enum clk_id":
>>
>> @@ -163,9 +163,12 @@
>>   compatible = "mediatek,mt8173-scpsys";
>>   #power-domain-cells = <1>;
>>   reg = <0 0x10006000 0 0x1000>;
>> - clocks = <&clk26m>,
>> - <&topckgen CLK_TOP_MM_SEL>;
>> - clock-names = "mfg", "mm";
>> + clocks = <&topckgen CLK_TOP_MFG_SEL>,
>> + <&topckgen CLK_TOP_MM_SEL>,
>> + <&topckgen CLK_TOP_VDEC_SEL>,
>> + <&topckgen CLK_TOP_VENC_SEL>,
>> + <&topckgen CLK_TOP_VENC_LT_SEL>;
>> + clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
>>   infracfg = <&infracfg>;
>>   };
>
> These clocks come from topckgen. In our term, they are "top clocks".
> Subsystem clocks which mentioned in my patch set are provided by
> subsystems such as mmsys, vdecsys, vencsys and so on.


This is all great news!
Thanks for the detailed update.

Best Regards,
-Daniel

>
>
> Best regards,
>
> James
>

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[James Liao]

Hi Daniel,

On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
> On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao@mediatek.com> wrote:
> >
> > Sascha is right. I had confirmed with our designer that MFG on MT8173
> > uses clk26m to check state. I also tested MFG domain power on/off with
> > CLK_TOP_MFG_SEL off and it worked correctly.
> 
> Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
> Now I am even more confused.
> Which is the correct clock to use for the mfg power domains?

I tested MFG domain power on/off with MFG_SEL "OFF". If MFG domain use
MFG_SEL as its bus clock, it will be timeout while waiting SRAM ACK. But
in my test, MFG power domain can power on/off without MFG_SEL. That
means it doesn't need MFG_SEL while power on/off MFG domains.

> >
> > My patch set yesterday add subsystem clocks, which are not needed by
> > power domain on/off. So I think these 2 patch set are independent.
> 
> In other versions of the SCPSYS patch set, the scpsys node has
> additional "subsystem bus clocks".

That's my fault because I provided wrong information to Sascha. So in
his early version of mtk-scpsys driver, the clocks setting of power
domains are incorrect. The correct clock setting for each power domain
should be:

POWER_DOMAIN_MFG:     clk26m (no need to enable topckgen clocks)
POWER_DOMAIN_DISP:    mm_sel
POWER_DOMAIN_VDEC:    mm_sel
POWER_DOMAIN_VENC:    mm_sel
POWER_DOMAIN_VENC_LT: mm_sel
POWER_DOMAIN_ISP:     mm_sel

> So will we need additional patches later to add back these additional
> clocks which have been removed from the current version of this pach?

No. Clocks provided by topckgen are enough for scpsys driver. Please see
my comments below.

> In other words, will there be a follow up patch like below, plus
> another patch to add these clocks to "enum clk_id":
> 
> @@ -163,9 +163,12 @@
>   compatible = "mediatek,mt8173-scpsys";
>   #power-domain-cells = <1>;
>   reg = <0 0x10006000 0 0x1000>;
> - clocks = <&clk26m>,
> - <&topckgen CLK_TOP_MM_SEL>;
> - clock-names = "mfg", "mm";
> + clocks = <&topckgen CLK_TOP_MFG_SEL>,
> + <&topckgen CLK_TOP_MM_SEL>,
> + <&topckgen CLK_TOP_VDEC_SEL>,
> + <&topckgen CLK_TOP_VENC_SEL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
>   infracfg = <&infracfg>;
>   };

These clocks come from topckgen. In our term, they are "top clocks".
Subsystem clocks which mentioned in my patch set are provided by
subsystems such as mmsys, vdecsys, vencsys and so on.


Best regards,

James

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[James Liao]

Hi Daniel,

On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
> On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> >
> > Sascha is right. I had confirmed with our designer that MFG on MT8173
> > uses clk26m to check state. I also tested MFG domain power on/off with
> > CLK_TOP_MFG_SEL off and it worked correctly.
> 
> Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
> Now I am even more confused.
> Which is the correct clock to use for the mfg power domains?

I tested MFG domain power on/off with MFG_SEL "OFF". If MFG domain use
MFG_SEL as its bus clock, it will be timeout while waiting SRAM ACK. But
in my test, MFG power domain can power on/off without MFG_SEL. That
means it doesn't need MFG_SEL while power on/off MFG domains.

> >
> > My patch set yesterday add subsystem clocks, which are not needed by
> > power domain on/off. So I think these 2 patch set are independent.
> 
> In other versions of the SCPSYS patch set, the scpsys node has
> additional "subsystem bus clocks".

That's my fault because I provided wrong information to Sascha. So in
his early version of mtk-scpsys driver, the clocks setting of power
domains are incorrect. The correct clock setting for each power domain
should be:

POWER_DOMAIN_MFG:     clk26m (no need to enable topckgen clocks)
POWER_DOMAIN_DISP:    mm_sel
POWER_DOMAIN_VDEC:    mm_sel
POWER_DOMAIN_VENC:    mm_sel
POWER_DOMAIN_VENC_LT: mm_sel
POWER_DOMAIN_ISP:     mm_sel

> So will we need additional patches later to add back these additional
> clocks which have been removed from the current version of this pach?

No. Clocks provided by topckgen are enough for scpsys driver. Please see
my comments below.

> In other words, will there be a follow up patch like below, plus
> another patch to add these clocks to "enum clk_id":
> 
> @@ -163,9 +163,12 @@
>   compatible = "mediatek,mt8173-scpsys";
>   #power-domain-cells = <1>;
>   reg = <0 0x10006000 0 0x1000>;
> - clocks = <&clk26m>,
> - <&topckgen CLK_TOP_MM_SEL>;
> - clock-names = "mfg", "mm";
> + clocks = <&topckgen CLK_TOP_MFG_SEL>,
> + <&topckgen CLK_TOP_MM_SEL>,
> + <&topckgen CLK_TOP_VDEC_SEL>,
> + <&topckgen CLK_TOP_VENC_SEL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
>   infracfg = <&infracfg>;
>   };

These clocks come from topckgen. In our term, they are "top clocks".
Subsystem clocks which mentioned in my patch set are provided by
subsystems such as mmsys, vdecsys, vencsys and so on.


Best regards,

James

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[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[James Liao]

Hi Daniel,

On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
> On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao@mediatek.com> wrote:
> >
> > Sascha is right. I had confirmed with our designer that MFG on MT8173
> > uses clk26m to check state. I also tested MFG domain power on/off with
> > CLK_TOP_MFG_SEL off and it worked correctly.
> 
> Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
> Now I am even more confused.
> Which is the correct clock to use for the mfg power domains?

I tested MFG domain power on/off with MFG_SEL "OFF". If MFG domain use
MFG_SEL as its bus clock, it will be timeout while waiting SRAM ACK. But
in my test, MFG power domain can power on/off without MFG_SEL. That
means it doesn't need MFG_SEL while power on/off MFG domains.

> >
> > My patch set yesterday add subsystem clocks, which are not needed by
> > power domain on/off. So I think these 2 patch set are independent.
> 
> In other versions of the SCPSYS patch set, the scpsys node has
> additional "subsystem bus clocks".

That's my fault because I provided wrong information to Sascha. So in
his early version of mtk-scpsys driver, the clocks setting of power
domains are incorrect. The correct clock setting for each power domain
should be:

POWER_DOMAIN_MFG:     clk26m (no need to enable topckgen clocks)
POWER_DOMAIN_DISP:    mm_sel
POWER_DOMAIN_VDEC:    mm_sel
POWER_DOMAIN_VENC:    mm_sel
POWER_DOMAIN_VENC_LT: mm_sel
POWER_DOMAIN_ISP:     mm_sel

> So will we need additional patches later to add back these additional
> clocks which have been removed from the current version of this pach?

No. Clocks provided by topckgen are enough for scpsys driver. Please see
my comments below.

> In other words, will there be a follow up patch like below, plus
> another patch to add these clocks to "enum clk_id":
> 
> @@ -163,9 +163,12 @@
>   compatible = "mediatek,mt8173-scpsys";
>   #power-domain-cells = <1>;
>   reg = <0 0x10006000 0 0x1000>;
> - clocks = <&clk26m>,
> - <&topckgen CLK_TOP_MM_SEL>;
> - clock-names = "mfg", "mm";
> + clocks = <&topckgen CLK_TOP_MFG_SEL>,
> + <&topckgen CLK_TOP_MM_SEL>,
> + <&topckgen CLK_TOP_VDEC_SEL>,
> + <&topckgen CLK_TOP_VENC_SEL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
>   infracfg = <&infracfg>;
>   };

These clocks come from topckgen. In our term, they are "top clocks".
Subsystem clocks which mentioned in my patch set are provided by
subsystems such as mmsys, vdecsys, vencsys and so on.


Best regards,

James

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao@mediatek.com> wrote:
> Hi Daniel,
>
> On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
>> On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
>> > > +               scpsys: scpsys@10006000 {
>> > > +                       compatible = "mediatek,mt8173-scpsys";
>> > > +                       #power-domain-cells = <1>;
>> > > +                       reg = <0 0x10006000 0 0x1000>;
>> > > +                       clocks = <&clk26m>,
>> >
>> > Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
>>
>> Because James Liao said to me that it is derived from clk26m and not
>> from mfg_sel.
>
> Sascha is right. I had confirmed with our designer that MFG on MT8173
> uses clk26m to check state. I also tested MFG domain power on/off with
> CLK_TOP_MFG_SEL off and it worked correctly.

Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
Now I am even more confused.
Which is the correct clock to use for the mfg power domains?

>
>> > I saw another patch set on the list today from James Liao that adds more clocks.
>> > Perhaps we can move the SCPSYS set on top of that one and include more clocks?
>> >
>> > > +                                <&topckgen CLK_TOP_MM_SEL>;
>
> The clocks used by scpsys driver are subsystem bus clocks that need to
> be on before power on these domains. On MT8173, subsystem bus clocks are
> come from topckgen.
>
> My patch set yesterday add subsystem clocks, which are not needed by
> power domain on/off. So I think these 2 patch set are independent.

In other versions of the SCPSYS patch set, the scpsys node has
additional "subsystem bus clocks".
So will we need additional patches later to add back these additional
clocks which have been removed from the current version of this pach?
In other words, will there be a follow up patch like below, plus
another patch to add these clocks to "enum clk_id":

@@ -163,9 +163,12 @@
  compatible = "mediatek,mt8173-scpsys";
  #power-domain-cells = <1>;
  reg = <0 0x10006000 0 0x1000>;
- clocks = <&clk26m>,
- <&topckgen CLK_TOP_MM_SEL>;
- clock-names = "mfg", "mm";
+ clocks = <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
  infracfg = <&infracfg>;
  };


@@ -57,7 +57,10 @@ enum clk_id {
  MT8173_CLK_NONE,
  MT8173_CLK_MM,
  MT8173_CLK_MFG,
- MT8173_CLK_MAX = MT8173_CLK_MFG,
+ MT8173_CLK_VDEC,
+ MT8173_CLK_VENC,
+ MT8173_CLK_VENC_LT,
+ MT8173_CLK_MAX = MT8173_CLK_VENC_LT,
 };


If so, is there a reason we cannot just include these clocks in the
current version of the SCPSYS driver?

Best,
-Dan

>
>
> Best regards,
>
> James
>
>

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao@mediatek.com> wrote:
> Hi Daniel,
>
> On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
>> On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
>> > > +               scpsys: scpsys@10006000 {
>> > > +                       compatible = "mediatek,mt8173-scpsys";
>> > > +                       #power-domain-cells = <1>;
>> > > +                       reg = <0 0x10006000 0 0x1000>;
>> > > +                       clocks = <&clk26m>,
>> >
>> > Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
>>
>> Because James Liao said to me that it is derived from clk26m and not
>> from mfg_sel.
>
> Sascha is right. I had confirmed with our designer that MFG on MT8173
> uses clk26m to check state. I also tested MFG domain power on/off with
> CLK_TOP_MFG_SEL off and it worked correctly.

Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
Now I am even more confused.
Which is the correct clock to use for the mfg power domains?

>
>> > I saw another patch set on the list today from James Liao that adds more clocks.
>> > Perhaps we can move the SCPSYS set on top of that one and include more clocks?
>> >
>> > > +                                <&topckgen CLK_TOP_MM_SEL>;
>
> The clocks used by scpsys driver are subsystem bus clocks that need to
> be on before power on these domains. On MT8173, subsystem bus clocks are
> come from topckgen.
>
> My patch set yesterday add subsystem clocks, which are not needed by
> power domain on/off. So I think these 2 patch set are independent.

In other versions of the SCPSYS patch set, the scpsys node has
additional "subsystem bus clocks".
So will we need additional patches later to add back these additional
clocks which have been removed from the current version of this pach?
In other words, will there be a follow up patch like below, plus
another patch to add these clocks to "enum clk_id":

@@ -163,9 +163,12 @@
  compatible = "mediatek,mt8173-scpsys";
  #power-domain-cells = <1>;
  reg = <0 0x10006000 0 0x1000>;
- clocks = <&clk26m>,
- <&topckgen CLK_TOP_MM_SEL>;
- clock-names = "mfg", "mm";
+ clocks = <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
  infracfg = <&infracfg>;
  };


@@ -57,7 +57,10 @@ enum clk_id {
  MT8173_CLK_NONE,
  MT8173_CLK_MM,
  MT8173_CLK_MFG,
- MT8173_CLK_MAX = MT8173_CLK_MFG,
+ MT8173_CLK_VDEC,
+ MT8173_CLK_VENC,
+ MT8173_CLK_VENC_LT,
+ MT8173_CLK_MAX = MT8173_CLK_VENC_LT,
 };


If so, is there a reason we cannot just include these clocks in the
current version of the SCPSYS driver?

Best,
-Dan

>
>
> Best regards,
>
> James
>
>

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

On Fri, May 22, 2015 at 10:41 AM, James Liao <jamesjj.liao@mediatek.com> wrote:
> Hi Daniel,
>
> On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
>> On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
>> > > +               scpsys: scpsys at 10006000 {
>> > > +                       compatible = "mediatek,mt8173-scpsys";
>> > > +                       #power-domain-cells = <1>;
>> > > +                       reg = <0 0x10006000 0 0x1000>;
>> > > +                       clocks = <&clk26m>,
>> >
>> > Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
>>
>> Because James Liao said to me that it is derived from clk26m and not
>> from mfg_sel.
>
> Sascha is right. I had confirmed with our designer that MFG on MT8173
> uses clk26m to check state. I also tested MFG domain power on/off with
> CLK_TOP_MFG_SEL off and it worked correctly.

Wait - the designer said to use clk26m, but you tested with CLK_TOP_MFG_SEL.
Now I am even more confused.
Which is the correct clock to use for the mfg power domains?

>
>> > I saw another patch set on the list today from James Liao that adds more clocks.
>> > Perhaps we can move the SCPSYS set on top of that one and include more clocks?
>> >
>> > > +                                <&topckgen CLK_TOP_MM_SEL>;
>
> The clocks used by scpsys driver are subsystem bus clocks that need to
> be on before power on these domains. On MT8173, subsystem bus clocks are
> come from topckgen.
>
> My patch set yesterday add subsystem clocks, which are not needed by
> power domain on/off. So I think these 2 patch set are independent.

In other versions of the SCPSYS patch set, the scpsys node has
additional "subsystem bus clocks".
So will we need additional patches later to add back these additional
clocks which have been removed from the current version of this pach?
In other words, will there be a follow up patch like below, plus
another patch to add these clocks to "enum clk_id":

@@ -163,9 +163,12 @@
  compatible = "mediatek,mt8173-scpsys";
  #power-domain-cells = <1>;
  reg = <0 0x10006000 0 0x1000>;
- clocks = <&clk26m>,
- <&topckgen CLK_TOP_MM_SEL>;
- clock-names = "mfg", "mm";
+ clocks = <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mfg", "mm", "vdec", "venc", "venc_lt";
  infracfg = <&infracfg>;
  };


@@ -57,7 +57,10 @@ enum clk_id {
  MT8173_CLK_NONE,
  MT8173_CLK_MM,
  MT8173_CLK_MFG,
- MT8173_CLK_MAX = MT8173_CLK_MFG,
+ MT8173_CLK_VDEC,
+ MT8173_CLK_VENC,
+ MT8173_CLK_VENC_LT,
+ MT8173_CLK_MAX = MT8173_CLK_VENC_LT,
 };


If so, is there a reason we cannot just include these clocks in the
current version of the SCPSYS driver?

Best,
-Dan

>
>
> Best regards,
>
> James
>
>

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[James Liao]

Hi Daniel,

On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
> On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
> > > +               scpsys: scpsys@10006000 {
> > > +                       compatible = "mediatek,mt8173-scpsys";
> > > +                       #power-domain-cells = <1>;
> > > +                       reg = <0 0x10006000 0 0x1000>;
> > > +                       clocks = <&clk26m>,
> > 
> > Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
> 
> Because James Liao said to me that it is derived from clk26m and not
> from mfg_sel.

Sascha is right. I had confirmed with our designer that MFG on MT8173
uses clk26m to check state. I also tested MFG domain power on/off with
CLK_TOP_MFG_SEL off and it worked correctly.

> > I saw another patch set on the list today from James Liao that adds more clocks.
> > Perhaps we can move the SCPSYS set on top of that one and include more clocks?
> > 
> > > +                                <&topckgen CLK_TOP_MM_SEL>;

The clocks used by scpsys driver are subsystem bus clocks that need to
be on before power on these domains. On MT8173, subsystem bus clocks are
come from topckgen.

My patch set yesterday add subsystem clocks, which are not needed by
power domain on/off. So I think these 2 patch set are independent.


Best regards,

James

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[James Liao]

Hi Daniel,

On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
> On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
> > > +               scpsys: scpsys@10006000 {
> > > +                       compatible = "mediatek,mt8173-scpsys";
> > > +                       #power-domain-cells = <1>;
> > > +                       reg = <0 0x10006000 0 0x1000>;
> > > +                       clocks = <&clk26m>,
> > 
> > Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
> 
> Because James Liao said to me that it is derived from clk26m and not
> from mfg_sel.

Sascha is right. I had confirmed with our designer that MFG on MT8173
uses clk26m to check state. I also tested MFG domain power on/off with
CLK_TOP_MFG_SEL off and it worked correctly.

> > I saw another patch set on the list today from James Liao that adds more clocks.
> > Perhaps we can move the SCPSYS set on top of that one and include more clocks?
> > 
> > > +                                <&topckgen CLK_TOP_MM_SEL>;

The clocks used by scpsys driver are subsystem bus clocks that need to
be on before power on these domains. On MT8173, subsystem bus clocks are
come from topckgen.

My patch set yesterday add subsystem clocks, which are not needed by
power domain on/off. So I think these 2 patch set are independent.


Best regards,

James

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[James Liao]

Hi Daniel,

On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
> On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
> > > +               scpsys: scpsys at 10006000 {
> > > +                       compatible = "mediatek,mt8173-scpsys";
> > > +                       #power-domain-cells = <1>;
> > > +                       reg = <0 0x10006000 0 0x1000>;
> > > +                       clocks = <&clk26m>,
> > 
> > Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
> 
> Because James Liao said to me that it is derived from clk26m and not
> from mfg_sel.

Sascha is right. I had confirmed with our designer that MFG on MT8173
uses clk26m to check state. I also tested MFG domain power on/off with
CLK_TOP_MFG_SEL off and it worked correctly.

> > I saw another patch set on the list today from James Liao that adds more clocks.
> > Perhaps we can move the SCPSYS set on top of that one and include more clocks?
> > 
> > > +                                <&topckgen CLK_TOP_MM_SEL>;

The clocks used by scpsys driver are subsystem bus clocks that need to
be on before power on these domains. On MT8173, subsystem bus clocks are
come from topckgen.

My patch set yesterday add subsystem clocks, which are not needed by
power domain on/off. So I think these 2 patch set are independent.


Best regards,

James

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
> On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > This adds the SCPSYS device node to the MT8173 dtsi file.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 924fdb6..12430f0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -125,6 +125,16 @@
> >                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> >                 };
> >
> > +               scpsys: scpsys@10006000 {
> > +                       compatible = "mediatek,mt8173-scpsys";
> > +                       #power-domain-cells = <1>;
> > +                       reg = <0 0x10006000 0 0x1000>;
> > +                       clocks = <&clk26m>,
> 
> Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?

Because James Liao said to me that it is derived from clk26m and not
from mfg_sel.

> I saw another patch set on the list today from James Liao that adds more clocks.
> Perhaps we can move the SCPSYS set on top of that one and include more clocks?
> 
> > +                                <&topckgen CLK_TOP_MM_SEL>;
> 
> FYI: the devicetree changes in this set depend on your other patch set
> starting with:
> 
> https://patchwork.kernel.org/patch/6446341/
> "arm64: dts: mt8173: Add clock controller device nodes"
> 
> This patch isn't based on top of the other set, though, so it may lead
> to a small merge conflict when folding in the .dtsi device nodes (ie,
> placing scpsys@10006000 after pwrap@1000d000).
> 
> I'm not sure how people usually resolve this or manage the ordering of
> co-dependent patch sets upstream.

This merge conflict should be easy to solve. However, I can rebase this
on Matthias' dts branch if desired.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
> On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > This adds the SCPSYS device node to the MT8173 dtsi file.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 924fdb6..12430f0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -125,6 +125,16 @@
> >                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> >                 };
> >
> > +               scpsys: scpsys@10006000 {
> > +                       compatible = "mediatek,mt8173-scpsys";
> > +                       #power-domain-cells = <1>;
> > +                       reg = <0 0x10006000 0 0x1000>;
> > +                       clocks = <&clk26m>,
> 
> Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?

Because James Liao said to me that it is derived from clk26m and not
from mfg_sel.

> I saw another patch set on the list today from James Liao that adds more clocks.
> Perhaps we can move the SCPSYS set on top of that one and include more clocks?
> 
> > +                                <&topckgen CLK_TOP_MM_SEL>;
> 
> FYI: the devicetree changes in this set depend on your other patch set
> starting with:
> 
> https://patchwork.kernel.org/patch/6446341/
> "arm64: dts: mt8173: Add clock controller device nodes"
> 
> This patch isn't based on top of the other set, though, so it may lead
> to a small merge conflict when folding in the .dtsi device nodes (ie,
> placing scpsys@10006000 after pwrap@1000d000).
> 
> I'm not sure how people usually resolve this or manage the ordering of
> co-dependent patch sets upstream.

This merge conflict should be easy to solve. However, I can rebase this
on Matthias' dts branch if desired.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
> On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > This adds the SCPSYS device node to the MT8173 dtsi file.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 924fdb6..12430f0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -125,6 +125,16 @@
> >                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> >                 };
> >
> > +               scpsys: scpsys at 10006000 {
> > +                       compatible = "mediatek,mt8173-scpsys";
> > +                       #power-domain-cells = <1>;
> > +                       reg = <0 0x10006000 0 0x1000>;
> > +                       clocks = <&clk26m>,
> 
> Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?

Because James Liao said to me that it is derived from clk26m and not
from mfg_sel.

> I saw another patch set on the list today from James Liao that adds more clocks.
> Perhaps we can move the SCPSYS set on top of that one and include more clocks?
> 
> > +                                <&topckgen CLK_TOP_MM_SEL>;
> 
> FYI: the devicetree changes in this set depend on your other patch set
> starting with:
> 
> https://patchwork.kernel.org/patch/6446341/
> "arm64: dts: mt8173: Add clock controller device nodes"
> 
> This patch isn't based on top of the other set, though, so it may lead
> to a small merge conflict when folding in the .dtsi device nodes (ie,
> placing scpsys at 10006000 after pwrap at 1000d000).
> 
> I'm not sure how people usually resolve this or manage the ordering of
> co-dependent patch sets upstream.

This merge conflict should be easy to solve. However, I can rebase this
on Matthias' dts branch if desired.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Matthias Brugger]

2015-05-21 16:32 GMT+02:00 Daniel Kurtz <djkurtz@chromium.org>:
> On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> This adds the SCPSYS device node to the MT8173 dtsi file.
>>
>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>> ---
>>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> index 924fdb6..12430f0 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> @@ -125,6 +125,16 @@
>>                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>>                 };
>>
>> +               scpsys: scpsys@10006000 {
>> +                       compatible = "mediatek,mt8173-scpsys";
>> +                       #power-domain-cells = <1>;
>> +                       reg = <0 0x10006000 0 0x1000>;
>> +                       clocks = <&clk26m>,
>
> Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
> I saw another patch set on the list today from James Liao that adds more clocks.
> Perhaps we can move the SCPSYS set on top of that one and include more clocks?
>
>> +                                <&topckgen CLK_TOP_MM_SEL>;
>
> FYI: the devicetree changes in this set depend on your other patch set
> starting with:
>
> https://patchwork.kernel.org/patch/6446341/
> "arm64: dts: mt8173: Add clock controller device nodes"
>
> This patch isn't based on top of the other set, though, so it may lead
> to a small merge conflict when folding in the .dtsi device nodes (ie,
> placing scpsys@10006000 after pwrap@1000d000).
>
> I'm not sure how people usually resolve this or manage the ordering of
> co-dependent patch sets upstream.

At the moment I suppose that patch-sets are based on -rc1 if not
stated different.

-- 
motzblog.wordpress.com

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Matthias Brugger]

2015-05-21 16:32 GMT+02:00 Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>:
> On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>> This adds the SCPSYS device node to the MT8173 dtsi file.
>>
>> Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> ---
>>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> index 924fdb6..12430f0 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> @@ -125,6 +125,16 @@
>>                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>>                 };
>>
>> +               scpsys: scpsys@10006000 {
>> +                       compatible = "mediatek,mt8173-scpsys";
>> +                       #power-domain-cells = <1>;
>> +                       reg = <0 0x10006000 0 0x1000>;
>> +                       clocks = <&clk26m>,
>
> Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
> I saw another patch set on the list today from James Liao that adds more clocks.
> Perhaps we can move the SCPSYS set on top of that one and include more clocks?
>
>> +                                <&topckgen CLK_TOP_MM_SEL>;
>
> FYI: the devicetree changes in this set depend on your other patch set
> starting with:
>
> https://patchwork.kernel.org/patch/6446341/
> "arm64: dts: mt8173: Add clock controller device nodes"
>
> This patch isn't based on top of the other set, though, so it may lead
> to a small merge conflict when folding in the .dtsi device nodes (ie,
> placing scpsys@10006000 after pwrap@1000d000).
>
> I'm not sure how people usually resolve this or manage the ordering of
> co-dependent patch sets upstream.

At the moment I suppose that patch-sets are based on -rc1 if not
stated different.

-- 
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[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Matthias Brugger]

2015-05-21 16:32 GMT+02:00 Daniel Kurtz <djkurtz@chromium.org>:
> On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> This adds the SCPSYS device node to the MT8173 dtsi file.
>>
>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>> ---
>>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> index 924fdb6..12430f0 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> @@ -125,6 +125,16 @@
>>                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>>                 };
>>
>> +               scpsys: scpsys at 10006000 {
>> +                       compatible = "mediatek,mt8173-scpsys";
>> +                       #power-domain-cells = <1>;
>> +                       reg = <0 0x10006000 0 0x1000>;
>> +                       clocks = <&clk26m>,
>
> Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
> I saw another patch set on the list today from James Liao that adds more clocks.
> Perhaps we can move the SCPSYS set on top of that one and include more clocks?
>
>> +                                <&topckgen CLK_TOP_MM_SEL>;
>
> FYI: the devicetree changes in this set depend on your other patch set
> starting with:
>
> https://patchwork.kernel.org/patch/6446341/
> "arm64: dts: mt8173: Add clock controller device nodes"
>
> This patch isn't based on top of the other set, though, so it may lead
> to a small merge conflict when folding in the .dtsi device nodes (ie,
> placing scpsys at 10006000 after pwrap at 1000d000).
>
> I'm not sure how people usually resolve this or manage the ordering of
> co-dependent patch sets upstream.

At the moment I suppose that patch-sets are based on -rc1 if not
stated different.

-- 
motzblog.wordpress.com

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 924fdb6..12430f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -125,6 +125,16 @@
>                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>
> +               scpsys: scpsys@10006000 {
> +                       compatible = "mediatek,mt8173-scpsys";
> +                       #power-domain-cells = <1>;
> +                       reg = <0 0x10006000 0 0x1000>;
> +                       clocks = <&clk26m>,

Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
I saw another patch set on the list today from James Liao that adds more clocks.
Perhaps we can move the SCPSYS set on top of that one and include more clocks?

> +                                <&topckgen CLK_TOP_MM_SEL>;

FYI: the devicetree changes in this set depend on your other patch set
starting with:

https://patchwork.kernel.org/patch/6446341/
"arm64: dts: mt8173: Add clock controller device nodes"

This patch isn't based on top of the other set, though, so it may lead
to a small merge conflict when folding in the .dtsi device nodes (ie,
placing scpsys@10006000 after pwrap@1000d000).

I'm not sure how people usually resolve this or manage the ordering of
co-dependent patch sets upstream.

-Dan

> +                       clock-names = "mfg", "mm";
> +                       infracfg = <&infracfg>;
> +               };
> +
>                 sysirq: intpol-controller@10200620 {
>                         compatible = "mediatek,mt8173-sysirq",
>                                         "mediatek,mt6577-sysirq";
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 924fdb6..12430f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -125,6 +125,16 @@
>                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>
> +               scpsys: scpsys@10006000 {
> +                       compatible = "mediatek,mt8173-scpsys";
> +                       #power-domain-cells = <1>;
> +                       reg = <0 0x10006000 0 0x1000>;
> +                       clocks = <&clk26m>,

Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
I saw another patch set on the list today from James Liao that adds more clocks.
Perhaps we can move the SCPSYS set on top of that one and include more clocks?

> +                                <&topckgen CLK_TOP_MM_SEL>;

FYI: the devicetree changes in this set depend on your other patch set
starting with:

https://patchwork.kernel.org/patch/6446341/
"arm64: dts: mt8173: Add clock controller device nodes"

This patch isn't based on top of the other set, though, so it may lead
to a small merge conflict when folding in the .dtsi device nodes (ie,
placing scpsys@10006000 after pwrap@1000d000).

I'm not sure how people usually resolve this or manage the ordering of
co-dependent patch sets upstream.

-Dan

> +                       clock-names = "mfg", "mm";
> +                       infracfg = <&infracfg>;
> +               };
> +
>                 sysirq: intpol-controller@10200620 {
>                         compatible = "mediatek,mt8173-sysirq",
>                                         "mediatek,mt6577-sysirq";
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Daniel Kurtz]

On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 924fdb6..12430f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -125,6 +125,16 @@
>                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>
> +               scpsys: scpsys at 10006000 {
> +                       compatible = "mediatek,mt8173-scpsys";
> +                       #power-domain-cells = <1>;
> +                       reg = <0 0x10006000 0 0x1000>;
> +                       clocks = <&clk26m>,

Why is mfg using <&clk26m> and not <&topckgen CLK_TOP_MFG_SEL>?
I saw another patch set on the list today from James Liao that adds more clocks.
Perhaps we can move the SCPSYS set on top of that one and include more clocks?

> +                                <&topckgen CLK_TOP_MM_SEL>;

FYI: the devicetree changes in this set depend on your other patch set
starting with:

https://patchwork.kernel.org/patch/6446341/
"arm64: dts: mt8173: Add clock controller device nodes"

This patch isn't based on top of the other set, though, so it may lead
to a small merge conflict when folding in the .dtsi device nodes (ie,
placing scpsys at 10006000 after pwrap at 1000d000).

I'm not sure how people usually resolve this or manage the ordering of
co-dependent patch sets upstream.

-Dan

> +                       clock-names = "mfg", "mm";
> +                       infracfg = <&infracfg>;
> +               };
> +
>                 sysirq: intpol-controller at 10200620 {
>                         compatible = "mediatek,mt8173-sysirq",
>                                         "mediatek,mt6577-sysirq";
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

This adds the SCPSYS device node to the MT8173 dtsi file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..12430f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,16 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		scpsys: scpsys@10006000 {
+			compatible = "mediatek,mt8173-scpsys";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&clk26m>,
+				 <&topckgen CLK_TOP_MM_SEL>;
+			clock-names = "mfg", "mm";
+			infracfg = <&infracfg>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
2.1.4

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

This adds the SCPSYS device node to the MT8173 dtsi file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..12430f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,16 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		scpsys: scpsys at 10006000 {
+			compatible = "mediatek,mt8173-scpsys";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&clk26m>,
+				 <&topckgen CLK_TOP_MM_SEL>;
+			clock-names = "mfg", "mm";
+			infracfg = <&infracfg>;
+		};
+
 		sysirq: intpol-controller at 10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
2.1.4

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

This adds the SCPSYS device node to the MT8173 dtsi file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..3c569b5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,18 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		scpsys: scpsys@10006000 {
+			compatible = "mediatek,mt8173-scpsys";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+				<&topckgen CLK_TOP_MFG_SEL>,
+				<&topckgen CLK_TOP_VENC_SEL>,
+				<&topckgen CLK_TOP_MM_SEL>,
+				<&topckgen CLK_TOP_VENC_LT_SEL>;
+			clock-names = "vdec", "mfg", "venc", "disp", "ven2";
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
2.1.4

[PATCH 5/5] ARM64: MediaTek MT8173: Add SCPSYS device node

[Sascha Hauer]

This adds the SCPSYS device node to the MT8173 dtsi file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..3c569b5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,18 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		scpsys: scpsys at 10006000 {
+			compatible = "mediatek,mt8173-scpsys";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+				<&topckgen CLK_TOP_MFG_SEL>,
+				<&topckgen CLK_TOP_VENC_SEL>,
+				<&topckgen CLK_TOP_MM_SEL>,
+				<&topckgen CLK_TOP_VENC_LT_SEL>;
+			clock-names = "vdec", "mfg", "venc", "disp", "ven2";
+		};
+
 		sysirq: intpol-controller at 10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
2.1.4