From: Paul Eggert <eggert@cs.ucla.edu>
To: Szabolcs Nagy <szabolcs.nagy@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arch@vger.kernel.org,
Richard Earnshaw <Richard.Earnshaw@arm.com>,
nd@arm.com, libc-alpha@sourceware.org,
Will Deacon <will@kernel.org>,
Andrey Konovalov <andreyknvl@google.com>,
Kevin Brodsky <kevin.brodsky@arm.com>,
linux-mm@kvack.org, Matthew Malcomson <Matthew.Malcomson@arm.com>,
Andrew Morton <akpm@linux-foundation.org>,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
Peter Collingbourne <pcc@google.com>,
Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 29/29] arm64: mte: Add Memory Tagging Extension documentation
Date: Thu, 20 Aug 2020 10:27:43 -0700 [thread overview]
Message-ID: <80a8937b-6e48-44ce-221c-84c6d27b211d@cs.ucla.edu> (raw)
In-Reply-To: <20200820164313.GL29343@arm.com>
On 8/20/20 9:43 AM, Szabolcs Nagy wrote:
> the compat issue with this is existing code
> using pointer top bits which i assume faults
> when dereferenced with the mte checks enabled.
> (although this should be very rare since
> top byte ignore on deref is aarch64 specific.)
Does anyone know of significant aarch64-specific application code that depends
on top byte ignore? I would think it's so rare (nonexistent?) as to not be worth
worrying about.
Even in the bad old days when Emacs used pointer top bits for typechecking, it
carefully removed those bits before dereferencing. Any other reasonably-portable
application would have to do the same of course.
This whole thing reminds me of the ancient IBM S/360 mainframes that were
documented to ignore the top 8 bits of 32-bit addresses merely because a single
model (the IBM 360/30, circa 1965) was so underpowered that it couldn't quickly
check that the top bits were zero. This has caused countless software hassles
over the years. Even today, the IBM z-Series hardware and software still
supports 24-bit addressing mode because of that early-1960s design mistake. See:
Mashey JR. The Long Road to 64 Bits. ACM Queue. 2006-10-10.
https://queue.acm.org/detail.cfm?id=1165766
WARNING: multiple messages have this Message-ID (diff)
From: Paul Eggert <eggert@cs.ucla.edu>
To: Szabolcs Nagy <szabolcs.nagy@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arch@vger.kernel.org,
Richard Earnshaw <Richard.Earnshaw@arm.com>,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
libc-alpha@sourceware.org, Peter Collingbourne <pcc@google.com>,
Andrey Konovalov <andreyknvl@google.com>,
Kevin Brodsky <kevin.brodsky@arm.com>,
linux-mm@kvack.org, Matthew Malcomson <Matthew.Malcomson@arm.com>,
Andrew Morton <akpm@linux-foundation.org>,
nd@arm.com, Will Deacon <will@kernel.org>,
Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 29/29] arm64: mte: Add Memory Tagging Extension documentation
Date: Thu, 20 Aug 2020 10:27:43 -0700 [thread overview]
Message-ID: <80a8937b-6e48-44ce-221c-84c6d27b211d@cs.ucla.edu> (raw)
In-Reply-To: <20200820164313.GL29343@arm.com>
On 8/20/20 9:43 AM, Szabolcs Nagy wrote:
> the compat issue with this is existing code
> using pointer top bits which i assume faults
> when dereferenced with the mte checks enabled.
> (although this should be very rare since
> top byte ignore on deref is aarch64 specific.)
Does anyone know of significant aarch64-specific application code that depends
on top byte ignore? I would think it's so rare (nonexistent?) as to not be worth
worrying about.
Even in the bad old days when Emacs used pointer top bits for typechecking, it
carefully removed those bits before dereferencing. Any other reasonably-portable
application would have to do the same of course.
This whole thing reminds me of the ancient IBM S/360 mainframes that were
documented to ignore the top 8 bits of 32-bit addresses merely because a single
model (the IBM 360/30, circa 1965) was so underpowered that it couldn't quickly
check that the top bits were zero. This has caused countless software hassles
over the years. Even today, the IBM z-Series hardware and software still
supports 24-bit addressing mode because of that early-1960s design mistake. See:
Mashey JR. The Long Road to 64 Bits. ACM Queue. 2006-10-10.
https://queue.acm.org/detail.cfm?id=1165766
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next prev parent reply other threads:[~2020-08-20 17:36 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-15 17:08 [PATCH v7 00/26] arm64: Memory Tagging Extension user-space support Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 01/29] arm64: mte: system register definitions Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 02/29] arm64: mte: CPU feature detection and initial sysreg configuration Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 03/29] arm64: mte: Use Normal Tagged attributes for the linear map Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 04/29] arm64: mte: Add specific SIGSEGV codes Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 05/29] arm64: mte: Handle synchronous and asynchronous tag check faults Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 06/29] mm: Add PG_arch_2 page flag Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 07/29] mm: Preserve the PG_arch_2 flag in __split_huge_page_tail() Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 08/29] arm64: mte: Clear the tags when a page is mapped in user-space with PROT_MTE Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 09/29] arm64: mte: Tags-aware copy_{user_,}highpage() implementations Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 10/29] arm64: Avoid unnecessary clear_user_page() indirection Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 11/29] arm64: mte: Tags-aware aware memcmp_pages() implementation Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 12/29] arm64: mte: Handle the MAIR_EL1 changes for late CPU bring-up Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 13/29] mm: Introduce arch_calc_vm_flag_bits() Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 14/29] arm64: mte: Add PROT_MTE support to mmap() and mprotect() Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 15/29] mm: Introduce arch_validate_flags() Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 16/29] arm64: mte: Validate the PROT_MTE request via arch_validate_flags() Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 17/29] mm: Allow arm64 mmap(PROT_MTE) on RAM-based files Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 18/29] arm64: mte: Allow user control of the tag check mode via prctl() Catalin Marinas
2020-07-20 15:30 ` Kevin Brodsky
2020-07-20 15:30 ` Kevin Brodsky
2020-07-20 17:00 ` Dave Martin
2020-07-20 17:00 ` Dave Martin
2020-07-22 10:28 ` Catalin Marinas
2020-07-22 10:28 ` Catalin Marinas
2020-07-23 19:33 ` Kevin Brodsky
2020-07-23 19:33 ` Kevin Brodsky
2020-07-22 11:09 ` Catalin Marinas
2020-07-22 11:09 ` Catalin Marinas
2020-08-04 19:34 ` Kevin Brodsky
2020-08-04 19:34 ` Kevin Brodsky
2020-08-05 9:24 ` Catalin Marinas
2020-08-05 9:24 ` Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 19/29] arm64: mte: Allow user control of the generated random tags " Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 20/29] arm64: mte: Restore the GCR_EL1 register after a suspend Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 21/29] arm64: mte: Allow {set,get}_tagged_addr_ctrl() on non-current tasks Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 22/29] arm64: mte: ptrace: Add PTRACE_{PEEK,POKE}MTETAGS support Catalin Marinas
2020-08-13 14:01 ` Luis Machado
2020-08-13 14:01 ` Luis Machado
2020-08-22 10:56 ` Catalin Marinas
2020-08-22 10:56 ` Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 23/29] arm64: mte: ptrace: Add NT_ARM_TAGGED_ADDR_CTRL regset Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 24/29] fs: Handle intra-page faults in copy_mount_options() Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 25/29] mm: Add arch hooks for saving/restoring tags Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 26/29] arm64: mte: Enable swap of tagged pages Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 27/29] arm64: mte: Save tags when hibernating Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 28/29] arm64: mte: Kconfig entry Catalin Marinas
2020-07-15 17:08 ` [PATCH v7 29/29] arm64: mte: Add Memory Tagging Extension documentation Catalin Marinas
2020-07-27 16:36 ` Szabolcs Nagy
2020-07-27 16:36 ` Szabolcs Nagy
2020-07-28 11:08 ` Dave Martin
2020-07-28 11:08 ` Dave Martin
2020-07-28 14:53 ` Szabolcs Nagy
2020-07-28 14:53 ` Szabolcs Nagy
2020-07-28 19:59 ` Catalin Marinas
2020-07-28 19:59 ` Catalin Marinas
2020-08-03 12:43 ` Szabolcs Nagy
2020-08-03 12:43 ` Szabolcs Nagy
2020-08-07 15:19 ` Catalin Marinas
2020-08-07 15:19 ` Catalin Marinas
2020-08-10 14:13 ` Szabolcs Nagy
2020-08-10 14:13 ` Szabolcs Nagy
2020-08-11 17:20 ` Catalin Marinas
2020-08-11 17:20 ` Catalin Marinas
2020-08-12 12:45 ` Szabolcs Nagy
2020-08-12 12:45 ` Szabolcs Nagy
2020-08-19 9:54 ` Catalin Marinas
2020-08-19 9:54 ` Catalin Marinas
2020-08-20 16:43 ` Szabolcs Nagy
2020-08-20 16:43 ` Szabolcs Nagy
2020-08-20 17:27 ` Paul Eggert [this message]
2020-08-20 17:27 ` Paul Eggert
2020-08-22 11:31 ` Catalin Marinas
2020-08-22 11:31 ` Catalin Marinas
2020-08-22 11:28 ` Catalin Marinas
2020-08-22 11:28 ` Catalin Marinas
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