* [PATCH v2 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
@ 2021-12-06 15:00 ` Biju Das
0 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-06 15:00 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring
Cc: Biju Das, dri-devel, devicetree, linux-clk, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
RZ/G2L SoC embeds Mali-G31 bifrost GPU.
This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 +
out of tree patch for (du + DSI) +
platfrom mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube
Using display 0xaaaadb6e7d30 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
....
===================================
^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost
82: 587287 0 GICv3 186 Level panfrost-job
83: 2 0 GICv3 187 Level panfrost-mmu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================
root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208
Platform specific Mesa patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',
src/gallium/targets/dri/target.c
+DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V1->V2:
* Removed clock patches from this seies, as it is accepted for 5.17
* Added Rb tag from Geert
* Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3):
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++
3 files changed, 115 insertions(+), 2 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
@ 2021-12-06 15:00 ` Biju Das
0 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-06 15:00 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Biju Das, linux-clk
RZ/G2L SoC embeds Mali-G31 bifrost GPU.
This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 +
out of tree patch for (du + DSI) +
platfrom mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube
Using display 0xaaaadb6e7d30 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
....
===================================
^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost
82: 587287 0 GICv3 186 Level panfrost-job
83: 2 0 GICv3 187 Level panfrost-mmu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================
root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208
Platform specific Mesa patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',
src/gallium/targets/dri/target.c
+DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V1->V2:
* Removed clock patches from this seies, as it is accepted for 5.17
* Added Rb tag from Geert
* Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3):
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++
3 files changed, 115 insertions(+), 2 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
2021-12-06 15:00 ` Biju Das
@ 2021-12-06 15:00 ` Biju Das
-1 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-06 15:00 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring
Cc: Biju Das, dri-devel, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
add a compatible string for it.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.
---
.../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++-
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 6f98dd55fb4c..c3b2f4ddd520 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -19,6 +19,7 @@ properties:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
+ - renesas,r9a07g044-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@@ -27,19 +28,30 @@ properties:
maxItems: 1
interrupts:
+ minItems: 3
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
+ - description: EVENT interrupt
interrupt-names:
+ minItems: 3
items:
- const: job
- const: mmu
- const: gpu
+ - const: event
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: gpu
+ - const: bus
+ - const: bus_ace
mali-supply: true
@@ -52,7 +64,14 @@ properties:
maxItems: 3
resets:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
+
+ reset-names:
+ items:
+ - const: rst
+ - const: axi_rst
+ - const: ace_rst
"#cooling-cells":
const: 2
@@ -113,6 +132,22 @@ allOf:
- sram-supply
- power-domains
- power-domain-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g044-mali
+ then:
+ properties:
+ interrupt-names:
+ minItems: 4
+ clock-names:
+ minItems: 3
+ required:
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
else:
properties:
power-domains:
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
@ 2021-12-06 15:00 ` Biju Das
0 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-06 15:00 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Biju Das
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
add a compatible string for it.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.
---
.../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++-
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 6f98dd55fb4c..c3b2f4ddd520 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -19,6 +19,7 @@ properties:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
+ - renesas,r9a07g044-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@@ -27,19 +28,30 @@ properties:
maxItems: 1
interrupts:
+ minItems: 3
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
+ - description: EVENT interrupt
interrupt-names:
+ minItems: 3
items:
- const: job
- const: mmu
- const: gpu
+ - const: event
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: gpu
+ - const: bus
+ - const: bus_ace
mali-supply: true
@@ -52,7 +64,14 @@ properties:
maxItems: 3
resets:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
+
+ reset-names:
+ items:
+ - const: rst
+ - const: axi_rst
+ - const: ace_rst
"#cooling-cells":
const: 2
@@ -113,6 +132,22 @@ allOf:
- sram-supply
- power-domains
- power-domain-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g044-mali
+ then:
+ properties:
+ interrupt-names:
+ minItems: 4
+ clock-names:
+ minItems: 3
+ required:
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
else:
properties:
power-domains:
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/3] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
2021-12-06 15:00 ` Biju Das
(?)
(?)
@ 2021-12-06 15:00 ` Biju Das
-1 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-06 15:00 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add Mali-G31 GPU node to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
* Added reset-names.
* Added Rb tag from Geert
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index f39265e51445..ea1bda166273 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -111,6 +111,50 @@
};
};
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-62500000 {
+ opp-hz = /bits/ 64 <62500000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -637,6 +681,27 @@
dma-channels = <16>;
};
+ gpu: gpu@11840000 {
+ compatible = "renesas,r9a07g044-mali",
+ "arm,mali-bifrost";
+ reg = <0x0 0x11840000 0x0 0x10000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu", "event";
+ clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
+ <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
+ <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
+ clock-names = "gpu", "bus", "bus_ace";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_GPU_RESETN>,
+ <&cpg R9A07G044_GPU_AXI_RESETN>,
+ <&cpg R9A07G044_GPU_ACE_RESETN>;
+ reset-names = "rst", "axi_rst", "ace_rst";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
2021-12-06 15:00 ` Biju Das
` (2 preceding siblings ...)
(?)
@ 2021-12-06 15:00 ` Biju Das
2021-12-07 8:38 ` Sergey Shtylyov
-1 siblings, 1 reply; 13+ messages in thread
From: Biju Das @ 2021-12-06 15:00 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add vdd core regulator (1.1 V).
This patch add regulator support for gpu.
On the H/W manual nothing mentioned about gpu
regulator. So using vdd core regulator for gpu.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
* Added Rb tag from Geert.
---
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index a4fc9517a0de..4ce799314f0f 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -52,6 +52,15 @@
regulator-always-on;
};
+ reg_1p1v: regulator-vdd-core {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@@ -130,6 +139,10 @@
clock-frequency = <24000000>;
};
+&gpu {
+ mali-supply = <®_1p1v>;
+};
+
&ostm1 {
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
2021-12-06 15:00 ` Biju Das
@ 2021-12-06 17:08 ` Robin Murphy
-1 siblings, 0 replies; 13+ messages in thread
From: Robin Murphy @ 2021-12-06 17:08 UTC (permalink / raw)
To: Biju Das, David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Alyssa Rosenzweig, tomeu.vizoso, Steven Price
On 2021-12-06 15:00, Biju Das wrote:
> The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
> add a compatible string for it.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Updated minItems for resets as 2
> * Documented optional property reset-names
> * Documented reset-names as required property for RZ/G2L SoC.
> ---
> .../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++-
> 1 file changed, 37 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> index 6f98dd55fb4c..c3b2f4ddd520 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> @@ -19,6 +19,7 @@ properties:
> - amlogic,meson-g12a-mali
> - mediatek,mt8183-mali
> - realtek,rtd1619-mali
> + - renesas,r9a07g044-mali
> - rockchip,px30-mali
> - rockchip,rk3568-mali
> - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
> @@ -27,19 +28,30 @@ properties:
> maxItems: 1
>
> interrupts:
> + minItems: 3
> items:
> - description: Job interrupt
> - description: MMU interrupt
> - description: GPU interrupt
> + - description: EVENT interrupt
I believe we haven't bothered with the "Event" interrupt so far since
there's no real meaningful use for it - it seems the downstream binding
for Arm's kbase driver doesn't mention it either.
> interrupt-names:
> + minItems: 3
> items:
> - const: job
> - const: mmu
> - const: gpu
> + - const: event
>
> clocks:
> - maxItems: 1
> + minItems: 1
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: gpu
> + - const: bus
> + - const: bus_ace
Note that the Bifrost GPUs themselves all only have a single external
clock and reset (unexcitingly named "CLK" and "RESETn" respectively,
FWIW). I can't help feeling wary that defining additional names for
vendor integration details in the core binding may quickly grow into a
mess of mutually-incompatible sets of values, for no great benefit. At
the very least, it would seem more sensible to put them in the
SoC-specific conditional schemas.
Robin.
>
> mali-supply: true
>
> @@ -52,7 +64,14 @@ properties:
> maxItems: 3
>
> resets:
> - maxItems: 2
> + minItems: 2
> + maxItems: 3
> +
> + reset-names:
> + items:
> + - const: rst
> + - const: axi_rst
> + - const: ace_rst
>
> "#cooling-cells":
> const: 2
> @@ -113,6 +132,22 @@ allOf:
> - sram-supply
> - power-domains
> - power-domain-names
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a07g044-mali
> + then:
> + properties:
> + interrupt-names:
> + minItems: 4
> + clock-names:
> + minItems: 3
> + required:
> + - clock-names
> + - power-domains
> + - resets
> + - reset-names
> else:
> properties:
> power-domains:
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
@ 2021-12-06 17:08 ` Robin Murphy
0 siblings, 0 replies; 13+ messages in thread
From: Robin Murphy @ 2021-12-06 17:08 UTC (permalink / raw)
To: Biju Das, David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, tomeu.vizoso, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Alyssa Rosenzweig, Steven Price
On 2021-12-06 15:00, Biju Das wrote:
> The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
> add a compatible string for it.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Updated minItems for resets as 2
> * Documented optional property reset-names
> * Documented reset-names as required property for RZ/G2L SoC.
> ---
> .../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++-
> 1 file changed, 37 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> index 6f98dd55fb4c..c3b2f4ddd520 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> @@ -19,6 +19,7 @@ properties:
> - amlogic,meson-g12a-mali
> - mediatek,mt8183-mali
> - realtek,rtd1619-mali
> + - renesas,r9a07g044-mali
> - rockchip,px30-mali
> - rockchip,rk3568-mali
> - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
> @@ -27,19 +28,30 @@ properties:
> maxItems: 1
>
> interrupts:
> + minItems: 3
> items:
> - description: Job interrupt
> - description: MMU interrupt
> - description: GPU interrupt
> + - description: EVENT interrupt
I believe we haven't bothered with the "Event" interrupt so far since
there's no real meaningful use for it - it seems the downstream binding
for Arm's kbase driver doesn't mention it either.
> interrupt-names:
> + minItems: 3
> items:
> - const: job
> - const: mmu
> - const: gpu
> + - const: event
>
> clocks:
> - maxItems: 1
> + minItems: 1
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: gpu
> + - const: bus
> + - const: bus_ace
Note that the Bifrost GPUs themselves all only have a single external
clock and reset (unexcitingly named "CLK" and "RESETn" respectively,
FWIW). I can't help feeling wary that defining additional names for
vendor integration details in the core binding may quickly grow into a
mess of mutually-incompatible sets of values, for no great benefit. At
the very least, it would seem more sensible to put them in the
SoC-specific conditional schemas.
Robin.
>
> mali-supply: true
>
> @@ -52,7 +64,14 @@ properties:
> maxItems: 3
>
> resets:
> - maxItems: 2
> + minItems: 2
> + maxItems: 3
> +
> + reset-names:
> + items:
> + - const: rst
> + - const: axi_rst
> + - const: ace_rst
>
> "#cooling-cells":
> const: 2
> @@ -113,6 +132,22 @@ allOf:
> - sram-supply
> - power-domains
> - power-domain-names
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a07g044-mali
> + then:
> + properties:
> + interrupt-names:
> + minItems: 4
> + clock-names:
> + minItems: 3
> + required:
> + - clock-names
> + - power-domains
> + - resets
> + - reset-names
> else:
> properties:
> power-domains:
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
2021-12-06 17:08 ` Robin Murphy
@ 2021-12-06 17:29 ` Biju Das
-1 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-06 17:29 UTC (permalink / raw)
To: Robin Murphy, David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Alyssa Rosenzweig, tomeu.vizoso, Steven Price
Hi Robin,
Thanks for the feedback.
> Subject: Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document
> RZ/G2L support
>
> On 2021-12-06 15:00, Biju Das wrote:
> > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31
> > GPU, add a compatible string for it.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2:
> > * Updated minItems for resets as 2
> > * Documented optional property reset-names
> > * Documented reset-names as required property for RZ/G2L SoC.
> > ---
> > .../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++-
> > 1 file changed, 37 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > index 6f98dd55fb4c..c3b2f4ddd520 100644
> > --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > @@ -19,6 +19,7 @@ properties:
> > - amlogic,meson-g12a-mali
> > - mediatek,mt8183-mali
> > - realtek,rtd1619-mali
> > + - renesas,r9a07g044-mali
> > - rockchip,px30-mali
> > - rockchip,rk3568-mali
> > - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is
> > fully discoverable @@ -27,19 +28,30 @@ properties:
> > maxItems: 1
> >
> > interrupts:
> > + minItems: 3
> > items:
> > - description: Job interrupt
> > - description: MMU interrupt
> > - description: GPU interrupt
> > + - description: EVENT interrupt
>
> I believe we haven't bothered with the "Event" interrupt so far since
> there's no real meaningful use for it - it seems the downstream binding
> for Arm's kbase driver doesn't mention it either.
I agree.
But DT binding describes the H/W. Our SoC, mention about Event interrupt.
That is the reason I have documented it.
I am ok for keeping it or removing it. Please let me know.
>
> > interrupt-names:
> > + minItems: 3
> > items:
> > - const: job
> > - const: mmu
> > - const: gpu
> > + - const: event
> >
> > clocks:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 3
> > +
> > + clock-names:
> > + items:
> > + - const: gpu
> > + - const: bus
> > + - const: bus_ace
>
> Note that the Bifrost GPUs themselves all only have a single external
> clock and reset (unexcitingly named "CLK" and "RESETn" respectively,
> FWIW). I can't help feeling wary that defining additional names for vendor
> integration details in the core binding may quickly grow into a mess of
> mutually-incompatible sets of values, for no great benefit. At the very
> least, it would seem more sensible to put them in the SoC-specific
> conditional schemas.
Initially GPU was not working on our platform. Then after debugging found that it needs, bus clock
to make it work. This information is missing in dt binding and I need to find this info from source code.
That is the reason, even if it is optional, I have documented with same name here.
Regards,
Biju
>
> Robin.
>
> >
> > mali-supply: true
> >
> > @@ -52,7 +64,14 @@ properties:
> > maxItems: 3
> >
> > resets:
> > - maxItems: 2
> > + minItems: 2
> > + maxItems: 3
> > +
> > + reset-names:
> > + items:
> > + - const: rst
> > + - const: axi_rst
> > + - const: ace_rst
> >
> > "#cooling-cells":
> > const: 2
> > @@ -113,6 +132,22 @@ allOf:
> > - sram-supply
> > - power-domains
> > - power-domain-names
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a07g044-mali
> > + then:
> > + properties:
> > + interrupt-names:
> > + minItems: 4
> > + clock-names:
> > + minItems: 3
> > + required:
> > + - clock-names
> > + - power-domains
> > + - resets
> > + - reset-names
> > else:
> > properties:
> > power-domains:
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
@ 2021-12-06 17:29 ` Biju Das
0 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-06 17:29 UTC (permalink / raw)
To: Robin Murphy, David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, tomeu.vizoso, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Alyssa Rosenzweig, Steven Price
Hi Robin,
Thanks for the feedback.
> Subject: Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document
> RZ/G2L support
>
> On 2021-12-06 15:00, Biju Das wrote:
> > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31
> > GPU, add a compatible string for it.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2:
> > * Updated minItems for resets as 2
> > * Documented optional property reset-names
> > * Documented reset-names as required property for RZ/G2L SoC.
> > ---
> > .../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++-
> > 1 file changed, 37 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > index 6f98dd55fb4c..c3b2f4ddd520 100644
> > --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > @@ -19,6 +19,7 @@ properties:
> > - amlogic,meson-g12a-mali
> > - mediatek,mt8183-mali
> > - realtek,rtd1619-mali
> > + - renesas,r9a07g044-mali
> > - rockchip,px30-mali
> > - rockchip,rk3568-mali
> > - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is
> > fully discoverable @@ -27,19 +28,30 @@ properties:
> > maxItems: 1
> >
> > interrupts:
> > + minItems: 3
> > items:
> > - description: Job interrupt
> > - description: MMU interrupt
> > - description: GPU interrupt
> > + - description: EVENT interrupt
>
> I believe we haven't bothered with the "Event" interrupt so far since
> there's no real meaningful use for it - it seems the downstream binding
> for Arm's kbase driver doesn't mention it either.
I agree.
But DT binding describes the H/W. Our SoC, mention about Event interrupt.
That is the reason I have documented it.
I am ok for keeping it or removing it. Please let me know.
>
> > interrupt-names:
> > + minItems: 3
> > items:
> > - const: job
> > - const: mmu
> > - const: gpu
> > + - const: event
> >
> > clocks:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 3
> > +
> > + clock-names:
> > + items:
> > + - const: gpu
> > + - const: bus
> > + - const: bus_ace
>
> Note that the Bifrost GPUs themselves all only have a single external
> clock and reset (unexcitingly named "CLK" and "RESETn" respectively,
> FWIW). I can't help feeling wary that defining additional names for vendor
> integration details in the core binding may quickly grow into a mess of
> mutually-incompatible sets of values, for no great benefit. At the very
> least, it would seem more sensible to put them in the SoC-specific
> conditional schemas.
Initially GPU was not working on our platform. Then after debugging found that it needs, bus clock
to make it work. This information is missing in dt binding and I need to find this info from source code.
That is the reason, even if it is optional, I have documented with same name here.
Regards,
Biju
>
> Robin.
>
> >
> > mali-supply: true
> >
> > @@ -52,7 +64,14 @@ properties:
> > maxItems: 3
> >
> > resets:
> > - maxItems: 2
> > + minItems: 2
> > + maxItems: 3
> > +
> > + reset-names:
> > + items:
> > + - const: rst
> > + - const: axi_rst
> > + - const: ace_rst
> >
> > "#cooling-cells":
> > const: 2
> > @@ -113,6 +132,22 @@ allOf:
> > - sram-supply
> > - power-domains
> > - power-domain-names
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a07g044-mali
> > + then:
> > + properties:
> > + interrupt-names:
> > + minItems: 4
> > + clock-names:
> > + minItems: 3
> > + required:
> > + - clock-names
> > + - power-domains
> > + - resets
> > + - reset-names
> > else:
> > properties:
> > power-domains:
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
2021-12-06 15:00 ` [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Biju Das
@ 2021-12-07 8:38 ` Sergey Shtylyov
0 siblings, 0 replies; 13+ messages in thread
From: Sergey Shtylyov @ 2021-12-07 8:38 UTC (permalink / raw)
To: Biju Das, Rob Herring
Cc: Geert Uytterhoeven, Magnus Damm, linux-renesas-soc, devicetree,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hello!
On 06.12.2021 18:00, Biju Das wrote:
> Add vdd core regulator (1.1 V).
>
> This patch add regulator support for gpu.
>
> On the H/W manual nothing mentioned about gpu
Mentioned nothing?
> regulator. So using vdd core regulator for gpu.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
2021-12-06 17:29 ` Biju Das
@ 2021-12-08 9:26 ` Biju Das
-1 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-08 9:26 UTC (permalink / raw)
To: Robin Murphy, David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Alyssa Rosenzweig, tomeu.vizoso, Steven Price
Hi,
> Subject: RE: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document
> RZ/G2L support
>
> Hi Robin,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document
> > RZ/G2L support
> >
> > On 2021-12-06 15:00, Biju Das wrote:
> > > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost
> > > Mali-G31 GPU, add a compatible string for it.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2:
> > > * Updated minItems for resets as 2
> > > * Documented optional property reset-names
> > > * Documented reset-names as required property for RZ/G2L SoC.
> > > ---
> > > .../bindings/gpu/arm,mali-bifrost.yaml | 39
> ++++++++++++++++++-
> > > 1 file changed, 37 insertions(+), 2 deletions(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > index 6f98dd55fb4c..c3b2f4ddd520 100644
> > > --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > @@ -19,6 +19,7 @@ properties:
> > > - amlogic,meson-g12a-mali
> > > - mediatek,mt8183-mali
> > > - realtek,rtd1619-mali
> > > + - renesas,r9a07g044-mali
> > > - rockchip,px30-mali
> > > - rockchip,rk3568-mali
> > > - const: arm,mali-bifrost # Mali Bifrost GPU model/revision
> > > is fully discoverable @@ -27,19 +28,30 @@ properties:
> > > maxItems: 1
> > >
> > > interrupts:
> > > + minItems: 3
> > > items:
> > > - description: Job interrupt
> > > - description: MMU interrupt
> > > - description: GPU interrupt
> > > + - description: EVENT interrupt
> >
> > I believe we haven't bothered with the "Event" interrupt so far since
> > there's no real meaningful use for it - it seems the downstream
> > binding for Arm's kbase driver doesn't mention it either.
>
> I agree.
> But DT binding describes the H/W. Our SoC, mention about Event interrupt.
> That is the reason I have documented it.
> >
> > > interrupt-names:
> > > + minItems: 3
> > > items:
> > > - const: job
> > > - const: mmu
> > > - const: gpu
> > > + - const: event
> > >
> > > clocks:
> > > - maxItems: 1
> > > + minItems: 1
> > > + maxItems: 3
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: gpu
> > > + - const: bus
> > > + - const: bus_ace
> >
> > Note that the Bifrost GPUs themselves all only have a single external
> > clock and reset (unexcitingly named "CLK" and "RESETn" respectively,
> > FWIW). I can't help feeling wary that defining additional names for
> > vendor integration details in the core binding may quickly grow into a
> > mess of mutually-incompatible sets of values, for no great benefit. At
> > the very least, it would seem more sensible to put them in the
> > SoC-specific conditional schemas.
>
I agree, All optional properties like clock-names and reset-names should go in the SoC-specific conditional schemas.
I will make clock-names and reset-names to true and handle it in the SoC-specific conditional schemas.
I will send V3, incorporating the above.
Regards,
Biju
>
> >
> > Robin.
> >
> > >
> > > mali-supply: true
> > >
> > > @@ -52,7 +64,14 @@ properties:
> > > maxItems: 3
> > >
> > > resets:
> > > - maxItems: 2
> > > + minItems: 2
> > > + maxItems: 3
> > > +
> > > + reset-names:
> > > + items:
> > > + - const: rst
> > > + - const: axi_rst
> > > + - const: ace_rst
> > >
> > > "#cooling-cells":
> > > const: 2
> > > @@ -113,6 +132,22 @@ allOf:
> > > - sram-supply
> > > - power-domains
> > > - power-domain-names
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: renesas,r9a07g044-mali
> > > + then:
> > > + properties:
> > > + interrupt-names:
> > > + minItems: 4
> > > + clock-names:
> > > + minItems: 3
> > > + required:
> > > + - clock-names
> > > + - power-domains
> > > + - resets
> > > + - reset-names
> > > else:
> > > properties:
> > > power-domains:
> > >
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
@ 2021-12-08 9:26 ` Biju Das
0 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2021-12-08 9:26 UTC (permalink / raw)
To: Robin Murphy, David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, tomeu.vizoso, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Alyssa Rosenzweig, Steven Price
Hi,
> Subject: RE: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document
> RZ/G2L support
>
> Hi Robin,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document
> > RZ/G2L support
> >
> > On 2021-12-06 15:00, Biju Das wrote:
> > > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost
> > > Mali-G31 GPU, add a compatible string for it.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2:
> > > * Updated minItems for resets as 2
> > > * Documented optional property reset-names
> > > * Documented reset-names as required property for RZ/G2L SoC.
> > > ---
> > > .../bindings/gpu/arm,mali-bifrost.yaml | 39
> ++++++++++++++++++-
> > > 1 file changed, 37 insertions(+), 2 deletions(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > index 6f98dd55fb4c..c3b2f4ddd520 100644
> > > --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > @@ -19,6 +19,7 @@ properties:
> > > - amlogic,meson-g12a-mali
> > > - mediatek,mt8183-mali
> > > - realtek,rtd1619-mali
> > > + - renesas,r9a07g044-mali
> > > - rockchip,px30-mali
> > > - rockchip,rk3568-mali
> > > - const: arm,mali-bifrost # Mali Bifrost GPU model/revision
> > > is fully discoverable @@ -27,19 +28,30 @@ properties:
> > > maxItems: 1
> > >
> > > interrupts:
> > > + minItems: 3
> > > items:
> > > - description: Job interrupt
> > > - description: MMU interrupt
> > > - description: GPU interrupt
> > > + - description: EVENT interrupt
> >
> > I believe we haven't bothered with the "Event" interrupt so far since
> > there's no real meaningful use for it - it seems the downstream
> > binding for Arm's kbase driver doesn't mention it either.
>
> I agree.
> But DT binding describes the H/W. Our SoC, mention about Event interrupt.
> That is the reason I have documented it.
> >
> > > interrupt-names:
> > > + minItems: 3
> > > items:
> > > - const: job
> > > - const: mmu
> > > - const: gpu
> > > + - const: event
> > >
> > > clocks:
> > > - maxItems: 1
> > > + minItems: 1
> > > + maxItems: 3
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: gpu
> > > + - const: bus
> > > + - const: bus_ace
> >
> > Note that the Bifrost GPUs themselves all only have a single external
> > clock and reset (unexcitingly named "CLK" and "RESETn" respectively,
> > FWIW). I can't help feeling wary that defining additional names for
> > vendor integration details in the core binding may quickly grow into a
> > mess of mutually-incompatible sets of values, for no great benefit. At
> > the very least, it would seem more sensible to put them in the
> > SoC-specific conditional schemas.
>
I agree, All optional properties like clock-names and reset-names should go in the SoC-specific conditional schemas.
I will make clock-names and reset-names to true and handle it in the SoC-specific conditional schemas.
I will send V3, incorporating the above.
Regards,
Biju
>
> >
> > Robin.
> >
> > >
> > > mali-supply: true
> > >
> > > @@ -52,7 +64,14 @@ properties:
> > > maxItems: 3
> > >
> > > resets:
> > > - maxItems: 2
> > > + minItems: 2
> > > + maxItems: 3
> > > +
> > > + reset-names:
> > > + items:
> > > + - const: rst
> > > + - const: axi_rst
> > > + - const: ace_rst
> > >
> > > "#cooling-cells":
> > > const: 2
> > > @@ -113,6 +132,22 @@ allOf:
> > > - sram-supply
> > > - power-domains
> > > - power-domain-names
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: renesas,r9a07g044-mali
> > > + then:
> > > + properties:
> > > + interrupt-names:
> > > + minItems: 4
> > > + clock-names:
> > > + minItems: 3
> > > + required:
> > > + - clock-names
> > > + - power-domains
> > > + - resets
> > > + - reset-names
> > > else:
> > > properties:
> > > power-domains:
> > >
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-12-08 9:26 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-06 15:00 [PATCH v2 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Biju Das
2021-12-06 15:00 ` Biju Das
2021-12-06 15:00 ` [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support Biju Das
2021-12-06 15:00 ` Biju Das
2021-12-06 17:08 ` Robin Murphy
2021-12-06 17:08 ` Robin Murphy
2021-12-06 17:29 ` Biju Das
2021-12-06 17:29 ` Biju Das
2021-12-08 9:26 ` Biju Das
2021-12-08 9:26 ` Biju Das
2021-12-06 15:00 ` [PATCH v2 2/3] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Biju Das
2021-12-06 15:00 ` [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Biju Das
2021-12-07 8:38 ` Sergey Shtylyov
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