* [PATCH] arm64: esr: Add ESR exception class encoding for trapped ERET
@ 2019-07-30 14:41 Will Deacon
2019-07-30 15:00 ` Mark Rutland
2019-07-30 15:06 ` Marc Zyngier
0 siblings, 2 replies; 3+ messages in thread
From: Will Deacon @ 2019-07-30 14:41 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: marc.zyngier, Will Deacon
The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated
by an ERET, ERETAA or ERETAB instruction as a result of a nested
virtualisation trap to EL2.
Add an encoding for this EC and a string description so that we identify
it correctly if we take one unexpectedly.
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/include/asm/esr.h | 3 ++-
arch/arm64/kernel/traps.c | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 65ac18400979..cb29253ae86b 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -34,7 +34,8 @@
#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
#define ESR_ELx_EC_SYS64 (0x18)
#define ESR_ELx_EC_SVE (0x19)
-/* Unallocated EC: 0x1A - 0x1E */
+#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
+/* Unallocated EC: 0x1b - 0x1E */
#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
#define ESR_ELx_EC_IABT_LOW (0x20)
#define ESR_ELx_EC_IABT_CUR (0x21)
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index d3313797cca9..42c8422cdf4a 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -743,6 +743,7 @@ static const char *esr_class_str[] = {
[ESR_ELx_EC_SMC64] = "SMC (AArch64)",
[ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
[ESR_ELx_EC_SVE] = "SVE",
+ [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB",
[ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
[ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
[ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
--
2.11.0
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: esr: Add ESR exception class encoding for trapped ERET
2019-07-30 14:41 [PATCH] arm64: esr: Add ESR exception class encoding for trapped ERET Will Deacon
@ 2019-07-30 15:00 ` Mark Rutland
2019-07-30 15:06 ` Marc Zyngier
1 sibling, 0 replies; 3+ messages in thread
From: Mark Rutland @ 2019-07-30 15:00 UTC (permalink / raw)
To: Will Deacon; +Cc: marc.zyngier, linux-arm-kernel
On Tue, Jul 30, 2019 at 03:41:47PM +0100, Will Deacon wrote:
> The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated
> by an ERET, ERETAA or ERETAB instruction as a result of a nested
> virtualisation trap to EL2.
>
> Add an encoding for this EC and a string description so that we identify
> it correctly if we take one unexpectedly.
>
> Signed-off-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> ---
> arch/arm64/include/asm/esr.h | 3 ++-
> arch/arm64/kernel/traps.c | 1 +
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index 65ac18400979..cb29253ae86b 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -34,7 +34,8 @@
> #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
> #define ESR_ELx_EC_SYS64 (0x18)
> #define ESR_ELx_EC_SVE (0x19)
> -/* Unallocated EC: 0x1A - 0x1E */
> +#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
> +/* Unallocated EC: 0x1b - 0x1E */
> #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
> #define ESR_ELx_EC_IABT_LOW (0x20)
> #define ESR_ELx_EC_IABT_CUR (0x21)
> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
> index d3313797cca9..42c8422cdf4a 100644
> --- a/arch/arm64/kernel/traps.c
> +++ b/arch/arm64/kernel/traps.c
> @@ -743,6 +743,7 @@ static const char *esr_class_str[] = {
> [ESR_ELx_EC_SMC64] = "SMC (AArch64)",
> [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
> [ESR_ELx_EC_SVE] = "SVE",
> + [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB",
> [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
> [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
> [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
> --
> 2.11.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: esr: Add ESR exception class encoding for trapped ERET
2019-07-30 14:41 [PATCH] arm64: esr: Add ESR exception class encoding for trapped ERET Will Deacon
2019-07-30 15:00 ` Mark Rutland
@ 2019-07-30 15:06 ` Marc Zyngier
1 sibling, 0 replies; 3+ messages in thread
From: Marc Zyngier @ 2019-07-30 15:06 UTC (permalink / raw)
To: Will Deacon, linux-arm-kernel
On 30/07/2019 15:41, Will Deacon wrote:
> The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated
> by an ERET, ERETAA or ERETAB instruction as a result of a nested
> virtualisation trap to EL2.
>
> Add an encoding for this EC and a string description so that we identify
> it correctly if we take one unexpectedly.
>
> Signed-off-by: Will Deacon <will@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Jazz is not dead, it just smells funny...
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-07-30 14:41 [PATCH] arm64: esr: Add ESR exception class encoding for trapped ERET Will Deacon
2019-07-30 15:00 ` Mark Rutland
2019-07-30 15:06 ` Marc Zyngier
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