* [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
@ 2021-06-28 23:50 Madhumitha Tolakanahalli Pradeep
2021-06-29 0:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Madhumitha Tolakanahalli Pradeep @ 2021-06-28 23:50 UTC (permalink / raw)
To: intel-gfx
PCH display HPD IRQ is not detected with default filter value.
So, PP_CONTROL is manually reprogrammed.
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
---
.../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
drivers/gpu/drm/i915/display/intel_hotplug.c | 16 ++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 285380079aab..e44323cc76f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -6385,8 +6385,16 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
void intel_display_power_suspend_late(struct drm_i915_private *i915)
{
+ struct drm_i915_private *dev_priv = i915;
+ u32 val;
if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
IS_BROXTON(i915)) {
+ val = intel_de_read(dev_priv, PP_CONTROL(0));
+ /* Wa_14013120569:tgl */
+ if (IS_TIGERLAKE(i915)) {
+ val &= ~PANEL_POWER_ON;
+ intel_de_write(dev_priv, PP_CONTROL(0), val);
+ }
bxt_enable_dc9(i915);
/* Tweaked Wa_14010685332:icp,jsp,mcc */
if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..8e3f84100daf 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -26,6 +26,7 @@
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_hotplug.h"
+#include "intel_de.h"
/**
* DOC: Hotplug
@@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
enum drm_connector_status old_status;
+ u32 val;
u64 old_epoch_counter;
bool ret = false;
@@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
drm_get_connector_status_name(connector->base.status),
old_epoch_counter,
connector->base.epoch_counter);
+
+ /* Wa_14013120569:tgl */
+ if (IS_TIGERLAKE(dev_priv)) {
+ val = intel_de_read(dev_priv, PP_CONTROL(0));
+ if (connector->base.status == connector_status_connected) {
+ val |= PANEL_POWER_ON;
+ intel_de_write(dev_priv, PP_CONTROL(0), val);
+ }
+ else if (connector->base.status == connector_status_disconnected) {
+ val &= ~PANEL_POWER_ON;
+ intel_de_write(dev_priv, PP_CONTROL(0), val);
+ }
+ }
return INTEL_HOTPLUG_CHANGED;
}
return INTEL_HOTPLUG_UNCHANGED;
--
2.26.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/tgl: Implement Wa_14013120569
2021-06-28 23:50 [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569 Madhumitha Tolakanahalli Pradeep
@ 2021-06-29 0:12 ` Patchwork
2021-06-29 0:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-06-29 0:12 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display/tgl: Implement Wa_14013120569
URL : https://patchwork.freedesktop.org/series/91987/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7b3735152a04 drm/i915/display/tgl: Implement Wa_14013120569
-:20: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#20: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:6388:
+ struct drm_i915_private *dev_priv = i915;$
-:21: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#21: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:6389:
+ u32 val;$
-:67: ERROR:ELSE_AFTER_BRACE: else should follow close brace '}'
#67: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:302:
+ }
+ else if (connector->base.status == connector_status_disconnected) {
total: 1 errors, 2 warnings, 0 checks, 51 lines checked
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/tgl: Implement Wa_14013120569
2021-06-28 23:50 [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569 Madhumitha Tolakanahalli Pradeep
2021-06-29 0:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2021-06-29 0:43 ` Patchwork
2021-06-29 3:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-06-29 0:43 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2061 bytes --]
== Series Details ==
Series: drm/i915/display/tgl: Implement Wa_14013120569
URL : https://patchwork.freedesktop.org/series/91987/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10285 -> Patchwork_20481
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/index.html
Known issues
------------
Here are the changes found in Patchwork_20481 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][1] ([i915#1602] / [i915#2029])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][2] ([i915#1372]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
Participating hosts (40 -> 36)
------------------------------
Missing (4): fi-bsw-cyan fi-hsw-4200u fi-bdw-samus fi-bsw-n3050
Build changes
-------------
* Linux: CI_DRM_10285 -> Patchwork_20481
CI-20190529: 20190529
CI_DRM_10285: e65a658751fc5d3be5b0f4bcc4731e66ca1a537a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6121: a63ceb48e6c3e733d04156b32fba3b4f4d5ad794 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20481: 7b3735152a0422f87e8a431ade6bd063a8de12cc @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7b3735152a04 drm/i915/display/tgl: Implement Wa_14013120569
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/index.html
[-- Attachment #1.2: Type: text/html, Size: 2675 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/tgl: Implement Wa_14013120569
2021-06-28 23:50 [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569 Madhumitha Tolakanahalli Pradeep
2021-06-29 0:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-06-29 0:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-06-29 3:03 ` Patchwork
2021-06-29 22:25 ` [Intel-gfx] [PATCH] " Souza, Jose
2021-11-01 10:25 ` Jani Nikula
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-06-29 3:03 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30269 bytes --]
== Series Details ==
Series: drm/i915/display/tgl: Implement Wa_14013120569
URL : https://patchwork.freedesktop.org/series/91987/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10285_full -> Patchwork_20481_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20481_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@unwedge-stress:
- {shard-rkl-6}: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-rkl-6/igt@gem_eio@unwedge-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-rkl-1}: NOTRUN -> [INCOMPLETE][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-1/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- {shard-rkl-6}: [PASS][4] -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-rkl-6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- {shard-rkl-5}: NOTRUN -> [FAIL][6] +15 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- {shard-rkl-2}: NOTRUN -> [FAIL][7] +42 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-2/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_mmap_wc@set-cache-level:
- {shard-rkl-2}: NOTRUN -> [SKIP][8] +76 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-2/igt@gem_mmap_wc@set-cache-level.html
* {igt@kms_ccs@pipe-b-bad-pixel-format-yf_tiled_ccs}:
- {shard-rkl-1}: NOTRUN -> [FAIL][9] +38 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-1/igt@kms_ccs@pipe-b-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled:
- {shard-rkl-5}: NOTRUN -> [SKIP][10] +24 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- {shard-rkl-5}: NOTRUN -> [INCOMPLETE][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- {shard-rkl-2}: NOTRUN -> [INCOMPLETE][12] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render:
- {shard-rkl-1}: NOTRUN -> [SKIP][13] +217 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render.html
* igt@runner@aborted:
- {shard-rkl-2}: [FAIL][14] ([i915#3002]) -> [FAIL][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-rkl-2/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-2/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_20481_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) +4 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1099]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-snb7/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][21] ([i915#2846])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][22] -> [FAIL][23] ([i915#2842]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [PASS][24] -> [DMESG-WARN][25] ([i915#118] / [i915#95]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk7/igt@gem_exec_whisper@basic-queues-forked-all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk7/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl8/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-iclb: [PASS][27] -> [FAIL][28] ([i915#307])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#307])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk2/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk4/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_pread@exhaustion:
- shard-kbl: NOTRUN -> [WARN][31] ([i915#2658])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl6/igt@gem_pread@exhaustion.html
* igt@gem_spin_batch@spin-each:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#2898])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl2/igt@gem_spin_batch@spin-each.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl2/igt@gem_spin_batch@spin-each.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271]) +190 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-snb7/igt@gen9_exec_parse@batch-invalid-length.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#2521])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl8/igt@kms_async_flips@alternate-sync-async-flip.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-iclb: [PASS][37] -> [DMESG-WARN][38] ([i915#3621])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-iclb2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-iclb1/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +12 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl3/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl5/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-snb: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +10 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-snb6/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: NOTRUN -> [DMESG-WARN][42] ([i915#1982])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl5/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_color@pipe-b-ctm-0-75:
- shard-skl: [PASS][43] -> [DMESG-WARN][44] ([i915#1982])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl7/igt@kms_color@pipe-b-ctm-0-75.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl7/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +13 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl2/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][46] ([i915#1319])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl3/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][47] ([i915#180])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#2346])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][51] -> [INCOMPLETE][52] ([i915#180] / [i915#1982])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#2122]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2672])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271]) +137 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271]) +5 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-glk: NOTRUN -> [SKIP][58] ([fdo#109271]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][62] ([i915#265])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-kbl: NOTRUN -> [FAIL][63] ([i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][64] -> [FAIL][65] ([fdo#108145] / [i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl8/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][68] -> [SKIP][69] ([fdo#109441]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-kbl: [PASS][70] -> [INCOMPLETE][71] ([i915#155] / [i915#2828])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl3/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2437]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl7/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271]) +131 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl8/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][74] -> [FAIL][75] ([i915#1542])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-tglb1/igt@perf@polling-parameterized.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-tglb6/igt@perf@polling-parameterized.html
* igt@perf@short-reads:
- shard-skl: [PASS][76] -> [FAIL][77] ([i915#51])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl3/igt@perf@short-reads.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl2/igt@perf@short-reads.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl8/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2994])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl3/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_create@create-clear:
- shard-glk: [FAIL][80] ([i915#1888] / [i915#3160]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk3/igt@gem_create@create-clear.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk5/igt@gem_create@create-clear.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [DMESG-WARN][82] ([i915#180]) -> [PASS][83] +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-apl8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [FAIL][84] ([i915#2410]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-tglb3/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][86] ([i915#2369] / [i915#3063]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-tglb6/igt@gem_eio@unwedge-stress.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- {shard-rkl-6}: [FAIL][88] -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-rkl-6/igt@gem_exec_fair@basic-flow@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-rkl-6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [FAIL][90] ([i915#2842]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [FAIL][92] ([i915#2842]) -> [PASS][93] +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][94] ([i915#2842]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- shard-glk: [FAIL][96] ([i915#1888]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk5/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
* igt@gem_mmap_gtt@big-copy-odd:
- shard-skl: [FAIL][98] ([i915#307]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl9/igt@gem_mmap_gtt@big-copy-odd.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl1/igt@gem_mmap_gtt@big-copy-odd.html
- shard-glk: [FAIL][100] ([i915#307]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk1/igt@gem_mmap_gtt@big-copy-odd.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk2/igt@gem_mmap_gtt@big-copy-odd.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][102] ([i915#1436] / [i915#716]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk8/igt@gen9_exec_parse@allowed-all.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk8/igt@gen9_exec_parse@allowed-all.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][104] ([i915#118] / [i915#95]) -> [PASS][105] +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][106] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
- shard-glk: [FAIL][108] ([i915#79]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +6 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible@c-hdmi-a1:
- shard-glk: [FAIL][112] -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-glk8/igt@kms_flip@modeset-vs-vblank-race-interruptible@c-hdmi-a1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-glk8/igt@kms_flip@modeset-vs-vblank-race-interruptible@c-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate@b-dp1:
- shard-kbl: [FAIL][114] ([i915#2122]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl7/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl3/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][116] ([i915#1188]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-skl1/igt@kms_hdr@bpc-switch.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-skl10/igt@kms_hdr@bpc-switch.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][118] ([fdo#109441]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-iclb5/igt@kms_psr@psr2_basic.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][120] ([i915#180] / [i915#295]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][122] ([i915#588]) -> [SKIP][123] ([i915#658])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][124] ([i915#2920]) -> [SKIP][125] ([i915#658]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-iclb7/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][126] ([i915#658]) -> [SKIP][127] ([i915#2920]) +2 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92]) -> ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3363])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl7/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl1/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl6/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl3/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl1/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl6/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl6/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-kbl1/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl1/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl1/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl4/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl4/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-kbl6/igt@runner@aborted.html
- shard-apl: ([FAIL][144], [FAIL][145]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3363]) -> ([FAIL][146], [FAIL][147]) ([i915#180] / [i915#3363])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-apl1/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10285/shard-apl8/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl1/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/shard-apl6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109288]: https://bugs.freedesktop.org/show_bug.cgi?id=109288
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https:/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20481/index.html
[-- Attachment #1.2: Type: text/html, Size: 33951 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-06-28 23:50 [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569 Madhumitha Tolakanahalli Pradeep
` (2 preceding siblings ...)
2021-06-29 3:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-06-29 22:25 ` Souza, Jose
2021-07-05 10:28 ` Jani Nikula
2021-07-08 0:01 ` Tolakanahalli Pradeep, Madhumitha
2021-11-01 10:25 ` Jani Nikula
4 siblings, 2 replies; 14+ messages in thread
From: Souza, Jose @ 2021-06-29 22:25 UTC (permalink / raw)
To: intel-gfx, Tolakanahalli Pradeep, Madhumitha
On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep wrote:
> PCH display HPD IRQ is not detected with default filter value.
> So, PP_CONTROL is manually reprogrammed.
>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> drivers/gpu/drm/i915/display/intel_hotplug.c | 16 ++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 285380079aab..e44323cc76f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -6385,8 +6385,16 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
>
> void intel_display_power_suspend_late(struct drm_i915_private *i915)
> {
> + struct drm_i915_private *dev_priv = i915;
> + u32 val;
> if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> IS_BROXTON(i915)) {
> + val = intel_de_read(dev_priv, PP_CONTROL(0));
> + /* Wa_14013120569:tgl */
> + if (IS_TIGERLAKE(i915)) {
> + val &= ~PANEL_POWER_ON;
> + intel_de_write(dev_priv, PP_CONTROL(0), val);
> + }
Code style is all wrong, please fix it and run "dim checkpatch" to validate it before sending patches.
Also PP_CONTROL(0) don't point to the same register that the workaround is talking about, between generations register address change that might be
the case for this one.
This satisfy the "before going into sleep to allow CS entry" but it do not restore the workaround after waking up from suspend.
Also you could improve the code, you are reading the register even for platforms that don't need the wa, also check intel_de_rmw() it is better suited
to this case.
> bxt_enable_dc9(i915);
> /* Tweaked Wa_14010685332:icp,jsp,mcc */
> if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 47c85ac97c87..8e3f84100daf 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -26,6 +26,7 @@
> #include "i915_drv.h"
> #include "intel_display_types.h"
> #include "intel_hotplug.h"
> +#include "intel_de.h"
>
> /**
> * DOC: Hotplug
> @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
> struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> enum drm_connector_status old_status;
> + u32 val;
> u64 old_epoch_counter;
> bool ret = false;
>
> @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
> drm_get_connector_status_name(connector->base.status),
> old_epoch_counter,
> connector->base.epoch_counter);
> +
> + /* Wa_14013120569:tgl */
> + if (IS_TIGERLAKE(dev_priv)) {
> + val = intel_de_read(dev_priv, PP_CONTROL(0));
> + if (connector->base.status == connector_status_connected) {
> + val |= PANEL_POWER_ON;
> + intel_de_write(dev_priv, PP_CONTROL(0), val);
> + }
> + else if (connector->base.status == connector_status_disconnected) {
> + val &= ~PANEL_POWER_ON;
> + intel_de_write(dev_priv, PP_CONTROL(0), val);
> + }
> + }
Not sure if this is the best place but anyways it is missing handle the case were tigerlake boots with the external display connected.
No hotplug will happen and workaround will never be enabled.
> return INTEL_HOTPLUG_CHANGED;
> }
> return INTEL_HOTPLUG_UNCHANGED;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-06-29 22:25 ` [Intel-gfx] [PATCH] " Souza, Jose
@ 2021-07-05 10:28 ` Jani Nikula
2021-07-08 0:04 ` Tolakanahalli Pradeep, Madhumitha
2021-07-08 0:01 ` Tolakanahalli Pradeep, Madhumitha
1 sibling, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2021-07-05 10:28 UTC (permalink / raw)
To: Souza, Jose, intel-gfx, Tolakanahalli Pradeep, Madhumitha
On Tue, 29 Jun 2021, "Souza, Jose" <jose.souza@intel.com> wrote:
> On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep wrote:
>> PCH display HPD IRQ is not detected with default filter value.
>> So, PP_CONTROL is manually reprogrammed.
>>
>> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>> drivers/gpu/drm/i915/display/intel_hotplug.c | 16 ++++++++++++++++
>> 2 files changed, 24 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 285380079aab..e44323cc76f5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -6385,8 +6385,16 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
>>
>> void intel_display_power_suspend_late(struct drm_i915_private *i915)
>> {
>> + struct drm_i915_private *dev_priv = i915;
>> + u32 val;
>> if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
>> IS_BROXTON(i915)) {
>> + val = intel_de_read(dev_priv, PP_CONTROL(0));
>> + /* Wa_14013120569:tgl */
>> + if (IS_TIGERLAKE(i915)) {
>> + val &= ~PANEL_POWER_ON;
>> + intel_de_write(dev_priv, PP_CONTROL(0), val);
>> + }
>
> Code style is all wrong, please fix it and run "dim checkpatch" to validate it before sending patches.
> Also PP_CONTROL(0) don't point to the same register that the workaround is talking about, between generations register address change that might be
> the case for this one.
In general, I've put a bunch of effort into moving most PPS stuff and
PP_CONTROL reg access into intel_pps.c, not least because you must hold
appropriate locks and power domain references to poke at this. You can't
just mess with it nilly willy. I don't want these abstractions bypassed.
BR,
Jani.
>
> This satisfy the "before going into sleep to allow CS entry" but it do not restore the workaround after waking up from suspend.
> Also you could improve the code, you are reading the register even for platforms that don't need the wa, also check intel_de_rmw() it is better suited
> to this case.
>
>> bxt_enable_dc9(i915);
>> /* Tweaked Wa_14010685332:icp,jsp,mcc */
>> if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
>> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> index 47c85ac97c87..8e3f84100daf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> @@ -26,6 +26,7 @@
>> #include "i915_drv.h"
>> #include "intel_display_types.h"
>> #include "intel_hotplug.h"
>> +#include "intel_de.h"
>>
>> /**
>> * DOC: Hotplug
>> @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
>> struct intel_connector *connector)
>> {
>> struct drm_device *dev = connector->base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(dev);
>> enum drm_connector_status old_status;
>> + u32 val;
>> u64 old_epoch_counter;
>> bool ret = false;
>>
>> @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
>> drm_get_connector_status_name(connector->base.status),
>> old_epoch_counter,
>> connector->base.epoch_counter);
>> +
>> + /* Wa_14013120569:tgl */
>> + if (IS_TIGERLAKE(dev_priv)) {
>> + val = intel_de_read(dev_priv, PP_CONTROL(0));
>> + if (connector->base.status == connector_status_connected) {
>> + val |= PANEL_POWER_ON;
>> + intel_de_write(dev_priv, PP_CONTROL(0), val);
>> + }
>> + else if (connector->base.status == connector_status_disconnected) {
>> + val &= ~PANEL_POWER_ON;
>> + intel_de_write(dev_priv, PP_CONTROL(0), val);
>> + }
>> + }
>
> Not sure if this is the best place but anyways it is missing handle the case were tigerlake boots with the external display connected.
> No hotplug will happen and workaround will never be enabled.
>
>> return INTEL_HOTPLUG_CHANGED;
>> }
>> return INTEL_HOTPLUG_UNCHANGED;
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-06-29 22:25 ` [Intel-gfx] [PATCH] " Souza, Jose
2021-07-05 10:28 ` Jani Nikula
@ 2021-07-08 0:01 ` Tolakanahalli Pradeep, Madhumitha
1 sibling, 0 replies; 14+ messages in thread
From: Tolakanahalli Pradeep, Madhumitha @ 2021-07-08 0:01 UTC (permalink / raw)
To: intel-gfx, Souza, Jose
On Tue, 2021-06-29 at 22:25 +0000, Souza, Jose wrote:
> On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep
> wrote:
> > PCH display HPD IRQ is not detected with default filter value.
> > So, PP_CONTROL is manually reprogrammed.
> >
> > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > madhumitha.tolakanahalli.pradeep@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> > drivers/gpu/drm/i915/display/intel_hotplug.c | 16
> > ++++++++++++++++
> > 2 files changed, 24 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 285380079aab..e44323cc76f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -6385,8 +6385,16 @@ static void
> > intel_power_domains_verify_state(struct drm_i915_private *i915)
> >
> > void intel_display_power_suspend_late(struct drm_i915_private
> > *i915)
> > {
> > + struct drm_i915_private *dev_priv = i915;
> > + u32 val;
> > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> > IS_BROXTON(i915)) {
> > +val = intel_de_read(dev_priv, PP_CONTROL(0));
> > +/* Wa_14013120569:tgl */
> > +if (IS_TIGERLAKE(i915)) {
> > +val &= ~PANEL_POWER_ON;
> > +intel_de_write(dev_priv, PP_CONTROL(0), val);
> > +}
>
> Code style is all wrong, please fix it and run "dim checkpatch" to
> validate it before sending patches.
Thanks for pointing that out, I will fix it in the next version.
> Also PP_CONTROL(0) don't point to the same register that the
> workaround is talking about, between generations register address
> change that might be
> the case for this one.
Could you point me to the right register that I need to be
programming for this WA?
> This satisfy the "before going into sleep to allow CS entry" but it
> do not restore the workaround after waking up from suspend.
> do not restore the workaround after waking up from suspend.
Ah, I missed that point, will fix it in v2.
> Also you could improve the code, you are reading the register even
> for platforms that don't need the wa, also check intel_de_rmw() it is
> better suited
> to this case.
You're right, I will move that code under IS_TIGERLAKE().
>
> > bxt_enable_dc9(i915);
> > /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> > PCH_MCC)
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > index 47c85ac97c87..8e3f84100daf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > @@ -26,6 +26,7 @@
> > #include "i915_drv.h"
> > #include "intel_display_types.h"
> > #include "intel_hotplug.h"
> > +#include "intel_de.h"
> >
> > /**
> > * DOC: Hotplug
> > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder
> > *encoder,
> > struct intel_connector *connector)
> > {
> > struct drm_device *dev = connector->base.dev;
> > +struct drm_i915_private *dev_priv = to_i915(dev);
> > enum drm_connector_status old_status;
> > +u32 val;
> > u64 old_epoch_counter;
> > bool ret = false;
> >
> > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder
> > *encoder,
> > drm_get_connector_status_name(connector->base.status),
> > old_epoch_counter,
> > connector->base.epoch_counter);
> > +
> > +/* Wa_14013120569:tgl */
> > +if (IS_TIGERLAKE(dev_priv)) {
> > +val = intel_de_read(dev_priv, PP_CONTROL(0));
> > +if (connector->base.status == connector_status_connected) {
> > +val |= PANEL_POWER_ON;
> > +intel_de_write(dev_priv, PP_CONTROL(0), val);
> > +}
> > +else if (connector->base.status == connector_status_disconnected)
> > {
> > +val &= ~PANEL_POWER_ON;
> > +intel_de_write(dev_priv, PP_CONTROL(0), val);
> > +}
> > +}
>
> Not sure if this is the best place but anyways it is missing handle
> the case were tigerlake boots with the external display connected.
> No hotplug will happen and workaround will never be enabled.
Could you suggest a better place to add this WA?
I will add the check for TGL booting with external display connected
in v2.
>
> > return INTEL_HOTPLUG_CHANGED;
> > }
> > return INTEL_HOTPLUG_UNCHANGED;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-07-05 10:28 ` Jani Nikula
@ 2021-07-08 0:04 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 0 replies; 14+ messages in thread
From: Tolakanahalli Pradeep, Madhumitha @ 2021-07-08 0:04 UTC (permalink / raw)
To: intel-gfx, jani.nikula, Souza, Jose
On Mon, 2021-07-05 at 13:28 +0300, Jani Nikula wrote:
> On Tue, 29 Jun 2021, "Souza, Jose" <jose.souza@intel.com> wrote:
> > On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep
> > wrote:
> > > PCH display HPD IRQ is not detected with default filter value.
> > > So, PP_CONTROL is manually reprogrammed.
> > >
> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > > madhumitha.tolakanahalli.pradeep@intel.com>
> > > ---
> > > .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> > > drivers/gpu/drm/i915/display/intel_hotplug.c | 16
> > > ++++++++++++++++
> > > 2 files changed, 24 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 285380079aab..e44323cc76f5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -6385,8 +6385,16 @@ static void
> > > intel_power_domains_verify_state(struct drm_i915_private *i915)
> > >
> > > void intel_display_power_suspend_late(struct drm_i915_private
> > > *i915)
> > > {
> > > + struct drm_i915_private *dev_priv = i915;
> > > + u32 val;
> > > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> > > IS_BROXTON(i915)) {
> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(i915)) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0), val);
> > > + }
> >
> > Code style is all wrong, please fix it and run "dim checkpatch" to
> > validate it before sending patches.
> > Also PP_CONTROL(0) don't point to the same register that the
> > workaround is talking about, between generations register address
> > change that might be
> > the case for this one.
>
> In general, I've put a bunch of effort into moving most PPS stuff and
> PP_CONTROL reg access into intel_pps.c, not least because you must
> hold
> appropriate locks and power domain references to poke at this. You
> can't
> just mess with it nilly willy. I don't want these abstractions
> bypassed.
>
> BR,
> Jani.
Thank you for pointing that out, I will fix this in the next version.
- Madhumitha
>
> > This satisfy the "before going into sleep to allow CS entry" but it
> > do not restore the workaround after waking up from suspend.
> > Also you could improve the code, you are reading the register even
> > for platforms that don't need the wa, also check intel_de_rmw() it
> > is better suited
> > to this case.
> >
> > > bxt_enable_dc9(i915);
> > > /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > > if (INTEL_PCH_TYPE(i915) >= PCH_ICP &&
> > > INTEL_PCH_TYPE(i915) <= PCH_MCC)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > index 47c85ac97c87..8e3f84100daf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > @@ -26,6 +26,7 @@
> > > #include "i915_drv.h"
> > > #include "intel_display_types.h"
> > > #include "intel_hotplug.h"
> > > +#include "intel_de.h"
> > >
> > > /**
> > > * DOC: Hotplug
> > > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > > struct intel_connector *connector)
> > > {
> > > struct drm_device *dev = connector->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > enum drm_connector_status old_status;
> > > + u32 val;
> > > u64 old_epoch_counter;
> > > bool ret = false;
> > >
> > > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > > drm_get_connector_status_name(connector-
> > > >base.status),
> > > old_epoch_counter,
> > > connector->base.epoch_counter);
> > > +
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(dev_priv)) {
> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > > + if (connector->base.status ==
> > > connector_status_connected) {
> > > + val |= PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0),
> > > val);
> > > + }
> > > + else if (connector->base.status ==
> > > connector_status_disconnected) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0),
> > > val);
> > > + }
> > > + }
> >
> > Not sure if this is the best place but anyways it is missing handle
> > the case were tigerlake boots with the external display connected.
> > No hotplug will happen and workaround will never be enabled.
> >
> > > return INTEL_HOTPLUG_CHANGED;
> > > }
> > > return INTEL_HOTPLUG_UNCHANGED;
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-06-28 23:50 [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569 Madhumitha Tolakanahalli Pradeep
` (3 preceding siblings ...)
2021-06-29 22:25 ` [Intel-gfx] [PATCH] " Souza, Jose
@ 2021-11-01 10:25 ` Jani Nikula
2021-11-08 23:52 ` Navare, Manasi
4 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2021-11-01 10:25 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep, intel-gfx
On Mon, 28 Jun 2021, Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> wrote:
> PCH display HPD IRQ is not detected with default filter value.
> So, PP_CONTROL is manually reprogrammed.
Returning to this workaround.
You're not supposed to enable the workaround when there's eDP
connected. This is also crucial in avoiding issues with eDP PPS.
The workaround is specific to Tiger Lake PCH, so you need to check
against the PCH, not the GPU.
Also see comments inline.
>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> drivers/gpu/drm/i915/display/intel_hotplug.c | 16 ++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 285380079aab..e44323cc76f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -6385,8 +6385,16 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
>
> void intel_display_power_suspend_late(struct drm_i915_private *i915)
> {
> + struct drm_i915_private *dev_priv = i915;
> + u32 val;
> if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> IS_BROXTON(i915)) {
> + val = intel_de_read(dev_priv, PP_CONTROL(0));
> + /* Wa_14013120569:tgl */
> + if (IS_TIGERLAKE(i915)) {
> + val &= ~PANEL_POWER_ON;
> + intel_de_write(dev_priv, PP_CONTROL(0), val);
> + }
As José said, how do you enable the workaround after resume if external
displays are still connected?
> bxt_enable_dc9(i915);
> /* Tweaked Wa_14010685332:icp,jsp,mcc */
> if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 47c85ac97c87..8e3f84100daf 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -26,6 +26,7 @@
> #include "i915_drv.h"
> #include "intel_display_types.h"
> #include "intel_hotplug.h"
> +#include "intel_de.h"
>
> /**
> * DOC: Hotplug
> @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
> struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> enum drm_connector_status old_status;
> + u32 val;
> u64 old_epoch_counter;
> bool ret = false;
>
> @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
> drm_get_connector_status_name(connector->base.status),
> old_epoch_counter,
> connector->base.epoch_counter);
> +
> + /* Wa_14013120569:tgl */
> + if (IS_TIGERLAKE(dev_priv)) {
> + val = intel_de_read(dev_priv, PP_CONTROL(0));
> + if (connector->base.status == connector_status_connected) {
> + val |= PANEL_POWER_ON;
> + intel_de_write(dev_priv, PP_CONTROL(0), val);
> + }
> + else if (connector->base.status == connector_status_disconnected) {
> + val &= ~PANEL_POWER_ON;
> + intel_de_write(dev_priv, PP_CONTROL(0), val);
> + }
> + }
First off, usually if you have a clean, generic, high level function,
it's a hint you shouldn't stick low level register access there.
If you plug in two external displays and then unplug one of them, you
end up disabling the workaround, while it's supposed to remain enabled
if there's an external display connected. This is likely the most
annoying part about the workaround.
This does not seem like a trivial workaround to implement.
BR,
Jani.
> return INTEL_HOTPLUG_CHANGED;
> }
> return INTEL_HOTPLUG_UNCHANGED;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-11-01 10:25 ` Jani Nikula
@ 2021-11-08 23:52 ` Navare, Manasi
2021-12-02 1:25 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 1 reply; 14+ messages in thread
From: Navare, Manasi @ 2021-11-08 23:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Nov 01, 2021 at 12:25:21PM +0200, Jani Nikula wrote:
> On Mon, 28 Jun 2021, Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> wrote:
> > PCH display HPD IRQ is not detected with default filter value.
> > So, PP_CONTROL is manually reprogrammed.
>
> Returning to this workaround.
>
> You're not supposed to enable the workaround when there's eDP
> connected. This is also crucial in avoiding issues with eDP PPS.
>
> The workaround is specific to Tiger Lake PCH, so you need to check
> against the PCH, not the GPU.
>
> Also see comments inline.
>
> >
> > Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> > drivers/gpu/drm/i915/display/intel_hotplug.c | 16 ++++++++++++++++
> > 2 files changed, 24 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 285380079aab..e44323cc76f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -6385,8 +6385,16 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
> >
> > void intel_display_power_suspend_late(struct drm_i915_private *i915)
> > {
> > + struct drm_i915_private *dev_priv = i915;
> > + u32 val;
> > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> > IS_BROXTON(i915)) {
> > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > + /* Wa_14013120569:tgl */
> > + if (IS_TIGERLAKE(i915)) {
> > + val &= ~PANEL_POWER_ON;
> > + intel_de_write(dev_priv, PP_CONTROL(0), val);
> > + }
>
> As José said, how do you enable the workaround after resume if external
> displays are still connected?
>
> > bxt_enable_dc9(i915);
> > /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > index 47c85ac97c87..8e3f84100daf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > @@ -26,6 +26,7 @@
> > #include "i915_drv.h"
> > #include "intel_display_types.h"
> > #include "intel_hotplug.h"
> > +#include "intel_de.h"
> >
> > /**
> > * DOC: Hotplug
> > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
> > struct intel_connector *connector)
> > {
> > struct drm_device *dev = connector->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > enum drm_connector_status old_status;
> > + u32 val;
> > u64 old_epoch_counter;
> > bool ret = false;
> >
> > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
> > drm_get_connector_status_name(connector->base.status),
> > old_epoch_counter,
> > connector->base.epoch_counter);
> > +
> > + /* Wa_14013120569:tgl */
> > + if (IS_TIGERLAKE(dev_priv)) {
> > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > + if (connector->base.status == connector_status_connected) {
> > + val |= PANEL_POWER_ON;
> > + intel_de_write(dev_priv, PP_CONTROL(0), val);
> > + }
> > + else if (connector->base.status == connector_status_disconnected) {
> > + val &= ~PANEL_POWER_ON;
> > + intel_de_write(dev_priv, PP_CONTROL(0), val);
> > + }
> > + }
>
> First off, usually if you have a clean, generic, high level function,
> it's a hint you shouldn't stick low level register access there.
>
> If you plug in two external displays and then unplug one of them, you
> end up disabling the workaround, while it's supposed to remain enabled
> if there's an external display connected. This is likely the most
> annoying part about the workaround.
>
> This does not seem like a trivial workaround to implement.
>
Yes I agree, not a trivial W/A to implement. I think few main things to figure out:
- Right place to enable/disable the W/A at connect/disconnect and for the connectors already connected on boot - Probably in hdmi_init_connector() and dp_init_connector() for the connected conns
on boot and then intel_encoder_hptplug() at the time of ext display hotplug/unplug
@Jani having this W/A in above 2 places you think is good?
- The other thing like Jani pointed out is that we should enable/disable only if !edp - so add this check for init_connector functions before setting/ clearing the W/A
- Third thing is the wrapper function to be defined in intel_pps.c something like below:
intel_pps_wa_enable(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
with_intel_pps_lock(intel_dp, wakeref) {
i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
u32 pp;
pp = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
pp |= PANEL_POWER_ON;
intel_de_write(dev_priv, pp_ctrl_reg, pp);
intel_de_posting_read(dev_priv, pp_ctrl_reg);
}
}
And similar for disabling the wa
Then this function can be called in the appropriate places identified above.
@Jani this pps helper function for enable/disable W/A makes sense?
Regards
Manasi
}
>
> BR,
> Jani.
>
>
> > return INTEL_HOTPLUG_CHANGED;
> > }
> > return INTEL_HOTPLUG_UNCHANGED;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-11-08 23:52 ` Navare, Manasi
@ 2021-12-02 1:25 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 0 replies; 14+ messages in thread
From: Tolakanahalli Pradeep, Madhumitha @ 2021-12-02 1:25 UTC (permalink / raw)
To: jani.nikula, Navare, Manasi D; +Cc: intel-gfx
@Jani @Manasi
Bump.
On Mon, 2021-11-08 at 15:52 -0800, Navare, Manasi wrote:
> On Mon, Nov 01, 2021 at 12:25:21PM +0200, Jani Nikula wrote:
> > On Mon, 28 Jun 2021, Madhumitha Tolakanahalli Pradeep
> > <madhumitha.tolakanahalli.pradeep@intel.com> wrote:
> > > PCH display HPD IRQ is not detected with default filter value.
> > > So, PP_CONTROL is manually reprogrammed.
> >
> > Returning to this workaround.
> >
> > You're not supposed to enable the workaround when there's eDP
> > connected. This is also crucial in avoiding issues with eDP PPS.
> >
> > The workaround is specific to Tiger Lake PCH, so you need to check
> > against the PCH, not the GPU.
> >
> > Also see comments inline.
> >
> > >
> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep
> > > <madhumitha.tolakanahalli.pradeep@intel.com>
> > > ---
> > > .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> > > drivers/gpu/drm/i915/display/intel_hotplug.c | 16
> > > ++++++++++++++++
> > > 2 files changed, 24 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 285380079aab..e44323cc76f5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -6385,8 +6385,16 @@ static void
> > > intel_power_domains_verify_state(struct drm_i915_private *i915)
> > >
> > > void intel_display_power_suspend_late(struct drm_i915_private
> > > *i915)
> > > {
> > > + struct drm_i915_private *dev_priv = i915;
> > > + u32 val;
> > > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> > > IS_BROXTON(i915)) {
> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(i915)) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0),
> > > val);
> > > + }
> >
> > As José said, how do you enable the workaround after resume if
> > external
> > displays are still connected?
> >
> > > bxt_enable_dc9(i915);
> > > /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > > if (INTEL_PCH_TYPE(i915) >= PCH_ICP &&
> > > INTEL_PCH_TYPE(i915) <= PCH_MCC)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > index 47c85ac97c87..8e3f84100daf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > @@ -26,6 +26,7 @@
> > > #include "i915_drv.h"
> > > #include "intel_display_types.h"
> > > #include "intel_hotplug.h"
> > > +#include "intel_de.h"
> > >
> > > /**
> > > * DOC: Hotplug
> > > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > > struct intel_connector *connector)
> > > {
> > > struct drm_device *dev = connector->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > enum drm_connector_status old_status;
> > > + u32 val;
> > > u64 old_epoch_counter;
> > > bool ret = false;
> > >
> > > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > >
> > > drm_get_connector_status_name(connector->base.status),
> > > old_epoch_counter,
> > > connector->base.epoch_counter);
> > > +
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(dev_priv)) {
> > > + val = intel_de_read(dev_priv,
> > > PP_CONTROL(0));
> > > + if (connector->base.status ==
> > > connector_status_connected) {
> > > + val |= PANEL_POWER_ON;
> > > + intel_de_write(dev_priv,
> > > PP_CONTROL(0), val);
> > > + }
> > > + else if (connector->base.status ==
> > > connector_status_disconnected) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv,
> > > PP_CONTROL(0), val);
> > > + }
> > > + }
> >
> > First off, usually if you have a clean, generic, high level
> > function,
> > it's a hint you shouldn't stick low level register access there.
> >
> > If you plug in two external displays and then unplug one of them,
> > you
> > end up disabling the workaround, while it's supposed to remain
> > enabled
> > if there's an external display connected. This is likely the most
> > annoying part about the workaround.
> >
> > This does not seem like a trivial workaround to implement.
> >
>
> Yes I agree, not a trivial W/A to implement. I think few main things
> to figure out:
> - Right place to enable/disable the W/A at connect/disconnect and for
> the connectors already connected on boot - Probably in
> hdmi_init_connector() and dp_init_connector() for the connected conns
> on boot and then intel_encoder_hptplug() at the time of ext display
> hotplug/unplug
>
> @Jani having this W/A in above 2 places you think is good?
> - The other thing like Jani pointed out is that we should
> enable/disable only if !edp - so add this check for init_connector
> functions before setting/ clearing the W/A
>
> - Third thing is the wrapper function to be defined in intel_pps.c
> something like below:
>
> intel_pps_wa_enable(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> intel_wakeref_t wakeref;
>
> with_intel_pps_lock(intel_dp, wakeref) {
> i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> u32 pp;
>
> pp = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
> pp |= PANEL_POWER_ON;
> intel_de_write(dev_priv, pp_ctrl_reg, pp);
> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> }
> }
> And similar for disabling the wa
>
> Then this function can be called in the appropriate places identified
> above.
>
> @Jani this pps helper function for enable/disable W/A makes sense?
>
>
> Regards
> Manasi
> }
> >
> > BR,
> > Jani.
> >
> >
> > > return INTEL_HOTPLUG_CHANGED;
> > > }
> > > return INTEL_HOTPLUG_UNCHANGED;
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
- Madhumitha
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-10-27 14:55 ` Jani Nikula
@ 2021-10-30 0:13 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 0 replies; 14+ messages in thread
From: Tolakanahalli Pradeep, Madhumitha @ 2021-10-30 0:13 UTC (permalink / raw)
To: jani.nikula; +Cc: intel-gfx, Navare, Manasi D
On Wed, 2021-10-27 at 17:55 +0300, Jani Nikula wrote:
> On Wed, 27 Oct 2021, "Tolakanahalli Pradeep, Madhumitha" <
> madhumitha.tolakanahalli.pradeep@intel.com> wrote:
> > On Mon, 2021-07-05 at 13:28 +0300, Jani Nikula wrote:
> > > On Tue, 29 Jun 2021, "Souza, Jose" <jose.souza at intel.com>
> > > wrote:
> > > > On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli
> > > > Pradeep
> > > > wrote:
> > > > > PCH display HPD IRQ is not detected with default filter
> > > > > value.
> > > > > So, PP_CONTROL is manually reprogrammed.
> > > > >
> > > > > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > > > > madhumitha.tolakanahalli.pradeep at intel.com>
> > > > > ---
> > > > > .../gpu/drm/i915/display/intel_display_power.c | 8
> > > > > ++++++++
> > > > > drivers/gpu/drm/i915/display/intel_hotplug.c | 16
> > > > > ++++++++++++++++
> > > > > 2 files changed, 24 insertions(+)
> > > > >
> > > > > diff --git
> > > > > a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > index 285380079aab..e44323cc76f5 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > @@ -6385,8 +6385,16 @@ static void
> > > > > intel_power_domains_verify_state(struct drm_i915_private
> > > > > *i915)
> > > > >
> > > > > void intel_display_power_suspend_late(struct
> > > > > drm_i915_private
> > > > > *i915)
> > > > > {
> > > > > + struct drm_i915_private *dev_priv = i915;
> > > > > + u32 val;
> > > > > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> > > > > IS_BROXTON(i915)) {
> > > > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > > > > + /* Wa_14013120569:tgl */
> > > > > + if (IS_TIGERLAKE(i915)) {
> > > > > + val &= ~PANEL_POWER_ON;
> > > > > + intel_de_write(dev_priv, PP_CONTROL(0),
> > > > > val);
> > > > > + }
> > > >
> > > > Code style is all wrong, please fix it and run "dim checkpatch"
> > > > to
> > > > validate it before sending patches.
> > > > Also PP_CONTROL(0) don't point to the same register that the
> > > > workaround is talking about, between generations register
> > > > address
> > > > change that might be
> > > > the case for this one.
> > >
> > > In general, I've put a bunch of effort into moving most PPS stuff
> > > and
> > > PP_CONTROL reg access into intel_pps.c, not least because you
> > > must
> > > hold
> > > appropriate locks and power domain references to poke at this.
> > > You
> > > can't
> > > just mess with it nilly willy. I don't want these abstractions
> > > bypassed.
> > >
> > > BR,
> > > Jani.
> >
> > I see that intel_pps_get_registers(), populates the regs-
> > > pp_ctrl correctly. That is what I would want to access and set
> > > the
> > bits for this W/A. However as is I cannot call pps_get_registers()
> > in
> > intel_dp or intel_display.c for the external connector at
> > connect/disconnect time. Do you recommend making this function non
> > static and calling it for this W/A or is there a way I can access
> > the
> > populated i915_reg_t pp_ctrl to set the W/A?
> >
> > Or are you wanting to define another helper for enable/disable of
> > this
> > W/A in intel_pps.c that would then call pps_init_registers or
> > similar
> > function ?
>
> Basically don't access any of the PPS registers outside of
> intel_pps.c. Any access like that is probably going to get the
> locking
> and timeout rules wrong, as well as make the software and hardware
> states go out of sync. Things like these need to be abstracted
> better. Bottom line, you can't just go poke at the registers in
> random
> places, no matter what the W/A says, and expect it to work out fine.
>
> The commit message also doesn't properly explain what is going on,
> and
> *why* this change is needed. Especially when you're adding special
> cases, you need to take extra care to explain the rationale. People
> are
> going to look at git log and git blame literally years from now, and
> wonder what this is about.
>
> BR,
> Jani.
>
>
Wa_14013120569 requires PP_CONTROL bit #0 to be set to 1 when external
display is plugged or resume after sleep. Bit #0 is to be cleared when
external display is unplugged or before going to sleep. W/A isnt
enabled when eDP is connected.
I shall add these details in v2, thank you for pointing that out.
As this W/A is required in a non-eDP scenario, I wouldn't be able to
use abstractions like intel_pps_on and intel_pps_off.
So would I need to create new wrapper functions in intel_pps.c for
setting and clearing the bits in PP_CONTROL with proper locks held,
and call these wrapper functions in intel_display.c/intel_dp.c?
> PS. Please try to ensure your mail client handles thread replies
> properly. This should have been in reply to:
>
> https://lore.kernel.org/r/54fada5eea99c1b5d7af300bcd6697711c3c5705.camel@intel.com
>
Sorry about that, fixed it.
- Madhumitha
>
> > - Madhumitha
> >
> > > > This satisfy the "before going into sleep to allow CS entry"
> > > > but it
> > > > do not restore the workaround after waking up from suspend.
> > > > Also you could improve the code, you are reading the register
> > > > even
> > > > for platforms that don't need the wa, also check intel_de_rmw()
> > > > it
> > > > is better suited
> > > > to this case.
> > > >
> > > > > bxt_enable_dc9(i915);
> > > > > /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > > > > if (INTEL_PCH_TYPE(i915) >= PCH_ICP &&
> > > > > INTEL_PCH_TYPE(i915) <= PCH_MCC)
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > > > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > > > index 47c85ac97c87..8e3f84100daf 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > > > @@ -26,6 +26,7 @@
> > > > > #include "i915_drv.h"
> > > > > #include "intel_display_types.h"
> > > > > #include "intel_hotplug.h"
> > > > > +#include "intel_de.h"
> > > > >
> > > > > /**
> > > > > * DOC: Hotplug
> > > > > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct
> > > > > intel_encoder
> > > > > *encoder,
> > > > > struct intel_connector *connector)
> > > > > {
> > > > > struct drm_device *dev = connector->base.dev;
> > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > enum drm_connector_status old_status;
> > > > > + u32 val;
> > > > > u64 old_epoch_counter;
> > > > > bool ret = false;
> > > > >
> > > > > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct
> > > > > intel_encoder
> > > > > *encoder,
> > > > > drm_get_connector_status_name(connect
> > > > > or-
> > > > > > base.status),
> > > > > old_epoch_counter,
> > > > > connector->base.epoch_counter);
> > > > > +
> > > > > + /* Wa_14013120569:tgl */
> > > > > + if (IS_TIGERLAKE(dev_priv)) {
> > > > > + val = intel_de_read(dev_priv,
> > > > > PP_CONTROL(0));
> > > > > + if (connector->base.status ==
> > > > > connector_status_connected) {
> > > > > + val |= PANEL_POWER_ON;
> > > > > + intel_de_write(dev_priv,
> > > > > PP_CONTROL(0),
> > > > > val);
> > > > > + }
> > > > > + else if (connector->base.status ==
> > > > > connector_status_disconnected) {
> > > > > + val &= ~PANEL_POWER_ON;
> > > > > + intel_de_write(dev_priv,
> > > > > PP_CONTROL(0),
> > > > > val);
> > > > > + }
> > > > > + }
> > > >
> > > > Not sure if this is the best place but anyways it is missing
> > > > handle
> > > > the case were tigerlake boots with the external display
> > > > connected.
> > > > No hotplug will happen and workaround will never be enabled.
> > > >
> > > > > return INTEL_HOTPLUG_CHANGED;
> > > > > }
> > > > > return INTEL_HOTPLUG_UNCHANGED;
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx at lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
2021-10-27 1:05 Tolakanahalli Pradeep, Madhumitha
@ 2021-10-27 14:55 ` Jani Nikula
2021-10-30 0:13 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2021-10-27 14:55 UTC (permalink / raw)
To: Tolakanahalli Pradeep, Madhumitha
Cc: intel-gfx, Tolakanahalli Pradeep, Madhumitha, Navare, Manasi D
On Wed, 27 Oct 2021, "Tolakanahalli Pradeep, Madhumitha" <madhumitha.tolakanahalli.pradeep@intel.com> wrote:
> On Mon, 2021-07-05 at 13:28 +0300, Jani Nikula wrote:
>> On Tue, 29 Jun 2021, "Souza, Jose" <jose.souza at intel.com> wrote:
>> > On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep
>> > wrote:
>> > > PCH display HPD IRQ is not detected with default filter value.
>> > > So, PP_CONTROL is manually reprogrammed.
>> > >
>> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
>> > > madhumitha.tolakanahalli.pradeep at intel.com>
>> > > ---
>> > > .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>> > > drivers/gpu/drm/i915/display/intel_hotplug.c | 16
>> > > ++++++++++++++++
>> > > 2 files changed, 24 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > index 285380079aab..e44323cc76f5 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > @@ -6385,8 +6385,16 @@ static void
>> > > intel_power_domains_verify_state(struct drm_i915_private *i915)
>> > >
>> > > void intel_display_power_suspend_late(struct drm_i915_private
>> > > *i915)
>> > > {
>> > > + struct drm_i915_private *dev_priv = i915;
>> > > + u32 val;
>> > > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
>> > > IS_BROXTON(i915)) {
>> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
>> > > + /* Wa_14013120569:tgl */
>> > > + if (IS_TIGERLAKE(i915)) {
>> > > + val &= ~PANEL_POWER_ON;
>> > > + intel_de_write(dev_priv, PP_CONTROL(0), val);
>> > > + }
>> >
>> > Code style is all wrong, please fix it and run "dim checkpatch" to
>> > validate it before sending patches.
>> > Also PP_CONTROL(0) don't point to the same register that the
>> > workaround is talking about, between generations register address
>> > change that might be
>> > the case for this one.
>>
>> In general, I've put a bunch of effort into moving most PPS stuff and
>> PP_CONTROL reg access into intel_pps.c, not least because you must
>> hold
>> appropriate locks and power domain references to poke at this. You
>> can't
>> just mess with it nilly willy. I don't want these abstractions
>> bypassed.
>>
>> BR,
>> Jani.
>
> I see that intel_pps_get_registers(), populates the regs-
> >pp_ctrl correctly. That is what I would want to access and set the
> bits for this W/A. However as is I cannot call pps_get_registers() in
> intel_dp or intel_display.c for the external connector at
> connect/disconnect time. Do you recommend making this function non
> static and calling it for this W/A or is there a way I can access the
> populated i915_reg_t pp_ctrl to set the W/A?
>
> Or are you wanting to define another helper for enable/disable of this
> W/A in intel_pps.c that would then call pps_init_registers or similar
> function ?
Basically don't access any of the PPS registers outside of
intel_pps.c. Any access like that is probably going to get the locking
and timeout rules wrong, as well as make the software and hardware
states go out of sync. Things like these need to be abstracted
better. Bottom line, you can't just go poke at the registers in random
places, no matter what the W/A says, and expect it to work out fine.
The commit message also doesn't properly explain what is going on, and
*why* this change is needed. Especially when you're adding special
cases, you need to take extra care to explain the rationale. People are
going to look at git log and git blame literally years from now, and
wonder what this is about.
BR,
Jani.
PS. Please try to ensure your mail client handles thread replies
properly. This should have been in reply to:
https://lore.kernel.org/r/54fada5eea99c1b5d7af300bcd6697711c3c5705.camel@intel.com
>
> - Madhumitha
>
>>
>> > This satisfy the "before going into sleep to allow CS entry" but it
>> > do not restore the workaround after waking up from suspend.
>> > Also you could improve the code, you are reading the register even
>> > for platforms that don't need the wa, also check intel_de_rmw() it
>> > is better suited
>> > to this case.
>> >
>> > > bxt_enable_dc9(i915);
>> > > /* Tweaked Wa_14010685332:icp,jsp,mcc */
>> > > if (INTEL_PCH_TYPE(i915) >= PCH_ICP &&
>> > > INTEL_PCH_TYPE(i915) <= PCH_MCC)
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
>> > > b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> > > index 47c85ac97c87..8e3f84100daf 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> > > @@ -26,6 +26,7 @@
>> > > #include "i915_drv.h"
>> > > #include "intel_display_types.h"
>> > > #include "intel_hotplug.h"
>> > > +#include "intel_de.h"
>> > >
>> > > /**
>> > > * DOC: Hotplug
>> > > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder
>> > > *encoder,
>> > > struct intel_connector *connector)
>> > > {
>> > > struct drm_device *dev = connector->base.dev;
>> > > + struct drm_i915_private *dev_priv = to_i915(dev);
>> > > enum drm_connector_status old_status;
>> > > + u32 val;
>> > > u64 old_epoch_counter;
>> > > bool ret = false;
>> > >
>> > > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder
>> > > *encoder,
>> > > drm_get_connector_status_name(connector-
>> > > >base.status),
>> > > old_epoch_counter,
>> > > connector->base.epoch_counter);
>> > > +
>> > > + /* Wa_14013120569:tgl */
>> > > + if (IS_TIGERLAKE(dev_priv)) {
>> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
>> > > + if (connector->base.status ==
>> > > connector_status_connected) {
>> > > + val |= PANEL_POWER_ON;
>> > > + intel_de_write(dev_priv, PP_CONTROL(0),
>> > > val);
>> > > + }
>> > > + else if (connector->base.status ==
>> > > connector_status_disconnected) {
>> > > + val &= ~PANEL_POWER_ON;
>> > > + intel_de_write(dev_priv, PP_CONTROL(0),
>> > > val);
>> > > + }
>> > > + }
>> >
>> > Not sure if this is the best place but anyways it is missing handle
>> > the case were tigerlake boots with the external display connected.
>> > No hotplug will happen and workaround will never be enabled.
>> >
>> > > return INTEL_HOTPLUG_CHANGED;
>> > > }
>> > > return INTEL_HOTPLUG_UNCHANGED;
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx at lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
@ 2021-10-27 1:05 Tolakanahalli Pradeep, Madhumitha
2021-10-27 14:55 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Tolakanahalli Pradeep, Madhumitha @ 2021-10-27 1:05 UTC (permalink / raw)
To: jani.nikula
Cc: Nikula, Jani, intel-gfx, Tolakanahalli Pradeep, Madhumitha,
Navare, Manasi D
On Mon, 2021-07-05 at 13:28 +0300, Jani Nikula wrote:
> On Tue, 29 Jun 2021, "Souza, Jose" <jose.souza at intel.com> wrote:
> > On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep
> > wrote:
> > > PCH display HPD IRQ is not detected with default filter value.
> > > So, PP_CONTROL is manually reprogrammed.
> > >
> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > > madhumitha.tolakanahalli.pradeep at intel.com>
> > > ---
> > > .../gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> > > drivers/gpu/drm/i915/display/intel_hotplug.c | 16
> > > ++++++++++++++++
> > > 2 files changed, 24 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 285380079aab..e44323cc76f5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -6385,8 +6385,16 @@ static void
> > > intel_power_domains_verify_state(struct drm_i915_private *i915)
> > >
> > > void intel_display_power_suspend_late(struct drm_i915_private
> > > *i915)
> > > {
> > > + struct drm_i915_private *dev_priv = i915;
> > > + u32 val;
> > > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> > > IS_BROXTON(i915)) {
> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(i915)) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0), val);
> > > + }
> >
> > Code style is all wrong, please fix it and run "dim checkpatch" to
> > validate it before sending patches.
> > Also PP_CONTROL(0) don't point to the same register that the
> > workaround is talking about, between generations register address
> > change that might be
> > the case for this one.
>
> In general, I've put a bunch of effort into moving most PPS stuff and
> PP_CONTROL reg access into intel_pps.c, not least because you must
> hold
> appropriate locks and power domain references to poke at this. You
> can't
> just mess with it nilly willy. I don't want these abstractions
> bypassed.
>
> BR,
> Jani.
I see that intel_pps_get_registers(), populates the regs-
>pp_ctrl correctly. That is what I would want to access and set the
bits for this W/A. However as is I cannot call pps_get_registers() in
intel_dp or intel_display.c for the external connector at
connect/disconnect time. Do you recommend making this function non
static and calling it for this W/A or is there a way I can access the
populated i915_reg_t pp_ctrl to set the W/A?
Or are you wanting to define another helper for enable/disable of this
W/A in intel_pps.c that would then call pps_init_registers or similar
function ?
- Madhumitha
>
> > This satisfy the "before going into sleep to allow CS entry" but it
> > do not restore the workaround after waking up from suspend.
> > Also you could improve the code, you are reading the register even
> > for platforms that don't need the wa, also check intel_de_rmw() it
> > is better suited
> > to this case.
> >
> > > bxt_enable_dc9(i915);
> > > /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > > if (INTEL_PCH_TYPE(i915) >= PCH_ICP &&
> > > INTEL_PCH_TYPE(i915) <= PCH_MCC)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > index 47c85ac97c87..8e3f84100daf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > @@ -26,6 +26,7 @@
> > > #include "i915_drv.h"
> > > #include "intel_display_types.h"
> > > #include "intel_hotplug.h"
> > > +#include "intel_de.h"
> > >
> > > /**
> > > * DOC: Hotplug
> > > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > > struct intel_connector *connector)
> > > {
> > > struct drm_device *dev = connector->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > enum drm_connector_status old_status;
> > > + u32 val;
> > > u64 old_epoch_counter;
> > > bool ret = false;
> > >
> > > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > > drm_get_connector_status_name(connector-
> > > >base.status),
> > > old_epoch_counter,
> > > connector->base.epoch_counter);
> > > +
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(dev_priv)) {
> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > > + if (connector->base.status ==
> > > connector_status_connected) {
> > > + val |= PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0),
> > > val);
> > > + }
> > > + else if (connector->base.status ==
> > > connector_status_disconnected) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0),
> > > val);
> > > + }
> > > + }
> >
> > Not sure if this is the best place but anyways it is missing handle
> > the case were tigerlake boots with the external display connected.
> > No hotplug will happen and workaround will never be enabled.
> >
> > > return INTEL_HOTPLUG_CHANGED;
> > > }
> > > return INTEL_HOTPLUG_UNCHANGED;
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-12-02 1:25 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-28 23:50 [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569 Madhumitha Tolakanahalli Pradeep
2021-06-29 0:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-06-29 0:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-29 3:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-29 22:25 ` [Intel-gfx] [PATCH] " Souza, Jose
2021-07-05 10:28 ` Jani Nikula
2021-07-08 0:04 ` Tolakanahalli Pradeep, Madhumitha
2021-07-08 0:01 ` Tolakanahalli Pradeep, Madhumitha
2021-11-01 10:25 ` Jani Nikula
2021-11-08 23:52 ` Navare, Manasi
2021-12-02 1:25 ` Tolakanahalli Pradeep, Madhumitha
2021-10-27 1:05 Tolakanahalli Pradeep, Madhumitha
2021-10-27 14:55 ` Jani Nikula
2021-10-30 0:13 ` Tolakanahalli Pradeep, Madhumitha
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