* [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs @ 2017-01-04 0:55 David Daney 2017-01-04 0:55 ` [PATCH 2/3] gpio: Add gpio driver support for ThunderX and OCTEON-TX David Daney ` (2 more replies) 0 siblings, 3 replies; 10+ messages in thread From: David Daney @ 2017-01-04 0:55 UTC (permalink / raw) To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland, linux-gpio, devicetree, linux-kernel Cc: David Daney From: David Daney <david.daney@cavium.com> The subject says it all. The Cavium ThunderX and OCTEON-TX family of SoCs have on-chip GPIO lines. This patch set adds a driver for these. David Daney (3): dt-bindings: gpio: Add binding documentation for gpio-thunderx gpio: Add gpio driver support for ThunderX and OCTEON-TX MAINTAINERS: Add entry for THUNDERX GPIO Driver. .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++ MAINTAINERS | 5 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-thunderx.c | 467 +++++++++++++++++++++ 5 files changed, 513 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt create mode 100644 drivers/gpio/gpio-thunderx.c -- 1.8.3.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] gpio: Add gpio driver support for ThunderX and OCTEON-TX 2017-01-04 0:55 [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs David Daney @ 2017-01-04 0:55 ` David Daney 2017-01-04 0:55 ` [PATCH 3/3] MAINTAINERS: Add entry for THUNDERX GPIO Driver David Daney [not found] ` <1483491334-167095-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-04 0:55 UTC (permalink / raw) To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland, linux-gpio, devicetree, linux-kernel Cc: David Daney From: David Daney <david.daney@cavium.com> Cavium ThunderX and OCTEON-TX are arm64 based SoCs. Add driver for the on-chip GPIO pins. Signed-off-by: David Daney <david.daney@cavium.com> --- drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-thunderx.c | 467 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 475 insertions(+) create mode 100644 drivers/gpio/gpio-thunderx.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ed37e59..6655477 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -421,6 +421,13 @@ config GPIO_TS4800 help This driver support TS-4800 FPGA GPIO controllers. +config GPIO_THUNDERX + tristate "Cavium ThunderX/OCTEON-TX GPIO" + depends on ARCH_THUNDER || (64BIT && COMPILE_TEST) + help + Say yes here to support the on-chip GPIO lines on the ThunderX + and OCTEON-TX families of SoCs. + config GPIO_TZ1090 bool "Toumaz Xenif TZ1090 GPIO support" depends on SOC_TZ1090 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d074c22..ab387bf 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -107,6 +107,7 @@ obj-$(CONFIG_GPIO_SYSCON) += gpio-syscon.o obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o obj-$(CONFIG_GPIO_TEGRA) += gpio-tegra.o +obj-$(CONFIG_GPIO_THUNDERX) += gpio-thunderx.o obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o obj-$(CONFIG_GPIO_TPIC2810) += gpio-tpic2810.o diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c new file mode 100644 index 0000000..7830f4d --- /dev/null +++ b/drivers/gpio/gpio-thunderx.c @@ -0,0 +1,467 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2016 Cavium Inc. + */ + +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/pci.h> +#include <linux/io.h> + + +#define GPIO_RX_DAT 0x0 +#define GPIO_TX_SET 0x8 +#define GPIO_TX_CLR 0x10 +#define GPIO_CONST 0x90 +#define GPIO_CONST_GPIOS_MASK 0xff +#define GPIO_BIT_CFG 0x400 +#define GPIO_BIT_CFG_TX_OE BIT(0) +#define GPIO_BIT_CFG_PIN_XOR BIT(1) +#define GPIO_BIT_CFG_INT_EN BIT(2) +#define GPIO_BIT_CFG_INT_TYPE BIT(3) +#define GPIO_BIT_CFG_FIL_CNT_SHIFT 4 +#define GPIO_BIT_CFG_FIL_SEL_SHIFT 8 +#define GPIO_BIT_CFG_TX_OD BIT(12) +#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16) +#define GPIO_INTR 0x800 +#define GPIO_INTR_INTR BIT(0) +#define GPIO_INTR_INTR_W1S BIT(1) +#define GPIO_INTR_ENA_W1C BIT(2) +#define GPIO_INTR_ENA_W1S BIT(3) +#define GPIO_2ND_BANK 0x1400 + +#define GLITCH_FILTER_400NS ((4ull << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \ + (9ull << GPIO_BIT_CFG_FIL_CNT_SHIFT)) + +/* + * The address offset of the GPIO configuration register for a given + * line. + */ +static unsigned int bit_cfg_reg(unsigned int line) +{ + return 8 * line + GPIO_BIT_CFG; +} + +static unsigned int intr_reg(unsigned int line) +{ + return 8 * line + GPIO_INTR; +} + +struct thunderx_gpio; + +struct thunderx_irqdev { + struct thunderx_gpio *gpio; + char *name; + unsigned int line; +}; + +struct thunderx_gpio { + struct gpio_chip chip; + u8 __iomem *register_base; + struct msix_entry *msix_entries; + struct thunderx_irqdev *irqdev_entries; + raw_spinlock_t lock; + unsigned long invert_mask[2]; + unsigned long od_mask[2]; + int base_msi; +}; + +static bool thunderx_gpio_is_gpio(struct thunderx_gpio *gpio, unsigned int line) +{ + u64 bit_cfg = readq(gpio->register_base + bit_cfg_reg(line)); + bool rv = (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0; + + WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line); + + return rv; +} + +static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line) +{ + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + + if (!thunderx_gpio_is_gpio(gpio, line)) + return -EIO; + + raw_spin_lock(&gpio->lock); + clear_bit(line, gpio->invert_mask); + clear_bit(line, gpio->od_mask); + writeq(GLITCH_FILTER_400NS, gpio->register_base + bit_cfg_reg(line)); + raw_spin_unlock(&gpio->lock); + return 0; +} + +static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line, + int value) +{ + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + int bank = line / 64; + int bank_bit = line % 64; + + void __iomem *reg = gpio->register_base + + (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR); + + writeq(1ull << bank_bit, reg); +} + +static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line, + int value) +{ + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + u64 bit_cfg = GPIO_BIT_CFG_TX_OE; + + if (!thunderx_gpio_is_gpio(gpio, line)) + return -EIO; + + raw_spin_lock(&gpio->lock); + + thunderx_gpio_set(chip, line, value); + + if (test_bit(line, gpio->invert_mask)) + bit_cfg |= GPIO_BIT_CFG_PIN_XOR; + + if (test_bit(line, gpio->od_mask)) + bit_cfg |= GPIO_BIT_CFG_TX_OD; + + writeq(bit_cfg, gpio->register_base + bit_cfg_reg(line)); + + raw_spin_unlock(&gpio->lock); + return 0; +} + +static int thunderx_gpio_set_single_ended(struct gpio_chip *chip, + unsigned int line, + enum single_ended_mode mode) +{ + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + + if (mode == LINE_MODE_OPEN_SOURCE) + return -ENOTSUPP; + + if (!thunderx_gpio_is_gpio(gpio, line)) + return -EIO; + + raw_spin_lock(&gpio->lock); + if (mode == LINE_MODE_OPEN_DRAIN) { + set_bit(line, gpio->invert_mask); + set_bit(line, gpio->od_mask); + } else { + clear_bit(line, gpio->invert_mask); + clear_bit(line, gpio->od_mask); + } + raw_spin_unlock(&gpio->lock); + + return 0; +} + +static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line) +{ + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + int bank = line / 64; + int bank_bit = line % 64; + u64 read_bits = readq(gpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); + + read_bits >>= bank_bit; + + if (test_bit(line, gpio->invert_mask)) + return !(read_bits & 1); + else + return read_bits & 1; +} + +static void thunderx_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + int bank; + u64 set_bits, clear_bits; + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + + for (bank = 0; bank <= (chip->ngpio / 64); bank++) { + set_bits = bits[bank] & mask[bank]; + clear_bits = ~bits[bank] & mask[bank]; + writeq(set_bits, gpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); + writeq(clear_bits, gpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); + } +} + +static irqreturn_t thunderx_gpio_chain_handler(int irq, void *dev) +{ + struct thunderx_irqdev *irqdev = dev; + int chained_irq; + int ret; + + chained_irq = irq_find_mapping(irqdev->gpio->chip.irqdomain, irqdev->line); + if (!chained_irq) + return IRQ_NONE; + + ret = generic_handle_irq(chained_irq); + + return ret ? IRQ_NONE : IRQ_HANDLED; +} + +static int thunderx_gpio_irq_request_resources(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + unsigned int line = data->hwirq; + struct thunderx_irqdev *irqdev; + int err; + + if (!thunderx_gpio_is_gpio(gpio, line)) + return -EIO; + + irqdev = gpio->irqdev_entries + line; + + irqdev->gpio = gpio; + irqdev->line = line; + irqdev->name = devm_kasprintf(chip->parent, GFP_KERNEL, "gpio-%d", line + chip->base); + + writeq(GPIO_INTR_ENA_W1C, gpio->register_base + intr_reg(line)); + + err = devm_request_irq(chip->parent, gpio->msix_entries[line].vector, + thunderx_gpio_chain_handler, IRQF_NO_THREAD, irqdev->name, irqdev); + return err; +} + +static void thunderx_gpio_irq_release_resources(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + unsigned int line = data->hwirq; + struct thunderx_irqdev *irqdev; + + irqdev = gpio->irqdev_entries + line; + + devm_free_irq(chip->parent, gpio->msix_entries[line].vector, irqdev); + + writeq(GPIO_INTR_ENA_W1C, gpio->register_base + intr_reg(line)); + + devm_kfree(chip->parent, irqdev->name); +} + +static void thunderx_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + unsigned int line = data->hwirq; + + writeq(GPIO_INTR_INTR, + gpio->register_base + intr_reg(line)); +} + +static void thunderx_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + unsigned int line = data->hwirq; + + writeq(GPIO_INTR_ENA_W1C, gpio->register_base + intr_reg(line)); +} + +static void thunderx_gpio_irq_mask_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + unsigned int line = data->hwirq; + + writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, + gpio->register_base + intr_reg(line)); +} + +static void thunderx_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + unsigned int line = data->hwirq; + + writeq(GPIO_INTR_ENA_W1S, gpio->register_base + intr_reg(line)); +} + +static int thunderx_gpio_irq_set_type(struct irq_data *data, + unsigned int flow_type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct thunderx_gpio *gpio = container_of(chip, struct thunderx_gpio, chip); + unsigned int line = data->hwirq; + u64 bit_cfg; + + irqd_set_trigger_type(data, flow_type); + + bit_cfg = GLITCH_FILTER_400NS | GPIO_BIT_CFG_INT_EN; + + if (flow_type & IRQ_TYPE_EDGE_BOTH) { + irq_set_handler_locked(data, handle_edge_irq); + bit_cfg |= GPIO_BIT_CFG_INT_TYPE; + } else { + irq_set_handler_locked(data, handle_level_irq); + } + + raw_spin_lock(&gpio->lock); + if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) { + bit_cfg |= GPIO_BIT_CFG_PIN_XOR; + set_bit(line, gpio->invert_mask); + } else { + clear_bit(line, gpio->invert_mask); + } + clear_bit(line, gpio->od_mask); + writeq(bit_cfg, gpio->register_base + bit_cfg_reg(line)); + raw_spin_unlock(&gpio->lock); + + return IRQ_SET_MASK_OK; +} + +static struct irq_chip thunderx_gpio_irq_chip = { + .name = "GPIO", + .irq_enable = thunderx_gpio_irq_unmask, + .irq_disable = thunderx_gpio_irq_mask, + .irq_ack = thunderx_gpio_irq_ack, + .irq_mask = thunderx_gpio_irq_mask, + .irq_mask_ack = thunderx_gpio_irq_mask_ack, + .irq_unmask = thunderx_gpio_irq_unmask, + .irq_set_type = thunderx_gpio_irq_set_type, + .irq_request_resources = thunderx_gpio_irq_request_resources, + .irq_release_resources = thunderx_gpio_irq_release_resources, + .flags = IRQCHIP_SET_TYPE_MASKED +}; + +static int thunderx_gpio_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + void __iomem * const *tbl; + struct device *dev = &pdev->dev; + struct thunderx_gpio *gpio; + struct gpio_chip *chip; + int ngpio, i; + int err = 0; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + raw_spin_lock_init(&gpio->lock); + chip = &gpio->chip; + + pci_set_drvdata(pdev, gpio); + + err = pcim_enable_device(pdev); + if (err) { + dev_err(dev, "Failed to enable PCI device: err %d\n", err); + goto out; + } + + err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME); + if (err) { + dev_err(dev, "Failed to iomap PCI device: err %d\n", err); + goto out; + } + + tbl = pcim_iomap_table(pdev); + gpio->register_base = tbl[0]; + if (!gpio->register_base) { + dev_err(dev, "Cannot map PCI resource\n"); + err = -ENOMEM; + goto out; + } + + if (pdev->subsystem_device == 0xa10a) { + /* CN88XX has no GPIO_CONST register*/ + ngpio = 50; + gpio->base_msi = 48; + } else { + u64 c = readq(gpio->register_base + GPIO_CONST); + + ngpio = c & GPIO_CONST_GPIOS_MASK; + gpio->base_msi = (c >> 8) & 0xff; + } + + gpio->msix_entries = devm_kzalloc(&pdev->dev, sizeof(struct msix_entry) * ngpio, GFP_KERNEL); + if (!gpio->msix_entries) { + err = -ENOMEM; + goto out; + } + + gpio->irqdev_entries = devm_kzalloc(&pdev->dev, sizeof(struct thunderx_irqdev) * ngpio, GFP_KERNEL); + if (!gpio->irqdev_entries) { + err = -ENOMEM; + goto out; + } + + for (i = 0; i < ngpio; i++) + gpio->msix_entries[i].entry = gpio->base_msi + (2 * i); + + err = pci_enable_msix(pdev, gpio->msix_entries, ngpio); + if (err < 0) + goto out; + + chip->label = KBUILD_MODNAME; + chip->parent = &pdev->dev; + chip->owner = THIS_MODULE; + chip->base = -1; /* System allocated */ + chip->can_sleep = false; + chip->ngpio = ngpio; + chip->direction_input = thunderx_gpio_dir_in; + chip->get = thunderx_gpio_get; + chip->direction_output = thunderx_gpio_dir_out; + chip->set = thunderx_gpio_set; + chip->set_multiple = thunderx_gpio_set_multiple; + chip->set_single_ended = thunderx_gpio_set_single_ended; + err = gpiochip_add(chip); + if (err) + goto msix_out; + + err = gpiochip_irqchip_add(chip, &thunderx_gpio_irq_chip, 0, + handle_level_irq, IRQ_TYPE_NONE); + if (err) { + dev_err(dev, "gpiochip_irqchip_add failed: %d\n", err); + goto irqchip_out; + } + + dev_info(&pdev->dev, "ThunderX GPIO: %d lines with base %d.\n", + ngpio, chip->base); + return 0; + +irqchip_out: + gpiochip_remove(chip); + +msix_out: + pci_disable_msix(pdev); + +out: + pci_set_drvdata(pdev, NULL); + return err; +} + +static void thunderx_gpio_remove(struct pci_dev *pdev) +{ + struct thunderx_gpio *gpio = pci_get_drvdata(pdev); + + pci_disable_msix(pdev); + gpiochip_remove(&gpio->chip); + pci_set_drvdata(pdev, NULL); +} + +static const struct pci_device_id thunderx_gpio_id_table[] = { + { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) }, + { 0, } /* end of table */ +}; + +MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table); + +static struct pci_driver thunderx_gpio_driver = { + .name = KBUILD_MODNAME, + .id_table = thunderx_gpio_id_table, + .probe = thunderx_gpio_probe, + .remove = thunderx_gpio_remove, +}; + +module_pci_driver(thunderx_gpio_driver); + +MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver"); +MODULE_LICENSE("GPL"); -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] MAINTAINERS: Add entry for THUNDERX GPIO Driver. 2017-01-04 0:55 [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs David Daney 2017-01-04 0:55 ` [PATCH 2/3] gpio: Add gpio driver support for ThunderX and OCTEON-TX David Daney @ 2017-01-04 0:55 ` David Daney [not found] ` <1483491334-167095-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-04 0:55 UTC (permalink / raw) To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland, linux-gpio, devicetree, linux-kernel Cc: David Daney From: David Daney <david.daney@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 63cefa6..41c3208 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10660,6 +10660,11 @@ M: Andreas Noever <andreas.noever@gmail.com> S: Maintained F: drivers/thunderbolt/ +THUNDERX GPIO DRIVER +M: David Daney <david.daney@cavium.com> +S: Maintained +F: drivers/gpio/gpio-thunderx.c + TI BQ27XXX POWER SUPPLY DRIVER R: Andrew F. Davis <afd@ti.com> F: include/linux/power/bq27xxx_battery.h -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
[parent not found: <1483491334-167095-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx 2017-01-04 0:55 [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs David Daney @ 2017-01-04 0:55 ` David Daney 2017-01-04 0:55 ` [PATCH 3/3] MAINTAINERS: Add entry for THUNDERX GPIO Driver David Daney [not found] ` <1483491334-167095-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-04 0:55 UTC (permalink / raw) To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland, linux-gpio-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: David Daney From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> --- .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt new file mode 100644 index 0000000..ba3cdae --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt @@ -0,0 +1,33 @@ +Cavium ThunderX/OCTEON-TX GPIO controller bindings + +Required Properties: +- reg: The controller bus address. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Must be 2. + - First cell is the GPIO pin number relative to the controller. + - Second cell is standard of_gpio_flags: + 1 - Active Low. + 2 - Single Ended. + +Optional Properties: +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Must be present and have value of 2 if + "interrupt-controller" is present. + - First cell is the GPIO pin number relative to the controller. + - Second cell is triggering flags, one of: + 1 - Edge Rising + 2 - Edge Falling + 4 - Level High + 8 - Level Low + +Example: + +gpio_6_0: gpio0@6,0 { + compatible = "cavium,thunder-8890-gpio"; + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx @ 2017-01-04 0:55 ` David Daney 0 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-04 0:55 UTC (permalink / raw) To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland, linux-gpio, devicetree, linux-kernel Cc: David Daney From: David Daney <david.daney@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> --- .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt new file mode 100644 index 0000000..ba3cdae --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt @@ -0,0 +1,33 @@ +Cavium ThunderX/OCTEON-TX GPIO controller bindings + +Required Properties: +- reg: The controller bus address. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Must be 2. + - First cell is the GPIO pin number relative to the controller. + - Second cell is standard of_gpio_flags: + 1 - Active Low. + 2 - Single Ended. + +Optional Properties: +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Must be present and have value of 2 if + "interrupt-controller" is present. + - First cell is the GPIO pin number relative to the controller. + - Second cell is triggering flags, one of: + 1 - Edge Rising + 2 - Edge Falling + 4 - Level High + 8 - Level Low + +Example: + +gpio_6_0: gpio0@6,0 { + compatible = "cavium,thunder-8890-gpio"; + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx 2017-01-04 0:55 ` David Daney (?) @ 2017-01-04 14:33 ` Rob Herring 2017-01-06 23:26 ` David Daney -1 siblings, 1 reply; 10+ messages in thread From: Rob Herring @ 2017-01-04 14:33 UTC (permalink / raw) To: David Daney Cc: Linus Walleij, Alexandre Courbot, Mark Rutland, linux-gpio, devicetree, linux-kernel, David Daney On Tue, Jan 03, 2017 at 04:55:32PM -0800, David Daney wrote: > From: David Daney <david.daney@cavium.com> > > Signed-off-by: David Daney <david.daney@cavium.com> > --- > .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt > > diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt > new file mode 100644 > index 0000000..ba3cdae > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt > @@ -0,0 +1,33 @@ > +Cavium ThunderX/OCTEON-TX GPIO controller bindings > + > +Required Properties: > +- reg: The controller bus address. > +- gpio-controller: Marks the device node as a GPIO controller. > +- #gpio-cells: Must be 2. > + - First cell is the GPIO pin number relative to the controller. > + - Second cell is standard of_gpio_flags: > + 1 - Active Low. > + 2 - Single Ended. Just reference where these are defined. > + > +Optional Properties: > +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. > +- interrupt-controller: Marks the device node as an interrupt controller. > +- #interrupt-cells: Must be present and have value of 2 if > + "interrupt-controller" is present. > + - First cell is the GPIO pin number relative to the controller. > + - Second cell is triggering flags, one of: > + 1 - Edge Rising > + 2 - Edge Falling > + 4 - Level High > + 8 - Level Low Just reference interrupt-controller/interrupts.txt or the header defining these. > + > +Example: > + > +gpio_6_0: gpio0@6,0 { gpio@6,0 > + compatible = "cavium,thunder-8890-gpio"; > + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > +}; > -- > 1.8.3.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx 2017-01-04 14:33 ` Rob Herring @ 2017-01-06 23:26 ` David Daney 0 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-06 23:26 UTC (permalink / raw) To: Rob Herring Cc: Linus Walleij, Alexandre Courbot, Mark Rutland, linux-gpio-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, David Daney On 01/04/2017 06:33 AM, Rob Herring wrote: > On Tue, Jan 03, 2017 at 04:55:32PM -0800, David Daney wrote: >> From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >> >> Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >> --- >> .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++++++++++++++++++++++ >> 1 file changed, 33 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt >> >> diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt >> new file mode 100644 >> index 0000000..ba3cdae >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt >> @@ -0,0 +1,33 @@ >> +Cavium ThunderX/OCTEON-TX GPIO controller bindings >> + >> +Required Properties: >> +- reg: The controller bus address. >> +- gpio-controller: Marks the device node as a GPIO controller. >> +- #gpio-cells: Must be 2. >> + - First cell is the GPIO pin number relative to the controller. >> + - Second cell is standard of_gpio_flags: >> + 1 - Active Low. >> + 2 - Single Ended. > > Just reference where these are defined. Thanks for the review. This and the two changes below have been addressed in v2 of the patch set. David. > >> + >> +Optional Properties: >> +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. >> +- interrupt-controller: Marks the device node as an interrupt controller. >> +- #interrupt-cells: Must be present and have value of 2 if >> + "interrupt-controller" is present. >> + - First cell is the GPIO pin number relative to the controller. >> + - Second cell is triggering flags, one of: >> + 1 - Edge Rising >> + 2 - Edge Falling >> + 4 - Level High >> + 8 - Level Low > > Just reference interrupt-controller/interrupts.txt or the header > defining these. > >> + >> +Example: >> + >> +gpio_6_0: gpio0@6,0 { > > gpio@6,0 > >> + compatible = "cavium,thunder-8890-gpio"; >> + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> +}; >> -- >> 1.8.3.1 >> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx @ 2017-01-06 23:26 ` David Daney 0 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-06 23:26 UTC (permalink / raw) To: Rob Herring Cc: Linus Walleij, Alexandre Courbot, Mark Rutland, linux-gpio, devicetree, linux-kernel, David Daney On 01/04/2017 06:33 AM, Rob Herring wrote: > On Tue, Jan 03, 2017 at 04:55:32PM -0800, David Daney wrote: >> From: David Daney <david.daney@cavium.com> >> >> Signed-off-by: David Daney <david.daney@cavium.com> >> --- >> .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++++++++++++++++++++++ >> 1 file changed, 33 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt >> >> diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt >> new file mode 100644 >> index 0000000..ba3cdae >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt >> @@ -0,0 +1,33 @@ >> +Cavium ThunderX/OCTEON-TX GPIO controller bindings >> + >> +Required Properties: >> +- reg: The controller bus address. >> +- gpio-controller: Marks the device node as a GPIO controller. >> +- #gpio-cells: Must be 2. >> + - First cell is the GPIO pin number relative to the controller. >> + - Second cell is standard of_gpio_flags: >> + 1 - Active Low. >> + 2 - Single Ended. > > Just reference where these are defined. Thanks for the review. This and the two changes below have been addressed in v2 of the patch set. David. > >> + >> +Optional Properties: >> +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. >> +- interrupt-controller: Marks the device node as an interrupt controller. >> +- #interrupt-cells: Must be present and have value of 2 if >> + "interrupt-controller" is present. >> + - First cell is the GPIO pin number relative to the controller. >> + - Second cell is triggering flags, one of: >> + 1 - Edge Rising >> + 2 - Edge Falling >> + 4 - Level High >> + 8 - Level Low > > Just reference interrupt-controller/interrupts.txt or the header > defining these. > >> + >> +Example: >> + >> +gpio_6_0: gpio0@6,0 { > > gpio@6,0 > >> + compatible = "cavium,thunder-8890-gpio"; >> + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> +}; >> -- >> 1.8.3.1 >> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs 2017-01-04 0:55 [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs David Daney @ 2017-01-06 23:24 ` David Daney 2017-01-04 0:55 ` [PATCH 3/3] MAINTAINERS: Add entry for THUNDERX GPIO Driver David Daney [not found] ` <1483491334-167095-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-06 23:24 UTC (permalink / raw) To: David Daney, Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland, linux-gpio-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: David Daney This version is obsolete. v2 has been sent. Thanks, David Daney On 01/03/2017 04:55 PM, David Daney wrote: > From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> > > The subject says it all. The Cavium ThunderX and OCTEON-TX family of > SoCs have on-chip GPIO lines. This patch set adds a driver for these. > > David Daney (3): > dt-bindings: gpio: Add binding documentation for gpio-thunderx > gpio: Add gpio driver support for ThunderX and OCTEON-TX > MAINTAINERS: Add entry for THUNDERX GPIO Driver. > > .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++ > MAINTAINERS | 5 + > drivers/gpio/Kconfig | 7 + > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-thunderx.c | 467 +++++++++++++++++++++ > 5 files changed, 513 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt > create mode 100644 drivers/gpio/gpio-thunderx.c > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs @ 2017-01-06 23:24 ` David Daney 0 siblings, 0 replies; 10+ messages in thread From: David Daney @ 2017-01-06 23:24 UTC (permalink / raw) To: David Daney, Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland, linux-gpio, devicetree, linux-kernel Cc: David Daney This version is obsolete. v2 has been sent. Thanks, David Daney On 01/03/2017 04:55 PM, David Daney wrote: > From: David Daney <david.daney@cavium.com> > > The subject says it all. The Cavium ThunderX and OCTEON-TX family of > SoCs have on-chip GPIO lines. This patch set adds a driver for these. > > David Daney (3): > dt-bindings: gpio: Add binding documentation for gpio-thunderx > gpio: Add gpio driver support for ThunderX and OCTEON-TX > MAINTAINERS: Add entry for THUNDERX GPIO Driver. > > .../devicetree/bindings/gpio/gpio-thunderx.txt | 33 ++ > MAINTAINERS | 5 + > drivers/gpio/Kconfig | 7 + > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-thunderx.c | 467 +++++++++++++++++++++ > 5 files changed, 513 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt > create mode 100644 drivers/gpio/gpio-thunderx.c > ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-01-06 23:26 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-01-04 0:55 [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs David Daney 2017-01-04 0:55 ` [PATCH 2/3] gpio: Add gpio driver support for ThunderX and OCTEON-TX David Daney 2017-01-04 0:55 ` [PATCH 3/3] MAINTAINERS: Add entry for THUNDERX GPIO Driver David Daney [not found] ` <1483491334-167095-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2017-01-04 0:55 ` [PATCH 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx David Daney 2017-01-04 0:55 ` David Daney 2017-01-04 14:33 ` Rob Herring 2017-01-06 23:26 ` David Daney 2017-01-06 23:26 ` David Daney 2017-01-06 23:24 ` [PATCH 0/3] GPIO: Add driver for ThunderX and OCTEON-TX SoCs David Daney 2017-01-06 23:24 ` David Daney
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