* [PATCH v2 00/24] Manually convert thermal, crypto and misc devices to ReST
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Rich Felker, Benjamin Herrenschmidt, linux-sh, Catalin Marinas,
linux-pci, David Howells, keyrings, Paul Mackerras, Javi Merino,
Will Deacon, Herbert Xu, Yoshinori Sato, Jonathan Corbet,
Mauro Carvalho Chehab, Michael Ellerman, Daniel Lezcano,
Viresh Kumar, linux-pm, Bjorn Helgaas, Dan Williams,
linux-arm-kernel, Amit Daniel Kachhap, Rafael J. Wysocki,
linux-crypto, linuxppc-dev, David S. Miller
Manually convert some files from thermal, crypto and misc-devices
to ReST format.
This patch is against linux-next 20200217 tag.
v2:
- a small change at patch 2 to avoid uneeded whitespace changes;
- added 13 new patches at the end
Mauro Carvalho Chehab (24):
docs: thermal: convert cpu-idle-cooling.rst to ReST
docs: crypto: convert asymmetric-keys.txt to ReST
docs: crypto: convert api-intro.txt to ReST format
docs: crypto: convert async-tx-api.txt to ReST format
docs: crypto: descore-readme.txt: convert to ReST format
docs: misc-devices/spear-pcie-gadget.txt: convert to ReST
docs: misc-devices/pci-endpoint-test.txt: convert to ReST
docs: misc-devices/pci-endpoint-test.txt: convert to ReST
docs: misc-devices/c2port.txt: convert to ReST format
docs: misc-devices/bh1770glc.txt: convert to ReST
docs: misc-devices/apds990x.txt: convert to ReST format
docs: pci: endpoint/function/binding/pci-test.txt convert to ReST
docs: arm64: convert perf.txt to ReST format
docs: cpu-freq: convert index.txt to ReST
docs: cpu-freq: convert amd-powernow.txt to ReST
docs: cpu-freq: convert core.txt to ReST
docs: cpu-freq: convert cpu-drivers.txt to ReST
docs: cpu-freq: convert cpufreq-nforce2.txt to ReST
docs: cpu-freq: convert cpufreq-stats.txt to ReST
docs: cpu-freq: convert pcc-cpufreq.txt to ReST
docs: powerpc: convert vcpudispatch_stats.txt to ReST
docs: sh: convert new-machine.txt to ReST
docs: sh: convert register-banks.txt to ReST
docs: trace: ring-buffer-design.txt: convert to ReST format
.../endpoint/function/binding/pci-test.rst | 26 +
.../endpoint/function/binding/pci-test.txt | 19 -
Documentation/PCI/endpoint/index.rst | 2 +
Documentation/arm64/index.rst | 1 +
Documentation/arm64/{perf.txt => perf.rst} | 7 +-
.../{amd-powernow.txt => amd-powernow.rst} | 12 +-
Documentation/cpu-freq/{core.txt => core.rst} | 65 +-
.../{cpu-drivers.txt => cpu-drivers.rst} | 129 ++-
...pufreq-nforce2.txt => cpufreq-nforce2.rst} | 18 +-
.../{cpufreq-stats.txt => cpufreq-stats.rst} | 121 +--
Documentation/cpu-freq/index.rst | 42 +
Documentation/cpu-freq/index.txt | 56 --
.../{pcc-cpufreq.txt => pcc-cpufreq.rst} | 86 +-
.../crypto/{api-intro.txt => api-intro.rst} | 186 ++--
...symmetric-keys.txt => asymmetric-keys.rst} | 91 +-
.../{async-tx-api.txt => async-tx-api.rst} | 253 +++---
...{descore-readme.txt => descore-readme.rst} | 152 +++-
Documentation/crypto/index.rst | 5 +
.../driver-api/thermal/cpu-idle-cooling.rst | 18 +-
Documentation/driver-api/thermal/index.rst | 1 +
Documentation/index.rst | 1 +
.../{ad525x_dpot.txt => ad525x_dpot.rst} | 24 +-
.../{apds990x.txt => apds990x.rst} | 31 +-
.../{bh1770glc.txt => bh1770glc.rst} | 45 +-
.../misc-devices/{c2port.txt => c2port.rst} | 58 +-
Documentation/misc-devices/index.rst | 6 +
.../misc-devices/pci-endpoint-test.rst | 56 ++
.../misc-devices/pci-endpoint-test.txt | 41 -
.../misc-devices/spear-pcie-gadget.rst | 170 ++++
.../misc-devices/spear-pcie-gadget.txt | 130 ---
Documentation/powerpc/index.rst | 1 +
...patch_stats.txt => vcpudispatch_stats.rst} | 17 +-
Documentation/sh/index.rst | 6 +
.../sh/{new-machine.txt => new-machine.rst} | 193 +++--
...{register-banks.txt => register-banks.rst} | 12 +-
Documentation/trace/index.rst | 1 +
...ffer-design.txt => ring-buffer-design.rst} | 802 ++++++++++--------
37 files changed, 1603 insertions(+), 1281 deletions(-)
create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.rst
delete mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
rename Documentation/arm64/{perf.txt => perf.rst} (95%)
rename Documentation/cpu-freq/{amd-powernow.txt => amd-powernow.rst} (89%)
rename Documentation/cpu-freq/{core.txt => core.rst} (69%)
rename Documentation/cpu-freq/{cpu-drivers.txt => cpu-drivers.rst} (72%)
rename Documentation/cpu-freq/{cpufreq-nforce2.txt => cpufreq-nforce2.rst} (55%)
rename Documentation/cpu-freq/{cpufreq-stats.txt => cpufreq-stats.rst} (53%)
create mode 100644 Documentation/cpu-freq/index.rst
delete mode 100644 Documentation/cpu-freq/index.txt
rename Documentation/cpu-freq/{pcc-cpufreq.txt => pcc-cpufreq.rst} (80%)
rename Documentation/crypto/{api-intro.txt => api-intro.rst} (70%)
rename Documentation/crypto/{asymmetric-keys.txt => asymmetric-keys.rst} (91%)
rename Documentation/crypto/{async-tx-api.txt => async-tx-api.rst} (55%)
rename Documentation/crypto/{descore-readme.txt => descore-readme.rst} (81%)
rename Documentation/misc-devices/{ad525x_dpot.txt => ad525x_dpot.rst} (85%)
rename Documentation/misc-devices/{apds990x.txt => apds990x.rst} (86%)
rename Documentation/misc-devices/{bh1770glc.txt => bh1770glc.rst} (83%)
rename Documentation/misc-devices/{c2port.txt => c2port.rst} (59%)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.rst
delete mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
create mode 100644 Documentation/misc-devices/spear-pcie-gadget.rst
delete mode 100644 Documentation/misc-devices/spear-pcie-gadget.txt
rename Documentation/powerpc/{vcpudispatch_stats.txt => vcpudispatch_stats.rst} (94%)
rename Documentation/sh/{new-machine.txt => new-machine.rst} (73%)
rename Documentation/sh/{register-banks.txt => register-banks.rst} (88%)
rename Documentation/trace/{ring-buffer-design.txt => ring-buffer-design.rst} (55%)
--
2.24.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v2 00/24] Manually convert thermal, crypto and misc devices to ReST
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Rich Felker, linux-sh, Catalin Marinas, linux-pci, David Howells,
keyrings, Paul Mackerras, Javi Merino, Will Deacon, Herbert Xu,
Yoshinori Sato, Jonathan Corbet, Mauro Carvalho Chehab,
Daniel Lezcano, Viresh Kumar, linux-pm, Bjorn Helgaas,
Dan Williams, linux-arm-kernel, Amit Daniel Kachhap,
Rafael J. Wysocki, linux-crypto, linuxppc-dev, David S. Miller
Manually convert some files from thermal, crypto and misc-devices
to ReST format.
This patch is against linux-next 20200217 tag.
v2:
- a small change at patch 2 to avoid uneeded whitespace changes;
- added 13 new patches at the end
Mauro Carvalho Chehab (24):
docs: thermal: convert cpu-idle-cooling.rst to ReST
docs: crypto: convert asymmetric-keys.txt to ReST
docs: crypto: convert api-intro.txt to ReST format
docs: crypto: convert async-tx-api.txt to ReST format
docs: crypto: descore-readme.txt: convert to ReST format
docs: misc-devices/spear-pcie-gadget.txt: convert to ReST
docs: misc-devices/pci-endpoint-test.txt: convert to ReST
docs: misc-devices/pci-endpoint-test.txt: convert to ReST
docs: misc-devices/c2port.txt: convert to ReST format
docs: misc-devices/bh1770glc.txt: convert to ReST
docs: misc-devices/apds990x.txt: convert to ReST format
docs: pci: endpoint/function/binding/pci-test.txt convert to ReST
docs: arm64: convert perf.txt to ReST format
docs: cpu-freq: convert index.txt to ReST
docs: cpu-freq: convert amd-powernow.txt to ReST
docs: cpu-freq: convert core.txt to ReST
docs: cpu-freq: convert cpu-drivers.txt to ReST
docs: cpu-freq: convert cpufreq-nforce2.txt to ReST
docs: cpu-freq: convert cpufreq-stats.txt to ReST
docs: cpu-freq: convert pcc-cpufreq.txt to ReST
docs: powerpc: convert vcpudispatch_stats.txt to ReST
docs: sh: convert new-machine.txt to ReST
docs: sh: convert register-banks.txt to ReST
docs: trace: ring-buffer-design.txt: convert to ReST format
.../endpoint/function/binding/pci-test.rst | 26 +
.../endpoint/function/binding/pci-test.txt | 19 -
Documentation/PCI/endpoint/index.rst | 2 +
Documentation/arm64/index.rst | 1 +
Documentation/arm64/{perf.txt => perf.rst} | 7 +-
.../{amd-powernow.txt => amd-powernow.rst} | 12 +-
Documentation/cpu-freq/{core.txt => core.rst} | 65 +-
.../{cpu-drivers.txt => cpu-drivers.rst} | 129 ++-
...pufreq-nforce2.txt => cpufreq-nforce2.rst} | 18 +-
.../{cpufreq-stats.txt => cpufreq-stats.rst} | 121 +--
Documentation/cpu-freq/index.rst | 42 +
Documentation/cpu-freq/index.txt | 56 --
.../{pcc-cpufreq.txt => pcc-cpufreq.rst} | 86 +-
.../crypto/{api-intro.txt => api-intro.rst} | 186 ++--
...symmetric-keys.txt => asymmetric-keys.rst} | 91 +-
.../{async-tx-api.txt => async-tx-api.rst} | 253 +++---
...{descore-readme.txt => descore-readme.rst} | 152 +++-
Documentation/crypto/index.rst | 5 +
.../driver-api/thermal/cpu-idle-cooling.rst | 18 +-
Documentation/driver-api/thermal/index.rst | 1 +
Documentation/index.rst | 1 +
.../{ad525x_dpot.txt => ad525x_dpot.rst} | 24 +-
.../{apds990x.txt => apds990x.rst} | 31 +-
.../{bh1770glc.txt => bh1770glc.rst} | 45 +-
.../misc-devices/{c2port.txt => c2port.rst} | 58 +-
Documentation/misc-devices/index.rst | 6 +
.../misc-devices/pci-endpoint-test.rst | 56 ++
.../misc-devices/pci-endpoint-test.txt | 41 -
.../misc-devices/spear-pcie-gadget.rst | 170 ++++
.../misc-devices/spear-pcie-gadget.txt | 130 ---
Documentation/powerpc/index.rst | 1 +
...patch_stats.txt => vcpudispatch_stats.rst} | 17 +-
Documentation/sh/index.rst | 6 +
.../sh/{new-machine.txt => new-machine.rst} | 193 +++--
...{register-banks.txt => register-banks.rst} | 12 +-
Documentation/trace/index.rst | 1 +
...ffer-design.txt => ring-buffer-design.rst} | 802 ++++++++++--------
37 files changed, 1603 insertions(+), 1281 deletions(-)
create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.rst
delete mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
rename Documentation/arm64/{perf.txt => perf.rst} (95%)
rename Documentation/cpu-freq/{amd-powernow.txt => amd-powernow.rst} (89%)
rename Documentation/cpu-freq/{core.txt => core.rst} (69%)
rename Documentation/cpu-freq/{cpu-drivers.txt => cpu-drivers.rst} (72%)
rename Documentation/cpu-freq/{cpufreq-nforce2.txt => cpufreq-nforce2.rst} (55%)
rename Documentation/cpu-freq/{cpufreq-stats.txt => cpufreq-stats.rst} (53%)
create mode 100644 Documentation/cpu-freq/index.rst
delete mode 100644 Documentation/cpu-freq/index.txt
rename Documentation/cpu-freq/{pcc-cpufreq.txt => pcc-cpufreq.rst} (80%)
rename Documentation/crypto/{api-intro.txt => api-intro.rst} (70%)
rename Documentation/crypto/{asymmetric-keys.txt => asymmetric-keys.rst} (91%)
rename Documentation/crypto/{async-tx-api.txt => async-tx-api.rst} (55%)
rename Documentation/crypto/{descore-readme.txt => descore-readme.rst} (81%)
rename Documentation/misc-devices/{ad525x_dpot.txt => ad525x_dpot.rst} (85%)
rename Documentation/misc-devices/{apds990x.txt => apds990x.rst} (86%)
rename Documentation/misc-devices/{bh1770glc.txt => bh1770glc.rst} (83%)
rename Documentation/misc-devices/{c2port.txt => c2port.rst} (59%)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.rst
delete mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
create mode 100644 Documentation/misc-devices/spear-pcie-gadget.rst
delete mode 100644 Documentation/misc-devices/spear-pcie-gadget.txt
rename Documentation/powerpc/{vcpudispatch_stats.txt => vcpudispatch_stats.rst} (94%)
rename Documentation/sh/{new-machine.txt => new-machine.rst} (73%)
rename Documentation/sh/{register-banks.txt => register-banks.rst} (88%)
rename Documentation/trace/{ring-buffer-design.txt => ring-buffer-design.rst} (55%)
--
2.24.1
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v2 00/24] Manually convert thermal, crypto and misc devices to ReST
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Daniel Lezcano,
David S. Miller, Paul Mackerras, linux-arm-kernel,
Rafael J. Wysocki, linux-sh, Will Deacon, Amit Daniel Kachhap,
linux-crypto, Catalin Marinas, keyrings, Viresh Kumar,
linuxppc-dev, Michael Ellerman, David Howells, linux-pci,
Herbert Xu, Bjorn Helgaas, Yoshinori Sato, Rich Felker, linux-pm,
Javi Merino, Dan Williams, Benjamin Herrenschmidt
Manually convert some files from thermal, crypto and misc-devices
to ReST format.
This patch is against linux-next 20200217 tag.
v2:
- a small change at patch 2 to avoid uneeded whitespace changes;
- added 13 new patches at the end
Mauro Carvalho Chehab (24):
docs: thermal: convert cpu-idle-cooling.rst to ReST
docs: crypto: convert asymmetric-keys.txt to ReST
docs: crypto: convert api-intro.txt to ReST format
docs: crypto: convert async-tx-api.txt to ReST format
docs: crypto: descore-readme.txt: convert to ReST format
docs: misc-devices/spear-pcie-gadget.txt: convert to ReST
docs: misc-devices/pci-endpoint-test.txt: convert to ReST
docs: misc-devices/pci-endpoint-test.txt: convert to ReST
docs: misc-devices/c2port.txt: convert to ReST format
docs: misc-devices/bh1770glc.txt: convert to ReST
docs: misc-devices/apds990x.txt: convert to ReST format
docs: pci: endpoint/function/binding/pci-test.txt convert to ReST
docs: arm64: convert perf.txt to ReST format
docs: cpu-freq: convert index.txt to ReST
docs: cpu-freq: convert amd-powernow.txt to ReST
docs: cpu-freq: convert core.txt to ReST
docs: cpu-freq: convert cpu-drivers.txt to ReST
docs: cpu-freq: convert cpufreq-nforce2.txt to ReST
docs: cpu-freq: convert cpufreq-stats.txt to ReST
docs: cpu-freq: convert pcc-cpufreq.txt to ReST
docs: powerpc: convert vcpudispatch_stats.txt to ReST
docs: sh: convert new-machine.txt to ReST
docs: sh: convert register-banks.txt to ReST
docs: trace: ring-buffer-design.txt: convert to ReST format
.../endpoint/function/binding/pci-test.rst | 26 +
.../endpoint/function/binding/pci-test.txt | 19 -
Documentation/PCI/endpoint/index.rst | 2 +
Documentation/arm64/index.rst | 1 +
Documentation/arm64/{perf.txt => perf.rst} | 7 +-
.../{amd-powernow.txt => amd-powernow.rst} | 12 +-
Documentation/cpu-freq/{core.txt => core.rst} | 65 +-
.../{cpu-drivers.txt => cpu-drivers.rst} | 129 ++-
...pufreq-nforce2.txt => cpufreq-nforce2.rst} | 18 +-
.../{cpufreq-stats.txt => cpufreq-stats.rst} | 121 +--
Documentation/cpu-freq/index.rst | 42 +
Documentation/cpu-freq/index.txt | 56 --
.../{pcc-cpufreq.txt => pcc-cpufreq.rst} | 86 +-
.../crypto/{api-intro.txt => api-intro.rst} | 186 ++--
...symmetric-keys.txt => asymmetric-keys.rst} | 91 +-
.../{async-tx-api.txt => async-tx-api.rst} | 253 +++---
...{descore-readme.txt => descore-readme.rst} | 152 +++-
Documentation/crypto/index.rst | 5 +
.../driver-api/thermal/cpu-idle-cooling.rst | 18 +-
Documentation/driver-api/thermal/index.rst | 1 +
Documentation/index.rst | 1 +
.../{ad525x_dpot.txt => ad525x_dpot.rst} | 24 +-
.../{apds990x.txt => apds990x.rst} | 31 +-
.../{bh1770glc.txt => bh1770glc.rst} | 45 +-
.../misc-devices/{c2port.txt => c2port.rst} | 58 +-
Documentation/misc-devices/index.rst | 6 +
.../misc-devices/pci-endpoint-test.rst | 56 ++
.../misc-devices/pci-endpoint-test.txt | 41 -
.../misc-devices/spear-pcie-gadget.rst | 170 ++++
.../misc-devices/spear-pcie-gadget.txt | 130 ---
Documentation/powerpc/index.rst | 1 +
...patch_stats.txt => vcpudispatch_stats.rst} | 17 +-
Documentation/sh/index.rst | 6 +
.../sh/{new-machine.txt => new-machine.rst} | 193 +++--
...{register-banks.txt => register-banks.rst} | 12 +-
Documentation/trace/index.rst | 1 +
...ffer-design.txt => ring-buffer-design.rst} | 802 ++++++++++--------
37 files changed, 1603 insertions(+), 1281 deletions(-)
create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.rst
delete mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
rename Documentation/arm64/{perf.txt => perf.rst} (95%)
rename Documentation/cpu-freq/{amd-powernow.txt => amd-powernow.rst} (89%)
rename Documentation/cpu-freq/{core.txt => core.rst} (69%)
rename Documentation/cpu-freq/{cpu-drivers.txt => cpu-drivers.rst} (72%)
rename Documentation/cpu-freq/{cpufreq-nforce2.txt => cpufreq-nforce2.rst} (55%)
rename Documentation/cpu-freq/{cpufreq-stats.txt => cpufreq-stats.rst} (53%)
create mode 100644 Documentation/cpu-freq/index.rst
delete mode 100644 Documentation/cpu-freq/index.txt
rename Documentation/cpu-freq/{pcc-cpufreq.txt => pcc-cpufreq.rst} (80%)
rename Documentation/crypto/{api-intro.txt => api-intro.rst} (70%)
rename Documentation/crypto/{asymmetric-keys.txt => asymmetric-keys.rst} (91%)
rename Documentation/crypto/{async-tx-api.txt => async-tx-api.rst} (55%)
rename Documentation/crypto/{descore-readme.txt => descore-readme.rst} (81%)
rename Documentation/misc-devices/{ad525x_dpot.txt => ad525x_dpot.rst} (85%)
rename Documentation/misc-devices/{apds990x.txt => apds990x.rst} (86%)
rename Documentation/misc-devices/{bh1770glc.txt => bh1770glc.rst} (83%)
rename Documentation/misc-devices/{c2port.txt => c2port.rst} (59%)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.rst
delete mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
create mode 100644 Documentation/misc-devices/spear-pcie-gadget.rst
delete mode 100644 Documentation/misc-devices/spear-pcie-gadget.txt
rename Documentation/powerpc/{vcpudispatch_stats.txt => vcpudispatch_stats.rst} (94%)
rename Documentation/sh/{new-machine.txt => new-machine.rst} (73%)
rename Documentation/sh/{register-banks.txt => register-banks.rst} (88%)
rename Documentation/trace/{ring-buffer-design.txt => ring-buffer-design.rst} (55%)
--
2.24.1
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v2 01/24] docs: thermal: convert cpu-idle-cooling.rst to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (2 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Amit Daniel Kachhap,
Daniel Lezcano, Viresh Kumar, Javi Merino, linux-pm
Despite being named with .rst extension, this file doesn't
match the ReST standard. It actually causes a crash at
Sphinx:
Sphinx parallel build error:
docutils.utils.SystemMessage: /devel/v4l/docs/Documentation/driver-api/thermal/cpu-idle-cooling.rst:69: (SEVERE/4) Unexpected section title.
Add needed markups for it to be properly parsed.
While here, add it to the thermal index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../driver-api/thermal/cpu-idle-cooling.rst | 18 ++++++++++++------
Documentation/driver-api/thermal/index.rst | 1 +
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/Documentation/driver-api/thermal/cpu-idle-cooling.rst b/Documentation/driver-api/thermal/cpu-idle-cooling.rst
index 9f0016ee4cfb..357d2f023605 100644
--- a/Documentation/driver-api/thermal/cpu-idle-cooling.rst
+++ b/Documentation/driver-api/thermal/cpu-idle-cooling.rst
@@ -1,3 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+================
+CPU Idle Cooling
+================
+
Situation:
----------
@@ -45,7 +51,7 @@ idle state target residency, we lead to dropping the static and the
dynamic leakage for this period (modulo the energy needed to enter
this state). So the sustainable power with idle cycles has a linear
relation with the OPP’s sustainable power and can be computed with a
-coefficient similar to:
+coefficient similar to::
Power(IdleCycle) = Coef x Power(OPP)
@@ -136,7 +142,7 @@ Power considerations
--------------------
When we reach the thermal trip point, we have to sustain a specified
-power for a specific temperature but at this time we consume:
+power for a specific temperature but at this time we consume::
Power = Capacitance x Voltage^2 x Frequency x Utilisation
@@ -145,7 +151,7 @@ wrong in the system setup). The ‘Capacitance’ and ‘Utilisation’ are a
fixed value, ‘Voltage’ and the ‘Frequency’ are fixed artificially
because we don’t want to change the OPP. We can group the
‘Capacitance’ and the ‘Utilisation’ into a single term which is the
-‘Dynamic Power Coefficient (Cdyn)’ Simplifying the above, we have:
+‘Dynamic Power Coefficient (Cdyn)’ Simplifying the above, we have::
Pdyn = Cdyn x Voltage^2 x Frequency
@@ -154,7 +160,7 @@ in order to target the sustainable power defined in the device
tree. So with the idle injection mechanism, we want an average power
(Ptarget) resulting in an amount of time running at full power on a
specific OPP and idle another amount of time. That could be put in a
-equation:
+equation::
P(opp)target = ((Trunning x (P(opp)running) + (Tidle x P(opp)idle)) /
(Trunning + Tidle)
@@ -165,7 +171,7 @@ equation:
At this point if we know the running period for the CPU, that gives us
the idle injection we need. Alternatively if we have the idle
-injection duration, we can compute the running duration with:
+injection duration, we can compute the running duration with::
Trunning = Tidle / ((P(opp)running / P(opp)target) - 1)
@@ -188,7 +194,7 @@ However, in this demonstration we ignore three aspects:
target residency, otherwise we end up consuming more energy and
potentially invert the mitigation effect
-So the final equation is:
+So the final equation is::
Trunning = (Tidle - Twakeup ) x
(((P(opp)dyn + P(opp)static ) - P(opp)target) / P(opp)target )
diff --git a/Documentation/driver-api/thermal/index.rst b/Documentation/driver-api/thermal/index.rst
index 5ba61d19c6ae..4cb0b9b6bfb8 100644
--- a/Documentation/driver-api/thermal/index.rst
+++ b/Documentation/driver-api/thermal/index.rst
@@ -8,6 +8,7 @@ Thermal
:maxdepth: 1
cpu-cooling-api
+ cpu-idle-cooling
sysfs-api
power_allocator
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 02/24] docs: crypto: convert asymmetric-keys.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Herbert Xu,
David S. Miller, David Howells, linux-crypto, keyrings
This file is almost compatible with ReST. Just minor changes
were needed:
- Adjust document and titles markups;
- Adjust numbered list markups;
- Add a comments markup for the Contents section;
- Add markups for literal blocks.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
...symmetric-keys.txt => asymmetric-keys.rst} | 91 +++++++++----------
Documentation/crypto/index.rst | 1 +
2 files changed, 44 insertions(+), 48 deletions(-)
rename Documentation/crypto/{asymmetric-keys.txt => asymmetric-keys.rst} (91%)
diff --git a/Documentation/crypto/asymmetric-keys.txt b/Documentation/crypto/asymmetric-keys.rst
similarity index 91%
rename from Documentation/crypto/asymmetric-keys.txt
rename to Documentation/crypto/asymmetric-keys.rst
index 8763866b11cf..349f44a29392 100644
--- a/Documentation/crypto/asymmetric-keys.txt
+++ b/Documentation/crypto/asymmetric-keys.rst
@@ -1,8 +1,10 @@
- =============================================
- ASYMMETRIC / PUBLIC-KEY CRYPTOGRAPHY KEY TYPE
- =============================================
+.. SPDX-License-Identifier: GPL-2.0
-Contents:
+=============================================
+Asymmetric / Public-key Cryptography Key Type
+=============================================
+
+.. Contents:
- Overview.
- Key identification.
@@ -13,8 +15,7 @@ Contents:
- Keyring link restrictions.
-========
-OVERVIEW
+Overview
========
The "asymmetric" key type is designed to be a container for the keys used in
@@ -42,8 +43,7 @@ key, or it may interpret it as a reference to a key held somewhere else in the
system (for example, a TPM).
-==================
-KEY IDENTIFICATION
+Key Identification
==================
If a key is added with an empty name, the instantiation data parsers are given
@@ -57,49 +57,48 @@ The asymmetric key type's match function can then perform a wider range of
comparisons than just the straightforward comparison of the description with
the criterion string:
- (1) If the criterion string is of the form "id:<hexdigits>" then the match
+ 1) If the criterion string is of the form "id:<hexdigits>" then the match
function will examine a key's fingerprint to see if the hex digits given
- after the "id:" match the tail. For instance:
+ after the "id:" match the tail. For instance::
keyctl search @s asymmetric id:5acc2142
- will match a key with fingerprint:
+ will match a key with fingerprint::
1A00 2040 7601 7889 DE11 882C 3823 04AD 5ACC 2142
- (2) If the criterion string is of the form "<subtype>:<hexdigits>" then the
+ 2) If the criterion string is of the form "<subtype>:<hexdigits>" then the
match will match the ID as in (1), but with the added restriction that
only keys of the specified subtype (e.g. tpm) will be matched. For
- instance:
+ instance::
keyctl search @s asymmetric tpm:5acc2142
Looking in /proc/keys, the last 8 hex digits of the key fingerprint are
-displayed, along with the subtype:
+displayed, along with the subtype::
1a39e171 I----- 1 perm 3f010000 0 0 asymmetric modsign.0: DSA 5acc2142 []
-=========================
-ACCESSING ASYMMETRIC KEYS
+Accessing Asymmetric Keys
=========================
For general access to asymmetric keys from within the kernel, the following
-inclusion is required:
+inclusion is required::
#include <crypto/public_key.h>
This gives access to functions for dealing with asymmetric / public keys.
Three enums are defined there for representing public-key cryptography
-algorithms:
+algorithms::
enum pkey_algo
-digest algorithms used by those:
+digest algorithms used by those::
enum pkey_hash_algo
-and key identifier representations:
+and key identifier representations::
enum pkey_id_type
@@ -110,25 +109,25 @@ PGP-specific metadata, whereas X.509 has arbitrary certificate identifiers.
The operations defined upon a key are:
- (1) Signature verification.
+ 1) Signature verification.
Other operations are possible (such as encryption) with the same key data
required for verification, but not currently supported, and others
(eg. decryption and signature generation) require extra key data.
-SIGNATURE VERIFICATION
+Signature Verification
----------------------
An operation is provided to perform cryptographic signature verification, using
-an asymmetric key to provide or to provide access to the public key.
+an asymmetric key to provide or to provide access to the public key::
int verify_signature(const struct key *key,
const struct public_key_signature *sig);
The caller must have already obtained the key from some source and can then use
it to check the signature. The caller must have parsed the signature and
-transferred the relevant bits to the structure pointed to by sig.
+transferred the relevant bits to the structure pointed to by sig::
struct public_key_signature {
u8 *digest;
@@ -159,8 +158,7 @@ data; or -ENOMEM if an allocation can't be performed. -EINVAL can be returned
if the key argument is the wrong type or is incompletely set up.
-=======================
-ASYMMETRIC KEY SUBTYPES
+Asymmetric Key Subtypes
=======================
Asymmetric keys have a subtype that defines the set of operations that can be
@@ -171,11 +169,11 @@ The subtype is selected by the key data parser and the parser must initialise
the data required for it. The asymmetric key retains a reference on the
subtype module.
-The subtype definition structure can be found in:
+The subtype definition structure can be found in::
#include <keys/asymmetric-subtype.h>
-and looks like the following:
+and looks like the following::
struct asymmetric_key_subtype {
struct module *owner;
@@ -198,39 +196,37 @@ the subtype. Currently, the name is only used for print statements.
There are a number of operations defined by the subtype:
- (1) describe().
+ 1) describe().
Mandatory. This allows the subtype to display something in /proc/keys
against the key. For instance the name of the public key algorithm type
could be displayed. The key type will display the tail of the key
identity string after this.
- (2) destroy().
+ 2) destroy().
Mandatory. This should free the memory associated with the key. The
asymmetric key will look after freeing the fingerprint and releasing the
reference on the subtype module.
- (3) query().
+ 3) query().
Mandatory. This is a function for querying the capabilities of a key.
- (4) eds_op().
+ 4) eds_op().
Optional. This is the entry point for the encryption, decryption and
signature creation operations (which are distinguished by the operation ID
in the parameter struct). The subtype may do anything it likes to
implement an operation, including offloading to hardware.
- (5) verify_signature().
+ 5) verify_signature().
Optional. This is the entry point for signature verification. The
subtype may do anything it likes to implement an operation, including
offloading to hardware.
-
-==========================
-INSTANTIATION DATA PARSERS
+Instantiation Data Parsers
==========================
The asymmetric key type doesn't generally want to store or to deal with a raw
@@ -254,11 +250,11 @@ Examples of blob formats for which parsers could be implemented include:
During key instantiation each parser in the list is tried until one doesn't
return -EBADMSG.
-The parser definition structure can be found in:
+The parser definition structure can be found in::
#include <keys/asymmetric-parser.h>
-and looks like the following:
+and looks like the following::
struct asymmetric_key_parser {
struct module *owner;
@@ -273,7 +269,7 @@ the parser.
There is currently only a single operation defined by the parser, and it is
mandatory:
- (1) parse().
+ 1) parse().
This is called to preparse the key from the key creation and update paths.
In particular, it is called during the key creation _before_ a key is
@@ -282,7 +278,7 @@ mandatory:
The caller passes a pointer to the following struct with all of the fields
cleared, except for data, datalen and quotalen [see
- Documentation/security/keys/core.rst].
+ Documentation/security/keys/core.rst]::
struct key_preparsed_payload {
char *description;
@@ -321,7 +317,7 @@ mandatory:
public-key algorithm such as RSA and DSA this will likely be a printable
hex version of the key's fingerprint.
-Functions are provided to register and unregister parsers:
+Functions are provided to register and unregister parsers::
int register_asymmetric_key_parser(struct asymmetric_key_parser *parser);
void unregister_asymmetric_key_parser(struct asymmetric_key_parser *subtype);
@@ -330,8 +326,7 @@ Parsers may not have the same name. The names are otherwise only used for
displaying in debugging messages.
-=========================
-KEYRING LINK RESTRICTIONS
+Keyring Link Restrictions
=========================
Keyrings created from userspace using add_key can be configured to check the
@@ -340,7 +335,7 @@ allowed to link.
Several restriction methods are available:
- (1) Restrict using the kernel builtin trusted keyring
+ 1) Restrict using the kernel builtin trusted keyring
- Option string used with KEYCTL_RESTRICT_KEYRING:
- "builtin_trusted"
@@ -350,7 +345,7 @@ Several restriction methods are available:
rejected. The ca_keys kernel parameter also affects which keys are used
for signature verification.
- (2) Restrict using the kernel builtin and secondary trusted keyrings
+ 2) Restrict using the kernel builtin and secondary trusted keyrings
- Option string used with KEYCTL_RESTRICT_KEYRING:
- "builtin_and_secondary_trusted"
@@ -361,7 +356,7 @@ Several restriction methods are available:
kernel parameter also affects which keys are used for signature
verification.
- (3) Restrict using a separate key or keyring
+ 3) Restrict using a separate key or keyring
- Option string used with KEYCTL_RESTRICT_KEYRING:
- "key_or_keyring:<key or keyring serial number>[:chain]"
@@ -378,7 +373,7 @@ Several restriction methods are available:
certificate in order (starting closest to the root) to a keyring. For
instance, one keyring can be populated with links to a set of root
certificates, with a separate, restricted keyring set up for each
- certificate chain to be validated:
+ certificate chain to be validated::
# Create and populate a keyring for root certificates
root_id=`keyctl add keyring root-certs "" @s`
@@ -400,7 +395,7 @@ Several restriction methods are available:
one of the root certificates.
A single keyring can be used to verify a chain of signatures by
- restricting the keyring after linking the root certificate:
+ restricting the keyring after linking the root certificate::
# Create a keyring for the certificate chain and add the root
chain2_id=`keyctl add keyring chain2 "" @s`
diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst
index c4ff5d791233..2bcaf422731e 100644
--- a/Documentation/crypto/index.rst
+++ b/Documentation/crypto/index.rst
@@ -18,6 +18,7 @@ for cryptographic use cases, as well as programming examples.
intro
architecture
+ asymmetric-keys
devel-algos
userspace-if
crypto_engine
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 02/24] docs: crypto: convert asymmetric-keys.txt to ReST
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Herbert Xu,
David S. Miller, David Howells, linux-crypto, keyrings
This file is almost compatible with ReST. Just minor changes
were needed:
- Adjust document and titles markups;
- Adjust numbered list markups;
- Add a comments markup for the Contents section;
- Add markups for literal blocks.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
...symmetric-keys.txt => asymmetric-keys.rst} | 91 +++++++++----------
Documentation/crypto/index.rst | 1 +
2 files changed, 44 insertions(+), 48 deletions(-)
rename Documentation/crypto/{asymmetric-keys.txt => asymmetric-keys.rst} (91%)
diff --git a/Documentation/crypto/asymmetric-keys.txt b/Documentation/crypto/asymmetric-keys.rst
similarity index 91%
rename from Documentation/crypto/asymmetric-keys.txt
rename to Documentation/crypto/asymmetric-keys.rst
index 8763866b11cf..349f44a29392 100644
--- a/Documentation/crypto/asymmetric-keys.txt
+++ b/Documentation/crypto/asymmetric-keys.rst
@@ -1,8 +1,10 @@
- ======================- ASYMMETRIC / PUBLIC-KEY CRYPTOGRAPHY KEY TYPE
- ======================+.. SPDX-License-Identifier: GPL-2.0
-Contents:
+======================+Asymmetric / Public-key Cryptography Key Type
+======================+
+.. Contents:
- Overview.
- Key identification.
@@ -13,8 +15,7 @@ Contents:
- Keyring link restrictions.
-====
-OVERVIEW
+Overview
====
The "asymmetric" key type is designed to be a container for the keys used in
@@ -42,8 +43,7 @@ key, or it may interpret it as a reference to a key held somewhere else in the
system (for example, a TPM).
-=========
-KEY IDENTIFICATION
+Key Identification
=========
If a key is added with an empty name, the instantiation data parsers are given
@@ -57,49 +57,48 @@ The asymmetric key type's match function can then perform a wider range of
comparisons than just the straightforward comparison of the description with
the criterion string:
- (1) If the criterion string is of the form "id:<hexdigits>" then the match
+ 1) If the criterion string is of the form "id:<hexdigits>" then the match
function will examine a key's fingerprint to see if the hex digits given
- after the "id:" match the tail. For instance:
+ after the "id:" match the tail. For instance::
keyctl search @s asymmetric id:5acc2142
- will match a key with fingerprint:
+ will match a key with fingerprint::
1A00 2040 7601 7889 DE11 882C 3823 04AD 5ACC 2142
- (2) If the criterion string is of the form "<subtype>:<hexdigits>" then the
+ 2) If the criterion string is of the form "<subtype>:<hexdigits>" then the
match will match the ID as in (1), but with the added restriction that
only keys of the specified subtype (e.g. tpm) will be matched. For
- instance:
+ instance::
keyctl search @s asymmetric tpm:5acc2142
Looking in /proc/keys, the last 8 hex digits of the key fingerprint are
-displayed, along with the subtype:
+displayed, along with the subtype::
1a39e171 I----- 1 perm 3f010000 0 0 asymmetric modsign.0: DSA 5acc2142 []
-============-ACCESSING ASYMMETRIC KEYS
+Accessing Asymmetric Keys
============
For general access to asymmetric keys from within the kernel, the following
-inclusion is required:
+inclusion is required::
#include <crypto/public_key.h>
This gives access to functions for dealing with asymmetric / public keys.
Three enums are defined there for representing public-key cryptography
-algorithms:
+algorithms::
enum pkey_algo
-digest algorithms used by those:
+digest algorithms used by those::
enum pkey_hash_algo
-and key identifier representations:
+and key identifier representations::
enum pkey_id_type
@@ -110,25 +109,25 @@ PGP-specific metadata, whereas X.509 has arbitrary certificate identifiers.
The operations defined upon a key are:
- (1) Signature verification.
+ 1) Signature verification.
Other operations are possible (such as encryption) with the same key data
required for verification, but not currently supported, and others
(eg. decryption and signature generation) require extra key data.
-SIGNATURE VERIFICATION
+Signature Verification
----------------------
An operation is provided to perform cryptographic signature verification, using
-an asymmetric key to provide or to provide access to the public key.
+an asymmetric key to provide or to provide access to the public key::
int verify_signature(const struct key *key,
const struct public_key_signature *sig);
The caller must have already obtained the key from some source and can then use
it to check the signature. The caller must have parsed the signature and
-transferred the relevant bits to the structure pointed to by sig.
+transferred the relevant bits to the structure pointed to by sig::
struct public_key_signature {
u8 *digest;
@@ -159,8 +158,7 @@ data; or -ENOMEM if an allocation can't be performed. -EINVAL can be returned
if the key argument is the wrong type or is incompletely set up.
-===========-ASYMMETRIC KEY SUBTYPES
+Asymmetric Key Subtypes
===========
Asymmetric keys have a subtype that defines the set of operations that can be
@@ -171,11 +169,11 @@ The subtype is selected by the key data parser and the parser must initialise
the data required for it. The asymmetric key retains a reference on the
subtype module.
-The subtype definition structure can be found in:
+The subtype definition structure can be found in::
#include <keys/asymmetric-subtype.h>
-and looks like the following:
+and looks like the following::
struct asymmetric_key_subtype {
struct module *owner;
@@ -198,39 +196,37 @@ the subtype. Currently, the name is only used for print statements.
There are a number of operations defined by the subtype:
- (1) describe().
+ 1) describe().
Mandatory. This allows the subtype to display something in /proc/keys
against the key. For instance the name of the public key algorithm type
could be displayed. The key type will display the tail of the key
identity string after this.
- (2) destroy().
+ 2) destroy().
Mandatory. This should free the memory associated with the key. The
asymmetric key will look after freeing the fingerprint and releasing the
reference on the subtype module.
- (3) query().
+ 3) query().
Mandatory. This is a function for querying the capabilities of a key.
- (4) eds_op().
+ 4) eds_op().
Optional. This is the entry point for the encryption, decryption and
signature creation operations (which are distinguished by the operation ID
in the parameter struct). The subtype may do anything it likes to
implement an operation, including offloading to hardware.
- (5) verify_signature().
+ 5) verify_signature().
Optional. This is the entry point for signature verification. The
subtype may do anything it likes to implement an operation, including
offloading to hardware.
-
-=============
-INSTANTIATION DATA PARSERS
+Instantiation Data Parsers
=============
The asymmetric key type doesn't generally want to store or to deal with a raw
@@ -254,11 +250,11 @@ Examples of blob formats for which parsers could be implemented include:
During key instantiation each parser in the list is tried until one doesn't
return -EBADMSG.
-The parser definition structure can be found in:
+The parser definition structure can be found in::
#include <keys/asymmetric-parser.h>
-and looks like the following:
+and looks like the following::
struct asymmetric_key_parser {
struct module *owner;
@@ -273,7 +269,7 @@ the parser.
There is currently only a single operation defined by the parser, and it is
mandatory:
- (1) parse().
+ 1) parse().
This is called to preparse the key from the key creation and update paths.
In particular, it is called during the key creation _before_ a key is
@@ -282,7 +278,7 @@ mandatory:
The caller passes a pointer to the following struct with all of the fields
cleared, except for data, datalen and quotalen [see
- Documentation/security/keys/core.rst].
+ Documentation/security/keys/core.rst]::
struct key_preparsed_payload {
char *description;
@@ -321,7 +317,7 @@ mandatory:
public-key algorithm such as RSA and DSA this will likely be a printable
hex version of the key's fingerprint.
-Functions are provided to register and unregister parsers:
+Functions are provided to register and unregister parsers::
int register_asymmetric_key_parser(struct asymmetric_key_parser *parser);
void unregister_asymmetric_key_parser(struct asymmetric_key_parser *subtype);
@@ -330,8 +326,7 @@ Parsers may not have the same name. The names are otherwise only used for
displaying in debugging messages.
-============-KEYRING LINK RESTRICTIONS
+Keyring Link Restrictions
============
Keyrings created from userspace using add_key can be configured to check the
@@ -340,7 +335,7 @@ allowed to link.
Several restriction methods are available:
- (1) Restrict using the kernel builtin trusted keyring
+ 1) Restrict using the kernel builtin trusted keyring
- Option string used with KEYCTL_RESTRICT_KEYRING:
- "builtin_trusted"
@@ -350,7 +345,7 @@ Several restriction methods are available:
rejected. The ca_keys kernel parameter also affects which keys are used
for signature verification.
- (2) Restrict using the kernel builtin and secondary trusted keyrings
+ 2) Restrict using the kernel builtin and secondary trusted keyrings
- Option string used with KEYCTL_RESTRICT_KEYRING:
- "builtin_and_secondary_trusted"
@@ -361,7 +356,7 @@ Several restriction methods are available:
kernel parameter also affects which keys are used for signature
verification.
- (3) Restrict using a separate key or keyring
+ 3) Restrict using a separate key or keyring
- Option string used with KEYCTL_RESTRICT_KEYRING:
- "key_or_keyring:<key or keyring serial number>[:chain]"
@@ -378,7 +373,7 @@ Several restriction methods are available:
certificate in order (starting closest to the root) to a keyring. For
instance, one keyring can be populated with links to a set of root
certificates, with a separate, restricted keyring set up for each
- certificate chain to be validated:
+ certificate chain to be validated::
# Create and populate a keyring for root certificates
root_id=`keyctl add keyring root-certs "" @s`
@@ -400,7 +395,7 @@ Several restriction methods are available:
one of the root certificates.
A single keyring can be used to verify a chain of signatures by
- restricting the keyring after linking the root certificate:
+ restricting the keyring after linking the root certificate::
# Create a keyring for the certificate chain and add the root
chain2_id=`keyctl add keyring chain2 "" @s`
diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst
index c4ff5d791233..2bcaf422731e 100644
--- a/Documentation/crypto/index.rst
+++ b/Documentation/crypto/index.rst
@@ -18,6 +18,7 @@ for cryptographic use cases, as well as programming examples.
intro
architecture
+ asymmetric-keys
devel-algos
userspace-if
crypto_engine
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 03/24] docs: crypto: convert api-intro.txt to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (4 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Herbert Xu,
David S. Miller, linux-crypto
- Change title markups;
- Mark literal blocks;
- Use list markups at authors/credits;
- Add blank lines when needed;
- Remove trailing whitespaces.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../crypto/{api-intro.txt => api-intro.rst} | 186 ++++++++++--------
Documentation/crypto/index.rst | 1 +
2 files changed, 100 insertions(+), 87 deletions(-)
rename Documentation/crypto/{api-intro.txt => api-intro.rst} (70%)
diff --git a/Documentation/crypto/api-intro.txt b/Documentation/crypto/api-intro.rst
similarity index 70%
rename from Documentation/crypto/api-intro.txt
rename to Documentation/crypto/api-intro.rst
index 45d943fcae5b..bcff47d42189 100644
--- a/Documentation/crypto/api-intro.txt
+++ b/Documentation/crypto/api-intro.rst
@@ -1,7 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0
- Scatterlist Cryptographic API
-
-INTRODUCTION
+=============================
+Scatterlist Cryptographic API
+=============================
+
+Introduction
+============
The Scatterlist Crypto API takes page vectors (scatterlists) as
arguments, and works directly on pages. In some cases (e.g. ECB
@@ -13,22 +17,23 @@ so that processing can be applied to paged skb's without the need
for linearization.
-DETAILS
+Details
+=======
At the lowest level are algorithms, which register dynamically with the
API.
'Transforms' are user-instantiated objects, which maintain state, handle all
-of the implementation logic (e.g. manipulating page vectors) and provide an
-abstraction to the underlying algorithms. However, at the user
+of the implementation logic (e.g. manipulating page vectors) and provide an
+abstraction to the underlying algorithms. However, at the user
level they are very simple.
-Conceptually, the API layering looks like this:
+Conceptually, the API layering looks like this::
[transform api] (user interface)
[transform ops] (per-type logic glue e.g. cipher.c, compress.c)
[algorithm api] (for registering algorithms)
-
+
The idea is to make the user interface and algorithm registration API
very simple, while hiding the core logic from both. Many good ideas
from existing APIs such as Cryptoapi and Nettle have been adapted for this.
@@ -44,21 +49,21 @@ one block while the former can operate on an arbitrary amount of data,
subject to block size requirements (i.e., non-stream ciphers can only
process multiples of blocks).
-Here's an example of how to use the API:
+Here's an example of how to use the API::
#include <crypto/hash.h>
#include <linux/err.h>
#include <linux/scatterlist.h>
-
+
struct scatterlist sg[2];
char result[128];
struct crypto_ahash *tfm;
struct ahash_request *req;
-
+
tfm = crypto_alloc_ahash("md5", 0, CRYPTO_ALG_ASYNC);
if (IS_ERR(tfm))
fail();
-
+
/* ... set up the scatterlists ... */
req = ahash_request_alloc(tfm, GFP_ATOMIC);
@@ -67,18 +72,19 @@ Here's an example of how to use the API:
ahash_request_set_callback(req, 0, NULL, NULL);
ahash_request_set_crypt(req, sg, result, 2);
-
+
if (crypto_ahash_digest(req))
fail();
ahash_request_free(req);
crypto_free_ahash(tfm);
-
+
Many real examples are available in the regression test module (tcrypt.c).
-DEVELOPER NOTES
+Developer Notes
+===============
Transforms may only be allocated in user context, and cryptographic
methods may only be called from softirq and user contexts. For
@@ -91,7 +97,8 @@ size (typically 8 bytes). This prevents having to do any copying
across non-aligned page fragment boundaries.
-ADDING NEW ALGORITHMS
+Adding New Algorithms
+=====================
When submitting a new algorithm for inclusion, a mandatory requirement
is that at least a few test vectors from known sources (preferably
@@ -119,132 +126,137 @@ Also check the TODO list at the web site listed below to see what people
might already be working on.
-BUGS
+Bugs
+====
Send bug reports to:
-linux-crypto@vger.kernel.org
-Cc: Herbert Xu <herbert@gondor.apana.org.au>,
+ linux-crypto@vger.kernel.org
+
+Cc:
+ Herbert Xu <herbert@gondor.apana.org.au>,
David S. Miller <davem@redhat.com>
-FURTHER INFORMATION
+Further Information
+===================
For further patches and various updates, including the current TODO
list, see:
http://gondor.apana.org.au/~herbert/crypto/
-AUTHORS
+Authors
+=======
-James Morris
-David S. Miller
-Herbert Xu
+- James Morris
+- David S. Miller
+- Herbert Xu
-CREDITS
+Credits
+=======
The following people provided invaluable feedback during the development
of the API:
- Alexey Kuznetzov
- Rusty Russell
- Herbert Valerio Riedel
- Jeff Garzik
- Michael Richardson
- Andrew Morton
- Ingo Oeser
- Christoph Hellwig
+ - Alexey Kuznetzov
+ - Rusty Russell
+ - Herbert Valerio Riedel
+ - Jeff Garzik
+ - Michael Richardson
+ - Andrew Morton
+ - Ingo Oeser
+ - Christoph Hellwig
Portions of this API were derived from the following projects:
-
+
Kerneli Cryptoapi (http://www.kerneli.org/)
- Alexander Kjeldaas
- Herbert Valerio Riedel
- Kyle McMartin
- Jean-Luc Cooke
- David Bryson
- Clemens Fruhwirth
- Tobias Ringstrom
- Harald Welte
+ - Alexander Kjeldaas
+ - Herbert Valerio Riedel
+ - Kyle McMartin
+ - Jean-Luc Cooke
+ - David Bryson
+ - Clemens Fruhwirth
+ - Tobias Ringstrom
+ - Harald Welte
and;
-
+
Nettle (http://www.lysator.liu.se/~nisse/nettle/)
- Niels Möller
+ - Niels Möller
Original developers of the crypto algorithms:
- Dana L. How (DES)
- Andrew Tridgell and Steve French (MD4)
- Colin Plumb (MD5)
- Steve Reid (SHA1)
- Jean-Luc Cooke (SHA256, SHA384, SHA512)
- Kazunori Miyazawa / USAGI (HMAC)
- Matthew Skala (Twofish)
- Dag Arne Osvik (Serpent)
- Brian Gladman (AES)
- Kartikey Mahendra Bhatt (CAST6)
- Jon Oberheide (ARC4)
- Jouni Malinen (Michael MIC)
- NTT(Nippon Telegraph and Telephone Corporation) (Camellia)
+ - Dana L. How (DES)
+ - Andrew Tridgell and Steve French (MD4)
+ - Colin Plumb (MD5)
+ - Steve Reid (SHA1)
+ - Jean-Luc Cooke (SHA256, SHA384, SHA512)
+ - Kazunori Miyazawa / USAGI (HMAC)
+ - Matthew Skala (Twofish)
+ - Dag Arne Osvik (Serpent)
+ - Brian Gladman (AES)
+ - Kartikey Mahendra Bhatt (CAST6)
+ - Jon Oberheide (ARC4)
+ - Jouni Malinen (Michael MIC)
+ - NTT(Nippon Telegraph and Telephone Corporation) (Camellia)
SHA1 algorithm contributors:
- Jean-Francois Dive
-
+ - Jean-Francois Dive
+
DES algorithm contributors:
- Raimar Falke
- Gisle Sælensminde
- Niels Möller
+ - Raimar Falke
+ - Gisle Sælensminde
+ - Niels Möller
Blowfish algorithm contributors:
- Herbert Valerio Riedel
- Kyle McMartin
+ - Herbert Valerio Riedel
+ - Kyle McMartin
Twofish algorithm contributors:
- Werner Koch
- Marc Mutz
+ - Werner Koch
+ - Marc Mutz
SHA256/384/512 algorithm contributors:
- Andrew McDonald
- Kyle McMartin
- Herbert Valerio Riedel
-
+ - Andrew McDonald
+ - Kyle McMartin
+ - Herbert Valerio Riedel
+
AES algorithm contributors:
- Alexander Kjeldaas
- Herbert Valerio Riedel
- Kyle McMartin
- Adam J. Richter
- Fruhwirth Clemens (i586)
- Linus Torvalds (i586)
+ - Alexander Kjeldaas
+ - Herbert Valerio Riedel
+ - Kyle McMartin
+ - Adam J. Richter
+ - Fruhwirth Clemens (i586)
+ - Linus Torvalds (i586)
CAST5 algorithm contributors:
- Kartikey Mahendra Bhatt (original developers unknown, FSF copyright).
+ - Kartikey Mahendra Bhatt (original developers unknown, FSF copyright).
TEA/XTEA algorithm contributors:
- Aaron Grothe
- Michael Ringe
+ - Aaron Grothe
+ - Michael Ringe
Khazad algorithm contributors:
- Aaron Grothe
+ - Aaron Grothe
Whirlpool algorithm contributors:
- Aaron Grothe
- Jean-Luc Cooke
+ - Aaron Grothe
+ - Jean-Luc Cooke
Anubis algorithm contributors:
- Aaron Grothe
+ - Aaron Grothe
Tiger algorithm contributors:
- Aaron Grothe
+ - Aaron Grothe
VIA PadLock contributors:
- Michal Ludvig
+ - Michal Ludvig
Camellia algorithm contributors:
- NTT(Nippon Telegraph and Telephone Corporation) (Camellia)
+ - NTT(Nippon Telegraph and Telephone Corporation) (Camellia)
Generic scatterwalk code by Adam J. Richter <adam@yggdrasil.com>
Please send any credits updates or corrections to:
Herbert Xu <herbert@gondor.apana.org.au>
-
diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst
index 2bcaf422731e..b2eeab3c8631 100644
--- a/Documentation/crypto/index.rst
+++ b/Documentation/crypto/index.rst
@@ -17,6 +17,7 @@ for cryptographic use cases, as well as programming examples.
:maxdepth: 2
intro
+ api-intro
architecture
asymmetric-keys
devel-algos
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 04/24] docs: crypto: convert async-tx-api.txt to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (5 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Herbert Xu,
David S. Miller, Dan Williams, linux-crypto
- Place the txt index inside a comment;
- Use title and chapter markups;
- Adjust markups for numbered list;
- Mark literal blocks as such;
- Use tables markup.
- Adjust indentation when needed.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../{async-tx-api.txt => async-tx-api.rst} | 253 +++++++++++-------
Documentation/crypto/index.rst | 2 +
2 files changed, 151 insertions(+), 104 deletions(-)
rename Documentation/crypto/{async-tx-api.txt => async-tx-api.rst} (55%)
diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.rst
similarity index 55%
rename from Documentation/crypto/async-tx-api.txt
rename to Documentation/crypto/async-tx-api.rst
index 7bf1be20d93a..bfc773991bdc 100644
--- a/Documentation/crypto/async-tx-api.txt
+++ b/Documentation/crypto/async-tx-api.rst
@@ -1,27 +1,32 @@
- Asynchronous Transfers/Transforms API
+.. SPDX-License-Identifier: GPL-2.0
-1 INTRODUCTION
+=====================================
+Asynchronous Transfers/Transforms API
+=====================================
-2 GENEALOGY
+.. Contents
-3 USAGE
-3.1 General format of the API
-3.2 Supported operations
-3.3 Descriptor management
-3.4 When does the operation execute?
-3.5 When does the operation complete?
-3.6 Constraints
-3.7 Example
+ 1. INTRODUCTION
-4 DMAENGINE DRIVER DEVELOPER NOTES
-4.1 Conformance points
-4.2 "My application needs exclusive control of hardware channels"
+ 2 GENEALOGY
-5 SOURCE
+ 3 USAGE
+ 3.1 General format of the API
+ 3.2 Supported operations
+ 3.3 Descriptor management
+ 3.4 When does the operation execute?
+ 3.5 When does the operation complete?
+ 3.6 Constraints
+ 3.7 Example
----
+ 4 DMAENGINE DRIVER DEVELOPER NOTES
+ 4.1 Conformance points
+ 4.2 "My application needs exclusive control of hardware channels"
-1 INTRODUCTION
+ 5 SOURCE
+
+1. Introduction
+===============
The async_tx API provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
@@ -31,7 +36,8 @@ that is written to the API can optimize for asynchronous operation and
the API will fit the chain of operations to the available offload
resources.
-2 GENEALOGY
+2.Genealogy
+===========
The API was initially designed to offload the memory copy and
xor-parity-calculations of the md-raid5 driver using the offload engines
@@ -39,40 +45,52 @@ present in the Intel(R) Xscale series of I/O processors. It also built
on the 'dmaengine' layer developed for offloading memory copies in the
network stack using Intel(R) I/OAT engines. The following design
features surfaced as a result:
-1/ implicit synchronous path: users of the API do not need to know if
+
+1. implicit synchronous path: users of the API do not need to know if
the platform they are running on has offload capabilities. The
operation will be offloaded when an engine is available and carried out
in software otherwise.
-2/ cross channel dependency chains: the API allows a chain of dependent
+2. cross channel dependency chains: the API allows a chain of dependent
operations to be submitted, like xor->copy->xor in the raid5 case. The
API automatically handles cases where the transition from one operation
to another implies a hardware channel switch.
-3/ dmaengine extensions to support multiple clients and operation types
+3. dmaengine extensions to support multiple clients and operation types
beyond 'memcpy'
-3 USAGE
+3. Usage
+========
-3.1 General format of the API:
-struct dma_async_tx_descriptor *
-async_<operation>(<op specific parameters>, struct async_submit ctl *submit)
+3.1 General format of the API
+-----------------------------
-3.2 Supported operations:
-memcpy - memory copy between a source and a destination buffer
-memset - fill a destination buffer with a byte value
-xor - xor a series of source buffers and write the result to a
+::
+
+ struct dma_async_tx_descriptor *
+ async_<operation>(<op specific parameters>, struct async_submit ctl *submit)
+
+3.2 Supported operations
+------------------------
+
+======== ====================================================================
+memcpy memory copy between a source and a destination buffer
+memset fill a destination buffer with a byte value
+xor xor a series of source buffers and write the result to a
destination buffer
-xor_val - xor a series of source buffers and set a flag if the
+xor_val xor a series of source buffers and set a flag if the
result is zero. The implementation attempts to prevent
writes to memory
-pq - generate the p+q (raid6 syndrome) from a series of source buffers
-pq_val - validate that a p and or q buffer are in sync with a given series of
+pq generate the p+q (raid6 syndrome) from a series of source buffers
+pq_val validate that a p and or q buffer are in sync with a given series of
sources
-datap - (raid6_datap_recov) recover a raid6 data block and the p block
+datap (raid6_datap_recov) recover a raid6 data block and the p block
from the given sources
-2data - (raid6_2data_recov) recover 2 raid6 data blocks from the given
+2data (raid6_2data_recov) recover 2 raid6 data blocks from the given
sources
+======== ====================================================================
+
+3.3 Descriptor management
+-------------------------
-3.3 Descriptor management:
The return value is non-NULL and points to a 'descriptor' when the operation
has been queued to execute asynchronously. Descriptors are recycled
resources, under control of the offload engine driver, to be reused as
@@ -82,12 +100,15 @@ before the dependency is submitted. This requires that all descriptors be
acknowledged by the application before the offload engine driver is allowed to
recycle (or free) the descriptor. A descriptor can be acked by one of the
following methods:
-1/ setting the ASYNC_TX_ACK flag if no child operations are to be submitted
-2/ submitting an unacknowledged descriptor as a dependency to another
+
+1. setting the ASYNC_TX_ACK flag if no child operations are to be submitted
+2. submitting an unacknowledged descriptor as a dependency to another
async_tx call will implicitly set the acknowledged state.
-3/ calling async_tx_ack() on the descriptor.
+3. calling async_tx_ack() on the descriptor.
3.4 When does the operation execute?
+------------------------------------
+
Operations do not immediately issue after return from the
async_<operation> call. Offload engine drivers batch operations to
improve performance by reducing the number of mmio cycles needed to
@@ -98,12 +119,15 @@ channels since the application has no knowledge of channel to operation
mapping.
3.5 When does the operation complete?
+-------------------------------------
+
There are two methods for an application to learn about the completion
of an operation.
-1/ Call dma_wait_for_async_tx(). This call causes the CPU to spin while
+
+1. Call dma_wait_for_async_tx(). This call causes the CPU to spin while
it polls for the completion of the operation. It handles dependency
chains and issuing pending operations.
-2/ Specify a completion callback. The callback routine runs in tasklet
+2. Specify a completion callback. The callback routine runs in tasklet
context if the offload engine driver supports interrupts, or it is
called in application context if the operation is carried out
synchronously in software. The callback can be set in the call to
@@ -111,83 +135,95 @@ of an operation.
unknown length it can use the async_trigger_callback() routine to set a
completion interrupt/callback at the end of the chain.
-3.6 Constraints:
-1/ Calls to async_<operation> are not permitted in IRQ context. Other
+3.6 Constraints
+---------------
+
+1. Calls to async_<operation> are not permitted in IRQ context. Other
contexts are permitted provided constraint #2 is not violated.
-2/ Completion callback routines cannot submit new operations. This
+2. Completion callback routines cannot submit new operations. This
results in recursion in the synchronous case and spin_locks being
acquired twice in the asynchronous case.
-3.7 Example:
+3.7 Example
+-----------
+
Perform a xor->copy->xor operation where each operation depends on the
-result from the previous operation:
-
-void callback(void *param)
-{
- struct completion *cmp = param;
-
- complete(cmp);
-}
-
-void run_xor_copy_xor(struct page **xor_srcs,
- int xor_src_cnt,
- struct page *xor_dest,
- size_t xor_len,
- struct page *copy_src,
- struct page *copy_dest,
- size_t copy_len)
-{
- struct dma_async_tx_descriptor *tx;
- addr_conv_t addr_conv[xor_src_cnt];
- struct async_submit_ctl submit;
- addr_conv_t addr_conv[NDISKS];
- struct completion cmp;
-
- init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL,
- addr_conv);
- tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit)
-
- submit->depend_tx = tx;
- tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, &submit);
-
- init_completion(&cmp);
- init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx,
- callback, &cmp, addr_conv);
- tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit);
-
- async_tx_issue_pending_all();
-
- wait_for_completion(&cmp);
-}
+result from the previous operation::
+
+ void callback(void *param)
+ {
+ struct completion *cmp = param;
+
+ complete(cmp);
+ }
+
+ void run_xor_copy_xor(struct page **xor_srcs,
+ int xor_src_cnt,
+ struct page *xor_dest,
+ size_t xor_len,
+ struct page *copy_src,
+ struct page *copy_dest,
+ size_t copy_len)
+ {
+ struct dma_async_tx_descriptor *tx;
+ addr_conv_t addr_conv[xor_src_cnt];
+ struct async_submit_ctl submit;
+ addr_conv_t addr_conv[NDISKS];
+ struct completion cmp;
+
+ init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL,
+ addr_conv);
+ tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit)
+
+ submit->depend_tx = tx;
+ tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, &submit);
+
+ init_completion(&cmp);
+ init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx,
+ callback, &cmp, addr_conv);
+ tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit);
+
+ async_tx_issue_pending_all();
+
+ wait_for_completion(&cmp);
+ }
See include/linux/async_tx.h for more information on the flags. See the
ops_run_* and ops_complete_* routines in drivers/md/raid5.c for more
implementation examples.
-4 DRIVER DEVELOPMENT NOTES
+4. Driver Development Notes
+===========================
+
+4.1 Conformance points
+----------------------
-4.1 Conformance points:
There are a few conformance points required in dmaengine drivers to
accommodate assumptions made by applications using the async_tx API:
-1/ Completion callbacks are expected to happen in tasklet context
-2/ dma_async_tx_descriptor fields are never manipulated in IRQ context
-3/ Use async_tx_run_dependencies() in the descriptor clean up path to
+
+1. Completion callbacks are expected to happen in tasklet context
+2. dma_async_tx_descriptor fields are never manipulated in IRQ context
+3. Use async_tx_run_dependencies() in the descriptor clean up path to
handle submission of dependent operations
4.2 "My application needs exclusive control of hardware channels"
+-----------------------------------------------------------------
+
Primarily this requirement arises from cases where a DMA engine driver
is being used to support device-to-memory operations. A channel that is
performing these operations cannot, for many platform specific reasons,
be shared. For these cases the dma_request_channel() interface is
provided.
-The interface is:
-struct dma_chan *dma_request_channel(dma_cap_mask_t mask,
- dma_filter_fn filter_fn,
- void *filter_param);
+The interface is::
-Where dma_filter_fn is defined as:
-typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
+ struct dma_chan *dma_request_channel(dma_cap_mask_t mask,
+ dma_filter_fn filter_fn,
+ void *filter_param);
+
+Where dma_filter_fn is defined as::
+
+ typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
When the optional 'filter_fn' parameter is set to NULL
dma_request_channel simply returns the first channel that satisfies the
@@ -207,19 +243,28 @@ private. Alternatively, it is set when dma_request_channel() finds an
unused "public" channel.
A couple caveats to note when implementing a driver and consumer:
-1/ Once a channel has been privately allocated it will no longer be
+
+1. Once a channel has been privately allocated it will no longer be
considered by the general-purpose allocator even after a call to
dma_release_channel().
-2/ Since capabilities are specified at the device level a dma_device
+2. Since capabilities are specified at the device level a dma_device
with multiple channels will either have all channels public, or all
channels private.
-5 SOURCE
+5. Source
+---------
-include/linux/dmaengine.h: core header file for DMA drivers and api users
-drivers/dma/dmaengine.c: offload engine channel management routines
-drivers/dma/: location for offload engine drivers
-include/linux/async_tx.h: core header file for the async_tx api
-crypto/async_tx/async_tx.c: async_tx interface to dmaengine and common code
-crypto/async_tx/async_memcpy.c: copy offload
-crypto/async_tx/async_xor.c: xor and xor zero sum offload
+include/linux/dmaengine.h:
+ core header file for DMA drivers and api users
+drivers/dma/dmaengine.c:
+ offload engine channel management routines
+drivers/dma/:
+ location for offload engine drivers
+include/linux/async_tx.h:
+ core header file for the async_tx api
+crypto/async_tx/async_tx.c:
+ async_tx interface to dmaengine and common code
+crypto/async_tx/async_memcpy.c:
+ copy offload
+crypto/async_tx/async_xor.c:
+ xor and xor zero sum offload
diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst
index b2eeab3c8631..22a6870bf356 100644
--- a/Documentation/crypto/index.rst
+++ b/Documentation/crypto/index.rst
@@ -19,6 +19,8 @@ for cryptographic use cases, as well as programming examples.
intro
api-intro
architecture
+
+ async-tx-api
asymmetric-keys
devel-algos
userspace-if
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 05/24] docs: crypto: descore-readme.txt: convert to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (6 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Herbert Xu,
David S. Miller, linux-crypto
Convert this readme file to ReST file format, preserving its
contents as-is as much as possible. The only changes are:
- Added chapter and title markups;
- Added blank lines where needed;
- Added list markups where needed;
- Use a table markup;
- replace markups like `foo' to ``foo``;
- add one extra literal markup to avoid warnings.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
...{descore-readme.txt => descore-readme.rst} | 152 ++++++++++++------
Documentation/crypto/index.rst | 1 +
2 files changed, 108 insertions(+), 45 deletions(-)
rename Documentation/crypto/{descore-readme.txt => descore-readme.rst} (81%)
diff --git a/Documentation/crypto/descore-readme.txt b/Documentation/crypto/descore-readme.rst
similarity index 81%
rename from Documentation/crypto/descore-readme.txt
rename to Documentation/crypto/descore-readme.rst
index 16e9e6350755..45bd9c8babf4 100644
--- a/Documentation/crypto/descore-readme.txt
+++ b/Documentation/crypto/descore-readme.rst
@@ -1,8 +1,20 @@
-Below is the original README file from the descore.shar package.
+.. SPDX-License-Identifier: GPL-2.0
+.. include:: <isonum.txt>
+
+===========================================
+Fast & Portable DES encryption & decryption
+===========================================
+
+.. note::
+
+ Below is the original README file from the descore.shar package,
+ converted to ReST format.
+
------------------------------------------------------------------------------
des - fast & portable DES encryption & decryption.
-Copyright (C) 1992 Dana L. How
+
+Copyright |copy| 1992 Dana L. How
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU Library General Public License as published by
@@ -20,13 +32,12 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
Author's address: how@isl.stanford.edu
-$Id: README,v 1.15 1992/05/20 00:25:32 how E $
-
-
-==>> To compile after untarring/unsharring, just `make' <<==
+.. README,v 1.15 1992/05/20 00:25:32 how E
+==>> To compile after untarring/unsharring, just ``make`` <<==
This package was designed with the following goals:
+
1. Highest possible encryption/decryption PERFORMANCE.
2. PORTABILITY to any byte-addressable host with a 32bit unsigned C type
3. Plug-compatible replacement for KERBEROS's low-level routines.
@@ -36,7 +47,7 @@ register-starved machines. My discussions with Richard Outerbridge,
71755.204@compuserve.com, sparked a number of these enhancements.
To more rapidly understand the code in this package, inspect desSmallFips.i
-(created by typing `make') BEFORE you tackle desCode.h. The latter is set
+(created by typing ``make``) BEFORE you tackle desCode.h. The latter is set
up in a parameterized fashion so it can easily be modified by speed-daemon
hackers in pursuit of that last microsecond. You will find it more
illuminating to inspect one specific implementation,
@@ -47,11 +58,13 @@ performance comparison to other available des code which i could
compile on a SPARCStation 1 (cc -O4, gcc -O2):
this code (byte-order independent):
- 30us per encryption (options: 64k tables, no IP/FP)
- 33us per encryption (options: 64k tables, FIPS standard bit ordering)
- 45us per encryption (options: 2k tables, no IP/FP)
- 48us per encryption (options: 2k tables, FIPS standard bit ordering)
- 275us to set a new key (uses 1k of key tables)
+
+ - 30us per encryption (options: 64k tables, no IP/FP)
+ - 33us per encryption (options: 64k tables, FIPS standard bit ordering)
+ - 45us per encryption (options: 2k tables, no IP/FP)
+ - 48us per encryption (options: 2k tables, FIPS standard bit ordering)
+ - 275us to set a new key (uses 1k of key tables)
+
this has the quickest encryption/decryption routines i've seen.
since i was interested in fast des filters rather than crypt(3)
and password cracking, i haven't really bothered yet to speed up
@@ -63,15 +76,20 @@ this code (byte-order independent):
are highly variable because of cache effects).
kerberos des replacement from australia (version 1.95):
- 53us per encryption (uses 2k of tables)
- 96us to set a new key (uses 2.25k of key tables)
+
+ - 53us per encryption (uses 2k of tables)
+ - 96us to set a new key (uses 2.25k of key tables)
+
so despite the author's inclusion of some of the performance
improvements i had suggested to him, this package's
encryption/decryption is still slower on the sparc and 68000.
more specifically, 19-40% slower on the 68020 and 11-35% slower
on the sparc, depending on the compiler;
in full gory detail (ALT_ECB is a libdes variant):
+
+ =============== ============== =============== =================
compiler machine desCore libdes ALT_ECB slower by
+ =============== ============== =============== =================
gcc 2.1 -O2 Sun 3/110 304 uS 369.5uS 461.8uS 22%
cc -O1 Sun 3/110 336 uS 436.6uS 399.3uS 19%
cc -O2 Sun 3/110 360 uS 532.4uS 505.1uS 40%
@@ -79,10 +97,15 @@ kerberos des replacement from australia (version 1.95):
gcc 2.1 -O2 Sun 4/50 48 uS 53.4uS 57.5uS 11%
cc -O2 Sun 4/50 48 uS 64.6uS 64.7uS 35%
cc -O4 Sun 4/50 48 uS 64.7uS 64.9uS 35%
+ =============== ============== =============== =================
+
(my time measurements are not as accurate as his).
+
the comments in my first release of desCore on version 1.92:
- 68us per encryption (uses 2k of tables)
- 96us to set a new key (uses 2.25k of key tables)
+
+ - 68us per encryption (uses 2k of tables)
+ - 96us to set a new key (uses 2.25k of key tables)
+
this is a very nice package which implements the most important
of the optimizations which i did in my encryption routines.
it's a bit weak on common low-level optimizations which is why
@@ -91,48 +114,60 @@ kerberos des replacement from australia (version 1.95):
speed up the key-setting routines with impressive results.
(at some point i may do the same in my package). he also implements
the rest of the mit des library.
+
(code from eay@psych.psy.uq.oz.au via comp.sources.misc)
fast crypt(3) package from denmark:
+
the des routine here is buried inside a loop to do the
crypt function and i didn't feel like ripping it out and measuring
performance. his code takes 26 sparc instructions to compute one
des iteration; above, Quick (64k) takes 21 and Small (2k) takes 37.
he claims to use 280k of tables but the iteration calculation seems
to use only 128k. his tables and code are machine independent.
+
(code from glad@daimi.aau.dk via alt.sources or comp.sources.misc)
swedish reimplementation of Kerberos des library
- 108us per encryption (uses 34k worth of tables)
- 134us to set a new key (uses 32k of key tables to get this speed!)
+
+ - 108us per encryption (uses 34k worth of tables)
+ - 134us to set a new key (uses 32k of key tables to get this speed!)
+
the tables used seem to be machine-independent;
he seems to have included a lot of special case code
- so that, e.g., `long' loads can be used instead of 4 `char' loads
+ so that, e.g., ``long`` loads can be used instead of 4 ``char`` loads
when the machine's architecture allows it.
+
(code obtained from chalmers.se:pub/des)
crack 3.3c package from england:
+
as in crypt above, the des routine is buried in a loop. it's
also very modified for crypt. his iteration code uses 16k
of tables and appears to be slow.
+
(code obtained from aem@aber.ac.uk via alt.sources or comp.sources.misc)
-``highly optimized'' and tweaked Kerberos/Athena code (byte-order dependent):
- 165us per encryption (uses 6k worth of tables)
- 478us to set a new key (uses <1k of key tables)
+``highly optimized`` and tweaked Kerberos/Athena code (byte-order dependent):
+
+ - 165us per encryption (uses 6k worth of tables)
+ - 478us to set a new key (uses <1k of key tables)
+
so despite the comments in this code, it was possible to get
faster code AND smaller tables, as well as making the tables
machine-independent.
(code obtained from prep.ai.mit.edu)
UC Berkeley code (depends on machine-endedness):
- 226us per encryption
-10848us to set a new key
+ - 226us per encryption
+ - 10848us to set a new key
+
table sizes are unclear, but they don't look very small
(code obtained from wuarchive.wustl.edu)
motivation and history
+======================
a while ago i wanted some des routines and the routines documented on sun's
man pages either didn't exist or dumped core. i had heard of kerberos,
@@ -142,10 +177,10 @@ it was too convoluted, the code had been written without taking
advantage of the regular structure of operations such as IP, E, and FP
(i.e. the author didn't sit down and think before coding),
it was excessively slow, the author had attempted to clarify the code
-by adding MORE statements to make the data movement more `consistent'
+by adding MORE statements to make the data movement more ``consistent``
instead of simplifying his implementation and cutting down on all data
movement (in particular, his use of L1, R1, L2, R2), and it was full of
-idiotic `tweaks' for particular machines which failed to deliver significant
+idiotic ``tweaks`` for particular machines which failed to deliver significant
speedups but which did obfuscate everything. so i took the test data
from his verification program and rewrote everything else.
@@ -167,12 +202,13 @@ than versions hand-written in assembly for the sparc!
porting notes
+=============
one thing i did not want to do was write an enormous mess
which depended on endedness and other machine quirks,
and which necessarily produced different code and different lookup tables
for different machines. see the kerberos code for an example
-of what i didn't want to do; all their endedness-specific `optimizations'
+of what i didn't want to do; all their endedness-specific ``optimizations``
obfuscate the code and in the end were slower than a simpler machine
independent approach. however, there are always some portability
considerations of some kind, and i have included some options
@@ -184,8 +220,8 @@ perhaps some will still regard the result as a mess!
i assume word pointers can be freely cast to and from char pointers.
note that 99% of C programs make these assumptions.
i always use unsigned char's if the high bit could be set.
-2) the typedef `word' means a 32 bit unsigned integral type.
- if `unsigned long' is not 32 bits, change the typedef in desCore.h.
+2) the typedef ``word`` means a 32 bit unsigned integral type.
+ if ``unsigned long`` is not 32 bits, change the typedef in desCore.h.
i assume sizeof(word) == 4 EVERYWHERE.
the (worst-case) cost of my NOT doing endedness-specific optimizations
@@ -195,40 +231,46 @@ the input and output work areas do not need to be word-aligned.
OPTIONAL performance optimizations
+==================================
-1) you should define one of `i386,' `vax,' `mc68000,' or `sparc,'
+1) you should define one of ``i386,`` ``vax,`` ``mc68000,`` or ``sparc,``
whichever one is closest to the capabilities of your machine.
see the start of desCode.h to see exactly what this selection implies.
note that if you select the wrong one, the des code will still work;
these are just performance tweaks.
-2) for those with functional `asm' keywords: you should change the
+2) for those with functional ``asm`` keywords: you should change the
ROR and ROL macros to use machine rotate instructions if you have them.
this will save 2 instructions and a temporary per use,
or about 32 to 40 instructions per en/decryption.
+
note that gcc is smart enough to translate the ROL/R macros into
machine rotates!
these optimizations are all rather persnickety, yet with them you should
be able to get performance equal to assembly-coding, except that:
+
1) with the lack of a bit rotate operator in C, rotates have to be synthesized
- from shifts. so access to `asm' will speed things up if your machine
+ from shifts. so access to ``asm`` will speed things up if your machine
has rotates, as explained above in (3) (not necessary if you use gcc).
2) if your machine has less than 12 32-bit registers i doubt your compiler will
generate good code.
- `i386' tries to configure the code for a 386 by only declaring 3 registers
+
+ ``i386`` tries to configure the code for a 386 by only declaring 3 registers
(it appears that gcc can use ebx, esi and edi to hold register variables).
however, if you like assembly coding, the 386 does have 7 32-bit registers,
- and if you use ALL of them, use `scaled by 8' address modes with displacement
+ and if you use ALL of them, use ``scaled by 8`` address modes with displacement
and other tricks, you can get reasonable routines for DesQuickCore... with
about 250 instructions apiece. For DesSmall... it will help to rearrange
des_keymap, i.e., now the sbox # is the high part of the index and
the 6 bits of data is the low part; it helps to exchange these.
+
since i have no way to conveniently test it i have not provided my
shoehorned 386 version. note that with this release of desCore, gcc is able
to put everything in registers(!), and generate about 370 instructions apiece
for the DesQuickCore... routines!
coding notes
+============
the en/decryption routines each use 6 necessary register variables,
with 4 being actively used at once during the inner iterations.
@@ -236,15 +278,18 @@ if you don't have 4 register variables get a new machine.
up to 8 more registers are used to hold constants in some configurations.
i assume that the use of a constant is more expensive than using a register:
+
a) additionally, i have tried to put the larger constants in registers.
registering priority was by the following:
- anything more than 12 bits (bad for RISC and CISC)
- greater than 127 in value (can't use movq or byte immediate on CISC)
- 9-127 (may not be able to use CISC shift immediate or add/sub quick),
- 1-8 were never registered, being the cheapest constants.
+
+ - anything more than 12 bits (bad for RISC and CISC)
+ - greater than 127 in value (can't use movq or byte immediate on CISC)
+ - 9-127 (may not be able to use CISC shift immediate or add/sub quick),
+ - 1-8 were never registered, being the cheapest constants.
+
b) the compiler may be too stupid to realize table and table+256 should
be assigned to different constant registers and instead repetitively
- do the arithmetic, so i assign these to explicit `m' register variables
+ do the arithmetic, so i assign these to explicit ``m`` register variables
when possible and helpful.
i assume that indexing is cheaper or equivalent to auto increment/decrement,
@@ -253,25 +298,31 @@ this assumption is reversed for 68k and vax.
i assume that addresses can be cheaply formed from two registers,
or from a register and a small constant.
-for the 68000, the `two registers and small offset' form is used sparingly.
+for the 68000, the ``two registers and small offset`` form is used sparingly.
all index scaling is done explicitly - no hidden shifts by log2(sizeof).
the code is written so that even a dumb compiler
should never need more than one hidden temporary,
increasing the chance that everything will fit in the registers.
KEEP THIS MORE SUBTLE POINT IN MIND IF YOU REWRITE ANYTHING.
+
(actually, there are some code fragments now which do require two temps,
but fixing it would either break the structure of the macros or
require declaring another temporary).
special efficient data format
+==============================
+
+bits are manipulated in this arrangement most of the time (S7 S5 S3 S1)::
-bits are manipulated in this arrangement most of the time (S7 S5 S3 S1):
003130292827xxxx242322212019xxxx161514131211xxxx080706050403xxxx
+
(the x bits are still there, i'm just emphasizing where the S boxes are).
-bits are rotated left 4 when computing S6 S4 S2 S0:
+bits are rotated left 4 when computing S6 S4 S2 S0::
+
282726252423xxxx201918171615xxxx121110090807xxxx040302010031xxxx
+
the rightmost two bits are usually cleared so the lower byte can be used
as an index into an sbox mapping table. the next two x'd bits are set
to various values to access different parts of the tables.
@@ -288,7 +339,7 @@ datatypes:
must be long-aligned.
DesQuickInit()
- call this before using any other routine with `Quick' in its name.
+ call this before using any other routine with ``Quick`` in its name.
it generates the special 64k table these routines need.
DesQuickDone()
frees this table
@@ -298,6 +349,7 @@ DesMethod(m, k)
which must have odd parity (or -1 is returned) and which must
not be a (semi-)weak key (or -2 is returned).
normally DesMethod() returns 0.
+
m is filled in from k so that when one of the routines below
is called with m, the routine will act like standard des
en/decryption with the key k. if you use DesMethod,
@@ -308,19 +360,26 @@ DesMethod(m, k)
will be set to magic constants which speed up the encryption/decryption
on some machines. and yes, each byte controls
a specific sbox during a specific iteration.
+
you really shouldn't use the 768bit format directly; i should
provide a routine that converts 128 6-bit bytes (specified in
S-box mapping order or something) into the right format for you.
this would entail some byte concatenation and rotation.
Des{Small|Quick}{Fips|Core}{Encrypt|Decrypt}(d, m, s)
- performs des on the 8 bytes at s into the 8 bytes at d. (d,s: char *).
+ performs des on the 8 bytes at s into the 8 bytes at
+ ``d. (d,s: char *)``.
+
uses m as a 768bit key as explained above.
+
the Encrypt|Decrypt choice is obvious.
+
Fips|Core determines whether a completely standard FIPS initial
and final permutation is done; if not, then the data is loaded
and stored in a nonstandard bit order (FIPS w/o IP/FP).
+
Fips slows down Quick by 10%, Small by 9%.
+
Small|Quick determines whether you use the normal routine
or the crazy quick one which gobbles up 64k more of memory.
Small is 50% slower then Quick, but Quick needs 32 times as much
@@ -329,15 +388,17 @@ Des{Small|Quick}{Fips|Core}{Encrypt|Decrypt}(d, m, s)
Getting it to compile on your machine
+=====================================
there are no machine-dependencies in the code (see porting),
-except perhaps the `now()' macro in desTest.c.
+except perhaps the ``now()`` macro in desTest.c.
ALL generated tables are machine independent.
you should edit the Makefile with the appropriate optimization flags
for your compiler (MAX optimization).
Speeding up kerberos (and/or its des library)
+=============================================
note that i have included a kerberos-compatible interface in desUtil.c
through the functions des_key_sched() and des_ecb_encrypt().
@@ -347,6 +408,7 @@ you should not need to #include desCore.h; just include the header
file provided with the kerberos library.
Other uses
+==========
the macros in desCode.h would be very useful for putting inline des
functions in more complicated encryption routines.
diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst
index 22a6870bf356..21338fa92642 100644
--- a/Documentation/crypto/index.rst
+++ b/Documentation/crypto/index.rst
@@ -27,3 +27,4 @@ for cryptographic use cases, as well as programming examples.
crypto_engine
api
api-samples
+ descore-readme
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 06/24] docs: misc-devices/spear-pcie-gadget.txt: convert to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (7 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List; +Cc: Mauro Carvalho Chehab, Jonathan Corbet
- Use title/chapter markups;
- Use table markups;
- Mark literal blocks as such;
- Adjust indentation.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/misc-devices/index.rst | 1 +
.../misc-devices/spear-pcie-gadget.rst | 170 ++++++++++++++++++
.../misc-devices/spear-pcie-gadget.txt | 130 --------------
3 files changed, 171 insertions(+), 130 deletions(-)
create mode 100644 Documentation/misc-devices/spear-pcie-gadget.rst
delete mode 100644 Documentation/misc-devices/spear-pcie-gadget.txt
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index f11c5daeada5..2d454b413aef 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -20,4 +20,5 @@ fit into other categories.
isl29003
lis3lv02d
max6875
+ spear-pcie-gadget
xilinx_sdfec
diff --git a/Documentation/misc-devices/spear-pcie-gadget.rst b/Documentation/misc-devices/spear-pcie-gadget.rst
new file mode 100644
index 000000000000..09b9d6c7ac15
--- /dev/null
+++ b/Documentation/misc-devices/spear-pcie-gadget.rst
@@ -0,0 +1,170 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+========================
+Spear PCIe Gadget Driver
+========================
+
+Author
+======
+Pratyush Anand (pratyush.anand@gmail.com)
+
+Location
+========
+driver/misc/spear13xx_pcie_gadget.c
+
+Supported Chip:
+===============
+SPEAr1300
+SPEAr1310
+
+Menuconfig option:
+==================
+Device Drivers
+ Misc devices
+ PCIe gadget support for SPEAr13XX platform
+
+purpose
+=======
+This driver has several nodes which can be read/written by configfs interface.
+Its main purpose is to configure selected dual mode PCIe controller as device
+and then program its various registers to configure it as a particular device
+type. This driver can be used to show spear's PCIe device capability.
+
+Description of different nodes:
+===============================
+
+read behavior of nodes:
+-----------------------
+
+=============== ==============================================================
+link gives ltssm status.
+int_type type of supported interrupt
+no_of_msi zero if MSI is not enabled by host. A positive value is the
+ number of MSI vector granted.
+vendor_id returns programmed vendor id (hex)
+device_id returns programmed device id(hex)
+bar0_size: returns size of bar0 in hex.
+bar0_address returns address of bar0 mapped area in hex.
+bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
+bar0_data returns data at bar0_rw_offset.
+=============== ==============================================================
+
+write behavior of nodes:
+------------------------
+
+=============== ================================================================
+link write UP to enable ltsmm DOWN to disable
+int_type write interrupt type to be configured and (int_type could be
+ INTA, MSI or NO_INT). Select MSI only when you have programmed
+ no_of_msi node.
+no_of_msi number of MSI vector needed.
+inta write 1 to assert INTA and 0 to de-assert.
+send_msi write MSI vector to be sent.
+vendor_id write vendor id(hex) to be programmed.
+device_id write device id(hex) to be programmed.
+bar0_size write size of bar0 in hex. default bar0 size is 1000 (hex)
+ bytes.
+bar0_address write address of bar0 mapped area in hex. (default mapping of
+ bar0 is SYSRAM1(E0800000). Always program bar size before bar
+ address. Kernel might modify bar size and address for alignment,
+ so read back bar size and address after writing to cross check.
+bar0_rw_offset write offset of bar0 for which bar0_data will write value.
+bar0_data write data to be written at bar0_rw_offset.
+=============== ================================================================
+
+Node programming example
+========================
+
+Program all PCIe registers in such a way that when this device is connected
+to the PCIe host, then host sees this device as 1MB RAM.
+
+::
+
+ #mount -t configfs none /Config
+
+For nth PCIe Device Controller::
+
+ # cd /config/pcie_gadget.n/
+
+Now you have all the nodes in this directory.
+program vendor id as 0x104a::
+
+ # echo 104A >> vendor_id
+
+program device id as 0xCD80::
+
+ # echo CD80 >> device_id
+
+program BAR0 size as 1MB::
+
+ # echo 100000 >> bar0_size
+
+check for programmed bar0 size::
+
+ # cat bar0_size
+
+Program BAR0 Address as DDR (0x2100000). This is the physical address of
+memory, which is to be made visible to PCIe host. Similarly any other peripheral
+can also be made visible to PCIe host. E.g., if you program base address of UART
+as BAR0 address then when this device will be connected to a host, it will be
+visible as UART.
+
+::
+
+ # echo 2100000 >> bar0_address
+
+program interrupt type : INTA::
+
+ # echo INTA >> int_type
+
+go for link up now::
+
+ # echo UP >> link
+
+It will have to be insured that, once link up is done on gadget, then only host
+is initialized and start to search PCIe devices on its port.
+
+::
+
+ /*wait till link is up*/
+ # cat link
+
+Wait till it returns UP.
+
+To assert INTA::
+
+ # echo 1 >> inta
+
+To de-assert INTA::
+
+ # echo 0 >> inta
+
+if MSI is to be used as interrupt, program no of msi vector needed (say4)::
+
+ # echo 4 >> no_of_msi
+
+select MSI as interrupt type::
+
+ # echo MSI >> int_type
+
+go for link up now::
+
+ # echo UP >> link
+
+wait till link is up::
+
+ # cat link
+
+An application can repetitively read this node till link is found UP. It can
+sleep between two read.
+
+wait till msi is enabled::
+
+ # cat no_of_msi
+
+Should return 4 (number of requested MSI vector)
+
+to send msi vector 2::
+
+ # echo 2 >> send_msi
+ # cd -
diff --git a/Documentation/misc-devices/spear-pcie-gadget.txt b/Documentation/misc-devices/spear-pcie-gadget.txt
deleted file mode 100644
index 89b88dee4143..000000000000
--- a/Documentation/misc-devices/spear-pcie-gadget.txt
+++ /dev/null
@@ -1,130 +0,0 @@
-Spear PCIe Gadget Driver:
-
-Author
-=============
-Pratyush Anand (pratyush.anand@gmail.com)
-
-Location
-============
-driver/misc/spear13xx_pcie_gadget.c
-
-Supported Chip:
-===================
-SPEAr1300
-SPEAr1310
-
-Menuconfig option:
-==========================
-Device Drivers
- Misc devices
- PCIe gadget support for SPEAr13XX platform
-purpose
-===========
-This driver has several nodes which can be read/written by configfs interface.
-Its main purpose is to configure selected dual mode PCIe controller as device
-and then program its various registers to configure it as a particular device
-type. This driver can be used to show spear's PCIe device capability.
-
-Description of different nodes:
-=================================
-
-read behavior of nodes:
-------------------------------
-link :gives ltssm status.
-int_type :type of supported interrupt
-no_of_msi :zero if MSI is not enabled by host. A positive value is the
- number of MSI vector granted.
-vendor_id :returns programmed vendor id (hex)
-device_id :returns programmed device id(hex)
-bar0_size: :returns size of bar0 in hex.
-bar0_address :returns address of bar0 mapped area in hex.
-bar0_rw_offset :returns offset of bar0 for which bar0_data will return value.
-bar0_data :returns data at bar0_rw_offset.
-
-write behavior of nodes:
-------------------------------
-link :write UP to enable ltsmm DOWN to disable
-int_type :write interrupt type to be configured and (int_type could be
- INTA, MSI or NO_INT). Select MSI only when you have programmed
- no_of_msi node.
-no_of_msi :number of MSI vector needed.
-inta :write 1 to assert INTA and 0 to de-assert.
-send_msi :write MSI vector to be sent.
-vendor_id :write vendor id(hex) to be programmed.
-device_id :write device id(hex) to be programmed.
-bar0_size :write size of bar0 in hex. default bar0 size is 1000 (hex)
- bytes.
-bar0_address :write address of bar0 mapped area in hex. (default mapping of
- bar0 is SYSRAM1(E0800000). Always program bar size before bar
- address. Kernel might modify bar size and address for alignment, so
- read back bar size and address after writing to cross check.
-bar0_rw_offset :write offset of bar0 for which bar0_data will write value.
-bar0_data :write data to be written at bar0_rw_offset.
-
-Node programming example
-===========================
-Program all PCIe registers in such a way that when this device is connected
-to the PCIe host, then host sees this device as 1MB RAM.
-#mount -t configfs none /Config
-For nth PCIe Device Controller
-# cd /config/pcie_gadget.n/
-Now you have all the nodes in this directory.
-program vendor id as 0x104a
-# echo 104A >> vendor_id
-
-program device id as 0xCD80
-# echo CD80 >> device_id
-
-program BAR0 size as 1MB
-# echo 100000 >> bar0_size
-
-check for programmed bar0 size
-# cat bar0_size
-
-Program BAR0 Address as DDR (0x2100000). This is the physical address of
-memory, which is to be made visible to PCIe host. Similarly any other peripheral
-can also be made visible to PCIe host. E.g., if you program base address of UART
-as BAR0 address then when this device will be connected to a host, it will be
-visible as UART.
-# echo 2100000 >> bar0_address
-
-program interrupt type : INTA
-# echo INTA >> int_type
-
-go for link up now.
-# echo UP >> link
-
-It will have to be insured that, once link up is done on gadget, then only host
-is initialized and start to search PCIe devices on its port.
-
-/*wait till link is up*/
-# cat link
-wait till it returns UP.
-
-To assert INTA
-# echo 1 >> inta
-
-To de-assert INTA
-# echo 0 >> inta
-
-if MSI is to be used as interrupt, program no of msi vector needed (say4)
-# echo 4 >> no_of_msi
-
-select MSI as interrupt type
-# echo MSI >> int_type
-
-go for link up now
-# echo UP >> link
-
-wait till link is up
-# cat link
-An application can repetitively read this node till link is found UP. It can
-sleep between two read.
-
-wait till msi is enabled
-# cat no_of_msi
-Should return 4 (number of requested MSI vector)
-
-to send msi vector 2
-# echo 2 >> send_msi
-#cd -
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 07/24] docs: misc-devices/pci-endpoint-test.txt: convert to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (8 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List; +Cc: Mauro Carvalho Chehab, Jonathan Corbet
- use title markups;
- mark literal blocks.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../{ad525x_dpot.txt => ad525x_dpot.rst} | 24 +++++++++----------
Documentation/misc-devices/index.rst | 1 +
2 files changed, 13 insertions(+), 12 deletions(-)
rename Documentation/misc-devices/{ad525x_dpot.txt => ad525x_dpot.rst} (85%)
diff --git a/Documentation/misc-devices/ad525x_dpot.txt b/Documentation/misc-devices/ad525x_dpot.rst
similarity index 85%
rename from Documentation/misc-devices/ad525x_dpot.txt
rename to Documentation/misc-devices/ad525x_dpot.rst
index 0c9413b1cbf3..6483ec254520 100644
--- a/Documentation/misc-devices/ad525x_dpot.txt
+++ b/Documentation/misc-devices/ad525x_dpot.rst
@@ -1,6 +1,8 @@
----------------------------------
- AD525x Digital Potentiometers
----------------------------------
+.. SPDX-License-Identifier: GPL-2.0
+
+=============================
+AD525x Digital Potentiometers
+=============================
The ad525x_dpot driver exports a simple sysfs interface. This allows you to
work with the immediate resistance settings as well as update the saved startup
@@ -8,9 +10,8 @@ settings. Access to the factory programmed tolerance is also provided, but
interpretation of this settings is required by the end application according to
the specific part in use.
----------
- Files
----------
+Files
+=====
Each dpot device will have a set of eeprom, rdac, and tolerance files. How
many depends on the actual part you have, as will the range of allowed values.
@@ -24,23 +25,22 @@ and may vary greatly on a part-by-part basis. For exact interpretation of
this field, please consult the datasheet for your part. This is presented
as a hex file for easier parsing.
------------
- Example
------------
+Example
+=======
Locate the device in your sysfs tree. This is probably easiest by going into
-the common i2c directory and locating the device by the i2c slave address.
+the common i2c directory and locating the device by the i2c slave address::
# ls /sys/bus/i2c/devices/
0-0022 0-0027 0-002f
So assuming the device in question is on the first i2c bus and has the slave
-address of 0x2f, we descend (unrelated sysfs entries have been trimmed).
+address of 0x2f, we descend (unrelated sysfs entries have been trimmed)::
# ls /sys/bus/i2c/devices/0-002f/
eeprom0 rdac0 tolerance0
-You can use simple reads/writes to access these files:
+You can use simple reads/writes to access these files::
# cd /sys/bus/i2c/devices/0-002f/
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 2d454b413aef..005547c1ad5d 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -14,6 +14,7 @@ fit into other categories.
.. toctree::
:maxdepth: 2
+ ad525x_dpot
eeprom
ibmvmc
ics932s401
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 08/24] docs: misc-devices/pci-endpoint-test.txt: convert to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (9 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List; +Cc: Mauro Carvalho Chehab, Jonathan Corbet
- Use titles markups;
- Adjust identation;
- use literal markup;
- Use the proper notation for footnotes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/misc-devices/index.rst | 1 +
.../misc-devices/pci-endpoint-test.rst | 56 +++++++++++++++++++
.../misc-devices/pci-endpoint-test.txt | 41 --------------
3 files changed, 57 insertions(+), 41 deletions(-)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.rst
delete mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 005547c1ad5d..04f5dab2384c 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -21,5 +21,6 @@ fit into other categories.
isl29003
lis3lv02d
max6875
+ pci-endpoint-test
spear-pcie-gadget
xilinx_sdfec
diff --git a/Documentation/misc-devices/pci-endpoint-test.rst b/Documentation/misc-devices/pci-endpoint-test.rst
new file mode 100644
index 000000000000..26e5d9ba146b
--- /dev/null
+++ b/Documentation/misc-devices/pci-endpoint-test.rst
@@ -0,0 +1,56 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================================
+Driver for PCI Endpoint Test Function
+=====================================
+
+This driver should be used as a host side driver if the root complex is
+connected to a configurable PCI endpoint running ``pci_epf_test`` function
+driver configured according to [1]_.
+
+The "pci_endpoint_test" driver can be used to perform the following tests.
+
+The PCI driver for the test device performs the following tests:
+
+ #) verifying addresses programmed in BAR
+ #) raise legacy IRQ
+ #) raise MSI IRQ
+ #) raise MSI-X IRQ
+ #) read data
+ #) write data
+ #) copy data
+
+This misc driver creates /dev/pci-endpoint-test.<num> for every
+``pci_epf_test`` function connected to the root complex and "ioctls"
+should be used to perform the above tests.
+
+ioctl
+-----
+
+ PCITEST_BAR:
+ Tests the BAR. The number of the BAR to be tested
+ should be passed as argument.
+ PCITEST_LEGACY_IRQ:
+ Tests legacy IRQ
+ PCITEST_MSI:
+ Tests message signalled interrupts. The MSI number
+ to be tested should be passed as argument.
+ PCITEST_MSIX:
+ Tests message signalled interrupts. The MSI-X number
+ to be tested should be passed as argument.
+ PCITEST_SET_IRQTYPE:
+ Changes driver IRQ type configuration. The IRQ type
+ should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
+ PCITEST_GET_IRQTYPE:
+ Gets driver IRQ type configuration.
+ PCITEST_WRITE:
+ Perform write tests. The size of the buffer should be passed
+ as argument.
+ PCITEST_READ:
+ Perform read tests. The size of the buffer should be passed
+ as argument.
+ PCITEST_COPY:
+ Perform read tests. The size of the buffer should be passed
+ as argument.
+
+.. [1] Documentation/PCI/endpoint/function/binding/pci-test.txt
diff --git a/Documentation/misc-devices/pci-endpoint-test.txt b/Documentation/misc-devices/pci-endpoint-test.txt
deleted file mode 100644
index 58ccca4416b1..000000000000
--- a/Documentation/misc-devices/pci-endpoint-test.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Driver for PCI Endpoint Test Function
-
-This driver should be used as a host side driver if the root complex is
-connected to a configurable PCI endpoint running *pci_epf_test* function
-driver configured according to [1].
-
-The "pci_endpoint_test" driver can be used to perform the following tests.
-
-The PCI driver for the test device performs the following tests
- *) verifying addresses programmed in BAR
- *) raise legacy IRQ
- *) raise MSI IRQ
- *) raise MSI-X IRQ
- *) read data
- *) write data
- *) copy data
-
-This misc driver creates /dev/pci-endpoint-test.<num> for every
-*pci_epf_test* function connected to the root complex and "ioctls"
-should be used to perform the above tests.
-
-ioctl
------
- PCITEST_BAR: Tests the BAR. The number of the BAR to be tested
- should be passed as argument.
- PCITEST_LEGACY_IRQ: Tests legacy IRQ
- PCITEST_MSI: Tests message signalled interrupts. The MSI number
- to be tested should be passed as argument.
- PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
- to be tested should be passed as argument.
- PCITEST_SET_IRQTYPE: Changes driver IRQ type configuration. The IRQ type
- should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
- PCITEST_GET_IRQTYPE: Gets driver IRQ type configuration.
- PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
- as argument.
- PCITEST_READ: Perform read tests. The size of the buffer should be passed
- as argument.
- PCITEST_COPY: Perform read tests. The size of the buffer should be passed
- as argument.
-
-[1] -> Documentation/PCI/endpoint/function/binding/pci-test.txt
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 09/24] docs: misc-devices/c2port.txt: convert to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (10 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List; +Cc: Mauro Carvalho Chehab, Jonathan Corbet
- Use copyright symbol;
- use title markups;
- adjust indentation;
- mark literal blocks as such.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../misc-devices/{c2port.txt => c2port.rst} | 58 ++++++++++---------
Documentation/misc-devices/index.rst | 1 +
2 files changed, 32 insertions(+), 27 deletions(-)
rename Documentation/misc-devices/{c2port.txt => c2port.rst} (59%)
diff --git a/Documentation/misc-devices/c2port.txt b/Documentation/misc-devices/c2port.rst
similarity index 59%
rename from Documentation/misc-devices/c2port.txt
rename to Documentation/misc-devices/c2port.rst
index ea7344465610..258e1c1d43c7 100644
--- a/Documentation/misc-devices/c2port.txt
+++ b/Documentation/misc-devices/c2port.rst
@@ -1,7 +1,11 @@
- C2 port support
- ---------------
+.. SPDX-License-Identifier: GPL-2.0
+.. include:: <isonum.txt>
-(C) Copyright 2007 Rodolfo Giometti <giometti@enneenne.com>
+===============
+C2 port support
+===============
+
+|copy| Copyright 2007 Rodolfo Giometti <giometti@enneenne.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -32,10 +36,10 @@ The C2 Interface main references are at (http://www.silabs.com)
Silicon Laboratories site], see:
- AN127: FLASH Programming via the C2 Interface at
-http://www.silabs.com/Support Documents/TechnicalDocs/an127.pdf
+ http://www.silabs.com/Support Documents/TechnicalDocs/an127.pdf
- C2 Specification at
-http://www.silabs.com/pages/DownloadDoc.aspx?FILEURL=Support%20Documents/TechnicalDocs/an127.pdf&src=SearchResults
+ http://www.silabs.com/pages/DownloadDoc.aspx?FILEURL=Support%20Documents/TechnicalDocs/an127.pdf&src=SearchResults
however it implements a two wire serial communication protocol (bit
banging) designed to enable in-system programming, debugging, and
@@ -47,44 +51,44 @@ Using the driver
----------------
Once the driver is loaded you can use sysfs support to get C2port's
-info or read/write in-system flash.
+info or read/write in-system flash::
-# ls /sys/class/c2port/c2port0/
-access flash_block_size flash_erase rev_id
-dev_id flash_blocks_num flash_size subsystem/
-flash_access flash_data reset uevent
+ # ls /sys/class/c2port/c2port0/
+ access flash_block_size flash_erase rev_id
+ dev_id flash_blocks_num flash_size subsystem/
+ flash_access flash_data reset uevent
Initially the C2port access is disabled since you hardware may have
such lines multiplexed with other devices so, to get access to the
-C2port, you need the command:
+C2port, you need the command::
-# echo 1 > /sys/class/c2port/c2port0/access
+ # echo 1 > /sys/class/c2port/c2port0/access
after that you should read the device ID and revision ID of the
-connected micro controller:
+connected micro controller::
-# cat /sys/class/c2port/c2port0/dev_id
-8
-# cat /sys/class/c2port/c2port0/rev_id
-1
+ # cat /sys/class/c2port/c2port0/dev_id
+ 8
+ # cat /sys/class/c2port/c2port0/rev_id
+ 1
However, for security reasons, the in-system flash access in not
-enabled yet, to do so you need the command:
+enabled yet, to do so you need the command::
-# echo 1 > /sys/class/c2port/c2port0/flash_access
+ # echo 1 > /sys/class/c2port/c2port0/flash_access
-After that you can read the whole flash:
+After that you can read the whole flash::
-# cat /sys/class/c2port/c2port0/flash_data > image
+ # cat /sys/class/c2port/c2port0/flash_data > image
-erase it:
+erase it::
-# echo 1 > /sys/class/c2port/c2port0/flash_erase
+ # echo 1 > /sys/class/c2port/c2port0/flash_erase
-and write it:
+and write it::
-# cat image > /sys/class/c2port/c2port0/flash_data
+ # cat image > /sys/class/c2port/c2port0/flash_data
-after writing you have to reset the device to execute the new code:
+after writing you have to reset the device to execute the new code::
-# echo 1 > /sys/class/c2port/c2port0/reset
+ # echo 1 > /sys/class/c2port/c2port0/reset
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 04f5dab2384c..c2e880d78734 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -16,6 +16,7 @@ fit into other categories.
ad525x_dpot
eeprom
+ c2port
ibmvmc
ics932s401
isl29003
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 10/24] docs: misc-devices/bh1770glc.txt: convert to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (11 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List; +Cc: Mauro Carvalho Chehab, Jonathan Corbet
- Adjust document title markup;
- use list markups;
- Adjust identations to display properly at ReST output.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../{bh1770glc.txt => bh1770glc.rst} | 45 +++++++++++++------
Documentation/misc-devices/index.rst | 1 +
2 files changed, 33 insertions(+), 13 deletions(-)
rename Documentation/misc-devices/{bh1770glc.txt => bh1770glc.rst} (83%)
diff --git a/Documentation/misc-devices/bh1770glc.txt b/Documentation/misc-devices/bh1770glc.rst
similarity index 83%
rename from Documentation/misc-devices/bh1770glc.txt
rename to Documentation/misc-devices/bh1770glc.rst
index 7d64c014dc70..ea5ca58bb958 100644
--- a/Documentation/misc-devices/bh1770glc.txt
+++ b/Documentation/misc-devices/bh1770glc.rst
@@ -1,9 +1,13 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=======================
Kernel driver bh1770glc
=======================
Supported chips:
-ROHM BH1770GLC
-OSRAM SFH7770
+
+- ROHM BH1770GLC
+- OSRAM SFH7770
Data sheet:
Not freely available
@@ -48,12 +52,16 @@ chip_id
RO - shows detected chip type and version
power_state
- RW - enable / disable chip. Uses counting logic
- 1 enables the chip
- 0 disables the chip
+ RW - enable / disable chip
+
+ Uses counting logic
+
+ - 1 enables the chip
+ - 0 disables the chip
lux0_input
RO - measured lux value
+
sysfs_notify called when threshold interrupt occurs
lux0_sensor_range
@@ -66,16 +74,22 @@ lux0_rate_avail
RO - supported measurement rates
lux0_thresh_above_value
- RW - HI level threshold value. All results above the value
+ RW - HI level threshold value
+
+ All results above the value
trigs an interrupt. 65535 (i.e. sensor_range) disables the above
interrupt.
lux0_thresh_below_value
- RW - LO level threshold value. All results below the value
+ RW - LO level threshold value
+
+ All results below the value
trigs an interrupt. 0 disables the below interrupt.
lux0_calibscale
- RW - calibration value. Set to neutral value by default.
+ RW - calibration value
+
+ Set to neutral value by default.
Output results are multiplied with calibscale / calibscale_default
value.
@@ -84,32 +98,37 @@ lux0_calibscale_default
prox0_raw
RO - measured proximity value
+
sysfs_notify called when threshold interrupt occurs
prox0_sensor_range
RO - prox0_raw max value
prox0_raw_en
- RW - enable / disable proximity - uses counting logic
- 1 enables the proximity
- 0 disables the proximity
+ RW - enable / disable proximity
+
+ Uses counting logic
+
+ - 1 enables the proximity
+ - 0 disables the proximity
prox0_thresh_above_count
RW - number of proximity interrupts needed before triggering the event
prox0_rate_above
RW - Measurement rate (in Hz) when the level is above threshold
- i.e. when proximity on has been reported.
+ i.e. when proximity on has been reported.
prox0_rate_below
RW - Measurement rate (in Hz) when the level is below threshold
- i.e. when proximity off has been reported.
+ i.e. when proximity off has been reported.
prox0_rate_avail
RO - Supported proximity measurement rates in Hz
prox0_thresh_above0_value
RW - threshold level which trigs proximity events.
+
Filtered by persistence filter (prox0_thresh_above_count)
prox0_thresh_above1_value
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index c2e880d78734..40a4c104e7a2 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -15,6 +15,7 @@ fit into other categories.
:maxdepth: 2
ad525x_dpot
+ bh1770glc
eeprom
c2port
ibmvmc
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 11/24] docs: misc-devices/apds990x.txt: convert to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (12 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List; +Cc: Mauro Carvalho Chehab, Jonathan Corbet
- Adjust title markup;
- Adjust identation.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../{apds990x.txt => apds990x.rst} | 31 ++++++++++++++-----
Documentation/misc-devices/index.rst | 1 +
2 files changed, 25 insertions(+), 7 deletions(-)
rename Documentation/misc-devices/{apds990x.txt => apds990x.rst} (86%)
diff --git a/Documentation/misc-devices/apds990x.txt b/Documentation/misc-devices/apds990x.rst
similarity index 86%
rename from Documentation/misc-devices/apds990x.txt
rename to Documentation/misc-devices/apds990x.rst
index 454d95d623b3..e2f75577f731 100644
--- a/Documentation/misc-devices/apds990x.txt
+++ b/Documentation/misc-devices/apds990x.rst
@@ -1,3 +1,6 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+======================
Kernel driver apds990x
======================
@@ -50,14 +53,18 @@ chip_id
power_state
RW - enable / disable chip. Uses counting logic
+
1 enables the chip
0 disables the chip
lux0_input
RO - measured lux value
+
sysfs_notify called when threshold interrupt occurs
lux0_sensor_range
- RO - lux0_input max value. Actually never reaches since sensor tends
+ RO - lux0_input max value.
+
+ Actually never reaches since sensor tends
to saturate much before that. Real max value varies depending
on the light spectrum etc.
@@ -68,7 +75,9 @@ lux0_rate_avail
RO - supported measurement rates
lux0_calibscale
- RW - calibration value. Set to neutral value by default.
+ RW - calibration value.
+
+ Set to neutral value by default.
Output results are multiplied with calibscale / calibscale_default
value.
@@ -76,16 +85,21 @@ lux0_calibscale_default
RO - neutral calibration value
lux0_thresh_above_value
- RW - HI level threshold value. All results above the value
+ RW - HI level threshold value.
+
+ All results above the value
trigs an interrupt. 65535 (i.e. sensor_range) disables the above
interrupt.
lux0_thresh_below_value
- RW - LO level threshold value. All results below the value
+ RW - LO level threshold value.
+
+ All results below the value
trigs an interrupt. 0 disables the below interrupt.
prox0_raw
RO - measured proximity value
+
sysfs_notify called when threshold interrupt occurs
prox0_sensor_range
@@ -93,11 +107,14 @@ prox0_sensor_range
prox0_raw_en
RW - enable / disable proximity - uses counting logic
- 1 enables the proximity
- 0 disables the proximity
+
+ - 1 enables the proximity
+ - 0 disables the proximity
prox0_reporting_mode
- RW - trigger / periodic. In "trigger" mode the driver tells two possible
+ RW - trigger / periodic.
+
+ In "trigger" mode the driver tells two possible
values: 0 or prox0_sensor_range value. 0 means no proximity,
1023 means proximity. This causes minimal number of interrupts.
In "periodic" mode the driver reports all values above
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 40a4c104e7a2..16973310d32e 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -15,6 +15,7 @@ fit into other categories.
:maxdepth: 2
ad525x_dpot
+ apds990x
bh1770glc
eeprom
c2port
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 12/24] docs: pci: endpoint/function/binding/pci-test.txt convert to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (13 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
2020-02-27 23:03 ` Bjorn Helgaas
-1 siblings, 1 reply; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Bjorn Helgaas, linux-pci
Convert this file to ReST by adding a proper title to it and
use the right markups for a table.
While here, add a SPDX header.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../endpoint/function/binding/pci-test.rst | 26 +++++++++++++++++++
.../endpoint/function/binding/pci-test.txt | 19 --------------
Documentation/PCI/endpoint/index.rst | 2 ++
3 files changed, 28 insertions(+), 19 deletions(-)
create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.rst
delete mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.rst b/Documentation/PCI/endpoint/function/binding/pci-test.rst
new file mode 100644
index 000000000000..57ee866fb165
--- /dev/null
+++ b/Documentation/PCI/endpoint/function/binding/pci-test.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==========================
+PCI Test Endpoint Function
+==========================
+
+name: Should be "pci_epf_test" to bind to the pci_epf_test driver.
+
+Configurable Fields:
+
+================ ===========================================================
+vendorid should be 0x104c
+deviceid should be 0xb500 for DRA74x and 0xb501 for DRA72x
+revid don't care
+progif_code don't care
+subclass_code don't care
+baseclass_code should be 0xff
+cache_line_size don't care
+subsys_vendor_id don't care
+subsys_id don't care
+interrupt_pin Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
+msi_interrupts Should be 1 to 32 depending on the number of MSI interrupts
+ to test
+msix_interrupts Should be 1 to 2048 depending on the number of MSI-X
+ interrupts to test
+================ ===========================================================
diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt b/Documentation/PCI/endpoint/function/binding/pci-test.txt
deleted file mode 100644
index cd76ba47394b..000000000000
--- a/Documentation/PCI/endpoint/function/binding/pci-test.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-PCI TEST ENDPOINT FUNCTION
-
-name: Should be "pci_epf_test" to bind to the pci_epf_test driver.
-
-Configurable Fields:
-vendorid : should be 0x104c
-deviceid : should be 0xb500 for DRA74x and 0xb501 for DRA72x
-revid : don't care
-progif_code : don't care
-subclass_code : don't care
-baseclass_code : should be 0xff
-cache_line_size : don't care
-subsys_vendor_id : don't care
-subsys_id : don't care
-interrupt_pin : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
-msi_interrupts : Should be 1 to 32 depending on the number of MSI interrupts
- to test
-msix_interrupts : Should be 1 to 2048 depending on the number of MSI-X
- interrupts to test
diff --git a/Documentation/PCI/endpoint/index.rst b/Documentation/PCI/endpoint/index.rst
index d114ea74b444..4ca7439fbfc9 100644
--- a/Documentation/PCI/endpoint/index.rst
+++ b/Documentation/PCI/endpoint/index.rst
@@ -11,3 +11,5 @@ PCI Endpoint Framework
pci-endpoint-cfs
pci-test-function
pci-test-howto
+
+ function/binding/pci-test
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v2 12/24] docs: pci: endpoint/function/binding/pci-test.txt convert to ReST
2020-02-17 16:20 ` [PATCH v2 12/24] docs: pci: endpoint/function/binding/pci-test.txt convert to ReST Mauro Carvalho Chehab
@ 2020-02-27 23:03 ` Bjorn Helgaas
0 siblings, 0 replies; 43+ messages in thread
From: Bjorn Helgaas @ 2020-02-27 23:03 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: Linux Doc Mailing List, Jonathan Corbet, linux-pci
On Mon, Feb 17, 2020 at 05:20:30PM +0100, Mauro Carvalho Chehab wrote:
> Convert this file to ReST by adding a proper title to it and
> use the right markups for a table.
>
> While here, add a SPDX header.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
FWIW,
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
I assume you'll merge this, Jonathan. Let me know if I should do
anything else with this.
> ---
> .../endpoint/function/binding/pci-test.rst | 26 +++++++++++++++++++
> .../endpoint/function/binding/pci-test.txt | 19 --------------
> Documentation/PCI/endpoint/index.rst | 2 ++
> 3 files changed, 28 insertions(+), 19 deletions(-)
> create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.rst
> delete mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
>
> diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.rst b/Documentation/PCI/endpoint/function/binding/pci-test.rst
> new file mode 100644
> index 000000000000..57ee866fb165
> --- /dev/null
> +++ b/Documentation/PCI/endpoint/function/binding/pci-test.rst
> @@ -0,0 +1,26 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +==========================
> +PCI Test Endpoint Function
> +==========================
> +
> +name: Should be "pci_epf_test" to bind to the pci_epf_test driver.
> +
> +Configurable Fields:
> +
> +================ ===========================================================
> +vendorid should be 0x104c
> +deviceid should be 0xb500 for DRA74x and 0xb501 for DRA72x
> +revid don't care
> +progif_code don't care
> +subclass_code don't care
> +baseclass_code should be 0xff
> +cache_line_size don't care
> +subsys_vendor_id don't care
> +subsys_id don't care
> +interrupt_pin Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
> +msi_interrupts Should be 1 to 32 depending on the number of MSI interrupts
> + to test
> +msix_interrupts Should be 1 to 2048 depending on the number of MSI-X
> + interrupts to test
> +================ ===========================================================
> diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt b/Documentation/PCI/endpoint/function/binding/pci-test.txt
> deleted file mode 100644
> index cd76ba47394b..000000000000
> --- a/Documentation/PCI/endpoint/function/binding/pci-test.txt
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -PCI TEST ENDPOINT FUNCTION
> -
> -name: Should be "pci_epf_test" to bind to the pci_epf_test driver.
> -
> -Configurable Fields:
> -vendorid : should be 0x104c
> -deviceid : should be 0xb500 for DRA74x and 0xb501 for DRA72x
> -revid : don't care
> -progif_code : don't care
> -subclass_code : don't care
> -baseclass_code : should be 0xff
> -cache_line_size : don't care
> -subsys_vendor_id : don't care
> -subsys_id : don't care
> -interrupt_pin : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
> -msi_interrupts : Should be 1 to 32 depending on the number of MSI interrupts
> - to test
> -msix_interrupts : Should be 1 to 2048 depending on the number of MSI-X
> - interrupts to test
> diff --git a/Documentation/PCI/endpoint/index.rst b/Documentation/PCI/endpoint/index.rst
> index d114ea74b444..4ca7439fbfc9 100644
> --- a/Documentation/PCI/endpoint/index.rst
> +++ b/Documentation/PCI/endpoint/index.rst
> @@ -11,3 +11,5 @@ PCI Endpoint Framework
> pci-endpoint-cfs
> pci-test-function
> pci-test-howto
> +
> + function/binding/pci-test
> --
> 2.24.1
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2 13/24] docs: arm64: convert perf.txt to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Catalin Marinas,
Will Deacon, linux-arm-kernel
This file is almost in ReST. All it needs is a rename and
adding a :field: for the two fields at the beginning
(author and date).
While here, add a proper SPDX header, and use the standard
markup for document titles, just for consistency.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/arm64/index.rst | 1 +
Documentation/arm64/{perf.txt => perf.rst} | 7 +++++--
2 files changed, 6 insertions(+), 2 deletions(-)
rename Documentation/arm64/{perf.txt => perf.rst} (95%)
diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst
index 5c0c69dc58aa..c51d0fa80318 100644
--- a/Documentation/arm64/index.rst
+++ b/Documentation/arm64/index.rst
@@ -13,6 +13,7 @@ ARM64 Architecture
hugetlbpage
legacy_instructions
memory
+ perf
pointer-authentication
silicon-errata
sve
diff --git a/Documentation/arm64/perf.txt b/Documentation/arm64/perf.rst
similarity index 95%
rename from Documentation/arm64/perf.txt
rename to Documentation/arm64/perf.rst
index 0d6a7d87d49e..9c76a97baf28 100644
--- a/Documentation/arm64/perf.txt
+++ b/Documentation/arm64/perf.rst
@@ -1,8 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================
Perf Event Attributes
=====================
-Author: Andrew Murray <andrew.murray@arm.com>
-Date: 2019-03-06
+:Author: Andrew Murray <andrew.murray@arm.com>
+:Date: 2019-03-06
exclude_user
------------
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 13/24] docs: arm64: convert perf.txt to ReST format
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Catalin Marinas, Will Deacon,
linux-arm-kernel, Jonathan Corbet
This file is almost in ReST. All it needs is a rename and
adding a :field: for the two fields at the beginning
(author and date).
While here, add a proper SPDX header, and use the standard
markup for document titles, just for consistency.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/arm64/index.rst | 1 +
Documentation/arm64/{perf.txt => perf.rst} | 7 +++++--
2 files changed, 6 insertions(+), 2 deletions(-)
rename Documentation/arm64/{perf.txt => perf.rst} (95%)
diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst
index 5c0c69dc58aa..c51d0fa80318 100644
--- a/Documentation/arm64/index.rst
+++ b/Documentation/arm64/index.rst
@@ -13,6 +13,7 @@ ARM64 Architecture
hugetlbpage
legacy_instructions
memory
+ perf
pointer-authentication
silicon-errata
sve
diff --git a/Documentation/arm64/perf.txt b/Documentation/arm64/perf.rst
similarity index 95%
rename from Documentation/arm64/perf.txt
rename to Documentation/arm64/perf.rst
index 0d6a7d87d49e..9c76a97baf28 100644
--- a/Documentation/arm64/perf.txt
+++ b/Documentation/arm64/perf.rst
@@ -1,8 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================
Perf Event Attributes
=====================
-Author: Andrew Murray <andrew.murray@arm.com>
-Date: 2019-03-06
+:Author: Andrew Murray <andrew.murray@arm.com>
+:Date: 2019-03-06
exclude_user
------------
--
2.24.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v2 13/24] docs: arm64: convert perf.txt to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
@ 2020-06-02 21:01 ` Rob Herring
-1 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2020-06-02 21:01 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Linux Doc Mailing List, Catalin Marinas, Will Deacon,
linux-arm-kernel, Jonathan Corbet
On Mon, Feb 17, 2020 at 05:20:31PM +0100, Mauro Carvalho Chehab wrote:
> This file is almost in ReST. All it needs is a rename and
> adding a :field: for the two fields at the beginning
> (author and date).
>
> While here, add a proper SPDX header, and use the standard
> markup for document titles, just for consistency.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
> Documentation/arm64/index.rst | 1 +
> Documentation/arm64/{perf.txt => perf.rst} | 7 +++++--
> 2 files changed, 6 insertions(+), 2 deletions(-)
> rename Documentation/arm64/{perf.txt => perf.rst} (95%)
Is there some reason this hasn't been merged or commented on?
> diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst
> index 5c0c69dc58aa..c51d0fa80318 100644
> --- a/Documentation/arm64/index.rst
> +++ b/Documentation/arm64/index.rst
> @@ -13,6 +13,7 @@ ARM64 Architecture
> hugetlbpage
> legacy_instructions
> memory
> + perf
> pointer-authentication
> silicon-errata
> sve
> diff --git a/Documentation/arm64/perf.txt b/Documentation/arm64/perf.rst
> similarity index 95%
> rename from Documentation/arm64/perf.txt
> rename to Documentation/arm64/perf.rst
> index 0d6a7d87d49e..9c76a97baf28 100644
> --- a/Documentation/arm64/perf.txt
> +++ b/Documentation/arm64/perf.rst
> @@ -1,8 +1,11 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +=====================
> Perf Event Attributes
> =====================
>
> -Author: Andrew Murray <andrew.murray@arm.com>
> -Date: 2019-03-06
> +:Author: Andrew Murray <andrew.murray@arm.com>
> +:Date: 2019-03-06
Andrew is no long with Arm. Both lines look like things that become
stale, so I'd just remove them.
Rob
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v2 13/24] docs: arm64: convert perf.txt to ReST format
@ 2020-06-02 21:01 ` Rob Herring
0 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2020-06-02 21:01 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Catalin Marinas, Jonathan Corbet, Will Deacon, linux-arm-kernel,
Linux Doc Mailing List
On Mon, Feb 17, 2020 at 05:20:31PM +0100, Mauro Carvalho Chehab wrote:
> This file is almost in ReST. All it needs is a rename and
> adding a :field: for the two fields at the beginning
> (author and date).
>
> While here, add a proper SPDX header, and use the standard
> markup for document titles, just for consistency.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
> Documentation/arm64/index.rst | 1 +
> Documentation/arm64/{perf.txt => perf.rst} | 7 +++++--
> 2 files changed, 6 insertions(+), 2 deletions(-)
> rename Documentation/arm64/{perf.txt => perf.rst} (95%)
Is there some reason this hasn't been merged or commented on?
> diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst
> index 5c0c69dc58aa..c51d0fa80318 100644
> --- a/Documentation/arm64/index.rst
> +++ b/Documentation/arm64/index.rst
> @@ -13,6 +13,7 @@ ARM64 Architecture
> hugetlbpage
> legacy_instructions
> memory
> + perf
> pointer-authentication
> silicon-errata
> sve
> diff --git a/Documentation/arm64/perf.txt b/Documentation/arm64/perf.rst
> similarity index 95%
> rename from Documentation/arm64/perf.txt
> rename to Documentation/arm64/perf.rst
> index 0d6a7d87d49e..9c76a97baf28 100644
> --- a/Documentation/arm64/perf.txt
> +++ b/Documentation/arm64/perf.rst
> @@ -1,8 +1,11 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +=====================
> Perf Event Attributes
> =====================
>
> -Author: Andrew Murray <andrew.murray@arm.com>
> -Date: 2019-03-06
> +:Author: Andrew Murray <andrew.murray@arm.com>
> +:Date: 2019-03-06
Andrew is no long with Arm. Both lines look like things that become
stale, so I'd just remove them.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (15 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
2020-02-17 20:06 ` Rafael J. Wysocki
2020-03-02 21:19 ` Jonathan Corbet
-1 siblings, 2 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, linux-pm
most of the stuff there can be re-used with ReST format,
but we need to add an empty TOC and remove the existing
entries, as the following conversion patches will be re-adding
them, as they're converted.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/cpu-freq/index.rst | 35 ++++++++++++++++++++
Documentation/cpu-freq/index.txt | 56 --------------------------------
Documentation/index.rst | 1 +
3 files changed, 36 insertions(+), 56 deletions(-)
create mode 100644 Documentation/cpu-freq/index.rst
delete mode 100644 Documentation/cpu-freq/index.txt
diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
new file mode 100644
index 000000000000..1bff3dfddd23
--- /dev/null
+++ b/Documentation/cpu-freq/index.rst
@@ -0,0 +1,35 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==============================================================================
+Linux CPUFreq - CPU frequency and voltage scaling code in the Linux(TM) kernel
+==============================================================================
+
+Author: Dominik Brodowski <linux@brodo.de>
+
+ Clock scaling allows you to change the clock speed of the CPUs on the
+ fly. This is a nice method to save battery power, because the lower
+ the clock speed, the less power the CPU consumes.
+
+
+.. toctree::
+ :maxdepth: 1
+
+Mailing List
+------------
+There is a CPU frequency changing CVS commit and general list where
+you can report bugs, problems or submit patches. To post a message,
+send an email to linux-pm@vger.kernel.org.
+
+Links
+-----
+the FTP archives:
+* ftp://ftp.linux.org.uk/pub/linux/cpufreq/
+
+how to access the CVS repository:
+* http://cvs.arm.linux.org.uk/
+
+the CPUFreq Mailing list:
+* http://vger.kernel.org/vger-lists.html#linux-pm
+
+Clock and voltage scaling for the SA-1100:
+* http://www.lartmaker.nl/projects/scaling
diff --git a/Documentation/cpu-freq/index.txt b/Documentation/cpu-freq/index.txt
deleted file mode 100644
index c15e75386a05..000000000000
--- a/Documentation/cpu-freq/index.txt
+++ /dev/null
@@ -1,56 +0,0 @@
- CPU frequency and voltage scaling code in the Linux(TM) kernel
-
-
- L i n u x C P U F r e q
-
-
-
-
- Dominik Brodowski <linux@brodo.de>
-
-
-
- Clock scaling allows you to change the clock speed of the CPUs on the
- fly. This is a nice method to save battery power, because the lower
- the clock speed, the less power the CPU consumes.
-
-
-
-Documents in this directory:
-----------------------------
-
-amd-powernow.txt - AMD powernow driver specific file.
-
-core.txt - General description of the CPUFreq core and
- of CPUFreq notifiers.
-
-cpu-drivers.txt - How to implement a new cpufreq processor driver.
-
-cpufreq-nforce2.txt - nVidia nForce2 platform specific file.
-
-cpufreq-stats.txt - General description of sysfs cpufreq stats.
-
-index.txt - File index, Mailing list and Links (this document)
-
-pcc-cpufreq.txt - PCC cpufreq driver specific file.
-
-
-Mailing List
-------------
-There is a CPU frequency changing CVS commit and general list where
-you can report bugs, problems or submit patches. To post a message,
-send an email to linux-pm@vger.kernel.org.
-
-Links
------
-the FTP archives:
-* ftp://ftp.linux.org.uk/pub/linux/cpufreq/
-
-how to access the CVS repository:
-* http://cvs.arm.linux.org.uk/
-
-the CPUFreq Mailing list:
-* http://vger.kernel.org/vger-lists.html#linux-pm
-
-Clock and voltage scaling for the SA-1100:
-* http://www.lartmaker.nl/projects/scaling
diff --git a/Documentation/index.rst b/Documentation/index.rst
index e99d0bd2589d..4cf37ad1cd1d 100644
--- a/Documentation/index.rst
+++ b/Documentation/index.rst
@@ -99,6 +99,7 @@ needed).
accounting/index
block/index
cdrom/index
+ cpu-freq/index
ide/index
fb/index
fpga/index
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-02-17 16:20 ` [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST Mauro Carvalho Chehab
@ 2020-02-17 20:06 ` Rafael J. Wysocki
2020-02-28 9:14 ` Mauro Carvalho Chehab
2020-03-02 21:19 ` Jonathan Corbet
1 sibling, 1 reply; 43+ messages in thread
From: Rafael J. Wysocki @ 2020-02-17 20:06 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Linux Doc Mailing List, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, Linux PM
On Mon, Feb 17, 2020 at 5:20 PM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> most of the stuff there can be re-used with ReST format,
> but we need to add an empty TOC and remove the existing
> entries, as the following conversion patches will be re-adding
> them, as they're converted.
I see a very little value in converting the files in the cpu-freq
directory from .txt to .rst, which I have told you at least twice.
They are just old-style driver API documents for cpufreq, but moving
them under driver-api/ as they are would not be a good idea IMO,
because at least some of them are outdated (note that the admin-guide
part of the cpufreq documentation, in the .rst format, is located
under admin-guide/).
I haven't had the time to write a proper replacement for them yet and
honestly I find it quite obnoxious to see these reoccurring attempts
to blindly convert them to .rst without taking care of their contents
and location.
I will take care of these files at one point as promised, but that's
not going to happen today or tomorrow and please just leave them alone
if that is not a big deal.
Thanks!
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
> Documentation/cpu-freq/index.rst | 35 ++++++++++++++++++++
> Documentation/cpu-freq/index.txt | 56 --------------------------------
> Documentation/index.rst | 1 +
> 3 files changed, 36 insertions(+), 56 deletions(-)
> create mode 100644 Documentation/cpu-freq/index.rst
> delete mode 100644 Documentation/cpu-freq/index.txt
>
> diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
> new file mode 100644
> index 000000000000..1bff3dfddd23
> --- /dev/null
> +++ b/Documentation/cpu-freq/index.rst
> @@ -0,0 +1,35 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +==============================================================================
> +Linux CPUFreq - CPU frequency and voltage scaling code in the Linux(TM) kernel
> +==============================================================================
> +
> +Author: Dominik Brodowski <linux@brodo.de>
> +
> + Clock scaling allows you to change the clock speed of the CPUs on the
> + fly. This is a nice method to save battery power, because the lower
> + the clock speed, the less power the CPU consumes.
> +
> +
> +.. toctree::
> + :maxdepth: 1
> +
> +Mailing List
> +------------
> +There is a CPU frequency changing CVS commit and general list where
> +you can report bugs, problems or submit patches. To post a message,
> +send an email to linux-pm@vger.kernel.org.
> +
> +Links
> +-----
> +the FTP archives:
> +* ftp://ftp.linux.org.uk/pub/linux/cpufreq/
> +
> +how to access the CVS repository:
> +* http://cvs.arm.linux.org.uk/
> +
> +the CPUFreq Mailing list:
> +* http://vger.kernel.org/vger-lists.html#linux-pm
> +
> +Clock and voltage scaling for the SA-1100:
> +* http://www.lartmaker.nl/projects/scaling
> diff --git a/Documentation/cpu-freq/index.txt b/Documentation/cpu-freq/index.txt
> deleted file mode 100644
> index c15e75386a05..000000000000
> --- a/Documentation/cpu-freq/index.txt
> +++ /dev/null
> @@ -1,56 +0,0 @@
> - CPU frequency and voltage scaling code in the Linux(TM) kernel
> -
> -
> - L i n u x C P U F r e q
> -
> -
> -
> -
> - Dominik Brodowski <linux@brodo.de>
> -
> -
> -
> - Clock scaling allows you to change the clock speed of the CPUs on the
> - fly. This is a nice method to save battery power, because the lower
> - the clock speed, the less power the CPU consumes.
> -
> -
> -
> -Documents in this directory:
> -----------------------------
> -
> -amd-powernow.txt - AMD powernow driver specific file.
> -
> -core.txt - General description of the CPUFreq core and
> - of CPUFreq notifiers.
> -
> -cpu-drivers.txt - How to implement a new cpufreq processor driver.
> -
> -cpufreq-nforce2.txt - nVidia nForce2 platform specific file.
> -
> -cpufreq-stats.txt - General description of sysfs cpufreq stats.
> -
> -index.txt - File index, Mailing list and Links (this document)
> -
> -pcc-cpufreq.txt - PCC cpufreq driver specific file.
> -
> -
> -Mailing List
> -------------
> -There is a CPU frequency changing CVS commit and general list where
> -you can report bugs, problems or submit patches. To post a message,
> -send an email to linux-pm@vger.kernel.org.
> -
> -Links
> ------
> -the FTP archives:
> -* ftp://ftp.linux.org.uk/pub/linux/cpufreq/
> -
> -how to access the CVS repository:
> -* http://cvs.arm.linux.org.uk/
> -
> -the CPUFreq Mailing list:
> -* http://vger.kernel.org/vger-lists.html#linux-pm
> -
> -Clock and voltage scaling for the SA-1100:
> -* http://www.lartmaker.nl/projects/scaling
> diff --git a/Documentation/index.rst b/Documentation/index.rst
> index e99d0bd2589d..4cf37ad1cd1d 100644
> --- a/Documentation/index.rst
> +++ b/Documentation/index.rst
> @@ -99,6 +99,7 @@ needed).
> accounting/index
> block/index
> cdrom/index
> + cpu-freq/index
> ide/index
> fb/index
> fpga/index
> --
> 2.24.1
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-02-17 20:06 ` Rafael J. Wysocki
@ 2020-02-28 9:14 ` Mauro Carvalho Chehab
2020-02-28 9:33 ` Rafael J. Wysocki
0 siblings, 1 reply; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-28 9:14 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Linux Doc Mailing List, Jonathan Corbet, Viresh Kumar, Linux PM
Hi Rafael,
Em Mon, 17 Feb 2020 21:06:20 +0100
"Rafael J. Wysocki" <rafael@kernel.org> escreveu:
> On Mon, Feb 17, 2020 at 5:20 PM Mauro Carvalho Chehab
> <mchehab+huawei@kernel.org> wrote:
> >
> > most of the stuff there can be re-used with ReST format,
> > but we need to add an empty TOC and remove the existing
> > entries, as the following conversion patches will be re-adding
> > them, as they're converted.
>
> I see a very little value in converting the files in the cpu-freq
> directory from .txt to .rst, which I have told you at least twice.
>
> They are just old-style driver API documents for cpufreq, but moving
> them under driver-api/ as they are would not be a good idea IMO,
> because at least some of them are outdated (note that the admin-guide
> part of the cpufreq documentation, in the .rst format, is located
> under admin-guide/).
>
> I haven't had the time to write a proper replacement for them yet and
> honestly I find it quite obnoxious to see these reoccurring attempts
> to blindly convert them to .rst without taking care of their contents
> and location.
>
> I will take care of these files at one point as promised, but that's
> not going to happen today or tomorrow and please just leave them alone
> if that is not a big deal.
Sorry, I completely forgot that you asked to skip the old cpufreq docs.
My bad!
The thing is that I have now fully converted all docs to ReST (with a
handful exceptions for things that may not make sense to convert, like
configuration files that ends with .txt).
As a matter of helping those (like me) that are trying to finish this
huge conversion/reorganize task, I would very much prefer to keep those
files converted somewhere (or trashed, if their contents is now completely
garbage).
One of the things we discussed at linux-doc ML is to create a "staging"
area where we can place:
- things that aren't ready to be at the main documentation body yet;
- too obsolete docs that may require major work;
- things that we didn't find a good place to put yet.
From the last discussions, it seems we reach a consensus about creating that.
So, I should be preparing a separate patchset adding a Documentation/staging
dir.
Would it be OK for you if I change the cpufreq patches on this series to
be moving those into a new Documentation/staging/cpufreq directory?
Regards,
Mauro
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-02-28 9:14 ` Mauro Carvalho Chehab
@ 2020-02-28 9:33 ` Rafael J. Wysocki
0 siblings, 0 replies; 43+ messages in thread
From: Rafael J. Wysocki @ 2020-02-28 9:33 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Rafael J. Wysocki, Linux Doc Mailing List, Jonathan Corbet,
Viresh Kumar, Linux PM
On Fri, Feb 28, 2020 at 10:14 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Hi Rafael,
>
> Em Mon, 17 Feb 2020 21:06:20 +0100
> "Rafael J. Wysocki" <rafael@kernel.org> escreveu:
>
> > On Mon, Feb 17, 2020 at 5:20 PM Mauro Carvalho Chehab
> > <mchehab+huawei@kernel.org> wrote:
> > >
> > > most of the stuff there can be re-used with ReST format,
> > > but we need to add an empty TOC and remove the existing
> > > entries, as the following conversion patches will be re-adding
> > > them, as they're converted.
> >
> > I see a very little value in converting the files in the cpu-freq
> > directory from .txt to .rst, which I have told you at least twice.
> >
> > They are just old-style driver API documents for cpufreq, but moving
> > them under driver-api/ as they are would not be a good idea IMO,
> > because at least some of them are outdated (note that the admin-guide
> > part of the cpufreq documentation, in the .rst format, is located
> > under admin-guide/).
> >
> > I haven't had the time to write a proper replacement for them yet and
> > honestly I find it quite obnoxious to see these reoccurring attempts
> > to blindly convert them to .rst without taking care of their contents
> > and location.
> >
> > I will take care of these files at one point as promised, but that's
> > not going to happen today or tomorrow and please just leave them alone
> > if that is not a big deal.
>
> Sorry, I completely forgot that you asked to skip the old cpufreq docs.
> My bad!
>
> The thing is that I have now fully converted all docs to ReST (with a
> handful exceptions for things that may not make sense to convert, like
> configuration files that ends with .txt).
And I have this patch:
https://patchwork.kernel.org/patch/11411035/
so at least please drop the commits converting the three files affected by it.
> As a matter of helping those (like me) that are trying to finish this
> huge conversion/reorganize task, I would very much prefer to keep those
> files converted somewhere (or trashed, if their contents is now completely
> garbage).
>
> One of the things we discussed at linux-doc ML is to create a "staging"
> area where we can place:
>
> - things that aren't ready to be at the main documentation body yet;
> - too obsolete docs that may require major work;
> - things that we didn't find a good place to put yet.
>
> From the last discussions, it seems we reach a consensus about creating that.
So the other files in Documentation/cpu-freq/ can be converted to .rst
as far as I'm concerned (even though I still don't see much value in
doing that, just for the record).
They will be going away anyway in the future, regardless of the format
in which they are at that time. :-)
Cheers!
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-02-17 16:20 ` [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST Mauro Carvalho Chehab
2020-02-17 20:06 ` Rafael J. Wysocki
@ 2020-03-02 21:19 ` Jonathan Corbet
2020-03-02 22:16 ` Rafael J. Wysocki
2020-03-03 14:01 ` Mauro Carvalho Chehab
1 sibling, 2 replies; 43+ messages in thread
From: Jonathan Corbet @ 2020-03-02 21:19 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Linux Doc Mailing List, Rafael J. Wysocki, Viresh Kumar, linux-pm
On Mon, 17 Feb 2020 17:20:32 +0100
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote:
> most of the stuff there can be re-used with ReST format,
> but we need to add an empty TOC and remove the existing
> entries, as the following conversion patches will be re-adding
> them, as they're converted.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Rafael, do you want to carry the cpu-freq changes from this set, or should
I just apply the whole thing over here?
Thanks,
jon
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-03-02 21:19 ` Jonathan Corbet
@ 2020-03-02 22:16 ` Rafael J. Wysocki
2020-03-03 13:54 ` Mauro Carvalho Chehab
2020-03-03 14:01 ` Mauro Carvalho Chehab
1 sibling, 1 reply; 43+ messages in thread
From: Rafael J. Wysocki @ 2020-03-02 22:16 UTC (permalink / raw)
To: Jonathan Corbet
Cc: Mauro Carvalho Chehab, Linux Doc Mailing List, Rafael J. Wysocki,
Viresh Kumar, Linux PM
On Mon, Mar 2, 2020 at 10:19 PM Jonathan Corbet <corbet@lwn.net> wrote:
>
> On Mon, 17 Feb 2020 17:20:32 +0100
> Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote:
>
> > most of the stuff there can be re-used with ReST format,
> > but we need to add an empty TOC and remove the existing
> > entries, as the following conversion patches will be re-adding
> > them, as they're converted.
> >
> > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
>
> Rafael, do you want to carry the cpu-freq changes from this set, or should
> I just apply the whole thing over here?
I will take the ones that are applicable after rebasing on top of
https://patchwork.kernel.org/patch/11411035/
Cheers!
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-03-02 22:16 ` Rafael J. Wysocki
@ 2020-03-03 13:54 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-03-03 13:54 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Jonathan Corbet, Linux Doc Mailing List, Rafael J. Wysocki,
Viresh Kumar, Linux PM
Em Mon, 2 Mar 2020 23:16:10 +0100
"Rafael J. Wysocki" <rafael@kernel.org> escreveu:
> On Mon, Mar 2, 2020 at 10:19 PM Jonathan Corbet <corbet@lwn.net> wrote:
> >
> > On Mon, 17 Feb 2020 17:20:32 +0100
> > Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote:
> >
> > > most of the stuff there can be re-used with ReST format,
> > > but we need to add an empty TOC and remove the existing
> > > entries, as the following conversion patches will be re-adding
> > > them, as they're converted.
> > >
> > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> >
> > Rafael, do you want to carry the cpu-freq changes from this set, or should
> > I just apply the whole thing over here?
>
> I will take the ones that are applicable after rebasing on top of
> https://patchwork.kernel.org/patch/11411035/
Just rebased on the top of it (plus next-20200303) and sent.
Btw, patch 1/5 of such series is just a small fix for the above. It
addresses a Kconfig.x86 pointer to a documentation file that were moved
by the above patch.
Feel free to merge it with patch #11411035 if you want.
Regards,
Mauro
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 14/24] docs: cpu-freq: convert index.txt to ReST
2020-03-02 21:19 ` Jonathan Corbet
2020-03-02 22:16 ` Rafael J. Wysocki
@ 2020-03-03 14:01 ` Mauro Carvalho Chehab
1 sibling, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-03-03 14:01 UTC (permalink / raw)
To: Jonathan Corbet
Cc: Linux Doc Mailing List, Rafael J. Wysocki, Viresh Kumar, linux-pm
Em Mon, 2 Mar 2020 14:19:16 -0700
Jonathan Corbet <corbet@lwn.net> escreveu:
> On Mon, 17 Feb 2020 17:20:32 +0100
> Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote:
>
> > most of the stuff there can be re-used with ReST format,
> > but we need to add an empty TOC and remove the existing
> > entries, as the following conversion patches will be re-adding
> > them, as they're converted.
> >
> > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
>
> Rafael, do you want to carry the cpu-freq changes from this set, or should
> I just apply the whole thing over here?
Hi Jon,
As Rafael should be applying the cpu-freq via his tree, I'm re-sending the
remaining patches on this series as:
[PATCH v3 00/18] Manually convert thermal, crypto and misc devices to ReST
Regards,
Mauro
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2 15/24] docs: cpu-freq: convert amd-powernow.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (16 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, linux-pm
- Add a SPDX header;
- Add a document title, based on the original contents of
cpu-freq/index.txt;
- some whitespace fixes and new line breaks;
- Add it to cpu-freq/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../cpu-freq/{amd-powernow.txt => amd-powernow.rst} | 12 ++++++++++--
Documentation/cpu-freq/index.rst | 2 ++
2 files changed, 12 insertions(+), 2 deletions(-)
rename Documentation/cpu-freq/{amd-powernow.txt => amd-powernow.rst} (89%)
diff --git a/Documentation/cpu-freq/amd-powernow.txt b/Documentation/cpu-freq/amd-powernow.rst
similarity index 89%
rename from Documentation/cpu-freq/amd-powernow.txt
rename to Documentation/cpu-freq/amd-powernow.rst
index 254da155fa47..4a53612b62a2 100644
--- a/Documentation/cpu-freq/amd-powernow.txt
+++ b/Documentation/cpu-freq/amd-powernow.rst
@@ -1,3 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=============================
+AMD PowerNow Driver Specifics
+=============================
+
PowerNow! and Cool'n'Quiet are AMD names for frequency
management capabilities in AMD processors. As the hardware
@@ -23,16 +29,18 @@ not supply these tables.
7th Generation: powernow-k7: Athlon, Duron, Geode.
8th Generation: powernow-k8: Athlon, Athlon 64, Opteron, Sempron.
+
Documentation on this functionality in 8th generation processors
is available in the "BIOS and Kernel Developer's Guide", publication
-26094, in chapter 9, available for download from www.amd.com.
+26094, in chapter 9, available for download from www.amd.com.
BIOS supplied data, for powernow-k7 and for powernow-k8, may be
from either the PSB table or from ACPI objects. The ACPI support
is only available if the kernel config sets CONFIG_ACPI_PROCESSOR.
The powernow-k8 driver will attempt to use ACPI if so configured,
and fall back to PST if that fails.
+
The powernow-k7 driver will try to use the PSB support first, and
fall back to ACPI if the PSB support fails. A module parameter,
-acpi_force, is provided to force ACPI support to be used instead
+acpi_force, is provided to force ACPI support to be used instead
of PSB support.
diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
index 1bff3dfddd23..6f7c2a024447 100644
--- a/Documentation/cpu-freq/index.rst
+++ b/Documentation/cpu-freq/index.rst
@@ -14,6 +14,8 @@ Author: Dominik Brodowski <linux@brodo.de>
.. toctree::
:maxdepth: 1
+ amd-powernow
+
Mailing List
------------
There is a CPU frequency changing CVS commit and general list where
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 16/24] docs: cpu-freq: convert core.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (17 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, linux-pm
- Add a SPDX header;
- Adjust the document title, based on the original contents of
cpu-freq/index.txt;
- Use lists where needed;
- Comment out the existing text-only index;
- use ``foo`` to mark a literal expression with asterisk;
- Adjust some title marks;
- Add table markups;
- Add notes markups;
- Some whitespace fixes and new line breaks;
- Add it to cpu-freq/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/cpu-freq/{core.txt => core.rst} | 65 ++++++++++---------
Documentation/cpu-freq/index.rst | 1 +
2 files changed, 34 insertions(+), 32 deletions(-)
rename Documentation/cpu-freq/{core.txt => core.rst} (69%)
diff --git a/Documentation/cpu-freq/core.txt b/Documentation/cpu-freq/core.rst
similarity index 69%
rename from Documentation/cpu-freq/core.txt
rename to Documentation/cpu-freq/core.rst
index ed577d9c154b..33cb90bd1d8f 100644
--- a/Documentation/cpu-freq/core.txt
+++ b/Documentation/cpu-freq/core.rst
@@ -1,31 +1,23 @@
- CPU frequency and voltage scaling code in the Linux(TM) kernel
+.. SPDX-License-Identifier: GPL-2.0
+=============================================================
+General description of the CPUFreq core and CPUFreq notifiers
+=============================================================
- L i n u x C P U F r e q
+Authors:
+ - Dominik Brodowski <linux@brodo.de>
+ - David Kimdon <dwhedon@debian.org>
+ - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+ - Viresh Kumar <viresh.kumar@linaro.org>
- C P U F r e q C o r e
+.. Contents:
-
- Dominik Brodowski <linux@brodo.de>
- David Kimdon <dwhedon@debian.org>
- Rafael J. Wysocki <rafael.j.wysocki@intel.com>
- Viresh Kumar <viresh.kumar@linaro.org>
-
-
-
- Clock scaling allows you to change the clock speed of the CPUs on the
- fly. This is a nice method to save battery power, because the lower
- the clock speed, the less power the CPU consumes.
-
-
-Contents:
----------
-1. CPUFreq core and interfaces
-2. CPUFreq notifiers
-3. CPUFreq Table Generation with Operating Performance Point (OPP)
+ 1. CPUFreq core and interfaces
+ 2. CPUFreq notifiers
+ 3. CPUFreq Table Generation with Operating Performance Point (OPP)
1. General Information
-=======================
+======================
The CPUFreq core code is located in drivers/cpufreq/cpufreq.c. This
cpufreq code offers a standardized interface for the CPUFreq
@@ -63,7 +55,7 @@ The phase is specified in the second argument to the notifier. The phase is
CPUFREQ_CREATE_POLICY when the policy is first created and it is
CPUFREQ_REMOVE_POLICY when the policy is removed.
-The third argument, a void *pointer, points to a struct cpufreq_policy
+The third argument, a ``void *pointer``, points to a struct cpufreq_policy
consisting of several values, including min, max (the lower and upper
frequencies (in kHz) of the new policy).
@@ -80,10 +72,13 @@ CPUFREQ_POSTCHANGE.
The third argument is a struct cpufreq_freqs with the following
values:
-cpu - number of the affected CPU
-old - old frequency
-new - new frequency
-flags - flags of the cpufreq driver
+
+===== ===========================
+cpu number of the affected CPU
+old old frequency
+new new frequency
+flags flags of the cpufreq driver
+===== ===========================
3. CPUFreq Table Generation with Operating Performance Point (OPP)
==================================================================
@@ -94,9 +89,12 @@ dev_pm_opp_init_cpufreq_table -
the OPP layer's internal information about the available frequencies
into a format readily providable to cpufreq.
- WARNING: Do not use this function in interrupt context.
+ .. Warning::
+
+ Do not use this function in interrupt context.
+
+ Example::
- Example:
soc_pm_init()
{
/* Do things */
@@ -106,7 +104,10 @@ dev_pm_opp_init_cpufreq_table -
/* Do other things */
}
- NOTE: This function is available only if CONFIG_CPU_FREQ is enabled in
- addition to CONFIG_PM_OPP.
+ .. note::
-dev_pm_opp_free_cpufreq_table - Free up the table allocated by dev_pm_opp_init_cpufreq_table
+ This function is available only if CONFIG_CPU_FREQ is enabled in
+ addition to CONFIG_PM_OPP.
+
+dev_pm_opp_free_cpufreq_table
+ Free up the table allocated by dev_pm_opp_init_cpufreq_table
diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
index 6f7c2a024447..8babc5a212dd 100644
--- a/Documentation/cpu-freq/index.rst
+++ b/Documentation/cpu-freq/index.rst
@@ -15,6 +15,7 @@ Author: Dominik Brodowski <linux@brodo.de>
:maxdepth: 1
amd-powernow
+ core
Mailing List
------------
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 17/24] docs: cpu-freq: convert cpu-drivers.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (18 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, linux-pm
- Add a SPDX header;
- Add a document title, based on the original contents of
cpu-freq/index.txt;
- Use lists where needed;
- Comment out the existing text-only index;
- Adjust some title marks;
- Add table markups;
- Add notes markups;
- Mark literal blocks as such;
- use ``foo`` for literal texts;
- Some whitespace fixes and new line breaks;
- Add it to cpu-freq/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../{cpu-drivers.txt => cpu-drivers.rst} | 129 +++++++++---------
Documentation/cpu-freq/index.rst | 1 +
2 files changed, 64 insertions(+), 66 deletions(-)
rename Documentation/cpu-freq/{cpu-drivers.txt => cpu-drivers.rst} (72%)
diff --git a/Documentation/cpu-freq/cpu-drivers.txt b/Documentation/cpu-freq/cpu-drivers.rst
similarity index 72%
rename from Documentation/cpu-freq/cpu-drivers.txt
rename to Documentation/cpu-freq/cpu-drivers.rst
index 6e353d00cdc6..a697278ce190 100644
--- a/Documentation/cpu-freq/cpu-drivers.txt
+++ b/Documentation/cpu-freq/cpu-drivers.rst
@@ -1,35 +1,27 @@
- CPU frequency and voltage scaling code in the Linux(TM) kernel
+.. SPDX-License-Identifier: GPL-2.0
+===============================================
+How to Implement a new CPUFreq Processor Driver
+===============================================
- L i n u x C P U F r e q
+Authors:
- C P U D r i v e r s
- - information for developers -
+ - Dominik Brodowski <linux@brodo.de>
+ - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+ - Viresh Kumar <viresh.kumar@linaro.org>
+.. Contents
- Dominik Brodowski <linux@brodo.de>
- Rafael J. Wysocki <rafael.j.wysocki@intel.com>
- Viresh Kumar <viresh.kumar@linaro.org>
-
-
-
- Clock scaling allows you to change the clock speed of the CPUs on the
- fly. This is a nice method to save battery power, because the lower
- the clock speed, the less power the CPU consumes.
-
-
-Contents:
----------
-1. What To Do?
-1.1 Initialization
-1.2 Per-CPU Initialization
-1.3 verify
-1.4 target/target_index or setpolicy?
-1.5 target/target_index
-1.6 setpolicy
-1.7 get_intermediate and target_intermediate
-2. Frequency Table Helpers
+ 1. What To Do?
+ 1.1 Initialization
+ 1.2 Per-CPU Initialization
+ 1.3 verify
+ 1.4 target/target_index or setpolicy?
+ 1.5 target/target_index
+ 1.6 setpolicy
+ 1.7 get_intermediate and target_intermediate
+ 2. Frequency Table Helpers
@@ -49,7 +41,7 @@ function check whether this kernel runs on the right CPU and the right
chipset. If so, register a struct cpufreq_driver with the CPUfreq core
using cpufreq_register_driver()
-What shall this struct cpufreq_driver contain?
+What shall this struct cpufreq_driver contain?
.name - The name of this driver.
@@ -108,37 +100,42 @@ Whenever a new CPU is registered with the device model, or after the
cpufreq driver registers itself, the per-policy initialization function
cpufreq_driver.init is called if no cpufreq policy existed for the CPU.
Note that the .init() and .exit() routines are called only once for the
-policy and not for each CPU managed by the policy. It takes a struct
-cpufreq_policy *policy as argument. What to do now?
+policy and not for each CPU managed by the policy. It takes a ``struct
+cpufreq_policy *policy`` as argument. What to do now?
If necessary, activate the CPUfreq support on your CPU.
Then, the driver must fill in the following values:
-policy->cpuinfo.min_freq _and_
-policy->cpuinfo.max_freq - the minimum and maximum frequency
- (in kHz) which is supported by
- this CPU
-policy->cpuinfo.transition_latency the time it takes on this CPU to
- switch between two frequencies in
- nanoseconds (if appropriate, else
- specify CPUFREQ_ETERNAL)
-
-policy->cur The current operating frequency of
- this CPU (if appropriate)
-policy->min,
-policy->max,
-policy->policy and, if necessary,
-policy->governor must contain the "default policy" for
- this CPU. A few moments later,
- cpufreq_driver.verify and either
- cpufreq_driver.setpolicy or
- cpufreq_driver.target/target_index is called
- with these values.
-policy->cpus Update this with the masks of the
- (online + offline) CPUs that do DVFS
- along with this CPU (i.e. that share
- clock/voltage rails with it).
++-----------------------------------+--------------------------------------+
+|policy->cpuinfo.min_freq _and_ | |
+|policy->cpuinfo.max_freq | the minimum and maximum frequency |
+| | (in kHz) which is supported by |
+| | this CPU |
++-----------------------------------+--------------------------------------+
+|policy->cpuinfo.transition_latency | the time it takes on this CPU to |
+| | switch between two frequencies in |
+| | nanoseconds (if appropriate, else |
+| | specify CPUFREQ_ETERNAL) |
++-----------------------------------+--------------------------------------+
+|policy->cur | The current operating frequency of |
+| | this CPU (if appropriate) |
++-----------------------------------+--------------------------------------+
+|policy->min, | |
+|policy->max, | |
+|policy->policy and, if necessary, | |
+|policy->governor | must contain the "default policy" for|
+| | this CPU. A few moments later, |
+| | cpufreq_driver.verify and either |
+| | cpufreq_driver.setpolicy or |
+| | cpufreq_driver.target/target_index is|
+| | called with these values. |
++-----------------------------------+--------------------------------------+
+|policy->cpus | Update this with the masks of the |
+| | (online + offline) CPUs that do DVFS |
+| | along with this CPU (i.e. that share|
+| | clock/voltage rails with it). |
++-----------------------------------+--------------------------------------+
For setting some of these values (cpuinfo.min[max]_freq, policy->min[max]), the
frequency table helpers might be helpful. See the section 2 for more information
@@ -151,8 +148,8 @@ on them.
When the user decides a new policy (consisting of
"policy,governor,min,max") shall be set, this policy must be validated
so that incompatible values can be corrected. For verifying these
-values cpufreq_verify_within_limits(struct cpufreq_policy *policy,
-unsigned int min_freq, unsigned int max_freq) function might be helpful.
+values cpufreq_verify_within_limits(``struct cpufreq_policy *policy``,
+``unsigned int min_freq``, ``unsigned int max_freq``) function might be helpful.
See section 2 for details on frequency table helpers.
You need to make sure that at least one valid frequency (or operating
@@ -163,7 +160,7 @@ policy->max first, and only if this is no solution, decrease policy->min.
1.4 target or target_index or setpolicy or fast_switch?
-------------------------------------------------------
-Most cpufreq drivers or even most cpu frequency scaling algorithms
+Most cpufreq drivers or even most cpu frequency scaling algorithms
only allow the CPU frequency to be set to predefined fixed values. For
these, you use the ->target(), ->target_index() or ->fast_switch()
callbacks.
@@ -175,8 +172,8 @@ limits on their own. These shall use the ->setpolicy() callback.
1.5. target/target_index
------------------------
-The target_index call has two arguments: struct cpufreq_policy *policy,
-and unsigned int index (into the exposed frequency table).
+The target_index call has two arguments: ``struct cpufreq_policy *policy``,
+and ``unsigned int`` index (into the exposed frequency table).
The CPUfreq driver must set the new frequency when called here. The
actual frequency must be determined by freq_table[index].frequency.
@@ -184,9 +181,9 @@ actual frequency must be determined by freq_table[index].frequency.
It should always restore to earlier frequency (i.e. policy->restore_freq) in
case of errors, even if we switched to intermediate frequency earlier.
-Deprecated:
+Deprecated
----------
-The target call has three arguments: struct cpufreq_policy *policy,
+The target call has three arguments: ``struct cpufreq_policy *policy``,
unsigned int target_frequency, unsigned int relation.
The CPUfreq driver must set the new frequency when called here. The
@@ -210,14 +207,14 @@ Not all drivers are expected to implement it, as sleeping from within
this callback isn't allowed. This callback must be highly optimized to
do switching as fast as possible.
-This function has two arguments: struct cpufreq_policy *policy and
-unsigned int target_frequency.
+This function has two arguments: ``struct cpufreq_policy *policy`` and
+``unsigned int target_frequency``.
1.7 setpolicy
-------------
-The setpolicy call only takes a struct cpufreq_policy *policy as
+The setpolicy call only takes a ``struct cpufreq_policy *policy`` as
argument. You need to set the lower limit of the in-processor or
in-chipset dynamic frequency switching to policy->min, the upper limit
to policy->max, and -if supported- select a performance-oriented
@@ -278,10 +275,10 @@ table.
cpufreq_for_each_valid_entry(pos, table) - iterates over all entries,
excluding CPUFREQ_ENTRY_INVALID frequencies.
-Use arguments "pos" - a cpufreq_frequency_table * as a loop cursor and
-"table" - the cpufreq_frequency_table * you want to iterate over.
+Use arguments "pos" - a ``cpufreq_frequency_table *`` as a loop cursor and
+"table" - the ``cpufreq_frequency_table *`` you want to iterate over.
-For example:
+For example::
struct cpufreq_frequency_table *pos, *driver_freq_table;
diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
index 8babc5a212dd..1ab3fff53956 100644
--- a/Documentation/cpu-freq/index.rst
+++ b/Documentation/cpu-freq/index.rst
@@ -16,6 +16,7 @@ Author: Dominik Brodowski <linux@brodo.de>
amd-powernow
core
+ cpu-drivers
Mailing List
------------
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 18/24] docs: cpu-freq: convert cpufreq-nforce2.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (19 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, linux-pm
- Add a SPDX header;
- Add a document title, based on the original contents of
cpu-freq/index.txt;
- Add table markups;
- Add notes markups;
- Add it to cpu-freq/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
...cpufreq-nforce2.txt => cpufreq-nforce2.rst} | 18 ++++++++++++++----
Documentation/cpu-freq/index.rst | 1 +
2 files changed, 15 insertions(+), 4 deletions(-)
rename Documentation/cpu-freq/{cpufreq-nforce2.txt => cpufreq-nforce2.rst} (55%)
diff --git a/Documentation/cpu-freq/cpufreq-nforce2.txt b/Documentation/cpu-freq/cpufreq-nforce2.rst
similarity index 55%
rename from Documentation/cpu-freq/cpufreq-nforce2.txt
rename to Documentation/cpu-freq/cpufreq-nforce2.rst
index babce1315026..aa0ef768a92e 100644
--- a/Documentation/cpu-freq/cpufreq-nforce2.txt
+++ b/Documentation/cpu-freq/cpufreq-nforce2.rst
@@ -1,3 +1,8 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=================================
+nVidia nForce2 Platform Specifics
+=================================
The cpufreq-nforce2 driver changes the FSB on nVidia nForce2 platforms.
@@ -6,14 +11,19 @@ can be controlled independently from the PCI/AGP clock.
The module has two options:
- fid: multiplier * 10 (for example 8.5 = 85)
- min_fsb: minimum FSB
+ ======= ======================================
+ fid multiplier * 10 (for example 8.5 = 85)
+ min_fsb minimum FSB
+ ======= ======================================
If not set, fid is calculated from the current CPU speed and the FSB.
min_fsb defaults to FSB at boot time - 50 MHz.
-IMPORTANT: The available range is limited downwards!
- Also the minimum available FSB can differ, for systems
+.. Important::
+
+ The available range is limited downwards!
+
+ Also the minimum available FSB can differ, for systems
booting with 200 MHz, 150 should always work.
diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
index 1ab3fff53956..3fa69e6614f6 100644
--- a/Documentation/cpu-freq/index.rst
+++ b/Documentation/cpu-freq/index.rst
@@ -17,6 +17,7 @@ Author: Dominik Brodowski <linux@brodo.de>
amd-powernow
core
cpu-drivers
+ cpufreq-nforce2
Mailing List
------------
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 19/24] docs: cpu-freq: convert cpufreq-stats.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (20 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, linux-pm
- Add a SPDX header;
- Add a document title, based on the original contents of
cpu-freq/index.txt;
- Use lists where needed;
- Comment out the existing text-only index;
- Adjust some title marks;
- Use bold on some places;
- Mark literal blocks as such;
- Some whitespace fixes and new line breaks;
- Add it to cpu-freq/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../{cpufreq-stats.txt => cpufreq-stats.rst} | 121 ++++++++++--------
Documentation/cpu-freq/index.rst | 1 +
2 files changed, 66 insertions(+), 56 deletions(-)
rename Documentation/cpu-freq/{cpufreq-stats.txt => cpufreq-stats.rst} (53%)
diff --git a/Documentation/cpu-freq/cpufreq-stats.txt b/Documentation/cpu-freq/cpufreq-stats.rst
similarity index 53%
rename from Documentation/cpu-freq/cpufreq-stats.txt
rename to Documentation/cpu-freq/cpufreq-stats.rst
index 14378cecb172..9ad695b1c7db 100644
--- a/Documentation/cpu-freq/cpufreq-stats.txt
+++ b/Documentation/cpu-freq/cpufreq-stats.rst
@@ -1,21 +1,23 @@
+.. SPDX-License-Identifier: GPL-2.0
- CPU frequency and voltage scaling statistics in the Linux(TM) kernel
+==========================================
+General Description of sysfs CPUFreq Stats
+==========================================
+information for users
- L i n u x c p u f r e q - s t a t s d r i v e r
- - information for users -
+Author: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
+.. Contents
- Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
-
-Contents
-1. Introduction
-2. Statistics Provided (with example)
-3. Configuring cpufreq-stats
+ 1. Introduction
+ 2. Statistics Provided (with example)
+ 3. Configuring cpufreq-stats
1. Introduction
+===============
cpufreq-stats is a driver that provides CPU frequency statistics for each CPU.
These statistics are provided in /sysfs as a bunch of read_only interfaces. This
@@ -28,8 +30,10 @@ that may be running on your CPU. So, it will work with any cpufreq_driver.
2. Statistics Provided (with example)
+=====================================
cpufreq stats provides following statistics (explained in detail below).
+
- time_in_state
- total_trans
- trans_table
@@ -39,53 +43,57 @@ All the statistics will be from the time the stats driver has been inserted
statistic is done. Obviously, stats driver will not have any information
about the frequency transitions before the stats driver insertion.
---------------------------------------------------------------------------------
-<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # ls -l
-total 0
-drwxr-xr-x 2 root root 0 May 14 16:06 .
-drwxr-xr-x 3 root root 0 May 14 15:58 ..
---w------- 1 root root 4096 May 14 16:06 reset
--r--r--r-- 1 root root 4096 May 14 16:06 time_in_state
--r--r--r-- 1 root root 4096 May 14 16:06 total_trans
--r--r--r-- 1 root root 4096 May 14 16:06 trans_table
---------------------------------------------------------------------------------
+::
+
+ <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # ls -l
+ total 0
+ drwxr-xr-x 2 root root 0 May 14 16:06 .
+ drwxr-xr-x 3 root root 0 May 14 15:58 ..
+ --w------- 1 root root 4096 May 14 16:06 reset
+ -r--r--r-- 1 root root 4096 May 14 16:06 time_in_state
+ -r--r--r-- 1 root root 4096 May 14 16:06 total_trans
+ -r--r--r-- 1 root root 4096 May 14 16:06 trans_table
+
+- **reset**
-- reset
Write-only attribute that can be used to reset the stat counters. This can be
useful for evaluating system behaviour under different governors without the
need for a reboot.
-- time_in_state
+- **time_in_state**
+
This gives the amount of time spent in each of the frequencies supported by
this CPU. The cat output will have "<frequency> <time>" pair in each line, which
will mean this CPU spent <time> usertime units of time at <frequency>. Output
-will have one line for each of the supported frequencies. usertime units here
+will have one line for each of the supported frequencies. usertime units here
is 10mS (similar to other time exported in /proc).
---------------------------------------------------------------------------------
-<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat time_in_state
-3600000 2089
-3400000 136
-3200000 34
-3000000 67
-2800000 172488
---------------------------------------------------------------------------------
-
-
-- total_trans
-This gives the total number of frequency transitions on this CPU. The cat
+::
+
+ <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat time_in_state
+ 3600000 2089
+ 3400000 136
+ 3200000 34
+ 3000000 67
+ 2800000 172488
+
+
+- **total_trans**
+
+This gives the total number of frequency transitions on this CPU. The cat
output will have a single count which is the total number of frequency
transitions.
---------------------------------------------------------------------------------
-<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat total_trans
-20
---------------------------------------------------------------------------------
+::
+
+ <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat total_trans
+ 20
+
+- **trans_table**
-- trans_table
This will give a fine grained information about all the CPU frequency
transitions. The cat output here is a two dimensional matrix, where an entry
-<i,j> (row i, column j) represents the count of number of transitions from
+<i,j> (row i, column j) represents the count of number of transitions from
Freq_i to Freq_j. Freq_i rows and Freq_j columns follow the sorting order in
which the driver has provided the frequency table initially to the cpufreq core
and so can be sorted (ascending or descending) or unsorted. The output here
@@ -95,26 +103,27 @@ readability.
If the transition table is bigger than PAGE_SIZE, reading this will
return an -EFBIG error.
---------------------------------------------------------------------------------
-<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat trans_table
- From : To
- : 3600000 3400000 3200000 3000000 2800000
- 3600000: 0 5 0 0 0
- 3400000: 4 0 2 0 0
- 3200000: 0 1 0 2 0
- 3000000: 0 0 1 0 3
- 2800000: 0 0 0 2 0
---------------------------------------------------------------------------------
+::
+ <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat trans_table
+ From : To
+ : 3600000 3400000 3200000 3000000 2800000
+ 3600000: 0 5 0 0 0
+ 3400000: 4 0 2 0 0
+ 3200000: 0 1 0 2 0
+ 3000000: 0 0 1 0 3
+ 2800000: 0 0 0 2 0
3. Configuring cpufreq-stats
+============================
-To configure cpufreq-stats in your kernel
-Config Main Menu
- Power management options (ACPI, APM) --->
- CPU Frequency scaling --->
- [*] CPU Frequency scaling
- [*] CPU frequency translation statistics
+To configure cpufreq-stats in your kernel::
+
+ Config Main Menu
+ Power management options (ACPI, APM) --->
+ CPU Frequency scaling --->
+ [*] CPU Frequency scaling
+ [*] CPU frequency translation statistics
"CPU Frequency scaling" (CONFIG_CPU_FREQ) should be enabled to configure
diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
index 3fa69e6614f6..d12ef0bb78a5 100644
--- a/Documentation/cpu-freq/index.rst
+++ b/Documentation/cpu-freq/index.rst
@@ -18,6 +18,7 @@ Author: Dominik Brodowski <linux@brodo.de>
core
cpu-drivers
cpufreq-nforce2
+ cpufreq-stats
Mailing List
------------
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 20/24] docs: cpu-freq: convert pcc-cpufreq.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (21 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Rafael J. Wysocki,
Viresh Kumar, linux-pm
- Add a SPDX header;
- Add a document title, based on the original contents of
cpu-freq/index.txt;
- Add copyright symbol;
- Remove a c-like comment, adding the useful info not covered
by the SPDX and document title headers as text;
- Comment out the existing text-only index;
- Mark literal blocks as such;
- Some whitespace fixes and new line breaks;
- Add it to cpu-freq/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/cpu-freq/index.rst | 1 +
.../{pcc-cpufreq.txt => pcc-cpufreq.rst} | 86 ++++++++-----------
2 files changed, 38 insertions(+), 49 deletions(-)
rename Documentation/cpu-freq/{pcc-cpufreq.txt => pcc-cpufreq.rst} (80%)
diff --git a/Documentation/cpu-freq/index.rst b/Documentation/cpu-freq/index.rst
index d12ef0bb78a5..fb2db2eb7eaf 100644
--- a/Documentation/cpu-freq/index.rst
+++ b/Documentation/cpu-freq/index.rst
@@ -19,6 +19,7 @@ Author: Dominik Brodowski <linux@brodo.de>
cpu-drivers
cpufreq-nforce2
cpufreq-stats
+ pcc-cpufreq
Mailing List
------------
diff --git a/Documentation/cpu-freq/pcc-cpufreq.txt b/Documentation/cpu-freq/pcc-cpufreq.rst
similarity index 80%
rename from Documentation/cpu-freq/pcc-cpufreq.txt
rename to Documentation/cpu-freq/pcc-cpufreq.rst
index 9e3c3b33514c..6fd891f757a7 100644
--- a/Documentation/cpu-freq/pcc-cpufreq.txt
+++ b/Documentation/cpu-freq/pcc-cpufreq.rst
@@ -1,45 +1,29 @@
-/*
- * pcc-cpufreq.txt - PCC interface documentation
- *
- * Copyright (C) 2009 Red Hat, Matthew Garrett <mjg@redhat.com>
- * Copyright (C) 2009 Hewlett-Packard Development Company, L.P.
- * Nagananda Chumbalkar <nagananda.chumbalkar@hp.com>
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or NON
- * INFRINGEMENT. See the GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- */
+.. SPDX-License-Identifier: GPL-2.0
+.. include:: <isonum.txt>
+=========================================================
+Processor Clocking Control (PCC) CPUFreq Driver Specifics
+=========================================================
- Processor Clocking Control Driver
- ---------------------------------
+Copyright |copy| 2009 Red Hat, Matthew Garrett <mjg@redhat.com>
-Contents:
----------
-1. Introduction
-1.1 PCC interface
-1.1.1 Get Average Frequency
-1.1.2 Set Desired Frequency
-1.2 Platforms affected
-2. Driver and /sys details
-2.1 scaling_available_frequencies
-2.2 cpuinfo_transition_latency
-2.3 cpuinfo_cur_freq
-2.4 related_cpus
-3. Caveats
+Copyright |copy| 2009 Hewlett-Packard Development Company, L.P.,
+Nagananda Chumbalkar <nagananda.chumbalkar@hp.com>
+
+
+.. Contents:
+
+ 1. Introduction
+ 1.1 PCC interface
+ 1.1.1 Get Average Frequency
+ 1.1.2 Set Desired Frequency
+ 1.2 Platforms affected
+ 2. Driver and /sys details
+ 2.1 scaling_available_frequencies
+ 2.2 cpuinfo_transition_latency
+ 2.3 cpuinfo_cur_freq
+ 2.4 related_cpus
+ 3. Caveats
1. Introduction:
----------------
@@ -140,7 +124,9 @@ Internally, there is no need for the driver to convert the "target" frequency
to a corresponding P-state.
The VERSION number for the driver will be of the format v.xy.ab.
-eg: 1.00.02
+eg::
+
+ 1.00.02
----- --
| |
| -- this will increase with bug fixes/enhancements to the driver
@@ -168,21 +154,21 @@ A) Often cpuinfo_cur_freq will show a value different than what is declared
in the scaling_available_frequencies or scaling_cur_freq, or scaling_max_freq.
This is due to "turbo boost" available on recent Intel processors. If certain
conditions are met the BIOS can achieve a slightly higher speed than requested
-by OSPM. An example:
+by OSPM. An example::
-scaling_cur_freq : 2933000
-cpuinfo_cur_freq : 3196000
+ scaling_cur_freq : 2933000
+ cpuinfo_cur_freq : 3196000
B) There is a round-off error associated with the cpuinfo_cur_freq value.
Since the driver obtains the current frequency as a "percentage" (%) of the
nominal frequency from the BIOS, sometimes, the values displayed by
-scaling_cur_freq and cpuinfo_cur_freq may not match. An example:
+scaling_cur_freq and cpuinfo_cur_freq may not match. An example::
-scaling_cur_freq : 1600000
-cpuinfo_cur_freq : 1583000
+ scaling_cur_freq : 1600000
+ cpuinfo_cur_freq : 1583000
In this example, the nominal frequency is 2933 MHz. The driver obtains the
-current frequency, cpuinfo_cur_freq, as 54% of the nominal frequency:
+current frequency, cpuinfo_cur_freq, as 54% of the nominal frequency::
54% of 2933 MHz = 1583 MHz
@@ -193,8 +179,10 @@ corresponds to the frequency of the P0 P-state.
-----------------
The related_cpus field is identical to affected_cpus.
-affected_cpus : 4
-related_cpus : 4
+::
+
+ affected_cpus : 4
+ related_cpus : 4
Currently, the PCC driver does not evaluate _PSD. The platforms that support
PCC do not implement SW_ALL. So OSPM doesn't need to perform any coordination
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 21/24] docs: powerpc: convert vcpudispatch_stats.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, linuxppc-dev
- Add a SPDX header;
- Use standard markup for document title;
- Adjust identation on lists and add blank lines where
needed;
- Add it to the powerpc index.rst file.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/powerpc/index.rst | 1 +
...ispatch_stats.txt => vcpudispatch_stats.rst} | 17 ++++++++++++-----
2 files changed, 13 insertions(+), 5 deletions(-)
rename Documentation/powerpc/{vcpudispatch_stats.txt => vcpudispatch_stats.rst} (94%)
diff --git a/Documentation/powerpc/index.rst b/Documentation/powerpc/index.rst
index 0d45f0fc8e57..29b90b1b6f20 100644
--- a/Documentation/powerpc/index.rst
+++ b/Documentation/powerpc/index.rst
@@ -30,6 +30,7 @@ powerpc
syscall64-abi
transactional_memory
ultravisor
+ vcpudispatch_stats
.. only:: subproject and html
diff --git a/Documentation/powerpc/vcpudispatch_stats.txt b/Documentation/powerpc/vcpudispatch_stats.rst
similarity index 94%
rename from Documentation/powerpc/vcpudispatch_stats.txt
rename to Documentation/powerpc/vcpudispatch_stats.rst
index e21476bfd78c..5704657a5987 100644
--- a/Documentation/powerpc/vcpudispatch_stats.txt
+++ b/Documentation/powerpc/vcpudispatch_stats.rst
@@ -1,5 +1,8 @@
-VCPU Dispatch Statistics:
-=========================
+.. SPDX-License-Identifier: GPL-2.0
+
+========================
+VCPU Dispatch Statistics
+========================
For Shared Processor LPARs, the POWER Hypervisor maintains a relatively
static mapping of the LPAR processors (vcpus) to physical processor
@@ -20,25 +23,29 @@ The statistics themselves are available by reading the procfs file
a vcpu as represented by the first field, followed by 8 numbers.
The first number corresponds to:
+
1. total vcpu dispatches since the beginning of statistics collection
The next 4 numbers represent vcpu dispatch dispersions:
+
2. number of times this vcpu was dispatched on the same processor as last
time
3. number of times this vcpu was dispatched on a different processor core
as last time, but within the same chip
4. number of times this vcpu was dispatched on a different chip
5. number of times this vcpu was dispatches on a different socket/drawer
-(next numa boundary)
+ (next numa boundary)
The final 3 numbers represent statistics in relation to the home node of
the vcpu:
+
6. number of times this vcpu was dispatched in its home node (chip)
7. number of times this vcpu was dispatched in a different node
8. number of times this vcpu was dispatched in a node further away (numa
-distance)
+ distance)
+
+An example output::
-An example output:
$ sudo cat /proc/powerpc/vcpudispatch_stats
cpu0 6839 4126 2683 30 0 6821 18 0
cpu1 2515 1274 1229 12 0 2509 6 0
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 21/24] docs: powerpc: convert vcpudispatch_stats.txt to ReST
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Jonathan Corbet, Mauro Carvalho Chehab, Paul Mackerras, linuxppc-dev
- Add a SPDX header;
- Use standard markup for document title;
- Adjust identation on lists and add blank lines where
needed;
- Add it to the powerpc index.rst file.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/powerpc/index.rst | 1 +
...ispatch_stats.txt => vcpudispatch_stats.rst} | 17 ++++++++++++-----
2 files changed, 13 insertions(+), 5 deletions(-)
rename Documentation/powerpc/{vcpudispatch_stats.txt => vcpudispatch_stats.rst} (94%)
diff --git a/Documentation/powerpc/index.rst b/Documentation/powerpc/index.rst
index 0d45f0fc8e57..29b90b1b6f20 100644
--- a/Documentation/powerpc/index.rst
+++ b/Documentation/powerpc/index.rst
@@ -30,6 +30,7 @@ powerpc
syscall64-abi
transactional_memory
ultravisor
+ vcpudispatch_stats
.. only:: subproject and html
diff --git a/Documentation/powerpc/vcpudispatch_stats.txt b/Documentation/powerpc/vcpudispatch_stats.rst
similarity index 94%
rename from Documentation/powerpc/vcpudispatch_stats.txt
rename to Documentation/powerpc/vcpudispatch_stats.rst
index e21476bfd78c..5704657a5987 100644
--- a/Documentation/powerpc/vcpudispatch_stats.txt
+++ b/Documentation/powerpc/vcpudispatch_stats.rst
@@ -1,5 +1,8 @@
-VCPU Dispatch Statistics:
-=========================
+.. SPDX-License-Identifier: GPL-2.0
+
+========================
+VCPU Dispatch Statistics
+========================
For Shared Processor LPARs, the POWER Hypervisor maintains a relatively
static mapping of the LPAR processors (vcpus) to physical processor
@@ -20,25 +23,29 @@ The statistics themselves are available by reading the procfs file
a vcpu as represented by the first field, followed by 8 numbers.
The first number corresponds to:
+
1. total vcpu dispatches since the beginning of statistics collection
The next 4 numbers represent vcpu dispatch dispersions:
+
2. number of times this vcpu was dispatched on the same processor as last
time
3. number of times this vcpu was dispatched on a different processor core
as last time, but within the same chip
4. number of times this vcpu was dispatched on a different chip
5. number of times this vcpu was dispatches on a different socket/drawer
-(next numa boundary)
+ (next numa boundary)
The final 3 numbers represent statistics in relation to the home node of
the vcpu:
+
6. number of times this vcpu was dispatched in its home node (chip)
7. number of times this vcpu was dispatched in a different node
8. number of times this vcpu was dispatched in a node further away (numa
-distance)
+ distance)
+
+An example output::
-An example output:
$ sudo cat /proc/powerpc/vcpudispatch_stats
cpu0 6839 4126 2683 30 0 6821 18 0
cpu1 2515 1274 1229 12 0 2509 6 0
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 22/24] docs: sh: convert new-machine.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Yoshinori Sato,
Rich Felker, linux-sh
- Add a SPDX header;
- Adjust document title to follow ReST style;
- Mark literal blocks as such;
- Mark a table as such;
- Add it to sh/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/sh/index.rst | 5 +
.../sh/{new-machine.txt => new-machine.rst} | 193 +++++++++---------
2 files changed, 105 insertions(+), 93 deletions(-)
rename Documentation/sh/{new-machine.txt => new-machine.rst} (73%)
diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst
index bc8db7ba894a..56c08790265d 100644
--- a/Documentation/sh/index.rst
+++ b/Documentation/sh/index.rst
@@ -4,6 +4,11 @@ SuperH Interfaces Guide
:Author: Paul Mundt
+.. toctree::
+ :maxdepth: 1
+
+ new-machine
+
Memory Management
========
diff --git a/Documentation/sh/new-machine.txt b/Documentation/sh/new-machine.rst
similarity index 73%
rename from Documentation/sh/new-machine.txt
rename to Documentation/sh/new-machine.rst
index e0961a66130b..07d69049c220 100644
--- a/Documentation/sh/new-machine.txt
+++ b/Documentation/sh/new-machine.rst
@@ -1,6 +1,8 @@
+.. SPDX-License-Identifier: GPL-2.0
- Adding a new board to LinuxSH
- ================
+==============+Adding a new board to LinuxSH
+==============
Paul Mundt <lethal@linux-sh.org>
@@ -19,65 +21,67 @@ include/asm-sh/. For the new kernel, things are broken out by board type,
companion chip type, and CPU type. Looking at a tree view of this directory
hierarchy looks like the following:
-Board-specific code:
+Board-specific code::
-.
-|-- arch
-| `-- sh
-| `-- boards
-| |-- adx
-| | `-- board-specific files
-| |-- bigsur
-| | `-- board-specific files
-| |
-| ... more boards here ...
-|
-`-- include
- `-- asm-sh
- |-- adx
- | `-- board-specific headers
- |-- bigsur
- | `-- board-specific headers
- |
- .. more boards here ...
+ .
+ |-- arch
+ | `-- sh
+ | `-- boards
+ | |-- adx
+ | | `-- board-specific files
+ | |-- bigsur
+ | | `-- board-specific files
+ | |
+ | ... more boards here ...
+ |
+ `-- include
+ `-- asm-sh
+ |-- adx
+ | `-- board-specific headers
+ |-- bigsur
+ | `-- board-specific headers
+ |
+ .. more boards here ...
-Next, for companion chips:
-.
-`-- arch
- `-- sh
- `-- cchips
- `-- hd6446x
- `-- hd64461
- `-- cchip-specific files
+Next, for companion chips::
+
+ .
+ `-- arch
+ `-- sh
+ `-- cchips
+ `-- hd6446x
+ `-- hd64461
+ `-- cchip-specific files
... and so on. Headers for the companion chips are treated the same way as
board-specific headers. Thus, include/asm-sh/hd64461 is home to all of the
hd64461-specific headers.
-Finally, CPU family support is also abstracted:
-.
-|-- arch
-| `-- sh
-| |-- kernel
-| | `-- cpu
-| | |-- sh2
-| | | `-- SH-2 generic files
-| | |-- sh3
-| | | `-- SH-3 generic files
-| | `-- sh4
-| | `-- SH-4 generic files
-| `-- mm
-| `-- This is also broken out per CPU family, so each family can
-| have their own set of cache/tlb functions.
-|
-`-- include
- `-- asm-sh
- |-- cpu-sh2
- | `-- SH-2 specific headers
- |-- cpu-sh3
- | `-- SH-3 specific headers
- `-- cpu-sh4
- `-- SH-4 specific headers
+Finally, CPU family support is also abstracted::
+
+ .
+ |-- arch
+ | `-- sh
+ | |-- kernel
+ | | `-- cpu
+ | | |-- sh2
+ | | | `-- SH-2 generic files
+ | | |-- sh3
+ | | | `-- SH-3 generic files
+ | | `-- sh4
+ | | `-- SH-4 generic files
+ | `-- mm
+ | `-- This is also broken out per CPU family, so each family can
+ | have their own set of cache/tlb functions.
+ |
+ `-- include
+ `-- asm-sh
+ |-- cpu-sh2
+ | `-- SH-2 specific headers
+ |-- cpu-sh3
+ | `-- SH-3 specific headers
+ `-- cpu-sh4
+ `-- SH-4 specific headers
It should be noted that CPU subtypes are _not_ abstracted. Thus, these still
need to be dealt with by the CPU family specific code.
@@ -110,33 +114,33 @@ arch/sh/boards and the include/asm-sh/ hierarchy. In order to better
explain this, we use some examples for adding an imaginary board. For
setup code, we're required at the very least to provide definitions for
get_system_type() and platform_setup(). For our imaginary board, this
-might look something like:
+might look something like::
-/*
- * arch/sh/boards/vapor/setup.c - Setup code for imaginary board
- */
-#include <linux/init.h>
+ /*
+ * arch/sh/boards/vapor/setup.c - Setup code for imaginary board
+ */
+ #include <linux/init.h>
-const char *get_system_type(void)
-{
- return "FooTech Vaporboard";
-}
+ const char *get_system_type(void)
+ {
+ return "FooTech Vaporboard";
+ }
-int __init platform_setup(void)
-{
- /*
- * If our hardware actually existed, we would do real
- * setup here. Though it's also sane to leave this empty
- * if there's no real init work that has to be done for
- * this board.
- */
+ int __init platform_setup(void)
+ {
+ /*
+ * If our hardware actually existed, we would do real
+ * setup here. Though it's also sane to leave this empty
+ * if there's no real init work that has to be done for
+ * this board.
+ */
- /* Start-up imaginary PCI ... */
+ /* Start-up imaginary PCI ... */
- /* And whatever else ... */
+ /* And whatever else ... */
- return 0;
-}
+ return 0;
+ }
Our new imaginary board will also have to tie into the machvec in order for it
to be of any use.
@@ -172,7 +176,7 @@ sufficient.
vector.
Note that these prototypes are generated automatically by setting
- __IO_PREFIX to something sensible. A typical example would be:
+ __IO_PREFIX to something sensible. A typical example would be::
#define __IO_PREFIX vapor
#include <asm/io_generic.h>
@@ -181,7 +185,7 @@ sufficient.
have a legacy io.h should remove it entirely and switch to the new model.
- Add machine vector definitions to the board's setup.c. At a bare minimum,
- this must be defined as something like:
+ this must be defined as something like::
struct sh_machine_vector mv_vapor __initmv = {
.mv_name = "vapor",
@@ -202,20 +206,20 @@ Large portions of the build system are now entirely dynamic, and merely
require the proper entry here and there in order to get things done.
The first thing to do is to add an entry to arch/sh/Kconfig, under the
-"System type" menu:
+"System type" menu::
-config SH_VAPOR
- bool "Vapor"
- help
- select Vapor if configuring for a FooTech Vaporboard.
+ config SH_VAPOR
+ bool "Vapor"
+ help
+ select Vapor if configuring for a FooTech Vaporboard.
next, this has to be added into arch/sh/Makefile. All boards require a
machdir-y entry in order to be built. This entry needs to be the name of
the board directory as it appears in arch/sh/boards, even if it is in a
sub-directory (in which case, all parent directories below arch/sh/boards/
-need to be listed). For our new board, this entry can look like:
+need to be listed). For our new board, this entry can look like::
-machdir-$(CONFIG_SH_VAPOR) += vapor
+ machdir-$(CONFIG_SH_VAPOR) += vapor
provided that we've placed everything in the arch/sh/boards/vapor/ directory.
@@ -230,7 +234,7 @@ This is done by adding an entry to the end of the arch/sh/tools/mach-types
list. The method for doing this is self explanatory, and so we won't waste
space restating it here. After this is done, you will be able to use
implicit checks for your board if you need this somewhere throughout the
-common code, such as:
+common code, such as::
/* Make sure we're on the FooTech Vaporboard */
if (!mach_is_vapor())
@@ -253,16 +257,19 @@ build target, and it will be implicitly listed as such in the help text.
Looking at the 'make help' output, you should now see something like:
Architecture specific targets (sh):
- zImage - Compressed kernel image (arch/sh/boot/zImage)
- adx_defconfig - Build for adx
- cqreek_defconfig - Build for cqreek
- dreamcast_defconfig - Build for dreamcast
-...
- vapor_defconfig - Build for vapor
-which then allows you to do:
+ ============ ======================+ zImage Compressed kernel image (arch/sh/boot/zImage)
+ adx_defconfig Build for adx
+ cqreek_defconfig Build for cqreek
+ dreamcast_defconfig Build for dreamcast
+ ...
+ vapor_defconfig Build for vapor
+ ============ ======================
-$ make ARCH=sh CROSS_COMPILE=sh4-linux- vapor_defconfig vmlinux
+which then allows you to do::
+
+ $ make ARCH=sh CROSS_COMPILE=sh4-linux- vapor_defconfig vmlinux
which will in turn copy the defconfig for this board, run it through
oldconfig (prompting you for any new options since the time of creation),
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 22/24] docs: sh: convert new-machine.txt to ReST
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Yoshinori Sato,
Rich Felker, linux-sh
- Add a SPDX header;
- Adjust document title to follow ReST style;
- Mark literal blocks as such;
- Mark a table as such;
- Add it to sh/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/sh/index.rst | 5 +
.../sh/{new-machine.txt => new-machine.rst} | 193 +++++++++---------
2 files changed, 105 insertions(+), 93 deletions(-)
rename Documentation/sh/{new-machine.txt => new-machine.rst} (73%)
diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst
index bc8db7ba894a..56c08790265d 100644
--- a/Documentation/sh/index.rst
+++ b/Documentation/sh/index.rst
@@ -4,6 +4,11 @@ SuperH Interfaces Guide
:Author: Paul Mundt
+.. toctree::
+ :maxdepth: 1
+
+ new-machine
+
Memory Management
=================
diff --git a/Documentation/sh/new-machine.txt b/Documentation/sh/new-machine.rst
similarity index 73%
rename from Documentation/sh/new-machine.txt
rename to Documentation/sh/new-machine.rst
index e0961a66130b..07d69049c220 100644
--- a/Documentation/sh/new-machine.txt
+++ b/Documentation/sh/new-machine.rst
@@ -1,6 +1,8 @@
+.. SPDX-License-Identifier: GPL-2.0
- Adding a new board to LinuxSH
- ================================
+=============================
+Adding a new board to LinuxSH
+=============================
Paul Mundt <lethal@linux-sh.org>
@@ -19,65 +21,67 @@ include/asm-sh/. For the new kernel, things are broken out by board type,
companion chip type, and CPU type. Looking at a tree view of this directory
hierarchy looks like the following:
-Board-specific code:
+Board-specific code::
-.
-|-- arch
-| `-- sh
-| `-- boards
-| |-- adx
-| | `-- board-specific files
-| |-- bigsur
-| | `-- board-specific files
-| |
-| ... more boards here ...
-|
-`-- include
- `-- asm-sh
- |-- adx
- | `-- board-specific headers
- |-- bigsur
- | `-- board-specific headers
- |
- .. more boards here ...
+ .
+ |-- arch
+ | `-- sh
+ | `-- boards
+ | |-- adx
+ | | `-- board-specific files
+ | |-- bigsur
+ | | `-- board-specific files
+ | |
+ | ... more boards here ...
+ |
+ `-- include
+ `-- asm-sh
+ |-- adx
+ | `-- board-specific headers
+ |-- bigsur
+ | `-- board-specific headers
+ |
+ .. more boards here ...
-Next, for companion chips:
-.
-`-- arch
- `-- sh
- `-- cchips
- `-- hd6446x
- `-- hd64461
- `-- cchip-specific files
+Next, for companion chips::
+
+ .
+ `-- arch
+ `-- sh
+ `-- cchips
+ `-- hd6446x
+ `-- hd64461
+ `-- cchip-specific files
... and so on. Headers for the companion chips are treated the same way as
board-specific headers. Thus, include/asm-sh/hd64461 is home to all of the
hd64461-specific headers.
-Finally, CPU family support is also abstracted:
-.
-|-- arch
-| `-- sh
-| |-- kernel
-| | `-- cpu
-| | |-- sh2
-| | | `-- SH-2 generic files
-| | |-- sh3
-| | | `-- SH-3 generic files
-| | `-- sh4
-| | `-- SH-4 generic files
-| `-- mm
-| `-- This is also broken out per CPU family, so each family can
-| have their own set of cache/tlb functions.
-|
-`-- include
- `-- asm-sh
- |-- cpu-sh2
- | `-- SH-2 specific headers
- |-- cpu-sh3
- | `-- SH-3 specific headers
- `-- cpu-sh4
- `-- SH-4 specific headers
+Finally, CPU family support is also abstracted::
+
+ .
+ |-- arch
+ | `-- sh
+ | |-- kernel
+ | | `-- cpu
+ | | |-- sh2
+ | | | `-- SH-2 generic files
+ | | |-- sh3
+ | | | `-- SH-3 generic files
+ | | `-- sh4
+ | | `-- SH-4 generic files
+ | `-- mm
+ | `-- This is also broken out per CPU family, so each family can
+ | have their own set of cache/tlb functions.
+ |
+ `-- include
+ `-- asm-sh
+ |-- cpu-sh2
+ | `-- SH-2 specific headers
+ |-- cpu-sh3
+ | `-- SH-3 specific headers
+ `-- cpu-sh4
+ `-- SH-4 specific headers
It should be noted that CPU subtypes are _not_ abstracted. Thus, these still
need to be dealt with by the CPU family specific code.
@@ -110,33 +114,33 @@ arch/sh/boards and the include/asm-sh/ hierarchy. In order to better
explain this, we use some examples for adding an imaginary board. For
setup code, we're required at the very least to provide definitions for
get_system_type() and platform_setup(). For our imaginary board, this
-might look something like:
+might look something like::
-/*
- * arch/sh/boards/vapor/setup.c - Setup code for imaginary board
- */
-#include <linux/init.h>
+ /*
+ * arch/sh/boards/vapor/setup.c - Setup code for imaginary board
+ */
+ #include <linux/init.h>
-const char *get_system_type(void)
-{
- return "FooTech Vaporboard";
-}
+ const char *get_system_type(void)
+ {
+ return "FooTech Vaporboard";
+ }
-int __init platform_setup(void)
-{
- /*
- * If our hardware actually existed, we would do real
- * setup here. Though it's also sane to leave this empty
- * if there's no real init work that has to be done for
- * this board.
- */
+ int __init platform_setup(void)
+ {
+ /*
+ * If our hardware actually existed, we would do real
+ * setup here. Though it's also sane to leave this empty
+ * if there's no real init work that has to be done for
+ * this board.
+ */
- /* Start-up imaginary PCI ... */
+ /* Start-up imaginary PCI ... */
- /* And whatever else ... */
+ /* And whatever else ... */
- return 0;
-}
+ return 0;
+ }
Our new imaginary board will also have to tie into the machvec in order for it
to be of any use.
@@ -172,7 +176,7 @@ sufficient.
vector.
Note that these prototypes are generated automatically by setting
- __IO_PREFIX to something sensible. A typical example would be:
+ __IO_PREFIX to something sensible. A typical example would be::
#define __IO_PREFIX vapor
#include <asm/io_generic.h>
@@ -181,7 +185,7 @@ sufficient.
have a legacy io.h should remove it entirely and switch to the new model.
- Add machine vector definitions to the board's setup.c. At a bare minimum,
- this must be defined as something like:
+ this must be defined as something like::
struct sh_machine_vector mv_vapor __initmv = {
.mv_name = "vapor",
@@ -202,20 +206,20 @@ Large portions of the build system are now entirely dynamic, and merely
require the proper entry here and there in order to get things done.
The first thing to do is to add an entry to arch/sh/Kconfig, under the
-"System type" menu:
+"System type" menu::
-config SH_VAPOR
- bool "Vapor"
- help
- select Vapor if configuring for a FooTech Vaporboard.
+ config SH_VAPOR
+ bool "Vapor"
+ help
+ select Vapor if configuring for a FooTech Vaporboard.
next, this has to be added into arch/sh/Makefile. All boards require a
machdir-y entry in order to be built. This entry needs to be the name of
the board directory as it appears in arch/sh/boards, even if it is in a
sub-directory (in which case, all parent directories below arch/sh/boards/
-need to be listed). For our new board, this entry can look like:
+need to be listed). For our new board, this entry can look like::
-machdir-$(CONFIG_SH_VAPOR) += vapor
+ machdir-$(CONFIG_SH_VAPOR) += vapor
provided that we've placed everything in the arch/sh/boards/vapor/ directory.
@@ -230,7 +234,7 @@ This is done by adding an entry to the end of the arch/sh/tools/mach-types
list. The method for doing this is self explanatory, and so we won't waste
space restating it here. After this is done, you will be able to use
implicit checks for your board if you need this somewhere throughout the
-common code, such as:
+common code, such as::
/* Make sure we're on the FooTech Vaporboard */
if (!mach_is_vapor())
@@ -253,16 +257,19 @@ build target, and it will be implicitly listed as such in the help text.
Looking at the 'make help' output, you should now see something like:
Architecture specific targets (sh):
- zImage - Compressed kernel image (arch/sh/boot/zImage)
- adx_defconfig - Build for adx
- cqreek_defconfig - Build for cqreek
- dreamcast_defconfig - Build for dreamcast
-...
- vapor_defconfig - Build for vapor
-which then allows you to do:
+ ======================= =============================================
+ zImage Compressed kernel image (arch/sh/boot/zImage)
+ adx_defconfig Build for adx
+ cqreek_defconfig Build for cqreek
+ dreamcast_defconfig Build for dreamcast
+ ...
+ vapor_defconfig Build for vapor
+ ======================= =============================================
-$ make ARCH=sh CROSS_COMPILE=sh4-linux- vapor_defconfig vmlinux
+which then allows you to do::
+
+ $ make ARCH=sh CROSS_COMPILE=sh4-linux- vapor_defconfig vmlinux
which will in turn copy the defconfig for this board, run it through
oldconfig (prompting you for any new options since the time of creation),
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 23/24] docs: sh: convert register-banks.txt to ReST
2020-02-17 16:20 ` Mauro Carvalho Chehab
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Yoshinori Sato,
Rich Felker, linux-sh
- Add a SPDX header;
- Adjust document title to follow ReST style;
- Add blank lines to make ReST markup happy
- Add it to sh/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/sh/index.rst | 1 +
.../sh/{register-banks.txt => register-banks.rst} | 12 ++++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
rename Documentation/sh/{register-banks.txt => register-banks.rst} (88%)
diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst
index 56c08790265d..580f3b17e841 100644
--- a/Documentation/sh/index.rst
+++ b/Documentation/sh/index.rst
@@ -8,6 +8,7 @@ SuperH Interfaces Guide
:maxdepth: 1
new-machine
+ register-banks
Memory Management
========diff --git a/Documentation/sh/register-banks.txt b/Documentation/sh/register-banks.rst
similarity index 88%
rename from Documentation/sh/register-banks.txt
rename to Documentation/sh/register-banks.rst
index a6719f2f6594..2f51212043f4 100644
--- a/Documentation/sh/register-banks.txt
+++ b/Documentation/sh/register-banks.rst
@@ -1,5 +1,8 @@
- Notes on register bank usage in the kernel
- =====================
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================
+Notes on register bank usage in the kernel
+=====================
Introduction
------------
@@ -23,11 +26,16 @@ Presently the kernel uses several of these registers.
- r0_bank, r1_bank (referenced as k0 and k1, used for scratch
registers when doing exception handling).
+
- r2_bank (used to track the EXPEVT/INTEVT code)
+
- Used by do_IRQ() and friends for doing irq mapping based off
of the interrupt exception vector jump table offset
+
- r6_bank (global interrupt mask)
+
- The SR.IMASK interrupt handler makes use of this to set the
interrupt priority level (used by local_irq_enable())
+
- r7_bank (current)
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2 23/24] docs: sh: convert register-banks.txt to ReST
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Jonathan Corbet, Yoshinori Sato,
Rich Felker, linux-sh
- Add a SPDX header;
- Adjust document title to follow ReST style;
- Add blank lines to make ReST markup happy
- Add it to sh/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/sh/index.rst | 1 +
.../sh/{register-banks.txt => register-banks.rst} | 12 ++++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
rename Documentation/sh/{register-banks.txt => register-banks.rst} (88%)
diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst
index 56c08790265d..580f3b17e841 100644
--- a/Documentation/sh/index.rst
+++ b/Documentation/sh/index.rst
@@ -8,6 +8,7 @@ SuperH Interfaces Guide
:maxdepth: 1
new-machine
+ register-banks
Memory Management
=================
diff --git a/Documentation/sh/register-banks.txt b/Documentation/sh/register-banks.rst
similarity index 88%
rename from Documentation/sh/register-banks.txt
rename to Documentation/sh/register-banks.rst
index a6719f2f6594..2f51212043f4 100644
--- a/Documentation/sh/register-banks.txt
+++ b/Documentation/sh/register-banks.rst
@@ -1,5 +1,8 @@
- Notes on register bank usage in the kernel
- ==========================================
+.. SPDX-License-Identifier: GPL-2.0
+
+==========================================
+Notes on register bank usage in the kernel
+==========================================
Introduction
------------
@@ -23,11 +26,16 @@ Presently the kernel uses several of these registers.
- r0_bank, r1_bank (referenced as k0 and k1, used for scratch
registers when doing exception handling).
+
- r2_bank (used to track the EXPEVT/INTEVT code)
+
- Used by do_IRQ() and friends for doing irq mapping based off
of the interrupt exception vector jump table offset
+
- r6_bank (global interrupt mask)
+
- The SR.IMASK interrupt handler makes use of this to set the
interrupt priority level (used by local_irq_enable())
+
- r7_bank (current)
--
2.24.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 24/24] docs: trace: ring-buffer-design.txt: convert to ReST format
2020-02-17 16:20 ` Mauro Carvalho Chehab
` (25 preceding siblings ...)
(?)
@ 2020-02-17 16:20 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 43+ messages in thread
From: Mauro Carvalho Chehab @ 2020-02-17 16:20 UTC (permalink / raw)
To: Linux Doc Mailing List; +Cc: Mauro Carvalho Chehab, Jonathan Corbet
- Just like some media documents, this file is dual licensed
with GPL and GFDL. As right now the GFDL SPDX definition is
bogus (as it doesn't tell anything about invariant parts),
let's not use SPDX here. Let's use, instead, the same test
as we have on media.
- Convert title to ReST format;
- use :field: markup;
- Proper mark literal blocks as such;
- Add it to trace/index.rst file.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
Documentation/trace/index.rst | 1 +
...ffer-design.txt => ring-buffer-design.rst} | 802 ++++++++++--------
2 files changed, 428 insertions(+), 375 deletions(-)
rename Documentation/trace/{ring-buffer-design.txt => ring-buffer-design.rst} (55%)
diff --git a/Documentation/trace/index.rst b/Documentation/trace/index.rst
index fa9e1c730f6a..7d83156c9ac1 100644
--- a/Documentation/trace/index.rst
+++ b/Documentation/trace/index.rst
@@ -22,6 +22,7 @@ Linux Tracing Technologies
boottime-trace
hwlat_detector
intel_th
+ ring-buffer-design
stm
sys-t
coresight/index
diff --git a/Documentation/trace/ring-buffer-design.txt b/Documentation/trace/ring-buffer-design.rst
similarity index 55%
rename from Documentation/trace/ring-buffer-design.txt
rename to Documentation/trace/ring-buffer-design.rst
index 2d53c6f25b91..7e3e75105cb6 100644
--- a/Documentation/trace/ring-buffer-design.txt
+++ b/Documentation/trace/ring-buffer-design.rst
@@ -1,11 +1,39 @@
- Lockless Ring Buffer Design
- ===========================
+.. This file is dual-licensed: you can use it either under the terms
+.. of the GPL 2.0 or the GFDL 1.2+ license, at your option. Note that this
+.. dual licensing only applies to this file, and not this project as a
+.. whole.
+..
+.. a) This file is free software; you can redistribute it and/or
+.. modify it under the terms of the GNU General Public License as
+.. published by the Free Software Foundation version 2 of
+.. the License.
+..
+.. This file is distributed in the hope that it will be useful,
+.. but WITHOUT ANY WARRANTY; without even the implied warranty of
+.. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+.. GNU General Public License for more details.
+..
+.. Or, alternatively,
+..
+.. b) Permission is granted to copy, distribute and/or modify this
+.. document under the terms of the GNU Free Documentation License,
+.. Version 1.1 or any later version published by the Free Software
+.. Foundation, with no Invariant Sections, no Front-Cover Texts
+.. and no Back-Cover Texts. A copy of the license is included at
+.. Documentation/media/uapi/fdl-appendix.rst.
+..
+.. TODO: replace it to GPL-2.0 OR GFDL-1.2-or-later WITH no-invariant-sections
+
+===========================
+Lockless Ring Buffer Design
+===========================
Copyright 2009 Red Hat Inc.
- Author: Steven Rostedt <srostedt@redhat.com>
- License: The GNU Free Documentation License, Version 1.2
- (dual licensed under the GPL v2)
-Reviewers: Mathieu Desnoyers, Huang Ying, Hidetoshi Seto,
+
+:Author: Steven Rostedt <srostedt@redhat.com>
+:License: The GNU Free Documentation License, Version 1.2
+ (dual licensed under the GPL v2)
+:Reviewers: Mathieu Desnoyers, Huang Ying, Hidetoshi Seto,
and Frederic Weisbecker.
@@ -14,37 +42,50 @@ Written for: 2.6.31
Terminology used in this Document
---------------------------------
-tail - where new writes happen in the ring buffer.
+tail
+ - where new writes happen in the ring buffer.
-head - where new reads happen in the ring buffer.
+head
+ - where new reads happen in the ring buffer.
-producer - the task that writes into the ring buffer (same as writer)
+producer
+ - the task that writes into the ring buffer (same as writer)
-writer - same as producer
+writer
+ - same as producer
-consumer - the task that reads from the buffer (same as reader)
+consumer
+ - the task that reads from the buffer (same as reader)
-reader - same as consumer.
+reader
+ - same as consumer.
-reader_page - A page outside the ring buffer used solely (for the most part)
- by the reader.
+reader_page
+ - A page outside the ring buffer used solely (for the most part)
+ by the reader.
-head_page - a pointer to the page that the reader will use next
+head_page
+ - a pointer to the page that the reader will use next
-tail_page - a pointer to the page that will be written to next
+tail_page
+ - a pointer to the page that will be written to next
-commit_page - a pointer to the page with the last finished non-nested write.
+commit_page
+ - a pointer to the page with the last finished non-nested write.
-cmpxchg - hardware-assisted atomic transaction that performs the following:
+cmpxchg
+ - hardware-assisted atomic transaction that performs the following::
- A = B if previous A == C
+ A = B if previous A == C
- R = cmpxchg(A, C, B) is saying that we replace A with B if and only if
- current A is equal to C, and we put the old (current) A into R
+ R = cmpxchg(A, C, B) is saying that we replace A with B if and only
+ if current A is equal to C, and we put the old (current)
+ A into R
- R gets the previous A regardless if A is updated with B or not.
+ R gets the previous A regardless if A is updated with B or not.
- To see if the update was successful a compare of R == C may be used.
+ To see if the update was successful a compare of ``R == C``
+ may be used.
The Generic Ring Buffer
-----------------------
@@ -64,7 +105,7 @@ No two writers can write at the same time (on the same per-cpu buffer),
but a writer may interrupt another writer, but it must finish writing
before the previous writer may continue. This is very important to the
algorithm. The writers act like a "stack". The way interrupts works
-enforces this behavior.
+enforces this behavior::
writer1 start
@@ -115,6 +156,8 @@ A sample of how the reader page is swapped: Note this does not
show the head page in the buffer, it is for demonstrating a swap
only.
+::
+
+------+
|reader| RING BUFFER
|page |
@@ -172,21 +215,22 @@ only.
It is possible that the page swapped is the commit page and the tail page,
if what is in the ring buffer is less than what is held in a buffer page.
+::
- reader page commit page tail page
- | | |
- v | |
- +---+ | |
- | |<----------+ |
- | |<------------------------+
- | |------+
- +---+ |
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ reader page commit page tail page
+ | | |
+ v | |
+ +---+ | |
+ | |<----------+ |
+ | |<------------------------+
+ | |------+
+ +---+ |
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
This case is still valid for this algorithm.
When the writer leaves the page, it simply goes into the ring buffer
@@ -196,15 +240,19 @@ buffer.
The main pointers:
- reader page - The page used solely by the reader and is not part
- of the ring buffer (may be swapped in)
+ reader page
+ - The page used solely by the reader and is not part
+ of the ring buffer (may be swapped in)
- head page - the next page in the ring buffer that will be swapped
+ head page
+ - the next page in the ring buffer that will be swapped
with the reader page.
- tail page - the page where the next write will take place.
+ tail page
+ - the page where the next write will take place.
- commit page - the page that last finished a write.
+ commit page
+ - the page that last finished a write.
The commit page only is updated by the outermost writer in the
writer stack. A writer that preempts another writer will not move the
@@ -219,7 +267,7 @@ transaction. If another write happens it must finish before continuing
with the previous write.
- Write reserve:
+ Write reserve::
Buffer page
+---------+
@@ -230,7 +278,7 @@ with the previous write.
| empty |
+---------+
- Write commit:
+ Write commit::
Buffer page
+---------+
@@ -242,7 +290,7 @@ with the previous write.
+---------+
- If a write happens after the first reserve:
+ If a write happens after the first reserve::
Buffer page
+---------+
@@ -253,7 +301,7 @@ with the previous write.
|reserved |
+---------+ <--- tail pointer
- After second writer commits:
+ After second writer commits::
Buffer page
@@ -266,7 +314,7 @@ with the previous write.
|commit |
+---------+ <--- tail pointer
- When the first writer commits:
+ When the first writer commits::
Buffer page
+---------+
@@ -292,21 +340,22 @@ be several pages ahead. If the tail page catches up to the commit
page then no more writes may take place (regardless of the mode
of the ring buffer: overwrite and produce/consumer).
-The order of pages is:
+The order of pages is::
head page
commit page
tail page
-Possible scenario:
- tail page
- head page commit page |
- | | |
- v v v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+Possible scenario::
+
+ tail page
+ head page commit page |
+ | | |
+ v v v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
There is a special case that the head page is after either the commit page
and possibly the tail page. That is when the commit (and tail) page has been
@@ -315,24 +364,25 @@ part of the ring buffer, but the reader page is not. Whenever there
has been less than a full page that has been committed inside the ring buffer,
and a reader swaps out a page, it will be swapping out the commit page.
+::
- reader page commit page tail page
- | | |
- v | |
- +---+ | |
- | |<----------+ |
- | |<------------------------+
- | |------+
- +---+ |
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
- ^
- |
- head page
+ reader page commit page tail page
+ | | |
+ v | |
+ +---+ | |
+ | |<----------+ |
+ | |<------------------------+
+ | |------+
+ +---+ |
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
+ ^
+ |
+ head page
In this case, the head page will not move when the tail and commit
@@ -347,42 +397,42 @@ When the tail meets the head page, if the buffer is in overwrite mode,
the head page will be pushed ahead one. If the buffer is in producer/consumer
mode, the write will fail.
-Overwrite mode:
+Overwrite mode::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
- ^
- |
- head page
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
+ ^
+ |
+ head page
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
- ^
- |
- head page
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
+ ^
+ |
+ head page
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
- ^
- |
- head page
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
+ ^
+ |
+ head page
Note, the reader page will still point to the previous head page.
But when a swap takes place, it will use the most recent head page.
@@ -397,7 +447,7 @@ State flags are placed inside the pointer to the page. To do this,
each page must be aligned in memory by 4 bytes. This will allow the 2
least significant bits of the address to be used as flags, since
they will always be zero for the address. To get the address,
-simply mask out the flags.
+simply mask out the flags::
MASK = ~3
@@ -405,24 +455,27 @@ simply mask out the flags.
Two flags will be kept by these two bits:
- HEADER - the page being pointed to is a head page
+ HEADER
+ - the page being pointed to is a head page
- UPDATE - the page being pointed to is being updated by a writer
+ UPDATE
+ - the page being pointed to is being updated by a writer
and was or is about to be a head page.
+::
- reader page
- |
- v
- +---+
- | |------+
- +---+ |
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-H->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ reader page
+ |
+ v
+ +---+
+ | |------+
+ +---+ |
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-H->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
The above pointer "-H->" would have the HEADER flag set. That is
@@ -430,24 +483,24 @@ the next page is the next page to be swapped out by the reader.
This pointer means the next page is the head page.
When the tail page meets the head pointer, it will use cmpxchg to
-change the pointer to the UPDATE state:
+change the pointer to the UPDATE state::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-H->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-H->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
"-U->" represents a pointer in the UPDATE state.
@@ -462,7 +515,7 @@ head page does not have the HEADER flag set, the compare will fail
and the reader will need to look for the new head page and try again.
Note, the flags UPDATE and HEADER are never set at the same time.
-The reader swaps the reader page as follows:
+The reader swaps the reader page as follows::
+------+
|reader| RING BUFFER
@@ -477,7 +530,7 @@ The reader swaps the reader page as follows:
+-----H-------------+
The reader sets the reader page next pointer as HEADER to the page after
-the head page.
+the head page::
+------+
@@ -495,7 +548,7 @@ the head page.
It does a cmpxchg with the pointer to the previous head page to make it
point to the reader page. Note that the new pointer does not have the HEADER
-flag set. This action atomically moves the head page forward.
+flag set. This action atomically moves the head page forward::
+------+
|reader| RING BUFFER
@@ -511,7 +564,7 @@ flag set. This action atomically moves the head page forward.
+------------------------------------+
After the new head page is set, the previous pointer of the head page is
-updated to the reader page.
+updated to the reader page::
+------+
|reader| RING BUFFER
@@ -548,7 +601,7 @@ prev pointers may not.
Note, the way to determine a reader page is simply by examining the previous
pointer of the page. If the next pointer of the previous page does not
-point back to the original page, then the original page is a reader page:
+point back to the original page, then the original page is a reader page::
+--------+
@@ -572,54 +625,54 @@ not be able to swap the head page from the buffer, nor will it be able to
move the head page, until the writer is finished with the move.
This eliminates any races that the reader can have on the writer. The reader
-must spin, and this is why the reader cannot preempt the writer.
+must spin, and this is why the reader cannot preempt the writer::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-H->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-H->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
-The following page will be made into the new head page.
+The following page will be made into the new head page::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
After the new head page has been set, we can set the old head page
-pointer back to NORMAL.
+pointer back to NORMAL::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
-After the head page has been moved, the tail page may now move forward.
+After the head page has been moved, the tail page may now move forward::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
The above are the trivial updates. Now for the more complex scenarios.
@@ -630,26 +683,26 @@ tail page may make it all the way around the buffer and meet the commit
page. At this time, we must start dropping writes (usually with some kind
of warning to the user). But what happens if the commit was still on the
reader page? The commit page is not part of the ring buffer. The tail page
-must account for this.
+must account for this::
- reader page commit page
- | |
- v |
- +---+ |
- | |<----------+
- | |
- | |------+
- +---+ |
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-H->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
- ^
- |
- tail page
+ reader page commit page
+ | |
+ v |
+ +---+ |
+ | |<----------+
+ | |
+ | |------+
+ +---+ |
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-H->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
+ ^
+ |
+ tail page
If the tail page were to simply push the head page forward, the commit when
leaving the reader page would not be pointing to the correct page.
@@ -676,7 +729,7 @@ the head page if the head page is the next page. If the head page
is not the next page, the tail page is simply updated with a cmpxchg.
Only writers move the tail page. This must be done atomically to protect
-against nested writers.
+against nested writers::
temp_page = tail_page
next_page = temp_page->next
@@ -684,54 +737,54 @@ against nested writers.
The above will update the tail page if it is still pointing to the expected
page. If this fails, a nested write pushed it forward, the current write
-does not need to push it.
+does not need to push it::
- temp page
- |
- v
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ temp page
+ |
+ v
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
-Nested write comes in and moves the tail page forward:
+Nested write comes in and moves the tail page forward::
- tail page (moved by nested writer)
- temp page |
- | |
- v v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page (moved by nested writer)
+ temp page |
+ | |
+ v v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
The above would fail the cmpxchg, but since the tail page has already
been moved forward, the writer will just try again to reserve storage
on the new tail page.
-But the moving of the head page is a bit more complex.
+But the moving of the head page is a bit more complex::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-H->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-H->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
-The write converts the head page pointer to UPDATE.
+The write converts the head page pointer to UPDATE::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
But if a nested writer preempts here, it will see that the next
page is a head page, but it is also nested. It will detect that
@@ -739,217 +792,216 @@ it is nested and will save that information. The detection is the
fact that it sees the UPDATE flag instead of a HEADER or NORMAL
pointer.
-The nested writer will set the new head page pointer.
+The nested writer will set the new head page pointer::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
But it will not reset the update back to normal. Only the writer
that converted a pointer from HEAD to UPDATE will convert it back
-to NORMAL.
+to NORMAL::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
After the nested writer finishes, the outermost writer will convert
-the UPDATE pointer to NORMAL.
+the UPDATE pointer to NORMAL::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
It can be even more complex if several nested writes came in and moved
-the tail page ahead several pages:
+the tail page ahead several pages::
-(first writer)
+ (first writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-H->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-H->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
-The write converts the head page pointer to UPDATE.
+The write converts the head page pointer to UPDATE::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
Next writer comes in, and sees the update and sets up the new
-head page.
+head page::
-(second writer)
+ (second writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
The nested writer moves the tail page forward. But does not set the old
-update page to NORMAL because it is not the outermost writer.
+update page to NORMAL because it is not the outermost writer::
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-H->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-H->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
Another writer preempts and sees the page after the tail page is a head page.
-It changes it from HEAD to UPDATE.
+It changes it from HEAD to UPDATE::
-(third writer)
+ (third writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-U->| |--->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-U->| |--->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
-The writer will move the head page forward:
+The writer will move the head page forward::
-(third writer)
+ (third writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-U->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-U->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
But now that the third writer did change the HEAD flag to UPDATE it
-will convert it to normal:
+will convert it to normal::
-(third writer)
+ (third writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
-Then it will move the tail page, and return back to the second writer.
+Then it will move the tail page, and return back to the second writer::
-(second writer)
+ (second writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
The second writer will fail to move the tail page because it was already
moved, so it will try again and add its data to the new tail page.
-It will return to the first writer.
+It will return to the first writer::
-(first writer)
+ (first writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
The first writer cannot know atomically if the tail page moved
while it updates the HEAD page. It will then update the head page to
-what it thinks is the new head page.
+what it thinks is the new head page::
-(first writer)
+ (first writer)
- tail page
- |
- v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-H->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ tail page
+ |
+ v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-H->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
Since the cmpxchg returns the old value of the pointer the first writer
will see it succeeded in updating the pointer from NORMAL to HEAD.
But as we can see, this is not good enough. It must also check to see
-if the tail page is either where it use to be or on the next page:
+if the tail page is either where it use to be or on the next page::
-(first writer)
+ (first writer)
- A B tail page
- | | |
- v v v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |-H->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ A B tail page
+ | | |
+ v v v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |-H->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
If tail page != A and tail page != B, then it must reset the pointer
back to NORMAL. The fact that it only needs to worry about nested
-writers means that it only needs to check this after setting the HEAD page.
+writers means that it only needs to check this after setting the HEAD page::
-(first writer)
+ (first writer)
- A B tail page
- | | |
- v v v
- +---+ +---+ +---+ +---+
-<---| |--->| |-U->| |--->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ A B tail page
+ | | |
+ v v v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |-U->| |--->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
Now the writer can update the head page. This is also why the head page must
remain in UPDATE and only reset by the outermost writer. This prevents
-the reader from seeing the incorrect head page.
+the reader from seeing the incorrect head page::
-(first writer)
-
- A B tail page
- | | |
- v v v
- +---+ +---+ +---+ +---+
-<---| |--->| |--->| |--->| |-H->
---->| |<---| |<---| |<---| |<---
- +---+ +---+ +---+ +---+
+ (first writer)
+ A B tail page
+ | | |
+ v v v
+ +---+ +---+ +---+ +---+
+ <---| |--->| |--->| |--->| |-H->
+ --->| |<---| |<---| |<---| |<---
+ +---+ +---+ +---+ +---+
--
2.24.1
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