* [PATCH 0/8]HuC Loading Patches
@ 2016-12-08 23:02 anushasr
2016-12-08 23:02 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general anushasr
` (8 more replies)
0 siblings, 9 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx
These patches add HuC loading support. The GuC is required to
authenticate the HuC. The userspace patches that check for a
fully loaded HuC firmware and use it can be found at:
https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/2016-September/004555.html
More information regarding the HuC, batch commands that configure the
HuC etc can be found at-
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf
https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf
v2: rebased.
v3: rebased. Changed the code following the review comments.
v4: Added action_lock initialization fix provided by Arek
(Hiler Arkadiusz) to the first patch in the series- Make the
GuC fw loading helper functions general.
v5: rebased on top of drm-tip. The patch series is now in sync with GuC
code reorganization efforts by Arek-
https://patchwork.freedesktop.org/series/15896/
v6: rebased. Organize the code-move contents of intel_huc.h to intel_uc.h. Update functions
intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev.
Anusha Srivatsa (3):
drm/i915/huc: Add HuC fw loading support
drm/i915/huc: Add BXT HuC Loading Support
drm/i915/HuC: Add KBL huC loading Support
Peter Antoine (5):
drm/i915/guc: Make the GuC fw loading helper functions general
drm/i915/huc: Unified css_header struct for GuC and HuC
drm/i915/huc: Add debugfs for HuC loading status check
drm/i915/huc: Support HuC authentication
drm/i915/get_params: Add HuC status to getparams
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 43 +++-
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 22 ++-
drivers/gpu/drm/i915/intel_guc_loader.c | 199 ++++++++++---------
drivers/gpu/drm/i915/intel_huc_loader.c | 303 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_uc.c | 61 ++++++
drivers/gpu/drm/i915/intel_uc.h | 68 +++++--
include/uapi/drm/i915_drm.h | 1 +
12 files changed, 593 insertions(+), 123 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-09 8:58 ` Arkadiusz Hiler
2016-12-09 11:28 ` Michal Wajdeczko
2016-12-08 23:02 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC anushasr
` (7 subsequent siblings)
8 siblings, 2 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.
v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: rebased again on drm-nightly.
v4: removed G from messages in shared fw fetch function.
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
and intel_guc_init().
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 157 +++++++++++++++--------------
drivers/gpu/drm/i915/intel_uc.h | 40 ++++----
4 files changed, 108 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a746130..0e5ef62 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2338,7 +2338,7 @@ static int i915_llc(struct seq_file *m, void *data)
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
u32 tmp, i;
if (!HAS_GUC_UCODE(dev_priv))
@@ -2346,15 +2346,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
- guc_fw->guc_fw_path);
+ guc_fw->uc_fw_path);
seq_printf(m, "\tfetch: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+ guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 7fa4e74..e156a4b 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1493,7 +1493,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
gen9_disable_guc_interrupts(dev_priv);
@@ -1520,7 +1520,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 21db697..8f04f6e 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
/* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
switch (status) {
- case GUC_FIRMWARE_FAIL:
+ case UC_FIRMWARE_FAIL:
return "FAIL";
- case GUC_FIRMWARE_NONE:
+ case UC_FIRMWARE_NONE:
return "NONE";
- case GUC_FIRMWARE_PENDING:
+ case UC_FIRMWARE_PENDING:
return "PENDING";
- case GUC_FIRMWARE_SUCCESS:
+ case UC_FIRMWARE_SUCCESS:
return "SUCCESS";
default:
return "UNKNOWN!";
@@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
struct i915_vma *vma)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
unsigned long offset;
struct sg_table *sg = vma->pages;
u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
@@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
*/
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
struct i915_vma *vma;
int ret;
- ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
+ ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
if (ret) {
DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
return ret;
}
- vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
+ vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
return PTR_ERR(vma);
@@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
*/
int intel_guc_setup(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
- const char *fw_path = guc_fw->guc_fw_path;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ const char *fw_path = guc_fw->uc_fw_path;
int retries, ret, err;
DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
fw_path,
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
/* Loading forbidden, or no firmware to load? */
if (!i915.enable_guc_loading) {
@@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
}
/* Fetch failed, or already fetched but failed to load? */
- if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
+ if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
err = -EIO;
goto fail;
- } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
+ } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
err = -ENOEXEC;
goto fail;
}
@@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
guc_interrupts_release(dev_priv);
gen9_reset_guc_interrupts(dev_priv);
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+ guc_fw->load_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
err = i915_guc_submission_init(dev_priv);
if (err)
@@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
"retry %d more time(s)\n", err, retries);
}
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
+ guc_fw->load_status = UC_FIRMWARE_SUCCESS;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
@@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
return 0;
fail:
- if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
+ if (guc_fw->load_status == UC_FIRMWARE_PENDING)
+ guc_fw->load_status = UC_FIRMWARE_FAIL;
guc_interrupts_release(dev_priv);
i915_guc_submission_disable(dev_priv);
@@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
return ret;
}
-static void guc_fw_fetch(struct drm_i915_private *dev_priv,
- struct intel_guc_fw *guc_fw)
+void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
+ struct intel_uc_fw *uc_fw)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
@@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
size_t size;
int err;
- DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
+ intel_uc_fw_status_repr(uc_fw->fetch_status));
- err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
+ err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
if (err)
goto fail;
if (!fw)
goto fail;
- DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
- guc_fw->guc_fw_path, fw);
+ DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
+ uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
if (fw->size < sizeof(struct guc_css_header)) {
@@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
css = (struct guc_css_header *)fw->data;
/* Firmware bits always start from header */
- guc_fw->header_offset = 0;
- guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+ uc_fw->header_offset = 0;
+ uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct guc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
/* then, uCode */
- guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
- guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+ uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
+ uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
/* now RSA */
if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
DRM_NOTE("RSA key size is bad\n");
goto fail;
}
- guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
- guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+ uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
+ uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
/* At least, it should have header, uCode and RSA. Size of all three. */
- size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+ size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
if (fw->size < size) {
DRM_NOTE("Missing firmware components\n");
goto fail;
}
/* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = guc_fw->header_size + guc_fw->ucode_size;
+ size = uc_fw->header_size + uc_fw->ucode_size;
if (size > guc_wopcm_size(dev_priv)) {
DRM_NOTE("Firmware is too large to fit in WOPCM\n");
goto fail;
@@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
- guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
-
- if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
- guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
- DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+
+ if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
+ uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
+ DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
err = -ENOEXEC;
goto fail;
}
DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
mutex_lock(&dev_priv->drm.struct_mutex);
obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
@@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
- guc_fw->guc_fw_obj = obj;
- guc_fw->guc_fw_size = fw->size;
+ uc_fw->uc_fw_obj = obj;
+ uc_fw->uc_fw_size = fw->size;
- DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
- guc_fw->guc_fw_obj);
+ DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
+ uc_fw->uc_fw_obj);
release_firmware(fw);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
+ uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
return;
fail:
- DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
- guc_fw->guc_fw_path, err);
- DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
- err, fw, guc_fw->guc_fw_obj);
+ DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
+ uc_fw->uc_fw_path, err);
+ DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
+ err, fw, uc_fw->uc_fw_obj);
mutex_lock(&dev_priv->drm.struct_mutex);
- obj = guc_fw->guc_fw_obj;
+ obj = uc_fw->uc_fw_obj;
if (obj)
i915_gem_object_put(obj);
- guc_fw->guc_fw_obj = NULL;
+ uc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev_priv->drm.struct_mutex);
release_firmware(fw); /* OK even if fw is NULL */
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+ uc_fw->fetch_status = UC_FIRMWARE_FAIL;
}
/**
@@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
*/
void intel_guc_init(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
const char *fw_path;
if (!HAS_GUC(dev_priv)) {
@@ -739,23 +739,24 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
fw_path = NULL;
} else if (IS_SKYLAKE(dev_priv)) {
fw_path = I915_SKL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
+ guc_fw->major_ver_wanted = SKL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = SKL_FW_MINOR;
} else if (IS_BROXTON(dev_priv)) {
fw_path = I915_BXT_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
+ guc_fw->major_ver_wanted = BXT_FW_MAJOR;
+ guc_fw->minor_ver_wanted = BXT_FW_MINOR;
} else if (IS_KABYLAKE(dev_priv)) {
fw_path = I915_KBL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
+ guc_fw->major_ver_wanted = KBL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_FW_MINOR;
} else {
fw_path = ""; /* unknown device */
}
- guc_fw->guc_fw_path = fw_path;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
+ guc_fw->uc_dev = &dev_priv->drm;
+ guc_fw->uc_fw_path = fw_path;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
+ guc_fw->load_status = UC_FIRMWARE_NONE;
/* Early (and silent) return if GuC loading is disabled */
if (!i915.enable_guc_loading)
@@ -765,9 +766,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
if (*fw_path == '\0')
return;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
+ guc_fw->fetch_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
- guc_fw_fetch(dev_priv, guc_fw);
+ intel_uc_fw_fetch(dev_priv, guc_fw);
/* status must now be FAIL or SUCCESS */
}
@@ -777,17 +778,17 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
*/
void intel_guc_fini(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
mutex_lock(&dev_priv->drm.struct_mutex);
guc_interrupts_release(dev_priv);
i915_guc_submission_disable(dev_priv);
i915_guc_submission_fini(dev_priv);
- if (guc_fw->guc_fw_obj)
- i915_gem_object_put(guc_fw->guc_fw_obj);
- guc_fw->guc_fw_obj = NULL;
+ if (guc_fw->uc_fw_obj)
+ i915_gem_object_put(guc_fw->uc_fw_obj);
+ guc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev_priv->drm.struct_mutex);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 11f5608..f9f598d 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -91,29 +91,31 @@ struct i915_guc_client {
uint64_t submissions[I915_NUM_ENGINES];
};
-enum intel_guc_fw_status {
- GUC_FIRMWARE_FAIL = -1,
- GUC_FIRMWARE_NONE = 0,
- GUC_FIRMWARE_PENDING,
- GUC_FIRMWARE_SUCCESS
+enum intel_uc_fw_status {
+ UC_FIRMWARE_FAIL = -1,
+ UC_FIRMWARE_NONE = 0,
+ UC_FIRMWARE_PENDING,
+ UC_FIRMWARE_SUCCESS
};
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
*/
-struct intel_guc_fw {
- const char * guc_fw_path;
- size_t guc_fw_size;
- struct drm_i915_gem_object * guc_fw_obj;
- enum intel_guc_fw_status guc_fw_fetch_status;
- enum intel_guc_fw_status guc_fw_load_status;
-
- uint16_t guc_fw_major_wanted;
- uint16_t guc_fw_minor_wanted;
- uint16_t guc_fw_major_found;
- uint16_t guc_fw_minor_found;
-
+struct intel_uc_fw {
+ struct drm_device *uc_dev;
+ const char *uc_fw_path;
+ size_t uc_fw_size;
+ struct drm_i915_gem_object *uc_fw_obj;
+ enum intel_uc_fw_status fetch_status;
+ enum intel_uc_fw_status load_status;
+
+ uint16_t major_ver_wanted;
+ uint16_t minor_ver_wanted;
+ uint16_t major_ver_found;
+ uint16_t minor_ver_found;
+
+ uint32_t fw_type;
uint32_t header_size;
uint32_t header_offset;
uint32_t rsa_size;
@@ -139,7 +141,7 @@ struct intel_guc_log {
};
struct intel_guc {
- struct intel_guc_fw guc_fw;
+ struct intel_uc_fw guc_fw;
struct intel_guc_log log;
/* intel_guc_recv interrupt related state */
@@ -181,7 +183,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
extern void intel_guc_init(struct drm_i915_private *dev_priv);
extern int intel_guc_setup(struct drm_i915_private *dev_priv);
extern void intel_guc_fini(struct drm_i915_private *dev_priv);
-extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
extern int intel_guc_resume(struct drm_i915_private *dev_priv);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
2016-12-08 23:02 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-09 9:20 ` Arkadiusz Hiler
2016-12-09 11:55 ` Michal Wajdeczko
2016-12-08 23:02 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support anushasr
` (6 subsequent siblings)
8 siblings, 2 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.
v2: rebased on-top of drm-intel-nightly
v3: rebased on-top of drm-intel-nightly (again).
v4: rebased + spaces.
v7: rebased.
v8: rebased.
v9: rebased. Rename device_id to guc_branch_client_version,
make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC
and UC_FW_TYPE_HUC into an enum.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip.
v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++----
drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_uc.h | 5 ++++
3 files changed, 50 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 3202b32..c1e7faf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -145,7 +145,7 @@
* The GuC firmware layout looks like this:
*
* +-------------------------------+
- * | guc_css_header |
+ * | uc_css_header |
* | |
* | contains major/minor version |
* +-------------------------------+
@@ -172,9 +172,16 @@
* 3. Length info of each component can be found in header, in dwords.
* 4. Modulus and exponent key are not required by driver. They may not appear
* in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
*/
-struct guc_css_header {
+struct uc_css_header {
uint32_t module_type;
/* header_size includes all non-uCode bits, including css_header, rsa
* key, modulus key and exponent data. */
@@ -205,8 +212,14 @@ struct guc_css_header {
char username[8];
char buildnumber[12];
- uint32_t device_id;
- uint32_t guc_sw_version;
+ union {
+ uint32_t guc_branch_client_version;
+ uint32_t huc_sw_version;
+ };
+ union {
+ uint32_t guc_sw_version;
+ uint32_t huc_reserved;
+ };
uint32_t prod_preprod_fw;
uint32_t reserved[12];
uint32_t header_info;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8f04f6e..26a184f 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
const struct firmware *fw = NULL;
- struct guc_css_header *css;
+ struct uc_css_header *css;
size_t size;
int err;
@@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
- if (fw->size < sizeof(struct guc_css_header)) {
+ if (fw->size < sizeof(struct uc_css_header)) {
DRM_NOTE("Firmware header is missing\n");
goto fail;
}
- css = (struct guc_css_header *)fw->data;
+ css = (struct uc_css_header *)fw->data;
/* Firmware bits always start from header */
uc_fw->header_offset = 0;
uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct uc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
@@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
- /* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = uc_fw->header_size + uc_fw->ucode_size;
- if (size > guc_wopcm_size(dev_priv)) {
- DRM_NOTE("Firmware is too large to fit in WOPCM\n");
- goto fail;
- }
-
/*
* The GuC firmware image has the version number embedded at a well-known
* offset within the firmware blob; note that major / minor version are
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- uc_fw->major_ver_found = css->guc_sw_version >> 16;
- uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ switch (uc_fw->fw_type) {
+ case UC_FW_TYPE_GUC:
+ /* Header and uCode will be loaded to WOPCM. Size of the two. */
+ size = uc_fw->header_size + uc_fw->ucode_size;
+
+ /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
+ if (size > guc_wopcm_size(dev_priv)) {
+ DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+ goto fail;
+ }
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ break;
+
+ case UC_FW_TYPE_HUC:
+ uc_fw->major_ver_found = css->huc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
+ break;
+
+ default:
+ DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+ err = -ENOEXEC;
+ goto fail;
+ }
if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index f9f598d..be89f0b 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -98,6 +98,11 @@ enum intel_uc_fw_status {
UC_FIRMWARE_SUCCESS
};
+enum {
+ UC_FW_TYPE_GUC,
+ UC_FW_TYPE_HUC
+};
+
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
2016-12-08 23:02 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general anushasr
2016-12-08 23:02 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-09 10:56 ` Arkadiusz Hiler
` (2 more replies)
2016-12-08 23:02 ` [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support anushasr
` (5 subsequent siblings)
8 siblings, 3 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
match the one in the huc package.
Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
change wait_for_atomic to wait_for.
v5: rebased + comment changes.
v7: rebased.
v8: rebased.
v9: rebased. Changed the year in the copyright message to reflect
the right year.Correct the comments,remove the unwanted WARN message,
replace drm_gem_object_unreference() with i915_gem_object_put().Make the
prototypes in intel_huc.h non-extern.
v10: rebased. Update the file construction done by HuC. It is similar to
GuC.Adopted the approach used in-
https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
v11: Fix warnings remove old declaration
v12: Change dev to dev_priv in macro definition.
Corrected comments.
v13: rebased.
v14: rebased on top of drm-tip
v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
of intel_huc.h to intel_uc.h
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +-
drivers/gpu/drm/i915/intel_huc_loader.c | 264 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_uc.h | 22 +++
7 files changed, 299 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3c30916..01d4f4b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_uc.o \
intel_guc_loader.o \
+ intel_huc_loader.o \
i915_guc_submission.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6428588..85a47c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
+ intel_huc_init(dev_priv);
intel_guc_init(dev_priv);
ret = i915_gem_init(dev_priv);
@@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev_priv);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev_priv);
@@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
-
+ intel_huc_fini(dev);
intel_guc_fini(dev_priv);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1480e73..0371ca4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2036,6 +2036,7 @@ struct drm_i915_private {
struct intel_gvt *gvt;
+ struct intel_huc huc;
struct intel_guc guc;
struct intel_csr csr;
@@ -2810,7 +2811,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
-
+#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 5e638fc..f9829f6 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
#define DMA_ADDRESS_SPACE_GTT (8 << 16)
#define DMA_COPY_SIZE _MMIO(0xc310)
#define DMA_CTRL _MMIO(0xc314)
+#define HUC_UKERNEL (1<<9)
#define UOS_MOVE (1<<4)
#define START_DMA (1<<0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
+#define HUC_LOADING_AGENT_VCR (0<<1)
+#define HUC_LOADING_AGENT_GUC (1<<1)
#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 26a184f..b971351 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/* Finally start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
-
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
+ _MASKED_BIT_DISABLE(HUC_UKERNEL));
/*
* Wait for the DMA to complete & the GuC to start up.
* NB: Docs recommend not using the interrupt for completion.
@@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
return ret;
}
-static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
{
u32 wopcm_size = GUC_WOPCM_TOP;
@@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
if (err)
goto fail;
+ intel_huc_load(dev_priv);
err = guc_ucode_xfer(dev_priv);
if (!err)
break;
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
new file mode 100644
index 0000000..e0efd1c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_uc.h"
+
+/**
+ * DOC: HuC Firmware
+ *
+ * Motivation:
+ * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ *
+ * Implementation:
+ * The same firmware loader is used as the GuC. However, the actual
+ * loading to HW is deferred until GEM initialization is done.
+ *
+ * Note that HuC firmware loading must be done before GuC loading.
+ */
+
+#define SKL_FW_MAJOR 01
+#define SKL_FW_MINOR 07
+#define SKL_BLD_NUM 1398
+
+#define HUC_FW_PATH(platform, major, minor, bld_num) \
+ "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
+ __stringify(minor) "_" __stringify(bld_num) ".bin"
+
+#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
+ SKL_FW_MINOR, SKL_BLD_NUM)
+MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+
+/**
+ * huc_ucode_xfer() - DMA's the firmware
+ * @dev_priv: the drm device
+ *
+ * This function takes the gem object containing the firmware, sets up the DMA
+ * engine MMIO, triggers the DMA operation and waits for it to finish.
+ *
+ * Transfer the firmware image to RAM for execution by the microcontroller.
+ *
+ * Return: 0 on success, non-zero on failure
+ */
+
+static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
+{
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ struct i915_vma *vma;
+ unsigned long offset = 0;
+ u32 size;
+ int ret;
+
+ ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
+ if (ret) {
+ DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
+ return ret;
+ }
+
+ vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+ return PTR_ERR(vma);
+ }
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* init WOPCM */
+ I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
+ I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
+ HUC_LOADING_AGENT_GUC);
+
+ /* Set the source address for the uCode */
+ offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
+ I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
+ I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+
+ /* Hardware doesn't look at destination address for HuC. Set it to 0,
+ * but still program the correct address space.
+ */
+ I915_WRITE(DMA_ADDR_1_LOW, 0);
+ I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+
+ size = huc_fw->header_size + huc_fw->ucode_size;
+ I915_WRITE(DMA_COPY_SIZE, size);
+
+ /* Start the DMA */
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
+
+ /* Wait for DMA to finish */
+ ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
+
+ DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ /*
+ * We keep the object pages for reuse during resume. But we can unpin it
+ * now that DMA has completed, so it doesn't continue to take up space.
+ */
+ i915_vma_unpin(vma);
+
+ return ret;
+}
+
+/**
+ * intel_huc_init() - initiate HuC firmware loading request
+ * @dev: the drm device
+ *
+ * Called early during driver load, but after GEM is initialised. The loading
+ * will continue only when driver explicitly specify firmware name and version.
+ * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
+ * capable or driver yet support it. And there will be no error message for
+ * UC_FIRMWARE_NONE cases.
+ *
+ * The DMA-copying to HW is done later when intel_huc_load() is called.
+ */
+void intel_huc_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_huc *huc = &dev_priv->huc;
+ struct intel_uc_fw *huc_fw = &huc->huc_fw;
+ const char *fw_path = NULL;
+
+ huc_fw->uc_fw_path = NULL;
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+ huc_fw->load_status = UC_FIRMWARE_NONE;
+ huc_fw->fw_type = UC_FW_TYPE_HUC;
+
+ if (!HAS_HUC_UCODE(dev_priv))
+ return;
+
+ if (IS_SKYLAKE(dev_priv)) {
+ fw_path = I915_SKL_HUC_UCODE;
+ huc_fw->major_ver_wanted = SKL_FW_MAJOR;
+ huc_fw->minor_ver_wanted = SKL_FW_MINOR;
+ }
+
+ huc_fw->uc_fw_path = fw_path;
+ huc_fw->fetch_status = UC_FIRMWARE_PENDING;
+
+ DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
+
+ intel_uc_fw_fetch(dev_priv, huc_fw);
+}
+
+/**
+ * intel_huc_load() - load HuC uCode to device
+ * @dev: the drm device
+ *
+ * Called from gem_init_hw() during driver loading and also after a GPU reset.
+ * Be note that HuC loading must be done before GuC loading.
+ *
+ * The firmware image should have already been fetched into memory by the
+ * earlier call to intel_huc_init(), so here we need only check that
+ * is succeeded, and then transfer the image to the h/w.
+ *
+ * Return: non-zero code on error
+ */
+int intel_huc_load(struct drm_i915_private *dev_priv)
+{
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ int err;
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
+ return 0;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
+ huc_fw->load_status == UC_FIRMWARE_FAIL)
+ return -ENOEXEC;
+
+ huc_fw->load_status = UC_FIRMWARE_PENDING;
+
+ switch (huc_fw->fetch_status) {
+ case UC_FIRMWARE_FAIL:
+ /* something went wrong :( */
+ err = -EIO;
+ goto fail;
+
+ case UC_FIRMWARE_NONE:
+ case UC_FIRMWARE_PENDING:
+ default:
+ /* "can't happen" */
+ WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ huc_fw->fetch_status);
+ err = -ENXIO;
+ goto fail;
+
+ case UC_FIRMWARE_SUCCESS:
+ break;
+ }
+
+ err = huc_ucode_xfer(dev_priv);
+ if (err)
+ goto fail;
+
+ huc_fw->load_status = UC_FIRMWARE_SUCCESS;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ return 0;
+
+fail:
+ if (huc_fw->load_status == UC_FIRMWARE_PENDING)
+ huc_fw->load_status = UC_FIRMWARE_FAIL;
+
+ DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
+
+ return err;
+}
+
+/**
+ * intel_huc_fini() - clean up resources allocated for HuC
+ * @dev: the drm device
+ *
+ * Cleans up by releasing the huc firmware GEM obj.
+ */
+void intel_huc_fini(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ mutex_lock(&dev->struct_mutex);
+ if (huc_fw->uc_fw_obj)
+ i915_gem_object_put(huc_fw->uc_fw_obj);
+ huc_fw->uc_fw_obj = NULL;
+ mutex_unlock(&dev->struct_mutex);
+
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+}
+
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index be89f0b..ac92946 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -24,6 +24,12 @@
#ifndef _INTEL_UC_H_
#define _INTEL_UC_H_
+#ifndef _INTEL_HUC_H_
+#define _INTEL_HUC_H_
+
+#define HUC_STATUS2 _MMIO(0xD3B0)
+#define HUC_FW_VERIFIED (1<<7)
+
#include "intel_guc_fwif.h"
#include "i915_guc_reg.h"
#include "intel_ringbuffer.h"
@@ -175,6 +181,13 @@ struct intel_guc {
struct mutex send_mutex;
};
+struct intel_huc {
+ /* Generic uC firmware management */
+ struct intel_uc_fw huc_fw;
+
+ /* HuC-specific additions */
+};
+
/* intel_uc.c */
void intel_uc_init_early(struct drm_i915_private *dev_priv);
bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status);
@@ -191,6 +204,9 @@ extern void intel_guc_fini(struct drm_i915_private *dev_priv);
extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
extern int intel_guc_resume(struct drm_i915_private *dev_priv);
+void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
+ struct intel_uc_fw *uc_fw);
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
@@ -205,4 +221,10 @@ void i915_guc_register(struct drm_i915_private *dev_priv);
void i915_guc_unregister(struct drm_i915_private *dev_priv);
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
+/* intel_huc_loader.c */
+void intel_huc_init(struct drm_i915_private *dev_priv);
+void intel_huc_fini(struct drm_device *dev);
+int intel_huc_load(struct drm_i915_private *dev_priv);
+
+#endif
#endif
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
` (2 preceding siblings ...)
2016-12-08 23:02 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-08 23:02 ` [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support anushasr
` (4 subsequent siblings)
8 siblings, 0 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
This patch adds the HuC Loading for the BXT by using
the updated file construction.
Version 1.7 of the HuC firmware.
v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/intel_huc_loader.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index e0efd1c..a7a1a7f 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -40,6 +40,10 @@
* Note that HuC firmware loading must be done before GuC loading.
*/
+#define BXT_FW_MAJOR 01
+#define BXT_FW_MINOR 07
+#define BXT_BLD_NUM 1398
+
#define SKL_FW_MAJOR 01
#define SKL_FW_MINOR 07
#define SKL_BLD_NUM 1398
@@ -52,6 +56,9 @@
SKL_FW_MINOR, SKL_BLD_NUM)
MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \
+ BXT_FW_MINOR, BXT_BLD_NUM)
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
/**
* huc_ucode_xfer() - DMA's the firmware
* @dev_priv: the drm device
@@ -157,6 +164,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_SKL_HUC_UCODE;
huc_fw->major_ver_wanted = SKL_FW_MAJOR;
huc_fw->minor_ver_wanted = SKL_FW_MINOR;
+ } else if (IS_BROXTON(dev_priv)) {
+ fw_path = I915_BXT_HUC_UCODE;
+ huc_fw->major_ver_wanted = BXT_FW_MAJOR;
+ huc_fw->minor_ver_wanted = BXT_FW_MINOR;
}
huc_fw->uc_fw_path = fw_path;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
` (3 preceding siblings ...)
2016-12-08 23:02 ` [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-08 23:02 ` [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check anushasr
` (3 subsequent siblings)
8 siblings, 0 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
This patch adds the support to load HuC on KBL
Version 2.0
v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/intel_huc_loader.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index a7a1a7f..96fc727 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -48,6 +48,10 @@
#define SKL_FW_MINOR 07
#define SKL_BLD_NUM 1398
+#define KBL_FW_MAJOR 02
+#define KBL_FW_MINOR 00
+#define KBL_BLD_NUM 1810
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -59,6 +63,11 @@ MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \
BXT_FW_MINOR, BXT_BLD_NUM)
MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
+#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_FW_MAJOR, \
+ KBL_FW_MINOR, KBL_BLD_NUM)
+MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+
/**
* huc_ucode_xfer() - DMA's the firmware
* @dev_priv: the drm device
@@ -168,8 +177,15 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_BXT_HUC_UCODE;
huc_fw->major_ver_wanted = BXT_FW_MAJOR;
huc_fw->minor_ver_wanted = BXT_FW_MINOR;
+ } else if (IS_KABYLAKE(dev_priv)) {
+ fw_path = I915_KBL_HUC_UCODE;
+ huc_fw->major_ver_wanted = KBL_FW_MAJOR;
+ huc_fw->minor_ver_wanted = KBL_FW_MINOR;
}
+ if (fw_path == NULL)
+ return;
+
huc_fw->uc_fw_path = fw_path;
huc_fw->fetch_status = UC_FIRMWARE_PENDING;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
` (4 preceding siblings ...)
2016-12-08 23:02 ` [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr
` (2 subsequent siblings)
8 siblings, 0 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
Add debugfs entry for HuC loading status check.
v2: rebase on-top of drm-intel-nightly.
v3: rebased again.
v7: rebased.
v8: rebased.
v9: rebased.
v10: rebased.
v11: rebased on top of drm-tip
v12: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0e5ef62..639b66d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2335,6 +2335,36 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
}
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ if (!HAS_HUC_UCODE(dev_priv))
+ return 0;
+
+ seq_puts(m, "HuC firmware status:\n");
+ seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+ seq_printf(m, "\tfetch: %s\n",
+ intel_uc_fw_status_repr(huc_fw->fetch_status));
+ seq_printf(m, "\tload: %s\n",
+ intel_uc_fw_status_repr(huc_fw->load_status));
+ seq_printf(m, "\tversion wanted: %d.%d\n",
+ huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+ seq_printf(m, "\tversion found: %d.%d\n",
+ huc_fw->major_ver_found, huc_fw->minor_ver_found);
+ seq_printf(m, "\theader: offset is %d; size = %d\n",
+ huc_fw->header_offset, huc_fw->header_size);
+ seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+ huc_fw->ucode_offset, huc_fw->ucode_size);
+ seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+ huc_fw->rsa_offset, huc_fw->rsa_size);
+
+ seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+ return 0;
+}
+
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5403,6 +5433,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
` (5 preceding siblings ...)
2016-12-08 23:02 ` [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-09 10:22 ` Arkadiusz Hiler
2016-12-09 12:36 ` Michal Wajdeczko
2016-12-08 23:02 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
2016-12-08 23:45 ` ✓ Fi.CI.BAT: success for HuC Loading Patches Patchwork
8 siblings, 2 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++
drivers/gpu/drm/i915/intel_uc.c | 61 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_uc.h | 1 +
4 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index c1e7faf..94a974d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -504,6 +504,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+ INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_LIMIT
};
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index b971351..89d092b 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
+ intel_guc_auth_huc(dev_priv);
+
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8ae6795..445b9ad 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+ struct intel_guc *guc = &dev_priv->guc;
+ struct intel_huc *huc = &dev_priv->huc;
+ struct i915_vma *vma;
+ int ret;
+ u32 data[2];
+
+ /* Bypass the case where there is no HuC firmware */
+ if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+ huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+ return;
+
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+ return;
+ }
+
+ if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+ return;
+ }
+
+ vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+ return;
+ }
+
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ /* Specify auth action and where public signature is. */
+ data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+ data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
+
+ ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+ if (ret) {
+ DRM_ERROR("HuC: GuC did not ack Auth request\n");
+ goto out;
+ }
+
+ /* Check authentication status, it should be done by now */
+ ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+ if (ret) {
+ DRM_ERROR("HuC: Authentication failed\n");
+ goto out;
+ }
+
+out:
+ i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index ac92946..1db8bc2 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_log_flush_complete(struct intel_guc *guc);
int intel_guc_log_flush(struct intel_guc *guc);
int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
/* intel_guc_loader.c */
extern void intel_guc_init(struct drm_i915_private *dev_priv);
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
` (6 preceding siblings ...)
2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr
@ 2016-12-08 23:02 ` anushasr
2016-12-08 23:55 ` Chris Wilson
2016-12-09 12:59 ` Michal Wajdeczko
2016-12-08 23:45 ` ✓ Fi.CI.BAT: success for HuC Loading Patches Patchwork
8 siblings, 2 replies; 71+ messages in thread
From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased on top of drm-tip.
v6: rebased. Removed any reference to intel_huc.h
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_uc.h | 1 +
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 85a47c2..6be06a27 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 96fc727..6704cc8 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -289,3 +289,15 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 1db8bc2..ccd3f69 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -226,6 +226,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
void intel_huc_init(struct drm_i915_private *dev_priv);
void intel_huc_fini(struct drm_device *dev);
int intel_huc_load(struct drm_i915_private *dev_priv);
+int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
#endif
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..3e1964c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* ✓ Fi.CI.BAT: success for HuC Loading Patches
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
` (7 preceding siblings ...)
2016-12-08 23:02 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
@ 2016-12-08 23:45 ` Patchwork
8 siblings, 0 replies; 71+ messages in thread
From: Patchwork @ 2016-12-08 23:45 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: HuC Loading Patches
URL : https://patchwork.freedesktop.org/series/16584/
State : success
== Summary ==
Series 16584v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/16584/revisions/1/mbox/
fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14
fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-t5700 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19
fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19
fi-ilk-650 total:247 pass:195 dwarn:0 dfail:0 fail:0 skip:52
fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:247 pass:224 dwarn:3 dfail:0 fail:0 skip:20
fi-skl-6770hq total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13
fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32
a967a5db05519675cd3a0f419fba30814ed457eb drm-tip: 2016y-12m-08d-20h-50m-10s UTC integration manifest
b50355c drm/i915/get_params: Add HuC status to getparams
0c33af1 drm/i915/huc: Support HuC authentication
8c9354e drm/i915/huc: Add debugfs for HuC loading status check
73b8768 drm/i915/HuC: Add KBL huC loading Support
0ef1bd0 drm/i915/huc: Add BXT HuC Loading Support
70b8dd7 drm/i915/huc: Add HuC fw loading support
1dec5f7 drm/i915/huc: Unified css_header struct for GuC and HuC
5941062 drm/i915/guc: Make the GuC fw loading helper functions general
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3245/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-08 23:02 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
@ 2016-12-08 23:55 ` Chris Wilson
2016-12-13 9:40 ` Arkadiusz Hiler
2016-12-09 12:59 ` Michal Wajdeczko
1 sibling, 1 reply; 71+ messages in thread
From: Chris Wilson @ 2016-12-08 23:55 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Peter Antoine
On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased on top of drm-tip.
> v6: rebased. Removed any reference to intel_huc.h
>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
> drivers/gpu/drm/i915/intel_uc.h | 1 +
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 85a47c2..6be06a27 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_uc.h"
>
> static struct drm_driver driver;
>
> @@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> */
> value = 1;
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
Why did you put it here? It breaks the pattern of case statements.
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 96fc727..6704cc8 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -289,3 +289,15 @@ void intel_huc_fini(struct drm_device *dev)
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
>
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
bool
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
(brackets (because (brackets)))
But what I really wanted to ask... Does this register access require the
device to be awake and powered?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-12-08 23:02 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general anushasr
@ 2016-12-09 8:58 ` Arkadiusz Hiler
2016-12-09 11:28 ` Michal Wajdeczko
1 sibling, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 8:58 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx
On Thu, Dec 08, 2016 at 03:02:12PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
> s/intel_guc_fw/intel_uc_fw/g
> s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> v2: rebased on top of nightly.
> reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
> v4: removed G from messages in shared fw fetch function.
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
> and intel_guc_init().
This is little bit misleading. It suggests that you did the change from
dev to dev_priv, while it really happened externally. You just had to
rebase and accomodate for that.
nontheless...
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
--
Cheers,
Arek
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-12-08 23:02 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC anushasr
@ 2016-12-09 9:20 ` Arkadiusz Hiler
2016-12-09 11:55 ` Michal Wajdeczko
1 sibling, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 9:20 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx
On Thu, Dec 08, 2016 at 03:02:13PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
>
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> v4: rebased + spaces.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename device_id to guc_branch_client_version,
> make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC
> and UC_FW_TYPE_HUC into an enum.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip.
> v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++----
> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_uc.h | 5 ++++
> 3 files changed, 50 insertions(+), 17 deletions(-)
--
Cheers,
Arek
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication
2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr
@ 2016-12-09 10:22 ` Arkadiusz Hiler
2016-12-09 12:36 ` Michal Wajdeczko
1 sibling, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 10:22 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx
On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++
> drivers/gpu/drm/i915/intel_uc.c | 61 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_uc.h | 1 +
> 4 files changed, 65 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index c1e7faf..94a974d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -504,6 +504,7 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
> INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> INTEL_GUC_ACTION_LIMIT
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index b971351..89d092b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> intel_uc_fw_status_repr(guc_fw->fetch_status),
> intel_uc_fw_status_repr(guc_fw->load_status));
>
> + intel_guc_auth_huc(dev_priv);
> +
> if (i915.enable_guc_submission) {
> if (i915.guc_log_level >= 0)
> gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 8ae6795..445b9ad 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
>
> return intel_guc_send(guc, action, ARRAY_SIZE(action));
> }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + /* Bypass the case where there is no HuC firmware */
> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> + return;
> +
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
> + return;
> + }
> +
> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> + return;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return;
> + }
> +
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. */
> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed\n");
> + goto out;
> + }
> +
> +out:
> + i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index ac92946..1db8bc2 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
> int intel_guc_log_flush_complete(struct intel_guc *guc);
> int intel_guc_log_flush(struct intel_guc *guc);
> int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>
> /* intel_guc_loader.c */
> extern void intel_guc_init(struct drm_i915_private *dev_priv);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-08 23:02 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support anushasr
@ 2016-12-09 10:56 ` Arkadiusz Hiler
2016-12-09 11:10 ` Chris Wilson
2016-12-09 12:17 ` Michal Wajdeczko
2016-12-12 18:52 ` Tvrtko Ursulin
2 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 10:56 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx
On Thu, Dec 08, 2016 at 03:02:14PM -0800, anushasr wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
>
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
>
> v2: rebased on-top of drm-intel-nightly.
> removed if(HAS_GUC()) before the guc call. (D.Gordon)
> update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
> match the one in the huc package.
> Changed dev->dev_private to to_i915()
> v4: moved function back to where it was.
> change wait_for_atomic to wait_for.
> v5: rebased + comment changes.
> v7: rebased.
> v8: rebased.
> v9: rebased. Changed the year in the copyright message to reflect
> the right year.Correct the comments,remove the unwanted WARN message,
> replace drm_gem_object_unreference() with i915_gem_object_put().Make the
> prototypes in intel_huc.h non-extern.
> v10: rebased. Update the file construction done by HuC. It is similar to
> GuC.Adopted the approach used in-
> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
> v11: Fix warnings remove old declaration
> v12: Change dev to dev_priv in macro definition.
> Corrected comments.
> v13: rebased.
> v14: rebased on top of drm-tip
> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
> of intel_huc.h to intel_uc.h
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 7 +-
> drivers/gpu/drm/i915/intel_huc_loader.c | 264 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_uc.h | 22 +++
> 7 files changed, 299 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 3c30916..01d4f4b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
> # general-purpose microcontroller (GuC) support
> i915-y += intel_uc.o \
> intel_guc_loader.o \
> + intel_huc_loader.o \
> i915_guc_submission.o
>
> # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6428588..85a47c2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> if (ret)
> goto cleanup_irq;
>
> + intel_huc_init(dev_priv);
> intel_guc_init(dev_priv);
>
> ret = i915_gem_init(dev_priv);
> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> i915_gem_fini(dev_priv);
> cleanup_irq:
> + intel_huc_fini(dev);
> intel_guc_fini(dev_priv);
> drm_irq_uninstall(dev);
> intel_teardown_gmbus(dev_priv);
> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
>
> /* Flush any outstanding unpin_work. */
> drain_workqueue(dev_priv->wq);
> -
> + intel_huc_fini(dev);
> intel_guc_fini(dev_priv);
> i915_gem_fini(dev_priv);
> intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1480e73..0371ca4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2036,6 +2036,7 @@ struct drm_i915_private {
>
> struct intel_gvt *gvt;
>
> + struct intel_huc huc;
> struct intel_guc guc;
>
> struct intel_csr csr;
> @@ -2810,7 +2811,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
> -
> +#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
>
> #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 5e638fc..f9829f6 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -61,9 +61,12 @@
> #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> #define DMA_COPY_SIZE _MMIO(0xc310)
> #define DMA_CTRL _MMIO(0xc314)
> +#define HUC_UKERNEL (1<<9)
> #define UOS_MOVE (1<<4)
> #define START_DMA (1<<0)
> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> +#define HUC_LOADING_AGENT_VCR (0<<1)
> +#define HUC_LOADING_AGENT_GUC (1<<1)
> #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
> #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 26a184f..b971351 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>
> /* Finally start the DMA */
> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> -
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
> + _MASKED_BIT_DISABLE(HUC_UKERNEL));
> /*
> * Wait for the DMA to complete & the GuC to start up.
> * NB: Docs recommend not using the interrupt for completion.
> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> {
> u32 wopcm_size = GUC_WOPCM_TOP;
>
> @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> if (err)
> goto fail;
>
> + intel_huc_load(dev_priv);
> err = guc_ucode_xfer(dev_priv);
> if (!err)
> break;
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> new file mode 100644
> index 0000000..e0efd1c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -0,0 +1,264 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#include <linux/firmware.h>
> +#include "i915_drv.h"
> +#include "intel_uc.h"
> +
> +/**
> + * DOC: HuC Firmware
> + *
> + * Motivation:
> + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can use the firmware
> + * capabilities by adding HuC specific commands to batch buffers.
> + *
> + * Implementation:
> + * The same firmware loader is used as the GuC. However, the actual
> + * loading to HW is deferred until GEM initialization is done.
> + *
> + * Note that HuC firmware loading must be done before GuC loading.
> + */
> +
> +#define SKL_FW_MAJOR 01
> +#define SKL_FW_MINOR 07
> +#define SKL_BLD_NUM 1398
> +
> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> + __stringify(minor) "_" __stringify(bld_num) ".bin"
> +
Generally the patch looks well, but I'll withold my r-b till we have a
consensus on what parts of the huc version should we lock the kernel.
> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
> + SKL_FW_MINOR, SKL_BLD_NUM)
> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> +
> +/**
> + * huc_ucode_xfer() - DMA's the firmware
> + * @dev_priv: the drm device
> + *
> + * This function takes the gem object containing the firmware, sets up the DMA
> + * engine MMIO, triggers the DMA operation and waits for it to finish.
> + *
> + * Transfer the firmware image to RAM for execution by the microcontroller.
> + *
> + * Return: 0 on success, non-zero on failure
> + */
> +
> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + struct i915_vma *vma;
> + unsigned long offset = 0;
> + u32 size;
> + int ret;
> +
> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> + if (ret) {
> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> + return ret;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return PTR_ERR(vma);
> + }
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> + /* init WOPCM */
> + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
> + HUC_LOADING_AGENT_GUC);
> +
> + /* Set the source address for the uCode */
> + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> +
> + /* Hardware doesn't look at destination address for HuC. Set it to 0,
> + * but still program the correct address space.
> + */
> + I915_WRITE(DMA_ADDR_1_LOW, 0);
> + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> +
> + size = huc_fw->header_size + huc_fw->ucode_size;
> + I915_WRITE(DMA_COPY_SIZE, size);
> +
> + /* Start the DMA */
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> +
> + /* Wait for DMA to finish */
> + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> +
> + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> +
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> + /*
> + * We keep the object pages for reuse during resume. But we can unpin it
> + * now that DMA has completed, so it doesn't continue to take up space.
> + */
> + i915_vma_unpin(vma);
> +
> + return ret;
> +}
> +
> +/**
> + * intel_huc_init() - initiate HuC firmware loading request
> + * @dev: the drm device
> + *
> + * Called early during driver load, but after GEM is initialised. The loading
> + * will continue only when driver explicitly specify firmware name and version.
> + * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
> + * capable or driver yet support it. And there will be no error message for
> + * UC_FIRMWARE_NONE cases.
> + *
> + * The DMA-copying to HW is done later when intel_huc_load() is called.
> + */
> +void intel_huc_init(struct drm_i915_private *dev_priv)
> +{
> + struct intel_huc *huc = &dev_priv->huc;
> + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> + const char *fw_path = NULL;
> +
> + huc_fw->uc_fw_path = NULL;
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> + huc_fw->load_status = UC_FIRMWARE_NONE;
> + huc_fw->fw_type = UC_FW_TYPE_HUC;
> +
> + if (!HAS_HUC_UCODE(dev_priv))
> + return;
> +
> + if (IS_SKYLAKE(dev_priv)) {
> + fw_path = I915_SKL_HUC_UCODE;
> + huc_fw->major_ver_wanted = SKL_FW_MAJOR;
> + huc_fw->minor_ver_wanted = SKL_FW_MINOR;
> + }
> +
> + huc_fw->uc_fw_path = fw_path;
> + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> +
> + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> +
> + intel_uc_fw_fetch(dev_priv, huc_fw);
> +}
> +
> +/**
> + * intel_huc_load() - load HuC uCode to device
> + * @dev: the drm device
> + *
> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> + * Be note that HuC loading must be done before GuC loading.
> + *
> + * The firmware image should have already been fetched into memory by the
> + * earlier call to intel_huc_init(), so here we need only check that
> + * is succeeded, and then transfer the image to the h/w.
> + *
> + * Return: non-zero code on error
> + */
> +int intel_huc_load(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + int err;
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> + return 0;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> + huc_fw->load_status == UC_FIRMWARE_FAIL)
> + return -ENOEXEC;
> +
> + huc_fw->load_status = UC_FIRMWARE_PENDING;
> +
> + switch (huc_fw->fetch_status) {
> + case UC_FIRMWARE_FAIL:
> + /* something went wrong :( */
> + err = -EIO;
> + goto fail;
> +
> + case UC_FIRMWARE_NONE:
> + case UC_FIRMWARE_PENDING:
> + default:
> + /* "can't happen" */
> + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + huc_fw->fetch_status);
> + err = -ENXIO;
> + goto fail;
> +
> + case UC_FIRMWARE_SUCCESS:
> + break;
> + }
> +
> + err = huc_ucode_xfer(dev_priv);
> + if (err)
> + goto fail;
> +
> + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + return 0;
> +
> +fail:
> + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> + huc_fw->load_status = UC_FIRMWARE_FAIL;
> +
> + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> +
> + return err;
> +}
> +
> +/**
> + * intel_huc_fini() - clean up resources allocated for HuC
> + * @dev: the drm device
> + *
> + * Cleans up by releasing the huc firmware GEM obj.
> + */
> +void intel_huc_fini(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + mutex_lock(&dev->struct_mutex);
> + if (huc_fw->uc_fw_obj)
> + i915_gem_object_put(huc_fw->uc_fw_obj);
> + huc_fw->uc_fw_obj = NULL;
> + mutex_unlock(&dev->struct_mutex);
> +
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> +}
> +
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index be89f0b..ac92946 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -24,6 +24,12 @@
> #ifndef _INTEL_UC_H_
> #define _INTEL_UC_H_
>
> +#ifndef _INTEL_HUC_H_
> +#define _INTEL_HUC_H_
> +
> +#define HUC_STATUS2 _MMIO(0xD3B0)
> +#define HUC_FW_VERIFIED (1<<7)
> +
> #include "intel_guc_fwif.h"
> #include "i915_guc_reg.h"
> #include "intel_ringbuffer.h"
> @@ -175,6 +181,13 @@ struct intel_guc {
> struct mutex send_mutex;
> };
>
> +struct intel_huc {
> + /* Generic uC firmware management */
> + struct intel_uc_fw huc_fw;
> +
> + /* HuC-specific additions */
> +};
> +
> /* intel_uc.c */
> void intel_uc_init_early(struct drm_i915_private *dev_priv);
> bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status);
> @@ -191,6 +204,9 @@ extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
> extern int intel_guc_resume(struct drm_i915_private *dev_priv);
> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> + struct intel_uc_fw *uc_fw);
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> @@ -205,4 +221,10 @@ void i915_guc_register(struct drm_i915_private *dev_priv);
> void i915_guc_unregister(struct drm_i915_private *dev_priv);
> int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
>
> +/* intel_huc_loader.c */
> +void intel_huc_init(struct drm_i915_private *dev_priv);
> +void intel_huc_fini(struct drm_device *dev);
> +int intel_huc_load(struct drm_i915_private *dev_priv);
> +
> +#endif
> #endif
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-09 10:56 ` Arkadiusz Hiler
@ 2016-12-09 11:10 ` Chris Wilson
2016-12-09 11:34 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Chris Wilson @ 2016-12-09 11:10 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: intel-gfx
On Fri, Dec 09, 2016 at 11:56:10AM +0100, Arkadiusz Hiler wrote:
> On Thu, Dec 08, 2016 at 03:02:14PM -0800, anushasr wrote:
> > -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > {
> > u32 wopcm_size = GUC_WOPCM_TOP;
> >
> > @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > if (err)
> > goto fail;
> >
> > + intel_huc_load(dev_priv);
We don't need error handling? That would simplify a lot of our code!
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-12-08 23:02 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general anushasr
2016-12-09 8:58 ` Arkadiusz Hiler
@ 2016-12-09 11:28 ` Michal Wajdeczko
2016-12-09 11:49 ` Arkadiusz Hiler
1 sibling, 1 reply; 71+ messages in thread
From: Michal Wajdeczko @ 2016-12-09 11:28 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Alex Dai, Peter Antoine
On Thu, Dec 08, 2016 at 03:02:12PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
> s/intel_guc_fw/intel_uc_fw/g
> s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> v2: rebased on top of nightly.
> reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
> v4: removed G from messages in shared fw fetch function.
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
> and intel_guc_init().
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
> drivers/gpu/drm/i915/intel_guc_loader.c | 157 +++++++++++++++--------------
> drivers/gpu/drm/i915/intel_uc.h | 40 ++++----
> 4 files changed, 108 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a746130..0e5ef62 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2338,7 +2338,7 @@ static int i915_llc(struct seq_file *m, void *data)
> static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> u32 tmp, i;
>
> if (!HAS_GUC_UCODE(dev_priv))
> @@ -2346,15 +2346,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
>
> seq_printf(m, "GuC firmware status:\n");
> seq_printf(m, "\tpath: %s\n",
> - guc_fw->guc_fw_path);
> + guc_fw->uc_fw_path);
> seq_printf(m, "\tfetch: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status));
> seq_printf(m, "\tload: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->load_status));
> seq_printf(m, "\tversion wanted: %d.%d\n",
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> seq_printf(m, "\tversion found: %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> seq_printf(m, "\theader: offset is %d; size = %d\n",
> guc_fw->header_offset, guc_fw->header_size);
> seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 7fa4e74..e156a4b 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1493,7 +1493,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> gen9_disable_guc_interrupts(dev_priv);
> @@ -1520,7 +1520,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> if (i915.guc_log_level >= 0)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 21db697..8f04f6e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>
> /* User-friendly representation of an enum */
> -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> {
> switch (status) {
> - case GUC_FIRMWARE_FAIL:
> + case UC_FIRMWARE_FAIL:
> return "FAIL";
> - case GUC_FIRMWARE_NONE:
> + case UC_FIRMWARE_NONE:
> return "NONE";
> - case GUC_FIRMWARE_PENDING:
> + case UC_FIRMWARE_PENDING:
> return "PENDING";
> - case GUC_FIRMWARE_SUCCESS:
> + case UC_FIRMWARE_SUCCESS:
> return "SUCCESS";
> default:
> return "UNKNOWN!";
> @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> struct i915_vma *vma)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> unsigned long offset;
> struct sg_table *sg = vma->pages;
> u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> @@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> */
> static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> struct i915_vma *vma;
> int ret;
>
> - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
> if (ret) {
> DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> return ret;
> }
>
> - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
> + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
> if (IS_ERR(vma)) {
> DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> return PTR_ERR(vma);
> @@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
> */
> int intel_guc_setup(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - const char *fw_path = guc_fw->guc_fw_path;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + const char *fw_path = guc_fw->uc_fw_path;
> int retries, ret, err;
>
> DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
> fw_path,
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> /* Loading forbidden, or no firmware to load? */
> if (!i915.enable_guc_loading) {
> @@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> }
>
> /* Fetch failed, or already fetched but failed to load? */
> - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
> err = -EIO;
> goto fail;
> - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
> err = -ENOEXEC;
> goto fail;
> }
> @@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> guc_interrupts_release(dev_priv);
> gen9_reset_guc_interrupts(dev_priv);
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> + guc_fw->load_status = UC_FIRMWARE_PENDING;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> err = i915_guc_submission_init(dev_priv);
> if (err)
> @@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> "retry %d more time(s)\n", err, retries);
> }
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> if (i915.enable_guc_submission) {
> if (i915.guc_log_level >= 0)
> @@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> return 0;
>
> fail:
> - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> + guc_fw->load_status = UC_FIRMWARE_FAIL;
>
> guc_interrupts_release(dev_priv);
> i915_guc_submission_disable(dev_priv);
> @@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> return ret;
> }
>
> -static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> - struct intel_guc_fw *guc_fw)
> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> + struct intel_uc_fw *uc_fw)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> struct drm_i915_gem_object *obj;
> @@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> size_t size;
> int err;
>
> - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
> + intel_uc_fw_status_repr(uc_fw->fetch_status));
>
> - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
> + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
> if (err)
> goto fail;
> if (!fw)
> goto fail;
>
> - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> - guc_fw->guc_fw_path, fw);
> + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> + uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> if (fw->size < sizeof(struct guc_css_header)) {
> @@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> css = (struct guc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> - guc_fw->header_offset = 0;
> - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> + uc_fw->header_offset = 0;
> + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> DRM_NOTE("CSS header definition mismatch\n");
> goto fail;
> }
>
> /* then, uCode */
> - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>
> /* now RSA */
> if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> DRM_NOTE("RSA key size is bad\n");
> goto fail;
> }
> - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>
> /* At least, it should have header, uCode and RSA. Size of all three. */
> - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
> if (fw->size < size) {
> DRM_NOTE("Missing firmware components\n");
> goto fail;
> }
>
> /* Header and uCode will be loaded to WOPCM. Size of the two. */
> - size = guc_fw->header_size + guc_fw->ucode_size;
> + size = uc_fw->header_size + uc_fw->ucode_size;
> if (size > guc_wopcm_size(dev_priv)) {
> DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> goto fail;
> @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> * in terms of bytes (u8).
> */
> - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> -
> - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> - DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> +
> + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> + DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> err = -ENOEXEC;
> goto fail;
> }
>
> DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>
> mutex_lock(&dev_priv->drm.struct_mutex);
> obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
> @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> goto fail;
> }
>
> - guc_fw->guc_fw_obj = obj;
> - guc_fw->guc_fw_size = fw->size;
> + uc_fw->uc_fw_obj = obj;
> + uc_fw->uc_fw_size = fw->size;
>
> - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> - guc_fw->guc_fw_obj);
> + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
> + uc_fw->uc_fw_obj);
>
> release_firmware(fw);
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> return;
>
> fail:
> - DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
> - guc_fw->guc_fw_path, err);
> - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> - err, fw, guc_fw->guc_fw_obj);
> + DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
> + uc_fw->uc_fw_path, err);
> + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> + err, fw, uc_fw->uc_fw_obj);
>
> mutex_lock(&dev_priv->drm.struct_mutex);
> - obj = guc_fw->guc_fw_obj;
> + obj = uc_fw->uc_fw_obj;
> if (obj)
> i915_gem_object_put(obj);
> - guc_fw->guc_fw_obj = NULL;
> + uc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev_priv->drm.struct_mutex);
>
> release_firmware(fw); /* OK even if fw is NULL */
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> }
>
> /**
> @@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> */
> void intel_guc_init(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> const char *fw_path;
>
> if (!HAS_GUC(dev_priv)) {
> @@ -739,23 +739,24 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> fw_path = NULL;
> } else if (IS_SKYLAKE(dev_priv)) {
> fw_path = I915_SKL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> + guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> + guc_fw->minor_ver_wanted = SKL_FW_MINOR;
> } else if (IS_BROXTON(dev_priv)) {
> fw_path = I915_BXT_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> + guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> + guc_fw->minor_ver_wanted = BXT_FW_MINOR;
> } else if (IS_KABYLAKE(dev_priv)) {
> fw_path = I915_KBL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> + guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> + guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> } else {
> fw_path = ""; /* unknown device */
> }
>
> - guc_fw->guc_fw_path = fw_path;
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> + guc_fw->uc_dev = &dev_priv->drm;
> + guc_fw->uc_fw_path = fw_path;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> + guc_fw->load_status = UC_FIRMWARE_NONE;
>
> /* Early (and silent) return if GuC loading is disabled */
> if (!i915.enable_guc_loading)
> @@ -765,9 +766,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> if (*fw_path == '\0')
> return;
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> - guc_fw_fetch(dev_priv, guc_fw);
> + intel_uc_fw_fetch(dev_priv, guc_fw);
> /* status must now be FAIL or SUCCESS */
> }
>
> @@ -777,17 +778,17 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> */
> void intel_guc_fini(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>
> mutex_lock(&dev_priv->drm.struct_mutex);
> guc_interrupts_release(dev_priv);
> i915_guc_submission_disable(dev_priv);
> i915_guc_submission_fini(dev_priv);
>
> - if (guc_fw->guc_fw_obj)
> - i915_gem_object_put(guc_fw->guc_fw_obj);
> - guc_fw->guc_fw_obj = NULL;
> + if (guc_fw->uc_fw_obj)
> + i915_gem_object_put(guc_fw->uc_fw_obj);
> + guc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev_priv->drm.struct_mutex);
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 11f5608..f9f598d 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -91,29 +91,31 @@ struct i915_guc_client {
> uint64_t submissions[I915_NUM_ENGINES];
> };
>
> -enum intel_guc_fw_status {
> - GUC_FIRMWARE_FAIL = -1,
> - GUC_FIRMWARE_NONE = 0,
> - GUC_FIRMWARE_PENDING,
> - GUC_FIRMWARE_SUCCESS
> +enum intel_uc_fw_status {
> + UC_FIRMWARE_FAIL = -1,
> + UC_FIRMWARE_NONE = 0,
> + UC_FIRMWARE_PENDING,
> + UC_FIRMWARE_SUCCESS
Shouldn't we use INTEL_UC_ prefix here (in similar way as in GUC_ACTION)?
> };
>
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> */
> -struct intel_guc_fw {
> - const char * guc_fw_path;
> - size_t guc_fw_size;
> - struct drm_i915_gem_object * guc_fw_obj;
> - enum intel_guc_fw_status guc_fw_fetch_status;
> - enum intel_guc_fw_status guc_fw_load_status;
> -
> - uint16_t guc_fw_major_wanted;
> - uint16_t guc_fw_minor_wanted;
> - uint16_t guc_fw_major_found;
> - uint16_t guc_fw_minor_found;
> -
> +struct intel_uc_fw {
> + struct drm_device *uc_dev;
Why do you need this back pointer to drm_dev ?
More likely all you need is pointer to dev_priv.
But for dev_priv you can always use guc_to_i915().
> + const char *uc_fw_path;
> + size_t uc_fw_size;
> + struct drm_i915_gem_object *uc_fw_obj;
All these uc_fw_ prefixes seem to be redundant as this struct is just about uc_fw.
> + enum intel_uc_fw_status fetch_status;
> + enum intel_uc_fw_status load_status;
> +
> + uint16_t major_ver_wanted;
> + uint16_t minor_ver_wanted;
> + uint16_t major_ver_found;
> + uint16_t minor_ver_found;
> +
> + uint32_t fw_type;
What is the purpose of this field ?
> uint32_t header_size;
> uint32_t header_offset;
> uint32_t rsa_size;
> @@ -139,7 +141,7 @@ struct intel_guc_log {
> };
>
> struct intel_guc {
> - struct intel_guc_fw guc_fw;
> + struct intel_uc_fw guc_fw;
Btw, guc_ prefix in field name here is also redundant.
> struct intel_guc_log log;
>
> /* intel_guc_recv interrupt related state */
> @@ -181,7 +183,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> extern void intel_guc_init(struct drm_i915_private *dev_priv);
> extern int intel_guc_setup(struct drm_i915_private *dev_priv);
> extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
> extern int intel_guc_resume(struct drm_i915_private *dev_priv);
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-09 11:10 ` Chris Wilson
@ 2016-12-09 11:34 ` Arkadiusz Hiler
2016-12-09 12:19 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 11:34 UTC (permalink / raw)
To: Chris Wilson, anushasr, intel-gfx
On Fri, Dec 09, 2016 at 11:10:03AM +0000, Chris Wilson wrote:
> On Fri, Dec 09, 2016 at 11:56:10AM +0100, Arkadiusz Hiler wrote:
> > On Thu, Dec 08, 2016 at 03:02:14PM -0800, anushasr wrote:
> > > -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > {
> > > u32 wopcm_size = GUC_WOPCM_TOP;
> > >
> > > @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > if (err)
> > > goto fail;
> > >
> > > + intel_huc_load(dev_priv);
>
> We don't need error handling? That would simplify a lot of our code!
> -Chris
With this patch series on this specific piece of code - not really.
HuC support it intorduce is _best-eforrty_.
If the function would report error we would not act on it in anyway
other than logging the fail (which the function already does for us).
As Anusha discussed here, there will be some code reorganization due to
introduction of i915.enable_huc and deprecation of enable_guc_loading.
Once we want to have enable_huc=2, there is a reason to change the
signature and report errors.
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-12-09 11:28 ` Michal Wajdeczko
@ 2016-12-09 11:49 ` Arkadiusz Hiler
2016-12-09 13:06 ` Michal Wajdeczko
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 11:49 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: Alex Dai, intel-gfx, Peter Antoine
On Fri, Dec 09, 2016 at 12:28:52PM +0100, Michal Wajdeczko wrote:
> On Thu, Dec 08, 2016 at 03:02:12PM -0800, anushasr wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > Rename some of the GuC fw loading code to make them more general. We
> > will utilise them for HuC loading as well.
> > s/intel_guc_fw/intel_uc_fw/g
> > s/GUC_FIRMWARE/UC_FIRMWARE/g
> >
> > Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> > such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> > same purpose.
> >
> > v2: rebased on top of nightly.
> > reapplied the search/replace as upstream code as changed.
> > v3: rebased again on drm-nightly.
> > v4: removed G from messages in shared fw fetch function.
> > v5: rebased.
> > v7: rebased.
> > v8: rebased.
> > v9: rebased.
> > v10: rebased.
> > v11: rebased.
> > v12: rebased on top of drm-tip
> > v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
> > and intel_guc_init().
> >
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> > drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
> > drivers/gpu/drm/i915/intel_guc_loader.c | 157 +++++++++++++++--------------
> > drivers/gpu/drm/i915/intel_uc.h | 40 ++++----
> > 4 files changed, 108 insertions(+), 105 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index a746130..0e5ef62 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2338,7 +2338,7 @@ static int i915_llc(struct seq_file *m, void *data)
> > static int i915_guc_load_status_info(struct seq_file *m, void *data)
> > {
> > struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > u32 tmp, i;
> >
> > if (!HAS_GUC_UCODE(dev_priv))
> > @@ -2346,15 +2346,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
> >
> > seq_printf(m, "GuC firmware status:\n");
> > seq_printf(m, "\tpath: %s\n",
> > - guc_fw->guc_fw_path);
> > + guc_fw->uc_fw_path);
> > seq_printf(m, "\tfetch: %s\n",
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> > + intel_uc_fw_status_repr(guc_fw->fetch_status));
> > seq_printf(m, "\tload: %s\n",
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > + intel_uc_fw_status_repr(guc_fw->load_status));
> > seq_printf(m, "\tversion wanted: %d.%d\n",
> > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> > seq_printf(m, "\tversion found: %d.%d\n",
> > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> > + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> > seq_printf(m, "\theader: offset is %d; size = %d\n",
> > guc_fw->header_offset, guc_fw->header_size);
> > seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> > index 7fa4e74..e156a4b 100644
> > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > @@ -1493,7 +1493,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
> > struct i915_gem_context *ctx;
> > u32 data[3];
> >
> > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> > return 0;
> >
> > gen9_disable_guc_interrupts(dev_priv);
> > @@ -1520,7 +1520,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
> > struct i915_gem_context *ctx;
> > u32 data[3];
> >
> > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> > return 0;
> >
> > if (i915.guc_log_level >= 0)
> > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > index 21db697..8f04f6e 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> > MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
> >
> > /* User-friendly representation of an enum */
> > -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> > +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> > {
> > switch (status) {
> > - case GUC_FIRMWARE_FAIL:
> > + case UC_FIRMWARE_FAIL:
> > return "FAIL";
> > - case GUC_FIRMWARE_NONE:
> > + case UC_FIRMWARE_NONE:
> > return "NONE";
> > - case GUC_FIRMWARE_PENDING:
> > + case UC_FIRMWARE_PENDING:
> > return "PENDING";
> > - case GUC_FIRMWARE_SUCCESS:
> > + case UC_FIRMWARE_SUCCESS:
> > return "SUCCESS";
> > default:
> > return "UNKNOWN!";
> > @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> > static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> > struct i915_vma *vma)
> > {
> > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > unsigned long offset;
> > struct sg_table *sg = vma->pages;
> > u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> > @@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > */
> > static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> > {
> > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > struct i915_vma *vma;
> > int ret;
> >
> > - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> > + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
> > if (ret) {
> > DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> > return ret;
> > }
> >
> > - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
> > + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
> > if (IS_ERR(vma)) {
> > DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> > return PTR_ERR(vma);
> > @@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
> > */
> > int intel_guc_setup(struct drm_i915_private *dev_priv)
> > {
> > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > - const char *fw_path = guc_fw->guc_fw_path;
> > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > + const char *fw_path = guc_fw->uc_fw_path;
> > int retries, ret, err;
> >
> > DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
> > fw_path,
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > + intel_uc_fw_status_repr(guc_fw->load_status));
> >
> > /* Loading forbidden, or no firmware to load? */
> > if (!i915.enable_guc_loading) {
> > @@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > }
> >
> > /* Fetch failed, or already fetched but failed to load? */
> > - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> > + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
> > err = -EIO;
> > goto fail;
> > - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> > + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
> > err = -ENOEXEC;
> > goto fail;
> > }
> > @@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > guc_interrupts_release(dev_priv);
> > gen9_reset_guc_interrupts(dev_priv);
> >
> > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> > + guc_fw->load_status = UC_FIRMWARE_PENDING;
> >
> > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > + intel_uc_fw_status_repr(guc_fw->load_status));
> >
> > err = i915_guc_submission_init(dev_priv);
> > if (err)
> > @@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > "retry %d more time(s)\n", err, retries);
> > }
> >
> > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> > + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
> >
> > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > + intel_uc_fw_status_repr(guc_fw->load_status));
> >
> > if (i915.enable_guc_submission) {
> > if (i915.guc_log_level >= 0)
> > @@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > return 0;
> >
> > fail:
> > - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> > + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> > + guc_fw->load_status = UC_FIRMWARE_FAIL;
> >
> > guc_interrupts_release(dev_priv);
> > i915_guc_submission_disable(dev_priv);
> > @@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > return ret;
> > }
> >
> > -static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > - struct intel_guc_fw *guc_fw)
> > +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> > + struct intel_uc_fw *uc_fw)
> > {
> > struct pci_dev *pdev = dev_priv->drm.pdev;
> > struct drm_i915_gem_object *obj;
> > @@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > size_t size;
> > int err;
> >
> > - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> > + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
> > + intel_uc_fw_status_repr(uc_fw->fetch_status));
> >
> > - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
> > + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
> > if (err)
> > goto fail;
> > if (!fw)
> > goto fail;
> >
> > - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> > - guc_fw->guc_fw_path, fw);
> > + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> > + uc_fw->uc_fw_path, fw);
> >
> > /* Check the size of the blob before examining buffer contents */
> > if (fw->size < sizeof(struct guc_css_header)) {
> > @@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > css = (struct guc_css_header *)fw->data;
> >
> > /* Firmware bits always start from header */
> > - guc_fw->header_offset = 0;
> > - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> > + uc_fw->header_offset = 0;
> > + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> > css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
> >
> > - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> > + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> > DRM_NOTE("CSS header definition mismatch\n");
> > goto fail;
> > }
> >
> > /* then, uCode */
> > - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> > - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> > + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> > + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> >
> > /* now RSA */
> > if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> > DRM_NOTE("RSA key size is bad\n");
> > goto fail;
> > }
> > - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> > - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> > + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> > + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> >
> > /* At least, it should have header, uCode and RSA. Size of all three. */
> > - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> > + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
> > if (fw->size < size) {
> > DRM_NOTE("Missing firmware components\n");
> > goto fail;
> > }
> >
> > /* Header and uCode will be loaded to WOPCM. Size of the two. */
> > - size = guc_fw->header_size + guc_fw->ucode_size;
> > + size = uc_fw->header_size + uc_fw->ucode_size;
> > if (size > guc_wopcm_size(dev_priv)) {
> > DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> > goto fail;
> > @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> > * in terms of bytes (u8).
> > */
> > - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> > - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> > -
> > - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> > - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> > - DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
> > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> > + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> > +
> > + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> > + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> > + DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
> > + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> > + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> > err = -ENOEXEC;
> > goto fail;
> > }
> >
> > DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> > + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> >
> > mutex_lock(&dev_priv->drm.struct_mutex);
> > obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
> > @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > goto fail;
> > }
> >
> > - guc_fw->guc_fw_obj = obj;
> > - guc_fw->guc_fw_size = fw->size;
> > + uc_fw->uc_fw_obj = obj;
> > + uc_fw->uc_fw_size = fw->size;
> >
> > - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> > - guc_fw->guc_fw_obj);
> > + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
> > + uc_fw->uc_fw_obj);
> >
> > release_firmware(fw);
> > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> > + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> > return;
> >
> > fail:
> > - DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
> > - guc_fw->guc_fw_path, err);
> > - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> > - err, fw, guc_fw->guc_fw_obj);
> > + DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
> > + uc_fw->uc_fw_path, err);
> > + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> > + err, fw, uc_fw->uc_fw_obj);
> >
> > mutex_lock(&dev_priv->drm.struct_mutex);
> > - obj = guc_fw->guc_fw_obj;
> > + obj = uc_fw->uc_fw_obj;
> > if (obj)
> > i915_gem_object_put(obj);
> > - guc_fw->guc_fw_obj = NULL;
> > + uc_fw->uc_fw_obj = NULL;
> > mutex_unlock(&dev_priv->drm.struct_mutex);
> >
> > release_firmware(fw); /* OK even if fw is NULL */
> > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> > + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> > }
> >
> > /**
> > @@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > */
> > void intel_guc_init(struct drm_i915_private *dev_priv)
> > {
> > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > const char *fw_path;
> >
> > if (!HAS_GUC(dev_priv)) {
> > @@ -739,23 +739,24 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > fw_path = NULL;
> > } else if (IS_SKYLAKE(dev_priv)) {
> > fw_path = I915_SKL_GUC_UCODE;
> > - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> > - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> > + guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> > + guc_fw->minor_ver_wanted = SKL_FW_MINOR;
> > } else if (IS_BROXTON(dev_priv)) {
> > fw_path = I915_BXT_GUC_UCODE;
> > - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> > - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> > + guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> > + guc_fw->minor_ver_wanted = BXT_FW_MINOR;
> > } else if (IS_KABYLAKE(dev_priv)) {
> > fw_path = I915_KBL_GUC_UCODE;
> > - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> > - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> > + guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> > + guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> > } else {
> > fw_path = ""; /* unknown device */
> > }
> >
> > - guc_fw->guc_fw_path = fw_path;
> > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> > + guc_fw->uc_dev = &dev_priv->drm;
> > + guc_fw->uc_fw_path = fw_path;
> > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > + guc_fw->load_status = UC_FIRMWARE_NONE;
> >
> > /* Early (and silent) return if GuC loading is disabled */
> > if (!i915.enable_guc_loading)
> > @@ -765,9 +766,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > if (*fw_path == '\0')
> > return;
> >
> > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> > + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> > DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> > - guc_fw_fetch(dev_priv, guc_fw);
> > + intel_uc_fw_fetch(dev_priv, guc_fw);
> > /* status must now be FAIL or SUCCESS */
> > }
> >
> > @@ -777,17 +778,17 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > */
> > void intel_guc_fini(struct drm_i915_private *dev_priv)
> > {
> > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> >
> > mutex_lock(&dev_priv->drm.struct_mutex);
> > guc_interrupts_release(dev_priv);
> > i915_guc_submission_disable(dev_priv);
> > i915_guc_submission_fini(dev_priv);
> >
> > - if (guc_fw->guc_fw_obj)
> > - i915_gem_object_put(guc_fw->guc_fw_obj);
> > - guc_fw->guc_fw_obj = NULL;
> > + if (guc_fw->uc_fw_obj)
> > + i915_gem_object_put(guc_fw->uc_fw_obj);
> > + guc_fw->uc_fw_obj = NULL;
> > mutex_unlock(&dev_priv->drm.struct_mutex);
> >
> > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> > index 11f5608..f9f598d 100644
> > --- a/drivers/gpu/drm/i915/intel_uc.h
> > +++ b/drivers/gpu/drm/i915/intel_uc.h
> > @@ -91,29 +91,31 @@ struct i915_guc_client {
> > uint64_t submissions[I915_NUM_ENGINES];
> > };
> >
> > -enum intel_guc_fw_status {
> > - GUC_FIRMWARE_FAIL = -1,
> > - GUC_FIRMWARE_NONE = 0,
> > - GUC_FIRMWARE_PENDING,
> > - GUC_FIRMWARE_SUCCESS
> > +enum intel_uc_fw_status {
> > + UC_FIRMWARE_FAIL = -1,
> > + UC_FIRMWARE_NONE = 0,
> > + UC_FIRMWARE_PENDING,
> > + UC_FIRMWARE_SUCCESS
>
> Shouldn't we use INTEL_UC_ prefix here (in similar way as in GUC_ACTION)?
>
>
> > };
> >
> > /*
> > * This structure encapsulates all the data needed during the process
> > * of fetching, caching, and loading the firmware image into the GuC.
> > */
> > -struct intel_guc_fw {
> > - const char * guc_fw_path;
> > - size_t guc_fw_size;
> > - struct drm_i915_gem_object * guc_fw_obj;
> > - enum intel_guc_fw_status guc_fw_fetch_status;
> > - enum intel_guc_fw_status guc_fw_load_status;
> > -
> > - uint16_t guc_fw_major_wanted;
> > - uint16_t guc_fw_minor_wanted;
> > - uint16_t guc_fw_major_found;
> > - uint16_t guc_fw_minor_found;
> > -
> > +struct intel_uc_fw {
> > + struct drm_device *uc_dev;
>
> Why do you need this back pointer to drm_dev ?
> More likely all you need is pointer to dev_priv.
> But for dev_priv you can always use guc_to_i915().
It seems like a left over from the old days. I have a series that
refactors all things GuC that I'll push here soon, including the removal
of this field.
Since this series advertises as a simple renaming I didn't force it
here.
> > + const char *uc_fw_path;
> > + size_t uc_fw_size;
> > + struct drm_i915_gem_object *uc_fw_obj;
>
> All these uc_fw_ prefixes seem to be redundant as this struct is just about uc_fw.
>
>
> > + enum intel_uc_fw_status fetch_status;
> > + enum intel_uc_fw_status load_status;
> > +
> > + uint16_t major_ver_wanted;
> > + uint16_t minor_ver_wanted;
> > + uint16_t major_ver_found;
> > + uint16_t minor_ver_found;
> > +
> > + uint32_t fw_type;
>
> What is the purpose of this field ?
It is used in the patch 2, to set {major,minor}_ver_found depending on
which firmware we pass to intel_uc_fw_fetch()
>
> > uint32_t header_size;
> > uint32_t header_offset;
> > uint32_t rsa_size;
> > @@ -139,7 +141,7 @@ struct intel_guc_log {
> > };
> >
> > struct intel_guc {
> > - struct intel_guc_fw guc_fw;
> > + struct intel_uc_fw guc_fw;
>
> Btw, guc_ prefix in field name here is also redundant.
>
>
> > struct intel_guc_log log;
> >
> > /* intel_guc_recv interrupt related state */
> > @@ -181,7 +183,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> > extern void intel_guc_init(struct drm_i915_private *dev_priv);
> > extern int intel_guc_setup(struct drm_i915_private *dev_priv);
> > extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> > -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> > +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> > extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
> > extern int intel_guc_resume(struct drm_i915_private *dev_priv);
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-12-08 23:02 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC anushasr
2016-12-09 9:20 ` Arkadiusz Hiler
@ 2016-12-09 11:55 ` Michal Wajdeczko
2016-12-09 21:42 ` Srivatsa, Anusha
1 sibling, 1 reply; 71+ messages in thread
From: Michal Wajdeczko @ 2016-12-09 11:55 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Alex Dai, Peter Antoine
On Thu, Dec 08, 2016 at 03:02:13PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
>
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> v4: rebased + spaces.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename device_id to guc_branch_client_version,
> make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC
> and UC_FW_TYPE_HUC into an enum.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip.
> v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++----
> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_uc.h | 5 ++++
> 3 files changed, 50 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 3202b32..c1e7faf 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -145,7 +145,7 @@
> * The GuC firmware layout looks like this:
> *
> * +-------------------------------+
> - * | guc_css_header |
> + * | uc_css_header |
> * | |
> * | contains major/minor version |
> * +-------------------------------+
> @@ -172,9 +172,16 @@
> * 3. Length info of each component can be found in header, in dwords.
> * 4. Modulus and exponent key are not required by driver. They may not appear
> * in fw. So driver will load a truncated firmware in this case.
> + *
> + * HuC firmware layout is same as GuC firmware.
> + *
> + * HuC firmware css header is different. However, the only difference is where
> + * the version information is saved. The uc_css_header is unified to support
> + * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
> + * uc_css_header.guc_sw_version for GuC.
> */
>
> -struct guc_css_header {
> +struct uc_css_header {
Hmm, I'm wondering why we don't use "intel_uc_" prefix for structs defined here.
It seems that only enums are defined with intel_ prefix.
Also, it looks that this struct definition is very similar to the intel_css_header
defined in intel_csr.c. Are there any plans to unify them all ?
> uint32_t module_type;
What values are used here? Are they the same as used in fw_type?
> /* header_size includes all non-uCode bits, including css_header, rsa
> * key, modulus key and exponent data. */
> @@ -205,8 +212,14 @@ struct guc_css_header {
>
> char username[8];
> char buildnumber[12];
> - uint32_t device_id;
> - uint32_t guc_sw_version;
> + union {
> + uint32_t guc_branch_client_version;
> + uint32_t huc_sw_version;
> + };
> + union {
> + uint32_t guc_sw_version;
> + uint32_t huc_reserved;
> + };
Maybe to make this a little easier to read we can use:
union {
struct {
uint32_t branch_client_version;
uint32_t sw_version;
} guc;
struct {
uint32_t sw_version;
unit32_t reserved;
} huc;
};
> uint32_t prod_preprod_fw;
> uint32_t reserved[12];
> uint32_t header_info;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 8f04f6e..26a184f 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> struct pci_dev *pdev = dev_priv->drm.pdev;
> struct drm_i915_gem_object *obj;
> const struct firmware *fw = NULL;
> - struct guc_css_header *css;
> + struct uc_css_header *css;
> size_t size;
> int err;
>
> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> - if (fw->size < sizeof(struct guc_css_header)) {
> + if (fw->size < sizeof(struct uc_css_header)) {
> DRM_NOTE("Firmware header is missing\n");
> goto fail;
> }
>
> - css = (struct guc_css_header *)fw->data;
> + css = (struct uc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> uc_fw->header_offset = 0;
> uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> - if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct uc_css_header)) {
> DRM_NOTE("CSS header definition mismatch\n");
> goto fail;
> }
> @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> goto fail;
> }
>
> - /* Header and uCode will be loaded to WOPCM. Size of the two. */
> - size = uc_fw->header_size + uc_fw->ucode_size;
> - if (size > guc_wopcm_size(dev_priv)) {
> - DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> - goto fail;
> - }
> -
> /*
> * The GuC firmware image has the version number embedded at a well-known
> * offset within the firmware blob; note that major / minor version are
> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> * in terms of bytes (u8).
> */
> - uc_fw->major_ver_found = css->guc_sw_version >> 16;
> - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> + switch (uc_fw->fw_type) {
> + case UC_FW_TYPE_GUC:
> + /* Header and uCode will be loaded to WOPCM. Size of the two. */
> + size = uc_fw->header_size + uc_fw->ucode_size;
> +
> + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
> + if (size > guc_wopcm_size(dev_priv)) {
> + DRM_ERROR("Firmware is too large to fit in WOPCM\n");
> + goto fail;
> + }
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> + break;
> +
> + case UC_FW_TYPE_HUC:
> + uc_fw->major_ver_found = css->huc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
> + break;
> +
> + default:
> + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
> + err = -ENOEXEC;
> + goto fail;
> + }
>
> if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index f9f598d..be89f0b 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -98,6 +98,11 @@ enum intel_uc_fw_status {
> UC_FIRMWARE_SUCCESS
> };
>
> +enum {
> + UC_FW_TYPE_GUC,
> + UC_FW_TYPE_HUC
Can we have INTEL_ prefix here?
> +};
> +
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-08 23:02 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support anushasr
2016-12-09 10:56 ` Arkadiusz Hiler
@ 2016-12-09 12:17 ` Michal Wajdeczko
2016-12-09 23:56 ` Srivatsa, Anusha
2016-12-12 18:52 ` Tvrtko Ursulin
2 siblings, 1 reply; 71+ messages in thread
From: Michal Wajdeczko @ 2016-12-09 12:17 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Alex Dai, Peter Antoine
On Thu, Dec 08, 2016 at 03:02:14PM -0800, anushasr wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
>
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
>
> v2: rebased on-top of drm-intel-nightly.
> removed if(HAS_GUC()) before the guc call. (D.Gordon)
> update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
> match the one in the huc package.
> Changed dev->dev_private to to_i915()
> v4: moved function back to where it was.
> change wait_for_atomic to wait_for.
> v5: rebased + comment changes.
> v7: rebased.
> v8: rebased.
> v9: rebased. Changed the year in the copyright message to reflect
> the right year.Correct the comments,remove the unwanted WARN message,
> replace drm_gem_object_unreference() with i915_gem_object_put().Make the
> prototypes in intel_huc.h non-extern.
> v10: rebased. Update the file construction done by HuC. It is similar to
> GuC.Adopted the approach used in-
> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
> v11: Fix warnings remove old declaration
> v12: Change dev to dev_priv in macro definition.
> Corrected comments.
> v13: rebased.
> v14: rebased on top of drm-tip
> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
> of intel_huc.h to intel_uc.h
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 7 +-
> drivers/gpu/drm/i915/intel_huc_loader.c | 264 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_uc.h | 22 +++
> 7 files changed, 299 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 3c30916..01d4f4b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
> # general-purpose microcontroller (GuC) support
> i915-y += intel_uc.o \
> intel_guc_loader.o \
> + intel_huc_loader.o \
> i915_guc_submission.o
>
> # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6428588..85a47c2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> if (ret)
> goto cleanup_irq;
>
> + intel_huc_init(dev_priv);
> intel_guc_init(dev_priv);
>
> ret = i915_gem_init(dev_priv);
> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> i915_gem_fini(dev_priv);
> cleanup_irq:
> + intel_huc_fini(dev);
> intel_guc_fini(dev_priv);
> drm_irq_uninstall(dev);
> intel_teardown_gmbus(dev_priv);
> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
>
> /* Flush any outstanding unpin_work. */
> drain_workqueue(dev_priv->wq);
> -
> + intel_huc_fini(dev);
> intel_guc_fini(dev_priv);
> i915_gem_fini(dev_priv);
> intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1480e73..0371ca4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2036,6 +2036,7 @@ struct drm_i915_private {
>
> struct intel_gvt *gvt;
>
> + struct intel_huc huc;
> struct intel_guc guc;
>
> struct intel_csr csr;
> @@ -2810,7 +2811,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
> -
> +#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
>
> #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 5e638fc..f9829f6 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -61,9 +61,12 @@
> #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> #define DMA_COPY_SIZE _MMIO(0xc310)
> #define DMA_CTRL _MMIO(0xc314)
> +#define HUC_UKERNEL (1<<9)
> #define UOS_MOVE (1<<4)
> #define START_DMA (1<<0)
> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> +#define HUC_LOADING_AGENT_VCR (0<<1)
> +#define HUC_LOADING_AGENT_GUC (1<<1)
> #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
> #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 26a184f..b971351 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>
> /* Finally start the DMA */
> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> -
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
> + _MASKED_BIT_DISABLE(HUC_UKERNEL));
> /*
> * Wait for the DMA to complete & the GuC to start up.
> * NB: Docs recommend not using the interrupt for completion.
> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> {
> u32 wopcm_size = GUC_WOPCM_TOP;
>
> @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> if (err)
> goto fail;
>
> + intel_huc_load(dev_priv);
> err = guc_ucode_xfer(dev_priv);
> if (!err)
> break;
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> new file mode 100644
> index 0000000..e0efd1c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -0,0 +1,264 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#include <linux/firmware.h>
> +#include "i915_drv.h"
> +#include "intel_uc.h"
> +
> +/**
> + * DOC: HuC Firmware
> + *
> + * Motivation:
> + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can use the firmware
> + * capabilities by adding HuC specific commands to batch buffers.
> + *
> + * Implementation:
> + * The same firmware loader is used as the GuC. However, the actual
> + * loading to HW is deferred until GEM initialization is done.
> + *
> + * Note that HuC firmware loading must be done before GuC loading.
> + */
> +
> +#define SKL_FW_MAJOR 01
> +#define SKL_FW_MINOR 07
Can we use SKL_HUC_FW_ prefix to distinguish these macros from similar
defined in intel_guc_loader.c ?
> +#define SKL_BLD_NUM 1398
> +
> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> + __stringify(minor) "_" __stringify(bld_num) ".bin"
> +
> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
> + SKL_FW_MINOR, SKL_BLD_NUM)
> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> +
> +/**
> + * huc_ucode_xfer() - DMA's the firmware
> + * @dev_priv: the drm device
> + *
> + * This function takes the gem object containing the firmware, sets up the DMA
> + * engine MMIO, triggers the DMA operation and waits for it to finish.
> + *
> + * Transfer the firmware image to RAM for execution by the microcontroller.
> + *
> + * Return: 0 on success, non-zero on failure
> + */
> +
> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + struct i915_vma *vma;
> + unsigned long offset = 0;
> + u32 size;
> + int ret;
> +
> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> + if (ret) {
> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> + return ret;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return PTR_ERR(vma);
> + }
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> + /* init WOPCM */
> + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
> + HUC_LOADING_AGENT_GUC);
> +
> + /* Set the source address for the uCode */
> + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> +
> + /* Hardware doesn't look at destination address for HuC. Set it to 0,
> + * but still program the correct address space.
> + */
> + I915_WRITE(DMA_ADDR_1_LOW, 0);
> + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> +
> + size = huc_fw->header_size + huc_fw->ucode_size;
> + I915_WRITE(DMA_COPY_SIZE, size);
> +
> + /* Start the DMA */
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> +
> + /* Wait for DMA to finish */
> + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> +
> + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> +
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> + /*
> + * We keep the object pages for reuse during resume. But we can unpin it
> + * now that DMA has completed, so it doesn't continue to take up space.
> + */
> + i915_vma_unpin(vma);
> +
> + return ret;
> +}
> +
> +/**
> + * intel_huc_init() - initiate HuC firmware loading request
> + * @dev: the drm device
Mismatched param name.
> + *
> + * Called early during driver load, but after GEM is initialised. The loading
> + * will continue only when driver explicitly specify firmware name and version.
> + * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
> + * capable or driver yet support it. And there will be no error message for
> + * UC_FIRMWARE_NONE cases.
> + *
> + * The DMA-copying to HW is done later when intel_huc_load() is called.
> + */
> +void intel_huc_init(struct drm_i915_private *dev_priv)
> +{
> + struct intel_huc *huc = &dev_priv->huc;
Maybe *huc shall be passed as only param (to match intel_huc function name).
Then dev_priv could be recreated from huc_to_i915().
> + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> + const char *fw_path = NULL;
> +
> + huc_fw->uc_fw_path = NULL;
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> + huc_fw->load_status = UC_FIRMWARE_NONE;
> + huc_fw->fw_type = UC_FW_TYPE_HUC;
> +
> + if (!HAS_HUC_UCODE(dev_priv))
> + return;
> +
> + if (IS_SKYLAKE(dev_priv)) {
> + fw_path = I915_SKL_HUC_UCODE;
> + huc_fw->major_ver_wanted = SKL_FW_MAJOR;
> + huc_fw->minor_ver_wanted = SKL_FW_MINOR;
> + }
> +
> + huc_fw->uc_fw_path = fw_path;
> + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> +
> + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> +
> + intel_uc_fw_fetch(dev_priv, huc_fw);
> +}
> +
> +/**
> + * intel_huc_load() - load HuC uCode to device
> + * @dev: the drm device
Mismatched param name.
> + *
> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> + * Be note that HuC loading must be done before GuC loading.
> + *
> + * The firmware image should have already been fetched into memory by the
> + * earlier call to intel_huc_init(), so here we need only check that
> + * is succeeded, and then transfer the image to the h/w.
> + *
> + * Return: non-zero code on error
> + */
> +int intel_huc_load(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + int err;
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> + return 0;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> + huc_fw->load_status == UC_FIRMWARE_FAIL)
> + return -ENOEXEC;
> +
> + huc_fw->load_status = UC_FIRMWARE_PENDING;
> +
> + switch (huc_fw->fetch_status) {
> + case UC_FIRMWARE_FAIL:
> + /* something went wrong :( */
> + err = -EIO;
> + goto fail;
> +
> + case UC_FIRMWARE_NONE:
> + case UC_FIRMWARE_PENDING:
> + default:
> + /* "can't happen" */
> + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + huc_fw->fetch_status);
> + err = -ENXIO;
> + goto fail;
> +
> + case UC_FIRMWARE_SUCCESS:
> + break;
> + }
> +
> + err = huc_ucode_xfer(dev_priv);
> + if (err)
> + goto fail;
> +
> + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + return 0;
> +
> +fail:
> + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> + huc_fw->load_status = UC_FIRMWARE_FAIL;
> +
> + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> +
> + return err;
> +}
> +
> +/**
> + * intel_huc_fini() - clean up resources allocated for HuC
> + * @dev: the drm device
> + *
> + * Cleans up by releasing the huc firmware GEM obj.
> + */
> +void intel_huc_fini(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + mutex_lock(&dev->struct_mutex);
> + if (huc_fw->uc_fw_obj)
> + i915_gem_object_put(huc_fw->uc_fw_obj);
> + huc_fw->uc_fw_obj = NULL;
> + mutex_unlock(&dev->struct_mutex);
> +
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> +}
> +
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index be89f0b..ac92946 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -24,6 +24,12 @@
> #ifndef _INTEL_UC_H_
> #define _INTEL_UC_H_
>
> +#ifndef _INTEL_HUC_H_
> +#define _INTEL_HUC_H_
Typo ? This is still intel_uc.h file, right ?
> +
> +#define HUC_STATUS2 _MMIO(0xD3B0)
> +#define HUC_FW_VERIFIED (1<<7)
> +
Is it correct place for these defs?
What about i915_guc_reg.h ?
> #include "intel_guc_fwif.h"
> #include "i915_guc_reg.h"
> #include "intel_ringbuffer.h"
> @@ -175,6 +181,13 @@ struct intel_guc {
> struct mutex send_mutex;
> };
>
> +struct intel_huc {
> + /* Generic uC firmware management */
> + struct intel_uc_fw huc_fw;
> +
> + /* HuC-specific additions */
> +};
> +
> /* intel_uc.c */
> void intel_uc_init_early(struct drm_i915_private *dev_priv);
> bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status);
> @@ -191,6 +204,9 @@ extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
> extern int intel_guc_resume(struct drm_i915_private *dev_priv);
> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> + struct intel_uc_fw *uc_fw);
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
All other public functions have intel_ prefix.
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> @@ -205,4 +221,10 @@ void i915_guc_register(struct drm_i915_private *dev_priv);
> void i915_guc_unregister(struct drm_i915_private *dev_priv);
> int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
>
> +/* intel_huc_loader.c */
> +void intel_huc_init(struct drm_i915_private *dev_priv);
> +void intel_huc_fini(struct drm_device *dev);
> +int intel_huc_load(struct drm_i915_private *dev_priv);
> +
> +#endif
> #endif
> --
> 2.7.4
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-09 11:34 ` Arkadiusz Hiler
@ 2016-12-09 12:19 ` Arkadiusz Hiler
0 siblings, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 12:19 UTC (permalink / raw)
To: Chris Wilson, anushasr, intel-gfx
On Fri, Dec 09, 2016 at 12:34:55PM +0100, Arkadiusz Hiler wrote:
> On Fri, Dec 09, 2016 at 11:10:03AM +0000, Chris Wilson wrote:
> > On Fri, Dec 09, 2016 at 11:56:10AM +0100, Arkadiusz Hiler wrote:
> > > On Thu, Dec 08, 2016 at 03:02:14PM -0800, anushasr wrote:
> > > > -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > > {
> > > > u32 wopcm_size = GUC_WOPCM_TOP;
> > > >
> > > > @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > > if (err)
> > > > goto fail;
> > > >
> > > > + intel_huc_load(dev_priv);
> >
> > We don't need error handling? That would simplify a lot of our code!
> > -Chris
>
> With this patch series on this specific piece of code - not really.
> HuC support it intorduce is _best-eforrty_.
>
> If the function would report error we would not act on it in anyway
> other than logging the fail (which the function already does for us).
>
> As Anusha discussed here, there will be some code reorganization due to
> introduction of i915.enable_huc and deprecation of enable_guc_loading.
> Once we want to have enable_huc=2, there is a reason to change the
> signature and report errors.
Ergh, I've got signatures of auth and load mixed up. But most of the
statement above still semi-holds.
--
Cheers,
Arek
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication
2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr
2016-12-09 10:22 ` Arkadiusz Hiler
@ 2016-12-09 12:36 ` Michal Wajdeczko
2016-12-11 0:03 ` Srivatsa, Anusha
1 sibling, 1 reply; 71+ messages in thread
From: Michal Wajdeczko @ 2016-12-09 12:36 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Alex Dai, Peter Antoine
On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++
> drivers/gpu/drm/i915/intel_uc.c | 61 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_uc.h | 1 +
> 4 files changed, 65 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index c1e7faf..94a974d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -504,6 +504,7 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
> INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> INTEL_GUC_ACTION_LIMIT
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index b971351..89d092b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> intel_uc_fw_status_repr(guc_fw->fetch_status),
> intel_uc_fw_status_repr(guc_fw->load_status));
>
> + intel_guc_auth_huc(dev_priv);
> +
> if (i915.enable_guc_submission) {
> if (i915.guc_log_level >= 0)
> gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 8ae6795..445b9ad 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
>
> return intel_guc_send(guc, action, ARRAY_SIZE(action));
> }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev: the drm device
Mismatched param name.
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
Can we use *guc as the first param to match other intel_guc functions?
> +{
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + /* Bypass the case where there is no HuC firmware */
> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> + return;
> +
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
Hmm, this looks like late handling of earlier error.
Note that other functions in this file assume that Guc is working fine.
> + return;
> + }
> +
> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> + return;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return;
> + }
> +
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. */
> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
Hmm, maybe this function shall be split into two parts:
intel_huc_auth() in intel_huc_loader.c that contains most of the logic
from current function, but calls intel_guc_auth_huc() from this file that
just sends action to the guc (similar to other simple functions in this file.
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed\n");
> + goto out;
> + }
> +
> +out:
> + i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index ac92946..1db8bc2 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
> int intel_guc_log_flush_complete(struct intel_guc *guc);
> int intel_guc_log_flush(struct intel_guc *guc);
> int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>
> /* intel_guc_loader.c */
> extern void intel_guc_init(struct drm_i915_private *dev_priv);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-08 23:02 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
2016-12-08 23:55 ` Chris Wilson
@ 2016-12-09 12:59 ` Michal Wajdeczko
2016-12-12 14:13 ` Arkadiusz Hiler
1 sibling, 1 reply; 71+ messages in thread
From: Michal Wajdeczko @ 2016-12-09 12:59 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Peter Antoine
On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased on top of drm-tip.
> v6: rebased. Removed any reference to intel_huc.h
>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
> drivers/gpu/drm/i915/intel_uc.h | 1 +
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 85a47c2..6be06a27 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_uc.h"
>
> static struct drm_driver driver;
>
> @@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> */
> value = 1;
> break;
> + case I915_PARAM_HAS_HUC:
For me this param name does not match returned result which maybe misleading.
Note that other HAS params return static driver/hw capability, not runtime.
I guess PARAM_HUC_STATUS would be better (0=no huc, 1=pending, 2=ok, -1=failed)
And you can cache huc status in intel_huc struct and make final modification in
intel_huc_auth() function to avoid registry read (unless we want to detect later
crash of the huc using this reg read)
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 96fc727..6704cc8 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -289,3 +289,15 @@ void intel_huc_fini(struct drm_device *dev)
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
>
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
Please change function return type to bool to match this description.
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 1db8bc2..ccd3f69 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -226,6 +226,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
> void intel_huc_init(struct drm_i915_private *dev_priv);
> void intel_huc_fini(struct drm_device *dev);
> int intel_huc_load(struct drm_i915_private *dev_priv);
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv);
>
> #endif
> #endif
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index da32c2f..3e1964c 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
> * priorities and the driver will attempt to execute batches in priority order.
> */
> #define I915_PARAM_HAS_SCHEDULER 41
> +#define I915_PARAM_HAS_HUC 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-12-09 11:49 ` Arkadiusz Hiler
@ 2016-12-09 13:06 ` Michal Wajdeczko
2016-12-09 13:09 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Michal Wajdeczko @ 2016-12-09 13:06 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: intel-gfx, Alex Dai, Peter Antoine
On Fri, Dec 09, 2016 at 12:49:02PM +0100, Arkadiusz Hiler wrote:
> On Fri, Dec 09, 2016 at 12:28:52PM +0100, Michal Wajdeczko wrote:
> > On Thu, Dec 08, 2016 at 03:02:12PM -0800, anushasr wrote:
> > > From: Peter Antoine <peter.antoine@intel.com>
> > >
> > > Rename some of the GuC fw loading code to make them more general. We
> > > will utilise them for HuC loading as well.
> > > s/intel_guc_fw/intel_uc_fw/g
> > > s/GUC_FIRMWARE/UC_FIRMWARE/g
> > >
> > > Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> > > such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> > > same purpose.
> > >
> > > v2: rebased on top of nightly.
> > > reapplied the search/replace as upstream code as changed.
> > > v3: rebased again on drm-nightly.
> > > v4: removed G from messages in shared fw fetch function.
> > > v5: rebased.
> > > v7: rebased.
> > > v8: rebased.
> > > v9: rebased.
> > > v10: rebased.
> > > v11: rebased.
> > > v12: rebased on top of drm-tip
> > > v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
> > > and intel_guc_init().
> > >
> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> > > drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
> > > drivers/gpu/drm/i915/intel_guc_loader.c | 157 +++++++++++++++--------------
> > > drivers/gpu/drm/i915/intel_uc.h | 40 ++++----
> > > 4 files changed, 108 insertions(+), 105 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index a746130..0e5ef62 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2338,7 +2338,7 @@ static int i915_llc(struct seq_file *m, void *data)
> > > static int i915_guc_load_status_info(struct seq_file *m, void *data)
> > > {
> > > struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > u32 tmp, i;
> > >
> > > if (!HAS_GUC_UCODE(dev_priv))
> > > @@ -2346,15 +2346,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
> > >
> > > seq_printf(m, "GuC firmware status:\n");
> > > seq_printf(m, "\tpath: %s\n",
> > > - guc_fw->guc_fw_path);
> > > + guc_fw->uc_fw_path);
> > > seq_printf(m, "\tfetch: %s\n",
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> > > + intel_uc_fw_status_repr(guc_fw->fetch_status));
> > > seq_printf(m, "\tload: %s\n",
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > > seq_printf(m, "\tversion wanted: %d.%d\n",
> > > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > > + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> > > seq_printf(m, "\tversion found: %d.%d\n",
> > > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> > > + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> > > seq_printf(m, "\theader: offset is %d; size = %d\n",
> > > guc_fw->header_offset, guc_fw->header_size);
> > > seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> > > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> > > index 7fa4e74..e156a4b 100644
> > > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > > @@ -1493,7 +1493,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
> > > struct i915_gem_context *ctx;
> > > u32 data[3];
> > >
> > > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> > > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> > > return 0;
> > >
> > > gen9_disable_guc_interrupts(dev_priv);
> > > @@ -1520,7 +1520,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
> > > struct i915_gem_context *ctx;
> > > u32 data[3];
> > >
> > > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> > > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> > > return 0;
> > >
> > > if (i915.guc_log_level >= 0)
> > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > index 21db697..8f04f6e 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> > > MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
> > >
> > > /* User-friendly representation of an enum */
> > > -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> > > +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> > > {
> > > switch (status) {
> > > - case GUC_FIRMWARE_FAIL:
> > > + case UC_FIRMWARE_FAIL:
> > > return "FAIL";
> > > - case GUC_FIRMWARE_NONE:
> > > + case UC_FIRMWARE_NONE:
> > > return "NONE";
> > > - case GUC_FIRMWARE_PENDING:
> > > + case UC_FIRMWARE_PENDING:
> > > return "PENDING";
> > > - case GUC_FIRMWARE_SUCCESS:
> > > + case UC_FIRMWARE_SUCCESS:
> > > return "SUCCESS";
> > > default:
> > > return "UNKNOWN!";
> > > @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> > > static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> > > struct i915_vma *vma)
> > > {
> > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > unsigned long offset;
> > > struct sg_table *sg = vma->pages;
> > > u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> > > @@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > */
> > > static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> > > {
> > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > struct i915_vma *vma;
> > > int ret;
> > >
> > > - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> > > + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
> > > if (ret) {
> > > DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> > > return ret;
> > > }
> > >
> > > - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
> > > + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
> > > if (IS_ERR(vma)) {
> > > DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> > > return PTR_ERR(vma);
> > > @@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
> > > */
> > > int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > {
> > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > - const char *fw_path = guc_fw->guc_fw_path;
> > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > + const char *fw_path = guc_fw->uc_fw_path;
> > > int retries, ret, err;
> > >
> > > DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
> > > fw_path,
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > >
> > > /* Loading forbidden, or no firmware to load? */
> > > if (!i915.enable_guc_loading) {
> > > @@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > }
> > >
> > > /* Fetch failed, or already fetched but failed to load? */
> > > - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> > > + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
> > > err = -EIO;
> > > goto fail;
> > > - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> > > + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
> > > err = -ENOEXEC;
> > > goto fail;
> > > }
> > > @@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > guc_interrupts_release(dev_priv);
> > > gen9_reset_guc_interrupts(dev_priv);
> > >
> > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> > > + guc_fw->load_status = UC_FIRMWARE_PENDING;
> > >
> > > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > >
> > > err = i915_guc_submission_init(dev_priv);
> > > if (err)
> > > @@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > "retry %d more time(s)\n", err, retries);
> > > }
> > >
> > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> > > + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
> > >
> > > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > >
> > > if (i915.enable_guc_submission) {
> > > if (i915.guc_log_level >= 0)
> > > @@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > return 0;
> > >
> > > fail:
> > > - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> > > + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> > > + guc_fw->load_status = UC_FIRMWARE_FAIL;
> > >
> > > guc_interrupts_release(dev_priv);
> > > i915_guc_submission_disable(dev_priv);
> > > @@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > return ret;
> > > }
> > >
> > > -static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > - struct intel_guc_fw *guc_fw)
> > > +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> > > + struct intel_uc_fw *uc_fw)
> > > {
> > > struct pci_dev *pdev = dev_priv->drm.pdev;
> > > struct drm_i915_gem_object *obj;
> > > @@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > size_t size;
> > > int err;
> > >
> > > - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> > > + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
> > > + intel_uc_fw_status_repr(uc_fw->fetch_status));
> > >
> > > - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
> > > + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
> > > if (err)
> > > goto fail;
> > > if (!fw)
> > > goto fail;
> > >
> > > - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> > > - guc_fw->guc_fw_path, fw);
> > > + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> > > + uc_fw->uc_fw_path, fw);
> > >
> > > /* Check the size of the blob before examining buffer contents */
> > > if (fw->size < sizeof(struct guc_css_header)) {
> > > @@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > css = (struct guc_css_header *)fw->data;
> > >
> > > /* Firmware bits always start from header */
> > > - guc_fw->header_offset = 0;
> > > - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> > > + uc_fw->header_offset = 0;
> > > + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> > > css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
> > >
> > > - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> > > + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> > > DRM_NOTE("CSS header definition mismatch\n");
> > > goto fail;
> > > }
> > >
> > > /* then, uCode */
> > > - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> > > - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> > > + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> > > + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> > >
> > > /* now RSA */
> > > if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> > > DRM_NOTE("RSA key size is bad\n");
> > > goto fail;
> > > }
> > > - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> > > - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> > > + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> > > + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> > >
> > > /* At least, it should have header, uCode and RSA. Size of all three. */
> > > - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> > > + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
> > > if (fw->size < size) {
> > > DRM_NOTE("Missing firmware components\n");
> > > goto fail;
> > > }
> > >
> > > /* Header and uCode will be loaded to WOPCM. Size of the two. */
> > > - size = guc_fw->header_size + guc_fw->ucode_size;
> > > + size = uc_fw->header_size + uc_fw->ucode_size;
> > > if (size > guc_wopcm_size(dev_priv)) {
> > > DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> > > goto fail;
> > > @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> > > * in terms of bytes (u8).
> > > */
> > > - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> > > - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> > > -
> > > - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> > > - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> > > - DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
> > > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> > > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > > + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> > > + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> > > +
> > > + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> > > + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> > > + DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
> > > + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> > > + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> > > err = -ENOEXEC;
> > > goto fail;
> > > }
> > >
> > > DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> > > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> > > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > > + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> > > + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> > >
> > > mutex_lock(&dev_priv->drm.struct_mutex);
> > > obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
> > > @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > goto fail;
> > > }
> > >
> > > - guc_fw->guc_fw_obj = obj;
> > > - guc_fw->guc_fw_size = fw->size;
> > > + uc_fw->uc_fw_obj = obj;
> > > + uc_fw->uc_fw_size = fw->size;
> > >
> > > - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> > > - guc_fw->guc_fw_obj);
> > > + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
> > > + uc_fw->uc_fw_obj);
> > >
> > > release_firmware(fw);
> > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> > > + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> > > return;
> > >
> > > fail:
> > > - DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
> > > - guc_fw->guc_fw_path, err);
> > > - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> > > - err, fw, guc_fw->guc_fw_obj);
> > > + DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
> > > + uc_fw->uc_fw_path, err);
> > > + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> > > + err, fw, uc_fw->uc_fw_obj);
> > >
> > > mutex_lock(&dev_priv->drm.struct_mutex);
> > > - obj = guc_fw->guc_fw_obj;
> > > + obj = uc_fw->uc_fw_obj;
> > > if (obj)
> > > i915_gem_object_put(obj);
> > > - guc_fw->guc_fw_obj = NULL;
> > > + uc_fw->uc_fw_obj = NULL;
> > > mutex_unlock(&dev_priv->drm.struct_mutex);
> > >
> > > release_firmware(fw); /* OK even if fw is NULL */
> > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> > > + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> > > }
> > >
> > > /**
> > > @@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > */
> > > void intel_guc_init(struct drm_i915_private *dev_priv)
> > > {
> > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > const char *fw_path;
> > >
> > > if (!HAS_GUC(dev_priv)) {
> > > @@ -739,23 +739,24 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > > fw_path = NULL;
> > > } else if (IS_SKYLAKE(dev_priv)) {
> > > fw_path = I915_SKL_GUC_UCODE;
> > > - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> > > - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> > > + guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> > > + guc_fw->minor_ver_wanted = SKL_FW_MINOR;
> > > } else if (IS_BROXTON(dev_priv)) {
> > > fw_path = I915_BXT_GUC_UCODE;
> > > - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> > > - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> > > + guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> > > + guc_fw->minor_ver_wanted = BXT_FW_MINOR;
> > > } else if (IS_KABYLAKE(dev_priv)) {
> > > fw_path = I915_KBL_GUC_UCODE;
> > > - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> > > - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> > > + guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> > > + guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> > > } else {
> > > fw_path = ""; /* unknown device */
> > > }
> > >
> > > - guc_fw->guc_fw_path = fw_path;
> > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> > > + guc_fw->uc_dev = &dev_priv->drm;
> > > + guc_fw->uc_fw_path = fw_path;
> > > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > + guc_fw->load_status = UC_FIRMWARE_NONE;
> > >
> > > /* Early (and silent) return if GuC loading is disabled */
> > > if (!i915.enable_guc_loading)
> > > @@ -765,9 +766,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > > if (*fw_path == '\0')
> > > return;
> > >
> > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> > > + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> > > DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> > > - guc_fw_fetch(dev_priv, guc_fw);
> > > + intel_uc_fw_fetch(dev_priv, guc_fw);
> > > /* status must now be FAIL or SUCCESS */
> > > }
> > >
> > > @@ -777,17 +778,17 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > > */
> > > void intel_guc_fini(struct drm_i915_private *dev_priv)
> > > {
> > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > >
> > > mutex_lock(&dev_priv->drm.struct_mutex);
> > > guc_interrupts_release(dev_priv);
> > > i915_guc_submission_disable(dev_priv);
> > > i915_guc_submission_fini(dev_priv);
> > >
> > > - if (guc_fw->guc_fw_obj)
> > > - i915_gem_object_put(guc_fw->guc_fw_obj);
> > > - guc_fw->guc_fw_obj = NULL;
> > > + if (guc_fw->uc_fw_obj)
> > > + i915_gem_object_put(guc_fw->uc_fw_obj);
> > > + guc_fw->uc_fw_obj = NULL;
> > > mutex_unlock(&dev_priv->drm.struct_mutex);
> > >
> > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> > > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > }
> > > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> > > index 11f5608..f9f598d 100644
> > > --- a/drivers/gpu/drm/i915/intel_uc.h
> > > +++ b/drivers/gpu/drm/i915/intel_uc.h
> > > @@ -91,29 +91,31 @@ struct i915_guc_client {
> > > uint64_t submissions[I915_NUM_ENGINES];
> > > };
> > >
> > > -enum intel_guc_fw_status {
> > > - GUC_FIRMWARE_FAIL = -1,
> > > - GUC_FIRMWARE_NONE = 0,
> > > - GUC_FIRMWARE_PENDING,
> > > - GUC_FIRMWARE_SUCCESS
> > > +enum intel_uc_fw_status {
> > > + UC_FIRMWARE_FAIL = -1,
> > > + UC_FIRMWARE_NONE = 0,
> > > + UC_FIRMWARE_PENDING,
> > > + UC_FIRMWARE_SUCCESS
> >
> > Shouldn't we use INTEL_UC_ prefix here (in similar way as in GUC_ACTION)?
> >
> >
> > > };
> > >
> > > /*
> > > * This structure encapsulates all the data needed during the process
> > > * of fetching, caching, and loading the firmware image into the GuC.
> > > */
> > > -struct intel_guc_fw {
> > > - const char * guc_fw_path;
> > > - size_t guc_fw_size;
> > > - struct drm_i915_gem_object * guc_fw_obj;
> > > - enum intel_guc_fw_status guc_fw_fetch_status;
> > > - enum intel_guc_fw_status guc_fw_load_status;
> > > -
> > > - uint16_t guc_fw_major_wanted;
> > > - uint16_t guc_fw_minor_wanted;
> > > - uint16_t guc_fw_major_found;
> > > - uint16_t guc_fw_minor_found;
> > > -
> > > +struct intel_uc_fw {
> > > + struct drm_device *uc_dev;
> >
> > Why do you need this back pointer to drm_dev ?
> > More likely all you need is pointer to dev_priv.
> > But for dev_priv you can always use guc_to_i915().
>
> It seems like a left over from the old days. I have a series that
> refactors all things GuC that I'll push here soon, including the removal
> of this field.
>
> Since this series advertises as a simple renaming I didn't force it
> here.
If you want to treat this as simple 'renaming' then 'adding' unused field
is even more undesired and shall be avoided.
>
> > > + const char *uc_fw_path;
> > > + size_t uc_fw_size;
> > > + struct drm_i915_gem_object *uc_fw_obj;
> >
> > All these uc_fw_ prefixes seem to be redundant as this struct is just about uc_fw.
> >
> >
> > > + enum intel_uc_fw_status fetch_status;
> > > + enum intel_uc_fw_status load_status;
> > > +
> > > + uint16_t major_ver_wanted;
> > > + uint16_t minor_ver_wanted;
> > > + uint16_t major_ver_found;
> > > + uint16_t minor_ver_found;
> > > +
> > > + uint32_t fw_type;
> >
> > What is the purpose of this field ?
>
> It is used in the patch 2, to set {major,minor}_ver_found depending on
> which firmware we pass to intel_uc_fw_fetch()
Then maybe is shall be moved to patch 2 ?
>
> >
> > > uint32_t header_size;
> > > uint32_t header_offset;
> > > uint32_t rsa_size;
> > > @@ -139,7 +141,7 @@ struct intel_guc_log {
> > > };
> > >
> > > struct intel_guc {
> > > - struct intel_guc_fw guc_fw;
> > > + struct intel_uc_fw guc_fw;
> >
> > Btw, guc_ prefix in field name here is also redundant.
> >
> >
> > > struct intel_guc_log log;
> > >
> > > /* intel_guc_recv interrupt related state */
> > > @@ -181,7 +183,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> > > extern void intel_guc_init(struct drm_i915_private *dev_priv);
> > > extern int intel_guc_setup(struct drm_i915_private *dev_priv);
> > > extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> > > -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> > > +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> > > extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
> > > extern int intel_guc_resume(struct drm_i915_private *dev_priv);
> > >
> > > --
> > > 2.7.4
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Cheers,
> Arek
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-12-09 13:06 ` Michal Wajdeczko
@ 2016-12-09 13:09 ` Arkadiusz Hiler
2016-12-09 19:34 ` Srivatsa, Anusha
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-09 13:09 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx, Alex Dai, Peter Antoine
On Fri, Dec 09, 2016 at 02:06:29PM +0100, Michal Wajdeczko wrote:
> On Fri, Dec 09, 2016 at 12:49:02PM +0100, Arkadiusz Hiler wrote:
> > On Fri, Dec 09, 2016 at 12:28:52PM +0100, Michal Wajdeczko wrote:
> > > On Thu, Dec 08, 2016 at 03:02:12PM -0800, anushasr wrote:
> > > > From: Peter Antoine <peter.antoine@intel.com>
> > > >
> > > > Rename some of the GuC fw loading code to make them more general. We
> > > > will utilise them for HuC loading as well.
> > > > s/intel_guc_fw/intel_uc_fw/g
> > > > s/GUC_FIRMWARE/UC_FIRMWARE/g
> > > >
> > > > Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> > > > such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> > > > same purpose.
> > > >
> > > > v2: rebased on top of nightly.
> > > > reapplied the search/replace as upstream code as changed.
> > > > v3: rebased again on drm-nightly.
> > > > v4: removed G from messages in shared fw fetch function.
> > > > v5: rebased.
> > > > v7: rebased.
> > > > v8: rebased.
> > > > v9: rebased.
> > > > v10: rebased.
> > > > v11: rebased.
> > > > v12: rebased on top of drm-tip
> > > > v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
> > > > and intel_guc_init().
> > > >
> > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> > > > drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
> > > > drivers/gpu/drm/i915/intel_guc_loader.c | 157 +++++++++++++++--------------
> > > > drivers/gpu/drm/i915/intel_uc.h | 40 ++++----
> > > > 4 files changed, 108 insertions(+), 105 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index a746130..0e5ef62 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -2338,7 +2338,7 @@ static int i915_llc(struct seq_file *m, void *data)
> > > > static int i915_guc_load_status_info(struct seq_file *m, void *data)
> > > > {
> > > > struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > u32 tmp, i;
> > > >
> > > > if (!HAS_GUC_UCODE(dev_priv))
> > > > @@ -2346,15 +2346,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
> > > >
> > > > seq_printf(m, "GuC firmware status:\n");
> > > > seq_printf(m, "\tpath: %s\n",
> > > > - guc_fw->guc_fw_path);
> > > > + guc_fw->uc_fw_path);
> > > > seq_printf(m, "\tfetch: %s\n",
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status));
> > > > seq_printf(m, "\tload: %s\n",
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > > > seq_printf(m, "\tversion wanted: %d.%d\n",
> > > > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > > > + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> > > > seq_printf(m, "\tversion found: %d.%d\n",
> > > > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> > > > + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> > > > seq_printf(m, "\theader: offset is %d; size = %d\n",
> > > > guc_fw->header_offset, guc_fw->header_size);
> > > > seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> > > > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> > > > index 7fa4e74..e156a4b 100644
> > > > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > > > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > > > @@ -1493,7 +1493,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
> > > > struct i915_gem_context *ctx;
> > > > u32 data[3];
> > > >
> > > > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> > > > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> > > > return 0;
> > > >
> > > > gen9_disable_guc_interrupts(dev_priv);
> > > > @@ -1520,7 +1520,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
> > > > struct i915_gem_context *ctx;
> > > > u32 data[3];
> > > >
> > > > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> > > > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> > > > return 0;
> > > >
> > > > if (i915.guc_log_level >= 0)
> > > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > index 21db697..8f04f6e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> > > > MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
> > > >
> > > > /* User-friendly representation of an enum */
> > > > -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> > > > +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> > > > {
> > > > switch (status) {
> > > > - case GUC_FIRMWARE_FAIL:
> > > > + case UC_FIRMWARE_FAIL:
> > > > return "FAIL";
> > > > - case GUC_FIRMWARE_NONE:
> > > > + case UC_FIRMWARE_NONE:
> > > > return "NONE";
> > > > - case GUC_FIRMWARE_PENDING:
> > > > + case UC_FIRMWARE_PENDING:
> > > > return "PENDING";
> > > > - case GUC_FIRMWARE_SUCCESS:
> > > > + case UC_FIRMWARE_SUCCESS:
> > > > return "SUCCESS";
> > > > default:
> > > > return "UNKNOWN!";
> > > > @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> > > > static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> > > > struct i915_vma *vma)
> > > > {
> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > unsigned long offset;
> > > > struct sg_table *sg = vma->pages;
> > > > u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> > > > @@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > > */
> > > > static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> > > > {
> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > struct i915_vma *vma;
> > > > int ret;
> > > >
> > > > - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> > > > + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
> > > > if (ret) {
> > > > DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> > > > return ret;
> > > > }
> > > >
> > > > - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
> > > > + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
> > > > if (IS_ERR(vma)) {
> > > > DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> > > > return PTR_ERR(vma);
> > > > @@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
> > > > */
> > > > int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > > {
> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > - const char *fw_path = guc_fw->guc_fw_path;
> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > + const char *fw_path = guc_fw->uc_fw_path;
> > > > int retries, ret, err;
> > > >
> > > > DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
> > > > fw_path,
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > > >
> > > > /* Loading forbidden, or no firmware to load? */
> > > > if (!i915.enable_guc_loading) {
> > > > @@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > > }
> > > >
> > > > /* Fetch failed, or already fetched but failed to load? */
> > > > - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> > > > + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
> > > > err = -EIO;
> > > > goto fail;
> > > > - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> > > > + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
> > > > err = -ENOEXEC;
> > > > goto fail;
> > > > }
> > > > @@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > > guc_interrupts_release(dev_priv);
> > > > gen9_reset_guc_interrupts(dev_priv);
> > > >
> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> > > > + guc_fw->load_status = UC_FIRMWARE_PENDING;
> > > >
> > > > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > > >
> > > > err = i915_guc_submission_init(dev_priv);
> > > > if (err)
> > > > @@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > > "retry %d more time(s)\n", err, retries);
> > > > }
> > > >
> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> > > > + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
> > > >
> > > > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
> > > >
> > > > if (i915.enable_guc_submission) {
> > > > if (i915.guc_log_level >= 0)
> > > > @@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > > return 0;
> > > >
> > > > fail:
> > > > - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> > > > + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> > > > + guc_fw->load_status = UC_FIRMWARE_FAIL;
> > > >
> > > > guc_interrupts_release(dev_priv);
> > > > i915_guc_submission_disable(dev_priv);
> > > > @@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> > > > return ret;
> > > > }
> > > >
> > > > -static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > > - struct intel_guc_fw *guc_fw)
> > > > +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> > > > + struct intel_uc_fw *uc_fw)
> > > > {
> > > > struct pci_dev *pdev = dev_priv->drm.pdev;
> > > > struct drm_i915_gem_object *obj;
> > > > @@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > > size_t size;
> > > > int err;
> > > >
> > > > - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> > > > + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
> > > > + intel_uc_fw_status_repr(uc_fw->fetch_status));
> > > >
> > > > - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
> > > > + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
> > > > if (err)
> > > > goto fail;
> > > > if (!fw)
> > > > goto fail;
> > > >
> > > > - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> > > > - guc_fw->guc_fw_path, fw);
> > > > + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> > > > + uc_fw->uc_fw_path, fw);
> > > >
> > > > /* Check the size of the blob before examining buffer contents */
> > > > if (fw->size < sizeof(struct guc_css_header)) {
> > > > @@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > > css = (struct guc_css_header *)fw->data;
> > > >
> > > > /* Firmware bits always start from header */
> > > > - guc_fw->header_offset = 0;
> > > > - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> > > > + uc_fw->header_offset = 0;
> > > > + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> > > > css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
> > > >
> > > > - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> > > > + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> > > > DRM_NOTE("CSS header definition mismatch\n");
> > > > goto fail;
> > > > }
> > > >
> > > > /* then, uCode */
> > > > - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> > > > - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> > > > + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> > > > + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> > > >
> > > > /* now RSA */
> > > > if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> > > > DRM_NOTE("RSA key size is bad\n");
> > > > goto fail;
> > > > }
> > > > - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> > > > - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> > > > + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> > > > + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> > > >
> > > > /* At least, it should have header, uCode and RSA. Size of all three. */
> > > > - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> > > > + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
> > > > if (fw->size < size) {
> > > > DRM_NOTE("Missing firmware components\n");
> > > > goto fail;
> > > > }
> > > >
> > > > /* Header and uCode will be loaded to WOPCM. Size of the two. */
> > > > - size = guc_fw->header_size + guc_fw->ucode_size;
> > > > + size = uc_fw->header_size + uc_fw->ucode_size;
> > > > if (size > guc_wopcm_size(dev_priv)) {
> > > > DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> > > > goto fail;
> > > > @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > > * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> > > > * in terms of bytes (u8).
> > > > */
> > > > - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> > > > - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> > > > -
> > > > - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> > > > - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> > > > - DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
> > > > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> > > > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > > > + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> > > > + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> > > > +
> > > > + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> > > > + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> > > > + DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
> > > > + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> > > > + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> > > > err = -ENOEXEC;
> > > > goto fail;
> > > > }
> > > >
> > > > DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> > > > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> > > > - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> > > > + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> > > > + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> > > >
> > > > mutex_lock(&dev_priv->drm.struct_mutex);
> > > > obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
> > > > @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > > goto fail;
> > > > }
> > > >
> > > > - guc_fw->guc_fw_obj = obj;
> > > > - guc_fw->guc_fw_size = fw->size;
> > > > + uc_fw->uc_fw_obj = obj;
> > > > + uc_fw->uc_fw_size = fw->size;
> > > >
> > > > - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> > > > - guc_fw->guc_fw_obj);
> > > > + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
> > > > + uc_fw->uc_fw_obj);
> > > >
> > > > release_firmware(fw);
> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> > > > + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> > > > return;
> > > >
> > > > fail:
> > > > - DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
> > > > - guc_fw->guc_fw_path, err);
> > > > - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> > > > - err, fw, guc_fw->guc_fw_obj);
> > > > + DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
> > > > + uc_fw->uc_fw_path, err);
> > > > + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> > > > + err, fw, uc_fw->uc_fw_obj);
> > > >
> > > > mutex_lock(&dev_priv->drm.struct_mutex);
> > > > - obj = guc_fw->guc_fw_obj;
> > > > + obj = uc_fw->uc_fw_obj;
> > > > if (obj)
> > > > i915_gem_object_put(obj);
> > > > - guc_fw->guc_fw_obj = NULL;
> > > > + uc_fw->uc_fw_obj = NULL;
> > > > mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >
> > > > release_firmware(fw); /* OK even if fw is NULL */
> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> > > > + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> > > > }
> > > >
> > > > /**
> > > > @@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> > > > */
> > > > void intel_guc_init(struct drm_i915_private *dev_priv)
> > > > {
> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > const char *fw_path;
> > > >
> > > > if (!HAS_GUC(dev_priv)) {
> > > > @@ -739,23 +739,24 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > > > fw_path = NULL;
> > > > } else if (IS_SKYLAKE(dev_priv)) {
> > > > fw_path = I915_SKL_GUC_UCODE;
> > > > - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> > > > - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> > > > + guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> > > > + guc_fw->minor_ver_wanted = SKL_FW_MINOR;
> > > > } else if (IS_BROXTON(dev_priv)) {
> > > > fw_path = I915_BXT_GUC_UCODE;
> > > > - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> > > > - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> > > > + guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> > > > + guc_fw->minor_ver_wanted = BXT_FW_MINOR;
> > > > } else if (IS_KABYLAKE(dev_priv)) {
> > > > fw_path = I915_KBL_GUC_UCODE;
> > > > - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> > > > - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> > > > + guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> > > > + guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> > > > } else {
> > > > fw_path = ""; /* unknown device */
> > > > }
> > > >
> > > > - guc_fw->guc_fw_path = fw_path;
> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> > > > + guc_fw->uc_dev = &dev_priv->drm;
> > > > + guc_fw->uc_fw_path = fw_path;
> > > > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > > + guc_fw->load_status = UC_FIRMWARE_NONE;
> > > >
> > > > /* Early (and silent) return if GuC loading is disabled */
> > > > if (!i915.enable_guc_loading)
> > > > @@ -765,9 +766,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > > > if (*fw_path == '\0')
> > > > return;
> > > >
> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> > > > + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> > > > DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> > > > - guc_fw_fetch(dev_priv, guc_fw);
> > > > + intel_uc_fw_fetch(dev_priv, guc_fw);
> > > > /* status must now be FAIL or SUCCESS */
> > > > }
> > > >
> > > > @@ -777,17 +778,17 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
> > > > */
> > > > void intel_guc_fini(struct drm_i915_private *dev_priv)
> > > > {
> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > >
> > > > mutex_lock(&dev_priv->drm.struct_mutex);
> > > > guc_interrupts_release(dev_priv);
> > > > i915_guc_submission_disable(dev_priv);
> > > > i915_guc_submission_fini(dev_priv);
> > > >
> > > > - if (guc_fw->guc_fw_obj)
> > > > - i915_gem_object_put(guc_fw->guc_fw_obj);
> > > > - guc_fw->guc_fw_obj = NULL;
> > > > + if (guc_fw->uc_fw_obj)
> > > > + i915_gem_object_put(guc_fw->uc_fw_obj);
> > > > + guc_fw->uc_fw_obj = NULL;
> > > > mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >
> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> > > > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > > }
> > > > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> > > > index 11f5608..f9f598d 100644
> > > > --- a/drivers/gpu/drm/i915/intel_uc.h
> > > > +++ b/drivers/gpu/drm/i915/intel_uc.h
> > > > @@ -91,29 +91,31 @@ struct i915_guc_client {
> > > > uint64_t submissions[I915_NUM_ENGINES];
> > > > };
> > > >
> > > > -enum intel_guc_fw_status {
> > > > - GUC_FIRMWARE_FAIL = -1,
> > > > - GUC_FIRMWARE_NONE = 0,
> > > > - GUC_FIRMWARE_PENDING,
> > > > - GUC_FIRMWARE_SUCCESS
> > > > +enum intel_uc_fw_status {
> > > > + UC_FIRMWARE_FAIL = -1,
> > > > + UC_FIRMWARE_NONE = 0,
> > > > + UC_FIRMWARE_PENDING,
> > > > + UC_FIRMWARE_SUCCESS
> > >
> > > Shouldn't we use INTEL_UC_ prefix here (in similar way as in GUC_ACTION)?
> > >
> > >
> > > > };
> > > >
> > > > /*
> > > > * This structure encapsulates all the data needed during the process
> > > > * of fetching, caching, and loading the firmware image into the GuC.
> > > > */
> > > > -struct intel_guc_fw {
> > > > - const char * guc_fw_path;
> > > > - size_t guc_fw_size;
> > > > - struct drm_i915_gem_object * guc_fw_obj;
> > > > - enum intel_guc_fw_status guc_fw_fetch_status;
> > > > - enum intel_guc_fw_status guc_fw_load_status;
> > > > -
> > > > - uint16_t guc_fw_major_wanted;
> > > > - uint16_t guc_fw_minor_wanted;
> > > > - uint16_t guc_fw_major_found;
> > > > - uint16_t guc_fw_minor_found;
> > > > -
> > > > +struct intel_uc_fw {
> > > > + struct drm_device *uc_dev;
> > >
> > > Why do you need this back pointer to drm_dev ?
> > > More likely all you need is pointer to dev_priv.
> > > But for dev_priv you can always use guc_to_i915().
> >
> > It seems like a left over from the old days. I have a series that
> > refactors all things GuC that I'll push here soon, including the removal
> > of this field.
> >
> > Since this series advertises as a simple renaming I didn't force it
> > here.
>
> If you want to treat this as simple 'renaming' then 'adding' unused field
> is even more undesired and shall be avoided.
>
> >
> > > > + const char *uc_fw_path;
> > > > + size_t uc_fw_size;
> > > > + struct drm_i915_gem_object *uc_fw_obj;
> > >
> > > All these uc_fw_ prefixes seem to be redundant as this struct is just about uc_fw.
> > >
> > >
> > > > + enum intel_uc_fw_status fetch_status;
> > > > + enum intel_uc_fw_status load_status;
> > > > +
> > > > + uint16_t major_ver_wanted;
> > > > + uint16_t minor_ver_wanted;
> > > > + uint16_t major_ver_found;
> > > > + uint16_t minor_ver_found;
> > > > +
> > > > + uint32_t fw_type;
> > >
> > > What is the purpose of this field ?
> >
> > It is used in the patch 2, to set {major,minor}_ver_found depending on
> > which firmware we pass to intel_uc_fw_fetch()
>
> Then maybe is shall be moved to patch 2 ?
Sound reasonable as that's the first usage, although is also fits here
along making te structs general. I have no strong opinion on that
though.
>
> >
> > >
> > > > uint32_t header_size;
> > > > uint32_t header_offset;
> > > > uint32_t rsa_size;
> > > > @@ -139,7 +141,7 @@ struct intel_guc_log {
> > > > };
> > > >
> > > > struct intel_guc {
> > > > - struct intel_guc_fw guc_fw;
> > > > + struct intel_uc_fw guc_fw;
> > >
> > > Btw, guc_ prefix in field name here is also redundant.
> > >
> > >
> > > > struct intel_guc_log log;
> > > >
> > > > /* intel_guc_recv interrupt related state */
> > > > @@ -181,7 +183,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> > > > extern void intel_guc_init(struct drm_i915_private *dev_priv);
> > > > extern int intel_guc_setup(struct drm_i915_private *dev_priv);
> > > > extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> > > > -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> > > > +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> > > > extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
> > > > extern int intel_guc_resume(struct drm_i915_private *dev_priv);
> > > >
> > > > --
> > > > 2.7.4
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Cheers,
> > Arek
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-12-09 13:09 ` Arkadiusz Hiler
@ 2016-12-09 19:34 ` Srivatsa, Anusha
0 siblings, 0 replies; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-09 19:34 UTC (permalink / raw)
To: Hiler, Arkadiusz, Michal Wajdeczko; +Cc: intel-gfx
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Arkadiusz Hiler
>Sent: Friday, December 9, 2016 5:09 AM
>To: Michal Wajdeczko <michal.wajdeczko@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading
>helper functions general
>
>On Fri, Dec 09, 2016 at 02:06:29PM +0100, Michal Wajdeczko wrote:
>> On Fri, Dec 09, 2016 at 12:49:02PM +0100, Arkadiusz Hiler wrote:
>> > On Fri, Dec 09, 2016 at 12:28:52PM +0100, Michal Wajdeczko wrote:
>> > > On Thu, Dec 08, 2016 at 03:02:12PM -0800, anushasr wrote:
>> > > > From: Peter Antoine <peter.antoine@intel.com>
>> > > >
>> > > > Rename some of the GuC fw loading code to make them more
>> > > > general. We will utilise them for HuC loading as well.
>> > > > s/intel_guc_fw/intel_uc_fw/g
>> > > > s/GUC_FIRMWARE/UC_FIRMWARE/g
>> > > >
>> > > > Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts
>> > > > members, such as 'guc' or 'guc_fw' either is renamed to 'uc' or
>> > > > removed for same purpose.
>> > > >
>> > > > v2: rebased on top of nightly.
>> > > > reapplied the search/replace as upstream code as changed.
>> > > > v3: rebased again on drm-nightly.
>> > > > v4: removed G from messages in shared fw fetch function.
>> > > > v5: rebased.
>> > > > v7: rebased.
>> > > > v8: rebased.
>> > > > v9: rebased.
>> > > > v10: rebased.
>> > > > v11: rebased.
>> > > > v12: rebased on top of drm-tip
>> > > > v13: rebased.Updated dev to dev_priv in intel_guc_setup(),
>> > > > guc_fw_getch() and intel_guc_init().
>> > > >
>> > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> > > > Signed-off-by: Alex Dai <yu.dai@intel.com>
>> > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> > > > ---
>> > > > drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
>> > > > drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
>> > > > drivers/gpu/drm/i915/intel_guc_loader.c | 157 +++++++++++++++-------
>-------
>> > > > drivers/gpu/drm/i915/intel_uc.h | 40 ++++----
>> > > > 4 files changed, 108 insertions(+), 105 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> > > > b/drivers/gpu/drm/i915/i915_debugfs.c
>> > > > index a746130..0e5ef62 100644
>> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> > > > @@ -2338,7 +2338,7 @@ static int i915_llc(struct seq_file *m,
>> > > > void *data) static int i915_guc_load_status_info(struct
>> > > > seq_file *m, void *data) {
>> > > > struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > u32 tmp, i;
>> > > >
>> > > > if (!HAS_GUC_UCODE(dev_priv))
>> > > > @@ -2346,15 +2346,15 @@ static int
>> > > > i915_guc_load_status_info(struct seq_file *m, void *data)
>> > > >
>> > > > seq_printf(m, "GuC firmware status:\n");
>> > > > seq_printf(m, "\tpath: %s\n",
>> > > > - guc_fw->guc_fw_path);
>> > > > + guc_fw->uc_fw_path);
>> > > > seq_printf(m, "\tfetch: %s\n",
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
>> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status));
>> > > > seq_printf(m, "\tload: %s\n",
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
>> > > > seq_printf(m, "\tversion wanted: %d.%d\n",
>> > > > - guc_fw->guc_fw_major_wanted, guc_fw-
>>guc_fw_minor_wanted);
>> > > > + guc_fw->major_ver_wanted, guc_fw-
>>minor_ver_wanted);
>> > > > seq_printf(m, "\tversion found: %d.%d\n",
>> > > > - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
>> > > > + guc_fw->major_ver_found, guc_fw->minor_ver_found);
>> > > > seq_printf(m, "\theader: offset is %d; size = %d\n",
>> > > > guc_fw->header_offset, guc_fw->header_size);
>> > > > seq_printf(m, "\tuCode: offset is %d; size = %d\n", diff --git
>> > > > a/drivers/gpu/drm/i915/i915_guc_submission.c
>> > > > b/drivers/gpu/drm/i915/i915_guc_submission.c
>> > > > index 7fa4e74..e156a4b 100644
>> > > > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
>> > > > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
>> > > > @@ -1493,7 +1493,7 @@ int intel_guc_suspend(struct drm_i915_private
>*dev_priv)
>> > > > struct i915_gem_context *ctx;
>> > > > u32 data[3];
>> > > >
>> > > > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
>> > > > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
>> > > > return 0;
>> > > >
>> > > > gen9_disable_guc_interrupts(dev_priv);
>> > > > @@ -1520,7 +1520,7 @@ int intel_guc_resume(struct drm_i915_private
>*dev_priv)
>> > > > struct i915_gem_context *ctx;
>> > > > u32 data[3];
>> > > >
>> > > > - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
>> > > > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
>> > > > return 0;
>> > > >
>> > > > if (i915.guc_log_level >= 0)
>> > > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> > > > b/drivers/gpu/drm/i915/intel_guc_loader.c
>> > > > index 21db697..8f04f6e 100644
>> > > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> > > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> > > > @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
>> > > > MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>> > > >
>> > > > /* User-friendly representation of an enum */ -const char
>> > > > *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
>> > > > +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status
>> > > > +status)
>> > > > {
>> > > > switch (status) {
>> > > > - case GUC_FIRMWARE_FAIL:
>> > > > + case UC_FIRMWARE_FAIL:
>> > > > return "FAIL";
>> > > > - case GUC_FIRMWARE_NONE:
>> > > > + case UC_FIRMWARE_NONE:
>> > > > return "NONE";
>> > > > - case GUC_FIRMWARE_PENDING:
>> > > > + case UC_FIRMWARE_PENDING:
>> > > > return "PENDING";
>> > > > - case GUC_FIRMWARE_SUCCESS:
>> > > > + case UC_FIRMWARE_SUCCESS:
>> > > > return "SUCCESS";
>> > > > default:
>> > > > return "UNKNOWN!";
>> > > > @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct
>> > > > drm_i915_private *dev_priv, static int guc_ucode_xfer_dma(struct
>drm_i915_private *dev_priv,
>> > > > struct i915_vma *vma)
>> > > > {
>> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > unsigned long offset;
>> > > > struct sg_table *sg = vma->pages;
>> > > > u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT]; @@ -350,17 +350,17
>> > > > @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>> > > > */
>> > > > static int guc_ucode_xfer(struct drm_i915_private *dev_priv) {
>> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > struct i915_vma *vma;
>> > > > int ret;
>> > > >
>> > > > - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
>> > > > + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj,
>> > > > +false);
>> > > > if (ret) {
>> > > > DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>> > > > return ret;
>> > > > }
>> > > >
>> > > > - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
>> > > > + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0,
>0,
>> > > > +0);
>> > > > if (IS_ERR(vma)) {
>> > > > DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>> > > > return PTR_ERR(vma);
>> > > > @@ -450,14 +450,14 @@ static int guc_hw_reset(struct
>drm_i915_private *dev_priv)
>> > > > */
>> > > > int intel_guc_setup(struct drm_i915_private *dev_priv) {
>> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > - const char *fw_path = guc_fw->guc_fw_path;
>> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > + const char *fw_path = guc_fw->uc_fw_path;
>> > > > int retries, ret, err;
>> > > >
>> > > > DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
>> > > > fw_path,
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
>> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
>> > > >
>> > > > /* Loading forbidden, or no firmware to load? */
>> > > > if (!i915.enable_guc_loading) { @@ -475,10 +475,10 @@ int
>> > > > intel_guc_setup(struct drm_i915_private *dev_priv)
>> > > > }
>> > > >
>> > > > /* Fetch failed, or already fetched but failed to load? */
>> > > > - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
>> > > > + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
>> > > > err = -EIO;
>> > > > goto fail;
>> > > > - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
>> > > > + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
>> > > > err = -ENOEXEC;
>> > > > goto fail;
>> > > > }
>> > > > @@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private
>*dev_priv)
>> > > > guc_interrupts_release(dev_priv);
>> > > > gen9_reset_guc_interrupts(dev_priv);
>> > > >
>> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
>> > > > + guc_fw->load_status = UC_FIRMWARE_PENDING;
>> > > >
>> > > > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
>> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
>> > > >
>> > > > err = i915_guc_submission_init(dev_priv);
>> > > > if (err)
>> > > > @@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private
>*dev_priv)
>> > > > "retry %d more time(s)\n", err, retries);
>> > > > }
>> > > >
>> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
>> > > > + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
>> > > >
>> > > > DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> > > > + intel_uc_fw_status_repr(guc_fw->fetch_status),
>> > > > + intel_uc_fw_status_repr(guc_fw->load_status));
>> > > >
>> > > > if (i915.enable_guc_submission) {
>> > > > if (i915.guc_log_level >= 0)
>> > > > @@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private
>*dev_priv)
>> > > > return 0;
>> > > >
>> > > > fail:
>> > > > - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
>> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
>> > > > + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
>> > > > + guc_fw->load_status = UC_FIRMWARE_FAIL;
>> > > >
>> > > > guc_interrupts_release(dev_priv);
>> > > > i915_guc_submission_disable(dev_priv);
>> > > > @@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private
>*dev_priv)
>> > > > return ret;
>> > > > }
>> > > >
>> > > > -static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>> > > > - struct intel_guc_fw *guc_fw)
>> > > > +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>> > > > + struct intel_uc_fw *uc_fw)
>> > > > {
>> > > > struct pci_dev *pdev = dev_priv->drm.pdev;
>> > > > struct drm_i915_gem_object *obj; @@ -597,17 +597,17 @@ static
>> > > > void guc_fw_fetch(struct drm_i915_private *dev_priv,
>> > > > size_t size;
>> > > > int err;
>> > > >
>> > > > - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status
>%s\n",
>> > > > - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
>> > > > + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch
>status %s\n",
>> > > > + intel_uc_fw_status_repr(uc_fw->fetch_status));
>> > > >
>> > > > - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
>> > > > + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
>> > > > if (err)
>> > > > goto fail;
>> > > > if (!fw)
>> > > > goto fail;
>> > > >
>> > > > - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
>> > > > - guc_fw->guc_fw_path, fw);
>> > > > + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw
>%p\n",
>> > > > + uc_fw->uc_fw_path, fw);
>> > > >
>> > > > /* Check the size of the blob before examining buffer contents */
>> > > > if (fw->size < sizeof(struct guc_css_header)) { @@ -618,36
>> > > > +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>> > > > css = (struct guc_css_header *)fw->data;
>> > > >
>> > > > /* Firmware bits always start from header */
>> > > > - guc_fw->header_offset = 0;
>> > > > - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>> > > > + uc_fw->header_offset = 0;
>> > > > + uc_fw->header_size = (css->header_size_dw -
>> > > > +css->modulus_size_dw -
>> > > > css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>> > > >
>> > > > - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
>> > > > + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
>> > > > DRM_NOTE("CSS header definition mismatch\n");
>> > > > goto fail;
>> > > > }
>> > > >
>> > > > /* then, uCode */
>> > > > - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
>> > > > - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) *
>sizeof(u32);
>> > > > + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw-
>>header_size;
>> > > > + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) *
>> > > > +sizeof(u32);
>> > > >
>> > > > /* now RSA */
>> > > > if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
>> > > > DRM_NOTE("RSA key size is bad\n");
>> > > > goto fail;
>> > > > }
>> > > > - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
>> > > > - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>> > > > + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
>> > > > + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>> > > >
>> > > > /* At least, it should have header, uCode and RSA. Size of all three. */
>> > > > - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
>> > > > + size = uc_fw->header_size + uc_fw->ucode_size +
>> > > > +uc_fw->rsa_size;
>> > > > if (fw->size < size) {
>> > > > DRM_NOTE("Missing firmware components\n");
>> > > > goto fail;
>> > > > }
>> > > >
>> > > > /* Header and uCode will be loaded to WOPCM. Size of the two. */
>> > > > - size = guc_fw->header_size + guc_fw->ucode_size;
>> > > > + size = uc_fw->header_size + uc_fw->ucode_size;
>> > > > if (size > guc_wopcm_size(dev_priv)) {
>> > > > DRM_NOTE("Firmware is too large to fit in WOPCM\n");
>> > > > goto fail;
>> > > > @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct
>drm_i915_private *dev_priv,
>> > > > * TWO bytes each (i.e. u16), although all pointers and offsets are defined
>> > > > * in terms of bytes (u8).
>> > > > */
>> > > > - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
>> > > > - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
>> > > > -
>> > > > - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
>> > > > - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
>> > > > - DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
>> > > > - guc_fw->guc_fw_major_found, guc_fw-
>>guc_fw_minor_found,
>> > > > - guc_fw->guc_fw_major_wanted, guc_fw-
>>guc_fw_minor_wanted);
>> > > > + uc_fw->major_ver_found = css->guc_sw_version >> 16;
>> > > > + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>> > > > +
>> > > > + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>> > > > + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
>> > > > + DRM_NOTE("uC firmware version %d.%d, required
>%d.%d\n",
>> > > > + uc_fw->major_ver_found, uc_fw-
>>minor_ver_found,
>> > > > + uc_fw->major_ver_wanted, uc_fw-
>>minor_ver_wanted);
>> > > > err = -ENOEXEC;
>> > > > goto fail;
>> > > > }
>> > > >
>> > > > DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum
>%d.%d)\n",
>> > > > - guc_fw->guc_fw_major_found, guc_fw-
>>guc_fw_minor_found,
>> > > > - guc_fw->guc_fw_major_wanted, guc_fw-
>>guc_fw_minor_wanted);
>> > > > + uc_fw->major_ver_found, uc_fw-
>>minor_ver_found,
>> > > > + uc_fw->major_ver_wanted, uc_fw-
>>minor_ver_wanted);
>> > > >
>> > > > mutex_lock(&dev_priv->drm.struct_mutex);
>> > > > obj = i915_gem_object_create_from_data(dev_priv, fw->data,
>> > > > fw->size); @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct
>drm_i915_private *dev_priv,
>> > > > goto fail;
>> > > > }
>> > > >
>> > > > - guc_fw->guc_fw_obj = obj;
>> > > > - guc_fw->guc_fw_size = fw->size;
>> > > > + uc_fw->uc_fw_obj = obj;
>> > > > + uc_fw->uc_fw_size = fw->size;
>> > > >
>> > > > - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
>> > > > - guc_fw->guc_fw_obj);
>> > > > + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
>> > > > + uc_fw->uc_fw_obj);
>> > > >
>> > > > release_firmware(fw);
>> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
>> > > > + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
>> > > > return;
>> > > >
>> > > > fail:
>> > > > - DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
>> > > > - guc_fw->guc_fw_path, err);
>> > > > - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj
>%p\n",
>> > > > - err, fw, guc_fw->guc_fw_obj);
>> > > > + DRM_WARN("Failed to fetch valid uC firmware from %s (error
>%d)\n",
>> > > > + uc_fw->uc_fw_path, err);
>> > > > + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p,
>obj %p\n",
>> > > > + err, fw, uc_fw->uc_fw_obj);
>> > > >
>> > > > mutex_lock(&dev_priv->drm.struct_mutex);
>> > > > - obj = guc_fw->guc_fw_obj;
>> > > > + obj = uc_fw->uc_fw_obj;
>> > > > if (obj)
>> > > > i915_gem_object_put(obj);
>> > > > - guc_fw->guc_fw_obj = NULL;
>> > > > + uc_fw->uc_fw_obj = NULL;
>> > > > mutex_unlock(&dev_priv->drm.struct_mutex);
>> > > >
>> > > > release_firmware(fw); /* OK even if fw is NULL */
>> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
>> > > > + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
>> > > > }
>> > > >
>> > > > /**
>> > > > @@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private
>*dev_priv,
>> > > > */
>> > > > void intel_guc_init(struct drm_i915_private *dev_priv) {
>> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > const char *fw_path;
>> > > >
>> > > > if (!HAS_GUC(dev_priv)) {
>> > > > @@ -739,23 +739,24 @@ void intel_guc_init(struct drm_i915_private
>*dev_priv)
>> > > > fw_path = NULL;
>> > > > } else if (IS_SKYLAKE(dev_priv)) {
>> > > > fw_path = I915_SKL_GUC_UCODE;
>> > > > - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
>> > > > - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
>> > > > + guc_fw->major_ver_wanted = SKL_FW_MAJOR;
>> > > > + guc_fw->minor_ver_wanted = SKL_FW_MINOR;
>> > > > } else if (IS_BROXTON(dev_priv)) {
>> > > > fw_path = I915_BXT_GUC_UCODE;
>> > > > - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
>> > > > - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
>> > > > + guc_fw->major_ver_wanted = BXT_FW_MAJOR;
>> > > > + guc_fw->minor_ver_wanted = BXT_FW_MINOR;
>> > > > } else if (IS_KABYLAKE(dev_priv)) {
>> > > > fw_path = I915_KBL_GUC_UCODE;
>> > > > - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
>> > > > - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
>> > > > + guc_fw->major_ver_wanted = KBL_FW_MAJOR;
>> > > > + guc_fw->minor_ver_wanted = KBL_FW_MINOR;
>> > > > } else {
>> > > > fw_path = ""; /* unknown device */
>> > > > }
>> > > >
>> > > > - guc_fw->guc_fw_path = fw_path;
>> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
>> > > > - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
>> > > > + guc_fw->uc_dev = &dev_priv->drm;
>> > > > + guc_fw->uc_fw_path = fw_path;
>> > > > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
>> > > > + guc_fw->load_status = UC_FIRMWARE_NONE;
>> > > >
>> > > > /* Early (and silent) return if GuC loading is disabled */
>> > > > if (!i915.enable_guc_loading)
>> > > > @@ -765,9 +766,9 @@ void intel_guc_init(struct drm_i915_private
>*dev_priv)
>> > > > if (*fw_path == '\0')
>> > > > return;
>> > > >
>> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
>> > > > + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
>> > > > DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
>> > > > - guc_fw_fetch(dev_priv, guc_fw);
>> > > > + intel_uc_fw_fetch(dev_priv, guc_fw);
>> > > > /* status must now be FAIL or SUCCESS */ }
>> > > >
>> > > > @@ -777,17 +778,17 @@ void intel_guc_init(struct drm_i915_private
>*dev_priv)
>> > > > */
>> > > > void intel_guc_fini(struct drm_i915_private *dev_priv) {
>> > > > - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> > > >
>> > > > mutex_lock(&dev_priv->drm.struct_mutex);
>> > > > guc_interrupts_release(dev_priv);
>> > > > i915_guc_submission_disable(dev_priv);
>> > > > i915_guc_submission_fini(dev_priv);
>> > > >
>> > > > - if (guc_fw->guc_fw_obj)
>> > > > - i915_gem_object_put(guc_fw->guc_fw_obj);
>> > > > - guc_fw->guc_fw_obj = NULL;
>> > > > + if (guc_fw->uc_fw_obj)
>> > > > + i915_gem_object_put(guc_fw->uc_fw_obj);
>> > > > + guc_fw->uc_fw_obj = NULL;
>> > > > mutex_unlock(&dev_priv->drm.struct_mutex);
>> > > >
>> > > > - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
>> > > > + guc_fw->fetch_status = UC_FIRMWARE_NONE;
>> > > > }
>> > > > diff --git a/drivers/gpu/drm/i915/intel_uc.h
>> > > > b/drivers/gpu/drm/i915/intel_uc.h index 11f5608..f9f598d 100644
>> > > > --- a/drivers/gpu/drm/i915/intel_uc.h
>> > > > +++ b/drivers/gpu/drm/i915/intel_uc.h
>> > > > @@ -91,29 +91,31 @@ struct i915_guc_client {
>> > > > uint64_t submissions[I915_NUM_ENGINES]; };
>> > > >
>> > > > -enum intel_guc_fw_status {
>> > > > - GUC_FIRMWARE_FAIL = -1,
>> > > > - GUC_FIRMWARE_NONE = 0,
>> > > > - GUC_FIRMWARE_PENDING,
>> > > > - GUC_FIRMWARE_SUCCESS
>> > > > +enum intel_uc_fw_status {
>> > > > + UC_FIRMWARE_FAIL = -1,
>> > > > + UC_FIRMWARE_NONE = 0,
>> > > > + UC_FIRMWARE_PENDING,
>> > > > + UC_FIRMWARE_SUCCESS
>> > >
>> > > Shouldn't we use INTEL_UC_ prefix here (in similar way as in GUC_ACTION)?
Will do. Thanks for your review.
-Anusha
>> > >
>> > > > };
>> > > >
>> > > > /*
>> > > > * This structure encapsulates all the data needed during the process
>> > > > * of fetching, caching, and loading the firmware image into the GuC.
>> > > > */
>> > > > -struct intel_guc_fw {
>> > > > - const char * guc_fw_path;
>> > > > - size_t guc_fw_size;
>> > > > - struct drm_i915_gem_object * guc_fw_obj;
>> > > > - enum intel_guc_fw_status guc_fw_fetch_status;
>> > > > - enum intel_guc_fw_status guc_fw_load_status;
>> > > > -
>> > > > - uint16_t guc_fw_major_wanted;
>> > > > - uint16_t guc_fw_minor_wanted;
>> > > > - uint16_t guc_fw_major_found;
>> > > > - uint16_t guc_fw_minor_found;
>> > > > -
>> > > > +struct intel_uc_fw {
>> > > > + struct drm_device *uc_dev;
>> > >
>> > > Why do you need this back pointer to drm_dev ?
>> > > More likely all you need is pointer to dev_priv.
>> > > But for dev_priv you can always use guc_to_i915().
>> >
>> > It seems like a left over from the old days. I have a series that
>> > refactors all things GuC that I'll push here soon, including the
>> > removal of this field.
>> >
>> > Since this series advertises as a simple renaming I didn't force it
>> > here.
>>
>> If you want to treat this as simple 'renaming' then 'adding' unused
>> field is even more undesired and shall be avoided.
Michal, I don’t think I follow you completely here. Do you want me to rename it or wait for Arek's series?
>> >
>> > > > + const char *uc_fw_path;
>> > > > + size_t uc_fw_size;
>> > > > + struct drm_i915_gem_object *uc_fw_obj;
>> > >
>> > > All these uc_fw_ prefixes seem to be redundant as this struct is just about
>uc_fw.
>> > >
>> > >
>> > > > + enum intel_uc_fw_status fetch_status;
>> > > > + enum intel_uc_fw_status load_status;
>> > > > +
>> > > > + uint16_t major_ver_wanted;
>> > > > + uint16_t minor_ver_wanted;
>> > > > + uint16_t major_ver_found;
>> > > > + uint16_t minor_ver_found;
>> > > > +
>> > > > + uint32_t fw_type;
>> > >
>> > > What is the purpose of this field ?
>> >
>> > It is used in the patch 2, to set {major,minor}_ver_found depending
>> > on which firmware we pass to intel_uc_fw_fetch()
>>
>> Then maybe is shall be moved to patch 2 ?
>
>Sound reasonable as that's the first usage, although is also fits here along making
>te structs general. I have no strong opinion on that though.
>
Will put it in patch 2 then. Thanks.
>> >
>> > >
>> > > > uint32_t header_size;
>> > > > uint32_t header_offset;
>> > > > uint32_t rsa_size;
>> > > > @@ -139,7 +141,7 @@ struct intel_guc_log { };
>> > > >
>> > > > struct intel_guc {
>> > > > - struct intel_guc_fw guc_fw;
>> > > > + struct intel_uc_fw guc_fw;
>> > >
>> > > Btw, guc_ prefix in field name here is also redundant.
>> > >
>> > > > struct intel_guc_log log;
>> > > >
>> > > > /* intel_guc_recv interrupt related state */ @@ -181,7 +183,7
>> > > > @@ int intel_guc_log_control(struct intel_guc *guc, u32
>> > > > control_val); extern void intel_guc_init(struct
>> > > > drm_i915_private *dev_priv); extern int intel_guc_setup(struct
>> > > > drm_i915_private *dev_priv); extern void intel_guc_fini(struct
>> > > > drm_i915_private *dev_priv); -extern const char
>> > > > *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
>> > > > +extern const char *intel_uc_fw_status_repr(enum
>> > > > +intel_uc_fw_status status);
>> > > > extern int intel_guc_suspend(struct drm_i915_private
>> > > > *dev_priv); extern int intel_guc_resume(struct drm_i915_private
>> > > > *dev_priv);
>> > > >
>> > > > --
>> > > > 2.7.4
>> > > >
>> > > > _______________________________________________
>> > > > Intel-gfx mailing list
>> > > > Intel-gfx@lists.freedesktop.org
>> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >
>> > --
>> > Cheers,
>> > Arek
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Cheers,
>Arek
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-12-09 11:55 ` Michal Wajdeczko
@ 2016-12-09 21:42 ` Srivatsa, Anusha
2016-12-12 11:56 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-09 21:42 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
>-----Original Message-----
>From: Michal Wajdeczko [mailto:michal.wajdeczko@linux.intel.com]
>Sent: Friday, December 9, 2016 3:56 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for
>GuC and HuC
>
>On Thu, Dec 08, 2016 at 03:02:13PM -0800, anushasr wrote:
>> From: Peter Antoine <peter.antoine@intel.com>
>>
>> HuC firmware css header has almost exactly same definition as GuC
>> firmware except for the sw_version. Also, add a new member fw_type
>> into intel_uc_fw to indicate what kind of fw it is. So, the loader
>> will pull right sw_version from header.
>>
>> v2: rebased on-top of drm-intel-nightly
>> v3: rebased on-top of drm-intel-nightly (again).
>> v4: rebased + spaces.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Rename device_id to guc_branch_client_version, make
>> guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC and
>> UC_FW_TYPE_HUC into an enum.
>> v10: rebased.
>> v11: rebased.
>> v12: rebased on top of drm-tip.
>> v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
>>
>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++----
>> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-------
>----
>> drivers/gpu/drm/i915/intel_uc.h | 5 ++++
>> 3 files changed, 50 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index 3202b32..c1e7faf 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -145,7 +145,7 @@
>> * The GuC firmware layout looks like this:
>> *
>> * +-------------------------------+
>> - * | guc_css_header |
>> + * | uc_css_header |
>> * | |
>> * | contains major/minor version |
>> * +-------------------------------+
>> @@ -172,9 +172,16 @@
>> * 3. Length info of each component can be found in header, in dwords.
>> * 4. Modulus and exponent key are not required by driver. They may not
>appear
>> * in fw. So driver will load a truncated firmware in this case.
>> + *
>> + * HuC firmware layout is same as GuC firmware.
>> + *
>> + * HuC firmware css header is different. However, the only difference
>> + is where
>> + * the version information is saved. The uc_css_header is unified to
>> + support
>> + * both. Driver should get HuC version from
>> + uc_css_header.huc_sw_version, while
>> + * uc_css_header.guc_sw_version for GuC.
>> */
>>
>> -struct guc_css_header {
>> +struct uc_css_header {
>
>Hmm, I'm wondering why we don't use "intel_uc_" prefix for structs defined here.
>It seems that only enums are defined with intel_ prefix.
If we rename it to intel_uc_css_header, wont it be confused with intel_css_header in intel_csr.c? Unles we want to combine them....
>Also, it looks that this struct definition is very similar to the intel_css_header
>defined in intel_csr.c. Are there any plans to unify them all ?
>
No idea about any plans regarding unifying the struct in intel_csr.c and this struct. Arek, any idea?
>> uint32_t module_type;
>
>What values are used here? Are they the same as used in fw_type?
>
>
>> /* header_size includes all non-uCode bits, including css_header, rsa
>> * key, modulus key and exponent data. */ @@ -205,8 +212,14 @@
>> struct guc_css_header {
>>
>> char username[8];
>> char buildnumber[12];
>> - uint32_t device_id;
>> - uint32_t guc_sw_version;
>> + union {
>> + uint32_t guc_branch_client_version;
>> + uint32_t huc_sw_version;
>> + };
>> + union {
>> + uint32_t guc_sw_version;
>> + uint32_t huc_reserved;
>> + };
>
>Maybe to make this a little easier to read we can use:
>
>union {
> struct {
> uint32_t branch_client_version;
> uint32_t sw_version;
> } guc;
> struct {
> uint32_t sw_version;
> unit32_t reserved;
> } huc;
>};
Yes. Will do.
>
>> uint32_t prod_preprod_fw;
>> uint32_t reserved[12];
>> uint32_t header_info;
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 8f04f6e..26a184f 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>> struct pci_dev *pdev = dev_priv->drm.pdev;
>> struct drm_i915_gem_object *obj;
>> const struct firmware *fw = NULL;
>> - struct guc_css_header *css;
>> + struct uc_css_header *css;
>> size_t size;
>> int err;
>>
>> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>> uc_fw->uc_fw_path, fw);
>>
>> /* Check the size of the blob before examining buffer contents */
>> - if (fw->size < sizeof(struct guc_css_header)) {
>> + if (fw->size < sizeof(struct uc_css_header)) {
>> DRM_NOTE("Firmware header is missing\n");
>> goto fail;
>> }
>>
>> - css = (struct guc_css_header *)fw->data;
>> + css = (struct uc_css_header *)fw->data;
>>
>> /* Firmware bits always start from header */
>> uc_fw->header_offset = 0;
>> uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>>
>> - if (uc_fw->header_size != sizeof(struct guc_css_header)) {
>> + if (uc_fw->header_size != sizeof(struct uc_css_header)) {
>> DRM_NOTE("CSS header definition mismatch\n");
>> goto fail;
>> }
>> @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>> goto fail;
>> }
>>
>> - /* Header and uCode will be loaded to WOPCM. Size of the two. */
>> - size = uc_fw->header_size + uc_fw->ucode_size;
>> - if (size > guc_wopcm_size(dev_priv)) {
>> - DRM_NOTE("Firmware is too large to fit in WOPCM\n");
>> - goto fail;
>> - }
>> -
>> /*
>> * The GuC firmware image has the version number embedded at a well-
>known
>> * offset within the firmware blob; note that major / minor version are
>> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
>> * in terms of bytes (u8).
>> */
>> - uc_fw->major_ver_found = css->guc_sw_version >> 16;
>> - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>> + switch (uc_fw->fw_type) {
>> + case UC_FW_TYPE_GUC:
>> + /* Header and uCode will be loaded to WOPCM. Size of the two.
>*/
>> + size = uc_fw->header_size + uc_fw->ucode_size;
>> +
>> + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context).
>*/
>> + if (size > guc_wopcm_size(dev_priv)) {
>> + DRM_ERROR("Firmware is too large to fit in
>WOPCM\n");
>> + goto fail;
>> + }
>> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
>> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>> + break;
>> +
>> + case UC_FW_TYPE_HUC:
>> + uc_fw->major_ver_found = css->huc_sw_version >> 16;
>> + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
>> + break;
>> +
>> + default:
>> + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
>> + err = -ENOEXEC;
>> + goto fail;
>> + }
>>
>> if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>> uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { diff --git
>> a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
>> index f9f598d..be89f0b 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -98,6 +98,11 @@ enum intel_uc_fw_status {
>> UC_FIRMWARE_SUCCESS
>> };
>>
>> +enum {
>> + UC_FW_TYPE_GUC,
>> + UC_FW_TYPE_HUC
>
>Can we have INTEL_ prefix here?
>
>> +};
>> Yes. Thanks Michal.
Anusha
>> /*
>> * This structure encapsulates all the data needed during the process
>> * of fetching, caching, and loading the firmware image into the GuC.
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-09 12:17 ` Michal Wajdeczko
@ 2016-12-09 23:56 ` Srivatsa, Anusha
2016-12-12 11:50 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-09 23:56 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
>-----Original Message-----
>From: Michal Wajdeczko [mailto:michal.wajdeczko@linux.intel.com]
>Sent: Friday, December 9, 2016 4:18 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>On Thu, Dec 08, 2016 at 03:02:14PM -0800, anushasr wrote:
>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is
>> used for both cases.
>>
>> HuC loading needs to be before GuC loading. The WOPCM setting must be
>> done early before loading any of them.
>>
>> v2: rebased on-top of drm-intel-nightly.
>> removed if(HAS_GUC()) before the guc call. (D.Gordon)
>> update huc_version number of format.
>> v3: rebased to drm-intel-nightly, changed the file name format to
>> match the one in the huc package.
>> Changed dev->dev_private to to_i915()
>> v4: moved function back to where it was.
>> change wait_for_atomic to wait_for.
>> v5: rebased + comment changes.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Changed the year in the copyright message to reflect the
>> right year.Correct the comments,remove the unwanted WARN message,
>> replace drm_gem_object_unreference() with i915_gem_object_put().Make
>> the prototypes in intel_huc.h non-extern.
>> v10: rebased. Update the file construction done by HuC. It is similar
>> to GuC.Adopted the approach used in-
>> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
>> v11: Fix warnings remove old declaration
>> v12: Change dev to dev_priv in macro definition.
>> Corrected comments.
>> v13: rebased.
>> v14: rebased on top of drm-tip
>> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
>> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
>> of intel_huc.h to intel_uc.h
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>> drivers/gpu/drm/i915/Makefile | 1 +
>> drivers/gpu/drm/i915/i915_drv.c | 4 +-
>> drivers/gpu/drm/i915/i915_drv.h | 3 +-
>> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
>> drivers/gpu/drm/i915/intel_guc_loader.c | 7 +-
>> drivers/gpu/drm/i915/intel_huc_loader.c | 264
>++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_uc.h | 22 +++
>> 7 files changed, 299 insertions(+), 5 deletions(-) create mode
>> 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile
>> b/drivers/gpu/drm/i915/Makefile index 3c30916..01d4f4b 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \ # general-purpose
>> microcontroller (GuC) support i915-y += intel_uc.o \
>> intel_guc_loader.o \
>> + intel_huc_loader.o \
>> i915_guc_submission.o
>>
>> # autogenerated null render state
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c index 6428588..85a47c2 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device
>*dev)
>> if (ret)
>> goto cleanup_irq;
>>
>> + intel_huc_init(dev_priv);
>> intel_guc_init(dev_priv);
>>
>> ret = i915_gem_init(dev_priv);
>> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device
>*dev)
>> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
>> i915_gem_fini(dev_priv);
>> cleanup_irq:
>> + intel_huc_fini(dev);
>> intel_guc_fini(dev_priv);
>> drm_irq_uninstall(dev);
>> intel_teardown_gmbus(dev_priv);
>> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
>>
>> /* Flush any outstanding unpin_work. */
>> drain_workqueue(dev_priv->wq);
>> -
>> + intel_huc_fini(dev);
>> intel_guc_fini(dev_priv);
>> i915_gem_fini(dev_priv);
>> intel_fbc_cleanup_cfb(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 1480e73..0371ca4 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2036,6 +2036,7 @@ struct drm_i915_private {
>>
>> struct intel_gvt *gvt;
>>
>> + struct intel_huc huc;
>> struct intel_guc guc;
>>
>> struct intel_csr csr;
>> @@ -2810,7 +2811,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>> #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
>> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
>> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
>> -
>> +#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
>> #define HAS_RESOURCE_STREAMER(dev_priv)
>> ((dev_priv)->info.has_resource_streamer)
>>
>> #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
>> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
>> b/drivers/gpu/drm/i915/i915_guc_reg.h
>> index 5e638fc..f9829f6 100644
>> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
>> @@ -61,9 +61,12 @@
>> #define DMA_ADDRESS_SPACE_GTT (8 << 16)
>> #define DMA_COPY_SIZE _MMIO(0xc310)
>> #define DMA_CTRL _MMIO(0xc314)
>> +#define HUC_UKERNEL (1<<9)
>> #define UOS_MOVE (1<<4)
>> #define START_DMA (1<<0)
>> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
>> +#define HUC_LOADING_AGENT_VCR (0<<1)
>> +#define HUC_LOADING_AGENT_GUC (1<<1)
>> #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
>> #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 26a184f..b971351 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
>*dev_priv,
>> I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>>
>> /* Finally start the DMA */
>> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
>START_DMA));
>> -
>> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
>START_DMA) |
>> + _MASKED_BIT_DISABLE(HUC_UKERNEL));
>> /*
>> * Wait for the DMA to complete & the GuC to start up.
>> * NB: Docs recommend not using the interrupt for completion.
>> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
>*dev_priv,
>> return ret;
>> }
>>
>> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>> {
>> u32 wopcm_size = GUC_WOPCM_TOP;
>>
>> @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>> if (err)
>> goto fail;
>>
>> + intel_huc_load(dev_priv);
>> err = guc_ucode_xfer(dev_priv);
>> if (!err)
>> break;
>> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
>> b/drivers/gpu/drm/i915/intel_huc_loader.c
>> new file mode 100644
>> index 0000000..e0efd1c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
>> @@ -0,0 +1,264 @@
>> +/*
>> + * Copyright (c) 2016 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person
>> +obtaining a
>> + * copy of this software and associated documentation files (the
>> +"Software"),
>> + * to deal in the Software without restriction, including without
>> +limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,
>> +sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom
>> +the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including
>> +the next
>> + * paragraph) shall be included in all copies or substantial portions
>> +of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> +EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> +MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>EVENT
>> +SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
>DAMAGES
>> +OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> +ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> +OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
>> +#include <linux/firmware.h>
>> +#include "i915_drv.h"
>> +#include "intel_uc.h"
>> +
>> +/**
>> + * DOC: HuC Firmware
>> + *
>> + * Motivation:
>> + * GEN9 introduces a new dedicated firmware for usage in media HEVC
>> +(High
>> + * Efficiency Video Coding) operations. Userspace can use the
>> +firmware
>> + * capabilities by adding HuC specific commands to batch buffers.
>> + *
>> + * Implementation:
>> + * The same firmware loader is used as the GuC. However, the actual
>> + * loading to HW is deferred until GEM initialization is done.
>> + *
>> + * Note that HuC firmware loading must be done before GuC loading.
>> + */
>> +
>> +#define SKL_FW_MAJOR 01
>> +#define SKL_FW_MINOR 07
>
>Can we use SKL_HUC_FW_ prefix to distinguish these macros from similar defined
>in intel_guc_loader.c ?
Sure
>
>> +#define SKL_BLD_NUM 1398
>> +
>> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
>> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>> + __stringify(minor) "_" __stringify(bld_num) ".bin"
>> +
>> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
>> + SKL_FW_MINOR, SKL_BLD_NUM)
>> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>> +
>> +/**
>> + * huc_ucode_xfer() - DMA's the firmware
>> + * @dev_priv: the drm device
>> + *
>> + * This function takes the gem object containing the firmware, sets
>> +up the DMA
>> + * engine MMIO, triggers the DMA operation and waits for it to finish.
>> + *
>> + * Transfer the firmware image to RAM for execution by the microcontroller.
>> + *
>> + * Return: 0 on success, non-zero on failure */
>> +
>> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv) {
>> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
>> + struct i915_vma *vma;
>> + unsigned long offset = 0;
>> + u32 size;
>> + int ret;
>> +
>> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
>> + if (ret) {
>> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>> + return ret;
>> + }
>> +
>> + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
>> + if (IS_ERR(vma)) {
>> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>> + return PTR_ERR(vma);
>> + }
>> +
>> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>> +
>> + /* init WOPCM */
>> + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
>> + I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>GUC_WOPCM_OFFSET_VALUE |
>> + HUC_LOADING_AGENT_GUC);
>> +
>> + /* Set the source address for the uCode */
>> + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
>> + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>> + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>> +
>> + /* Hardware doesn't look at destination address for HuC. Set it to 0,
>> + * but still program the correct address space.
>> + */
>> + I915_WRITE(DMA_ADDR_1_LOW, 0);
>> + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>> +
>> + size = huc_fw->header_size + huc_fw->ucode_size;
>> + I915_WRITE(DMA_COPY_SIZE, size);
>> +
>> + /* Start the DMA */
>> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL |
>START_DMA));
>> +
>> + /* Wait for DMA to finish */
>> + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
>> +
>> + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
>> +
>> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>> +
>> + /*
>> + * We keep the object pages for reuse during resume. But we can unpin it
>> + * now that DMA has completed, so it doesn't continue to take up space.
>> + */
>> + i915_vma_unpin(vma);
>> +
>> + return ret;
>> +}
>> +
>> +/**
>> + * intel_huc_init() - initiate HuC firmware loading request
>> + * @dev: the drm device
>
>Mismatched param name.
>
>> + *
>> + * Called early during driver load, but after GEM is initialised. The
>> +loading
>> + * will continue only when driver explicitly specify firmware name and version.
>> + * All other cases are considered as UC_FIRMWARE_NONE either because
>> +HW is not
>> + * capable or driver yet support it. And there will be no error
>> +message for
>> + * UC_FIRMWARE_NONE cases.
>> + *
>> + * The DMA-copying to HW is done later when intel_huc_load() is called.
>> + */
>> +void intel_huc_init(struct drm_i915_private *dev_priv) {
>> + struct intel_huc *huc = &dev_priv->huc;
>
>Maybe *huc shall be passed as only param (to match intel_huc function name).
>Then dev_priv could be recreated from huc_to_i915().
Why? Can you elaborate?
-anusha
>
>> + struct intel_uc_fw *huc_fw = &huc->huc_fw;
>> + const char *fw_path = NULL;
>> +
>> + huc_fw->uc_fw_path = NULL;
>> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
>> + huc_fw->load_status = UC_FIRMWARE_NONE;
>> + huc_fw->fw_type = UC_FW_TYPE_HUC;
>> +
>> + if (!HAS_HUC_UCODE(dev_priv))
>> + return;
>> +
>> + if (IS_SKYLAKE(dev_priv)) {
>> + fw_path = I915_SKL_HUC_UCODE;
>> + huc_fw->major_ver_wanted = SKL_FW_MAJOR;
>> + huc_fw->minor_ver_wanted = SKL_FW_MINOR;
>> + }
>> +
>> + huc_fw->uc_fw_path = fw_path;
>> + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
>> +
>> + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
>> +
>> + intel_uc_fw_fetch(dev_priv, huc_fw); }
>> +
>> +/**
>> + * intel_huc_load() - load HuC uCode to device
>> + * @dev: the drm device
>
>Mismatched param name.
>
>
>> + *
>> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
>> + * Be note that HuC loading must be done before GuC loading.
>> + *
>> + * The firmware image should have already been fetched into memory by
>> +the
>> + * earlier call to intel_huc_init(), so here we need only check that
>> + * is succeeded, and then transfer the image to the h/w.
>> + *
>> + * Return: non-zero code on error
>> + */
>> +int intel_huc_load(struct drm_i915_private *dev_priv) {
>> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
>> + int err;
>> +
>> + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
>> + return 0;
>> +
>> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
>> + huc_fw->uc_fw_path,
>> + intel_uc_fw_status_repr(huc_fw->fetch_status),
>> + intel_uc_fw_status_repr(huc_fw->load_status));
>> +
>> + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
>> + huc_fw->load_status == UC_FIRMWARE_FAIL)
>> + return -ENOEXEC;
>> +
>> + huc_fw->load_status = UC_FIRMWARE_PENDING;
>> +
>> + switch (huc_fw->fetch_status) {
>> + case UC_FIRMWARE_FAIL:
>> + /* something went wrong :( */
>> + err = -EIO;
>> + goto fail;
>> +
>> + case UC_FIRMWARE_NONE:
>> + case UC_FIRMWARE_PENDING:
>> + default:
>> + /* "can't happen" */
>> + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
>> + huc_fw->uc_fw_path,
>> + intel_uc_fw_status_repr(huc_fw->fetch_status),
>> + huc_fw->fetch_status);
>> + err = -ENXIO;
>> + goto fail;
>> +
>> + case UC_FIRMWARE_SUCCESS:
>> + break;
>> + }
>> +
>> + err = huc_ucode_xfer(dev_priv);
>> + if (err)
>> + goto fail;
>> +
>> + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
>> +
>> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
>> + huc_fw->uc_fw_path,
>> + intel_uc_fw_status_repr(huc_fw->fetch_status),
>> + intel_uc_fw_status_repr(huc_fw->load_status));
>> +
>> + return 0;
>> +
>> +fail:
>> + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
>> + huc_fw->load_status = UC_FIRMWARE_FAIL;
>> +
>> + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
>> +
>> + return err;
>> +}
>> +
>> +/**
>> + * intel_huc_fini() - clean up resources allocated for HuC
>> + * @dev: the drm device
>> + *
>> + * Cleans up by releasing the huc firmware GEM obj.
>> + */
>> +void intel_huc_fini(struct drm_device *dev) {
>> + struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
>> +
>> + mutex_lock(&dev->struct_mutex);
>> + if (huc_fw->uc_fw_obj)
>> + i915_gem_object_put(huc_fw->uc_fw_obj);
>> + huc_fw->uc_fw_obj = NULL;
>> + mutex_unlock(&dev->struct_mutex);
>> +
>> + huc_fw->fetch_status = UC_FIRMWARE_NONE; }
>> +
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h
>> b/drivers/gpu/drm/i915/intel_uc.h index be89f0b..ac92946 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -24,6 +24,12 @@
>> #ifndef _INTEL_UC_H_
>> #define _INTEL_UC_H_
>>
>> +#ifndef _INTEL_HUC_H_
>> +#define _INTEL_HUC_H_
>
>Typo ? This is still intel_uc.h file, right ?
Yes it is intel_uc.h. Initially the above two initializations were in intel_huc.h. But now its contents are moved to intel_uc.h. One common file for guc and huc declarations.....
>
>> +
>> +#define HUC_STATUS2 _MMIO(0xD3B0)
>> +#define HUC_FW_VERIFIED (1<<7)
>> +
>
>Is it correct place for these defs?
>What about i915_guc_reg.h ?
This was also initially in intel_huc.h.
>
>> #include "intel_guc_fwif.h"
>> #include "i915_guc_reg.h"
>> #include "intel_ringbuffer.h"
>> @@ -175,6 +181,13 @@ struct intel_guc {
>> struct mutex send_mutex;
>> };
>>
>> +struct intel_huc {
>> + /* Generic uC firmware management */
>> + struct intel_uc_fw huc_fw;
>> +
>> + /* HuC-specific additions */
>> +};
>> +
>> /* intel_uc.c */
>> void intel_uc_init_early(struct drm_i915_private *dev_priv); bool
>> intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status); @@
>> -191,6 +204,9 @@ extern void intel_guc_fini(struct drm_i915_private
>> *dev_priv); extern const char *intel_uc_fw_status_repr(enum
>> intel_uc_fw_status status); extern int intel_guc_suspend(struct
>> drm_i915_private *dev_priv); extern int intel_guc_resume(struct
>> drm_i915_private *dev_priv);
>> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>> + struct intel_uc_fw *uc_fw);
>> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
>
>All other public functions have intel_ prefix.
Got it. Will change. Thanks
Cheers,
Anusha
>
>>
>> /* i915_guc_submission.c */
>> int i915_guc_submission_init(struct drm_i915_private *dev_priv); @@
>> -205,4 +221,10 @@ void i915_guc_register(struct drm_i915_private
>> *dev_priv); void i915_guc_unregister(struct drm_i915_private
>> *dev_priv); int i915_guc_log_control(struct drm_i915_private
>> *dev_priv, u64 control_val);
>>
>> +/* intel_huc_loader.c */
>> +void intel_huc_init(struct drm_i915_private *dev_priv); void
>> +intel_huc_fini(struct drm_device *dev); int intel_huc_load(struct
>> +drm_i915_private *dev_priv);
>> +
>> +#endif
>> #endif
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication
2016-12-09 12:36 ` Michal Wajdeczko
@ 2016-12-11 0:03 ` Srivatsa, Anusha
0 siblings, 0 replies; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-11 0:03 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
>-----Original Message-----
>From: Michal Wajdeczko [mailto:michal.wajdeczko@linux.intel.com]
>Sent: Friday, December 9, 2016 4:37 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication
>
>On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote:
>> From: Peter Antoine <peter.antoine@intel.com>
>>
>> The HuC authentication is done by host2guc call. The HuC RSA keys are
>> sent to GuC for authentication.
>>
>> v2: rebased on top of drm-intel-nightly.
>> changed name format and upped version 1.7.
>> v3: rebased on top of drm-intel-nightly.
>> v4: changed wait_for_automic to wait_for
>> v5: rebased.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place
>> the prototype in intel_guc.h,correct the comments.
>> v10: rebased.
>> v11: rebased.
>> v12: rebased on top of drm-tip
>> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to
>> intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
>> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
>> AUTHENTICATE_HUC
>>
>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
>> drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++
>> drivers/gpu/drm/i915/intel_uc.c | 61
>+++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_uc.h | 1 +
>> 4 files changed, 65 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index c1e7faf..94a974d 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -504,6 +504,7 @@ enum intel_guc_action {
>> INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>> INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>> INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>> + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>> INTEL_GUC_ACTION_LIMIT
>> };
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index b971351..89d092b 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>> intel_uc_fw_status_repr(guc_fw->fetch_status),
>> intel_uc_fw_status_repr(guc_fw->load_status));
>>
>> + intel_guc_auth_huc(dev_priv);
>> +
>> if (i915.enable_guc_submission) {
>> if (i915.guc_log_level >= 0)
>> gen9_enable_guc_interrupts(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> b/drivers/gpu/drm/i915/intel_uc.c index 8ae6795..445b9ad 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc,
>> u32 control_val)
>>
>> return intel_guc_send(guc, action, ARRAY_SIZE(action)); }
>> +
>> +/**
>> + * intel_guc_auth_huc() - authenticate ucode
>> + * @dev: the drm device
>
>Mismatched param name.
>
>
>> + *
>> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
>> + * interface.
>> + */
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
>
>Can we use *guc as the first param to match other intel_guc functions?
>
In function intel_guc_init() and intel_guc_load() we are using dev_priv as the first parameter.....
>> +{
>> + struct intel_guc *guc = &dev_priv->guc;
>> + struct intel_huc *huc = &dev_priv->huc;
>> + struct i915_vma *vma;
>> + int ret;
>> + u32 data[2];
>> +
>> + /* Bypass the case where there is no HuC firmware */
>> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
>> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
>> + return;
>> +
>> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
>> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
>
>Hmm, this looks like late handling of earlier error.
>Note that other functions in this file assume that Guc is working fine.
Michal, after intel_uc_init_early() which initializes a mutex lock, intel_guc_auth_huc() is the first function that the control goes to and hence all checking happens here. If anything is wrong a suitable error message is displayed and we return out immediately. If on the other hand things are proper, as expected post error checking, the other functions are called....
Hope this clears your concern.
-Anusha
>
>> + return;
>> + }
>> +
>> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
>> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
>> + return;
>> + }
>> +
>> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0,
>0);
>> + if (IS_ERR(vma)) {
>> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>> + return;
>> + }
>> +
>> +
>> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> + /* Specify auth action and where public signature is. */
>> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
>> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
>> +
>> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
>
>Hmm, maybe this function shall be split into two parts:
>
>intel_huc_auth() in intel_huc_loader.c that contains most of the logic from
>current function, but calls intel_guc_auth_huc() from this file that just sends
>action to the guc (similar to other simple functions in this file.
>
The intention is to make intel_guc_auth_huc() as simple as other functions in the file?
Two points on my mind-
1. Wont splitting into intel_huc_auth() and intel_guc_auth_huc() be more confusing than just intel_guc_auth_huc?
2.Even on splitting we will have only the preliminary check - check if guc is loaded, check if huc is loaded in intel_huc_Auth. The actual specification of authentication action, sending it to guc, checking if that is a success or not has to happen in intel_huc_auth_guc().
Am I correct?
>> + if (ret) {
>> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
>> + goto out;
>> + }
>> +
>> + /* Check authentication status, it should be done by now */
>> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0,
>50);
>> + if (ret) {
>> + DRM_ERROR("HuC: Authentication failed\n");
>> + goto out;
>> + }
>> +
>> +out:
>> + i915_vma_unpin(vma);
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
>> index ac92946..1db8bc2 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
>> int intel_guc_log_flush_complete(struct intel_guc *guc);
>> int intel_guc_log_flush(struct intel_guc *guc);
>> int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>>
>> /* intel_guc_loader.c */
>> extern void intel_guc_init(struct drm_i915_private *dev_priv);
>> --
>> 2.7.4
>>
Cheers,
Anusha
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-09 23:56 ` Srivatsa, Anusha
@ 2016-12-12 11:50 ` Arkadiusz Hiler
0 siblings, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-12 11:50 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx, Michal Wajdeczko
On Fri, Dec 09, 2016 at 11:56:20PM +0000, Srivatsa, Anusha wrote:
>
>
> >-----Original Message-----
> >From: Michal Wajdeczko [mailto:michal.wajdeczko@linux.intel.com]
> >Sent: Friday, December 9, 2016 4:18 AM
> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
> ><peter.antoine@intel.com>
> >Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
> >
> >On Thu, Dec 08, 2016 at 03:02:14PM -0800, anushasr wrote:
> >> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >>
> >> The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is
> >> used for both cases.
> >>
> >> HuC loading needs to be before GuC loading. The WOPCM setting must be
> >> done early before loading any of them.
> >>
> >> v2: rebased on-top of drm-intel-nightly.
> >> removed if(HAS_GUC()) before the guc call. (D.Gordon)
> >> update huc_version number of format.
> >> v3: rebased to drm-intel-nightly, changed the file name format to
> >> match the one in the huc package.
> >> Changed dev->dev_private to to_i915()
> >> v4: moved function back to where it was.
> >> change wait_for_atomic to wait_for.
> >> v5: rebased + comment changes.
> >> v7: rebased.
> >> v8: rebased.
> >> v9: rebased. Changed the year in the copyright message to reflect the
> >> right year.Correct the comments,remove the unwanted WARN message,
> >> replace drm_gem_object_unreference() with i915_gem_object_put().Make
> >> the prototypes in intel_huc.h non-extern.
> >> v10: rebased. Update the file construction done by HuC. It is similar
> >> to GuC.Adopted the approach used in-
> >> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
> >> v11: Fix warnings remove old declaration
> >> v12: Change dev to dev_priv in macro definition.
> >> Corrected comments.
> >> v13: rebased.
> >> v14: rebased on top of drm-tip
> >> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
> >> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
> >> of intel_huc.h to intel_uc.h
> >>
> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> Signed-off-by: Alex Dai <yu.dai@intel.com>
> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/Makefile | 1 +
> >> drivers/gpu/drm/i915/i915_drv.c | 4 +-
> >> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> >> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> >> drivers/gpu/drm/i915/intel_guc_loader.c | 7 +-
> >> drivers/gpu/drm/i915/intel_huc_loader.c | 264
> >++++++++++++++++++++++++++++++++
> >> drivers/gpu/drm/i915/intel_uc.h | 22 +++
> >> 7 files changed, 299 insertions(+), 5 deletions(-) create mode
> >> 100644 drivers/gpu/drm/i915/intel_huc_loader.c
> >>
> >> diff --git a/drivers/gpu/drm/i915/Makefile
> >> b/drivers/gpu/drm/i915/Makefile index 3c30916..01d4f4b 100644
> >> --- a/drivers/gpu/drm/i915/Makefile
> >> +++ b/drivers/gpu/drm/i915/Makefile
> >> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \ # general-purpose
> >> microcontroller (GuC) support i915-y += intel_uc.o \
> >> intel_guc_loader.o \
> >> + intel_huc_loader.o \
> >> i915_guc_submission.o
> >>
> >> # autogenerated null render state
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> >> b/drivers/gpu/drm/i915/i915_drv.c index 6428588..85a47c2 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.c
> >> +++ b/drivers/gpu/drm/i915/i915_drv.c
> >> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device
> >*dev)
> >> if (ret)
> >> goto cleanup_irq;
> >>
> >> + intel_huc_init(dev_priv);
> >> intel_guc_init(dev_priv);
> >>
> >> ret = i915_gem_init(dev_priv);
> >> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device
> >*dev)
> >> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> >> i915_gem_fini(dev_priv);
> >> cleanup_irq:
> >> + intel_huc_fini(dev);
> >> intel_guc_fini(dev_priv);
> >> drm_irq_uninstall(dev);
> >> intel_teardown_gmbus(dev_priv);
> >> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
> >>
> >> /* Flush any outstanding unpin_work. */
> >> drain_workqueue(dev_priv->wq);
> >> -
> >> + intel_huc_fini(dev);
> >> intel_guc_fini(dev_priv);
> >> i915_gem_fini(dev_priv);
> >> intel_fbc_cleanup_cfb(dev_priv);
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> b/drivers/gpu/drm/i915/i915_drv.h index 1480e73..0371ca4 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -2036,6 +2036,7 @@ struct drm_i915_private {
> >>
> >> struct intel_gvt *gvt;
> >>
> >> + struct intel_huc huc;
> >> struct intel_guc guc;
> >>
> >> struct intel_csr csr;
> >> @@ -2810,7 +2811,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >> #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
> >> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> >> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
> >> -
> >> +#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> >> #define HAS_RESOURCE_STREAMER(dev_priv)
> >> ((dev_priv)->info.has_resource_streamer)
> >>
> >> #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
> >> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
> >> b/drivers/gpu/drm/i915/i915_guc_reg.h
> >> index 5e638fc..f9829f6 100644
> >> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> >> @@ -61,9 +61,12 @@
> >> #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> >> #define DMA_COPY_SIZE _MMIO(0xc310)
> >> #define DMA_CTRL _MMIO(0xc314)
> >> +#define HUC_UKERNEL (1<<9)
> >> #define UOS_MOVE (1<<4)
> >> #define START_DMA (1<<0)
> >> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> >> +#define HUC_LOADING_AGENT_VCR (0<<1)
> >> +#define HUC_LOADING_AGENT_GUC (1<<1)
> >> #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
> >> #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> >> b/drivers/gpu/drm/i915/intel_guc_loader.c
> >> index 26a184f..b971351 100644
> >> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> >> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> >> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
> >*dev_priv,
> >> I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> >>
> >> /* Finally start the DMA */
> >> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> >START_DMA));
> >> -
> >> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> >START_DMA) |
> >> + _MASKED_BIT_DISABLE(HUC_UKERNEL));
> >> /*
> >> * Wait for the DMA to complete & the GuC to start up.
> >> * NB: Docs recommend not using the interrupt for completion.
> >> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
> >*dev_priv,
> >> return ret;
> >> }
> >>
> >> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> >> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> >> {
> >> u32 wopcm_size = GUC_WOPCM_TOP;
> >>
> >> @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> >> if (err)
> >> goto fail;
> >>
> >> + intel_huc_load(dev_priv);
> >> err = guc_ucode_xfer(dev_priv);
> >> if (!err)
> >> break;
> >> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> >> b/drivers/gpu/drm/i915/intel_huc_loader.c
> >> new file mode 100644
> >> index 0000000..e0efd1c
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> >> @@ -0,0 +1,264 @@
> >> +/*
> >> + * Copyright (c) 2016 Intel Corporation
> >> + *
> >> + * Permission is hereby granted, free of charge, to any person
> >> +obtaining a
> >> + * copy of this software and associated documentation files (the
> >> +"Software"),
> >> + * to deal in the Software without restriction, including without
> >> +limitation
> >> + * the rights to use, copy, modify, merge, publish, distribute,
> >> +sublicense,
> >> + * and/or sell copies of the Software, and to permit persons to whom
> >> +the
> >> + * Software is furnished to do so, subject to the following conditions:
> >> + *
> >> + * The above copyright notice and this permission notice (including
> >> +the next
> >> + * paragraph) shall be included in all copies or substantial portions
> >> +of the
> >> + * Software.
> >> + *
> >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> +EXPRESS OR
> >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> +MERCHANTABILITY,
> >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> >EVENT
> >> +SHALL
> >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> >DAMAGES
> >> +OR OTHER
> >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >> +ARISING
> >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >> +OTHER DEALINGS
> >> + * IN THE SOFTWARE.
> >> + *
> >> + */
> >> +#include <linux/firmware.h>
> >> +#include "i915_drv.h"
> >> +#include "intel_uc.h"
> >> +
> >> +/**
> >> + * DOC: HuC Firmware
> >> + *
> >> + * Motivation:
> >> + * GEN9 introduces a new dedicated firmware for usage in media HEVC
> >> +(High
> >> + * Efficiency Video Coding) operations. Userspace can use the
> >> +firmware
> >> + * capabilities by adding HuC specific commands to batch buffers.
> >> + *
> >> + * Implementation:
> >> + * The same firmware loader is used as the GuC. However, the actual
> >> + * loading to HW is deferred until GEM initialization is done.
> >> + *
> >> + * Note that HuC firmware loading must be done before GuC loading.
> >> + */
> >> +
> >> +#define SKL_FW_MAJOR 01
> >> +#define SKL_FW_MINOR 07
> >
> >Can we use SKL_HUC_FW_ prefix to distinguish these macros from similar defined
> >in intel_guc_loader.c ?
>
> Sure
> >
> >> +#define SKL_BLD_NUM 1398
> >> +
> >> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
> >> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> >> + __stringify(minor) "_" __stringify(bld_num) ".bin"
> >> +
> >> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
> >> + SKL_FW_MINOR, SKL_BLD_NUM)
> >> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> >> +
> >> +/**
> >> + * huc_ucode_xfer() - DMA's the firmware
> >> + * @dev_priv: the drm device
> >> + *
> >> + * This function takes the gem object containing the firmware, sets
> >> +up the DMA
> >> + * engine MMIO, triggers the DMA operation and waits for it to finish.
> >> + *
> >> + * Transfer the firmware image to RAM for execution by the microcontroller.
> >> + *
> >> + * Return: 0 on success, non-zero on failure */
> >> +
> >> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv) {
> >> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> >> + struct i915_vma *vma;
> >> + unsigned long offset = 0;
> >> + u32 size;
> >> + int ret;
> >> +
> >> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> >> + if (ret) {
> >> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> >> + if (IS_ERR(vma)) {
> >> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> >> + return PTR_ERR(vma);
> >> + }
> >> +
> >> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> >> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> >> +
> >> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> >> +
> >> + /* init WOPCM */
> >> + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> >> + I915_WRITE(DMA_GUC_WOPCM_OFFSET,
> >GUC_WOPCM_OFFSET_VALUE |
> >> + HUC_LOADING_AGENT_GUC);
> >> +
> >> + /* Set the source address for the uCode */
> >> + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> >> + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> >> + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> >> +
> >> + /* Hardware doesn't look at destination address for HuC. Set it to 0,
> >> + * but still program the correct address space.
> >> + */
> >> + I915_WRITE(DMA_ADDR_1_LOW, 0);
> >> + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> >> +
> >> + size = huc_fw->header_size + huc_fw->ucode_size;
> >> + I915_WRITE(DMA_COPY_SIZE, size);
> >> +
> >> + /* Start the DMA */
> >> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL |
> >START_DMA));
> >> +
> >> + /* Wait for DMA to finish */
> >> + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> >> +
> >> + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> >> +
> >> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> >> +
> >> + /*
> >> + * We keep the object pages for reuse during resume. But we can unpin it
> >> + * now that DMA has completed, so it doesn't continue to take up space.
> >> + */
> >> + i915_vma_unpin(vma);
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +/**
> >> + * intel_huc_init() - initiate HuC firmware loading request
> >> + * @dev: the drm device
> >
> >Mismatched param name.
> >
> >> + *
> >> + * Called early during driver load, but after GEM is initialised. The
> >> +loading
> >> + * will continue only when driver explicitly specify firmware name and version.
> >> + * All other cases are considered as UC_FIRMWARE_NONE either because
> >> +HW is not
> >> + * capable or driver yet support it. And there will be no error
> >> +message for
> >> + * UC_FIRMWARE_NONE cases.
> >> + *
> >> + * The DMA-copying to HW is done later when intel_huc_load() is called.
> >> + */
> >> +void intel_huc_init(struct drm_i915_private *dev_priv) {
> >> + struct intel_huc *huc = &dev_priv->huc;
> >
> >Maybe *huc shall be passed as only param (to match intel_huc function name).
> >Then dev_priv could be recreated from huc_to_i915().
>
> Why? Can you elaborate?
> -anusha
> >
> >> + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> >> + const char *fw_path = NULL;
> >> +
> >> + huc_fw->uc_fw_path = NULL;
> >> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> >> + huc_fw->load_status = UC_FIRMWARE_NONE;
> >> + huc_fw->fw_type = UC_FW_TYPE_HUC;
> >> +
> >> + if (!HAS_HUC_UCODE(dev_priv))
> >> + return;
> >> +
> >> + if (IS_SKYLAKE(dev_priv)) {
> >> + fw_path = I915_SKL_HUC_UCODE;
> >> + huc_fw->major_ver_wanted = SKL_FW_MAJOR;
> >> + huc_fw->minor_ver_wanted = SKL_FW_MINOR;
> >> + }
> >> +
> >> + huc_fw->uc_fw_path = fw_path;
> >> + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> >> +
> >> + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> >> +
> >> + intel_uc_fw_fetch(dev_priv, huc_fw); }
> >> +
> >> +/**
> >> + * intel_huc_load() - load HuC uCode to device
> >> + * @dev: the drm device
> >
> >Mismatched param name.
> >
> >
> >> + *
> >> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> >> + * Be note that HuC loading must be done before GuC loading.
> >> + *
> >> + * The firmware image should have already been fetched into memory by
> >> +the
> >> + * earlier call to intel_huc_init(), so here we need only check that
> >> + * is succeeded, and then transfer the image to the h/w.
> >> + *
> >> + * Return: non-zero code on error
> >> + */
> >> +int intel_huc_load(struct drm_i915_private *dev_priv) {
> >> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> >> + int err;
> >> +
> >> + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> >> + return 0;
> >> +
> >> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> >> + huc_fw->uc_fw_path,
> >> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> >> + intel_uc_fw_status_repr(huc_fw->load_status));
> >> +
> >> + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> >> + huc_fw->load_status == UC_FIRMWARE_FAIL)
> >> + return -ENOEXEC;
> >> +
> >> + huc_fw->load_status = UC_FIRMWARE_PENDING;
> >> +
> >> + switch (huc_fw->fetch_status) {
> >> + case UC_FIRMWARE_FAIL:
> >> + /* something went wrong :( */
> >> + err = -EIO;
> >> + goto fail;
> >> +
> >> + case UC_FIRMWARE_NONE:
> >> + case UC_FIRMWARE_PENDING:
> >> + default:
> >> + /* "can't happen" */
> >> + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> >> + huc_fw->uc_fw_path,
> >> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> >> + huc_fw->fetch_status);
> >> + err = -ENXIO;
> >> + goto fail;
> >> +
> >> + case UC_FIRMWARE_SUCCESS:
> >> + break;
> >> + }
> >> +
> >> + err = huc_ucode_xfer(dev_priv);
> >> + if (err)
> >> + goto fail;
> >> +
> >> + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> >> +
> >> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> >> + huc_fw->uc_fw_path,
> >> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> >> + intel_uc_fw_status_repr(huc_fw->load_status));
> >> +
> >> + return 0;
> >> +
> >> +fail:
> >> + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> >> + huc_fw->load_status = UC_FIRMWARE_FAIL;
> >> +
> >> + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> >> +
> >> + return err;
> >> +}
> >> +
> >> +/**
> >> + * intel_huc_fini() - clean up resources allocated for HuC
> >> + * @dev: the drm device
> >> + *
> >> + * Cleans up by releasing the huc firmware GEM obj.
> >> + */
> >> +void intel_huc_fini(struct drm_device *dev) {
> >> + struct drm_i915_private *dev_priv = to_i915(dev);
> >> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> >> +
> >> + mutex_lock(&dev->struct_mutex);
> >> + if (huc_fw->uc_fw_obj)
> >> + i915_gem_object_put(huc_fw->uc_fw_obj);
> >> + huc_fw->uc_fw_obj = NULL;
> >> + mutex_unlock(&dev->struct_mutex);
> >> +
> >> + huc_fw->fetch_status = UC_FIRMWARE_NONE; }
> >> +
> >> diff --git a/drivers/gpu/drm/i915/intel_uc.h
> >> b/drivers/gpu/drm/i915/intel_uc.h index be89f0b..ac92946 100644
> >> --- a/drivers/gpu/drm/i915/intel_uc.h
> >> +++ b/drivers/gpu/drm/i915/intel_uc.h
> >> @@ -24,6 +24,12 @@
> >> #ifndef _INTEL_UC_H_
> >> #define _INTEL_UC_H_
> >>
> >> +#ifndef _INTEL_HUC_H_
> >> +#define _INTEL_HUC_H_
> >
> >Typo ? This is still intel_uc.h file, right ?
>
> Yes it is intel_uc.h. Initially the above two initializations were in intel_huc.h. But now its contents are moved to intel_uc.h. One common file for guc and huc declarations.....
But those are guards that assure us that the content of header file is
included one. The name should come strictly from the file name. One
guard is enough. So drop the _INTEL_HUC_H_ and just leave the
_INTEL_UC_H_
> >
> >> +
> >> +#define HUC_STATUS2 _MMIO(0xD3B0)
> >> +#define HUC_FW_VERIFIED (1<<7)
> >> +
> >
> >Is it correct place for these defs?
> >What about i915_guc_reg.h ?
> This was also initially in intel_huc.h.
> >
> >> #include "intel_guc_fwif.h"
> >> #include "i915_guc_reg.h"
> >> #include "intel_ringbuffer.h"
> >> @@ -175,6 +181,13 @@ struct intel_guc {
> >> struct mutex send_mutex;
> >> };
> >>
> >> +struct intel_huc {
> >> + /* Generic uC firmware management */
> >> + struct intel_uc_fw huc_fw;
> >> +
> >> + /* HuC-specific additions */
> >> +};
> >> +
> >> /* intel_uc.c */
> >> void intel_uc_init_early(struct drm_i915_private *dev_priv); bool
> >> intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status); @@
> >> -191,6 +204,9 @@ extern void intel_guc_fini(struct drm_i915_private
> >> *dev_priv); extern const char *intel_uc_fw_status_repr(enum
> >> intel_uc_fw_status status); extern int intel_guc_suspend(struct
> >> drm_i915_private *dev_priv); extern int intel_guc_resume(struct
> >> drm_i915_private *dev_priv);
> >> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> >> + struct intel_uc_fw *uc_fw);
> >> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
> >
> >All other public functions have intel_ prefix.
> Got it. Will change. Thanks
>
> Cheers,
> Anusha
> >
> >>
> >> /* i915_guc_submission.c */
> >> int i915_guc_submission_init(struct drm_i915_private *dev_priv); @@
> >> -205,4 +221,10 @@ void i915_guc_register(struct drm_i915_private
> >> *dev_priv); void i915_guc_unregister(struct drm_i915_private
> >> *dev_priv); int i915_guc_log_control(struct drm_i915_private
> >> *dev_priv, u64 control_val);
> >>
> >> +/* intel_huc_loader.c */
> >> +void intel_huc_init(struct drm_i915_private *dev_priv); void
> >> +intel_huc_fini(struct drm_device *dev); int intel_huc_load(struct
> >> +drm_i915_private *dev_priv);
> >> +
> >> +#endif
> >> #endif
> >> --
> >> 2.7.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-12-09 21:42 ` Srivatsa, Anusha
@ 2016-12-12 11:56 ` Arkadiusz Hiler
0 siblings, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-12 11:56 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx, Michal Wajdeczko
On Fri, Dec 09, 2016 at 09:42:06PM +0000, Srivatsa, Anusha wrote:
>
>
> >-----Original Message-----
> >From: Michal Wajdeczko [mailto:michal.wajdeczko@linux.intel.com]
> >Sent: Friday, December 9, 2016 3:56 AM
> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
> ><peter.antoine@intel.com>
> >Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for
> >GuC and HuC
> >
> >On Thu, Dec 08, 2016 at 03:02:13PM -0800, anushasr wrote:
> >> From: Peter Antoine <peter.antoine@intel.com>
> >>
> >> HuC firmware css header has almost exactly same definition as GuC
> >> firmware except for the sw_version. Also, add a new member fw_type
> >> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> >> will pull right sw_version from header.
> >>
> >> v2: rebased on-top of drm-intel-nightly
> >> v3: rebased on-top of drm-intel-nightly (again).
> >> v4: rebased + spaces.
> >> v7: rebased.
> >> v8: rebased.
> >> v9: rebased. Rename device_id to guc_branch_client_version, make
> >> guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC and
> >> UC_FW_TYPE_HUC into an enum.
> >> v10: rebased.
> >> v11: rebased.
> >> v12: rebased on top of drm-tip.
> >> v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
> >>
> >> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> Signed-off-by: Alex Dai <yu.dai@intel.com>
> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++----
> >> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-------
> >----
> >> drivers/gpu/drm/i915/intel_uc.h | 5 ++++
> >> 3 files changed, 50 insertions(+), 17 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> >> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> >> index 3202b32..c1e7faf 100644
> >> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> >> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> >> @@ -145,7 +145,7 @@
> >> * The GuC firmware layout looks like this:
> >> *
> >> * +-------------------------------+
> >> - * | guc_css_header |
> >> + * | uc_css_header |
> >> * | |
> >> * | contains major/minor version |
> >> * +-------------------------------+
> >> @@ -172,9 +172,16 @@
> >> * 3. Length info of each component can be found in header, in dwords.
> >> * 4. Modulus and exponent key are not required by driver. They may not
> >appear
> >> * in fw. So driver will load a truncated firmware in this case.
> >> + *
> >> + * HuC firmware layout is same as GuC firmware.
> >> + *
> >> + * HuC firmware css header is different. However, the only difference
> >> + is where
> >> + * the version information is saved. The uc_css_header is unified to
> >> + support
> >> + * both. Driver should get HuC version from
> >> + uc_css_header.huc_sw_version, while
> >> + * uc_css_header.guc_sw_version for GuC.
> >> */
> >>
> >> -struct guc_css_header {
> >> +struct uc_css_header {
> >
> >Hmm, I'm wondering why we don't use "intel_uc_" prefix for structs defined here.
> >It seems that only enums are defined with intel_ prefix.
> If we rename it to intel_uc_css_header, wont it be confused with intel_css_header in intel_csr.c? Unles we want to combine them....
>
> >Also, it looks that this struct definition is very similar to the intel_css_header
> >defined in intel_csr.c. Are there any plans to unify them all ?
> >
> No idea about any plans regarding unifying the struct in intel_csr.c and this struct. Arek, any idea?
Currently not, but that seems like idea worth exploring. I'll look into
it this week and if it turns sensible to do, I'll add it to my GuC
cleanup series.
> >> uint32_t module_type;
> >
> >What values are used here? Are they the same as used in fw_type?
module_type is just a part of HuC/GuC's firmware header (css). You can
read it from the blobs:
module_type for guc == 0006 0000 00a1 0000 (v6, v4)
module_type for huc == 0006 0000 00a1 0000 (v1)
It's kind of magic value to determine it's a firmware (I am not aware of
other values than the one above, but that might change in the future).
We do not check for that exact field though. We do not use it at all,
but that, as well, might change in the future.
fw_type provides means to distingush between HuC/GuC FW.
> >
> >> /* header_size includes all non-uCode bits, including css_header, rsa
> >> * key, modulus key and exponent data. */ @@ -205,8 +212,14 @@
> >> struct guc_css_header {
> >>
> >> char username[8];
> >> char buildnumber[12];
> >> - uint32_t device_id;
> >> - uint32_t guc_sw_version;
> >> + union {
> >> + uint32_t guc_branch_client_version;
> >> + uint32_t huc_sw_version;
> >> + };
> >> + union {
> >> + uint32_t guc_sw_version;
> >> + uint32_t huc_reserved;
> >> + };
> >
> >Maybe to make this a little easier to read we can use:
> >
> >union {
> > struct {
> > uint32_t branch_client_version;
> > uint32_t sw_version;
> > } guc;
> > struct {
> > uint32_t sw_version;
> > unit32_t reserved;
> > } huc;
> >};
> Yes. Will do.
> >
> >> uint32_t prod_preprod_fw;
> >> uint32_t reserved[12];
> >> uint32_t header_info;
> >> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> >> b/drivers/gpu/drm/i915/intel_guc_loader.c
> >> index 8f04f6e..26a184f 100644
> >> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> >> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> >> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_i915_private
> >*dev_priv,
> >> struct pci_dev *pdev = dev_priv->drm.pdev;
> >> struct drm_i915_gem_object *obj;
> >> const struct firmware *fw = NULL;
> >> - struct guc_css_header *css;
> >> + struct uc_css_header *css;
> >> size_t size;
> >> int err;
> >>
> >> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_i915_private
> >*dev_priv,
> >> uc_fw->uc_fw_path, fw);
> >>
> >> /* Check the size of the blob before examining buffer contents */
> >> - if (fw->size < sizeof(struct guc_css_header)) {
> >> + if (fw->size < sizeof(struct uc_css_header)) {
> >> DRM_NOTE("Firmware header is missing\n");
> >> goto fail;
> >> }
> >>
> >> - css = (struct guc_css_header *)fw->data;
> >> + css = (struct uc_css_header *)fw->data;
> >>
> >> /* Firmware bits always start from header */
> >> uc_fw->header_offset = 0;
> >> uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> >> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
> >>
> >> - if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> >> + if (uc_fw->header_size != sizeof(struct uc_css_header)) {
> >> DRM_NOTE("CSS header definition mismatch\n");
> >> goto fail;
> >> }
> >> @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_i915_private
> >*dev_priv,
> >> goto fail;
> >> }
> >>
> >> - /* Header and uCode will be loaded to WOPCM. Size of the two. */
> >> - size = uc_fw->header_size + uc_fw->ucode_size;
> >> - if (size > guc_wopcm_size(dev_priv)) {
> >> - DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> >> - goto fail;
> >> - }
> >> -
> >> /*
> >> * The GuC firmware image has the version number embedded at a well-
> >known
> >> * offset within the firmware blob; note that major / minor version are
> >> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> >> * in terms of bytes (u8).
> >> */
> >> - uc_fw->major_ver_found = css->guc_sw_version >> 16;
> >> - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> >> + switch (uc_fw->fw_type) {
> >> + case UC_FW_TYPE_GUC:
> >> + /* Header and uCode will be loaded to WOPCM. Size of the two.
> >*/
> >> + size = uc_fw->header_size + uc_fw->ucode_size;
> >> +
> >> + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context).
> >*/
> >> + if (size > guc_wopcm_size(dev_priv)) {
> >> + DRM_ERROR("Firmware is too large to fit in
> >WOPCM\n");
> >> + goto fail;
> >> + }
> >> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> >> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> >> + break;
> >> +
> >> + case UC_FW_TYPE_HUC:
> >> + uc_fw->major_ver_found = css->huc_sw_version >> 16;
> >> + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
> >> + break;
> >> +
> >> + default:
> >> + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
> >> + err = -ENOEXEC;
> >> + goto fail;
> >> + }
> >>
> >> if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> >> uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { diff --git
> >> a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> >> index f9f598d..be89f0b 100644
> >> --- a/drivers/gpu/drm/i915/intel_uc.h
> >> +++ b/drivers/gpu/drm/i915/intel_uc.h
> >> @@ -98,6 +98,11 @@ enum intel_uc_fw_status {
> >> UC_FIRMWARE_SUCCESS
> >> };
> >>
> >> +enum {
> >> + UC_FW_TYPE_GUC,
> >> + UC_FW_TYPE_HUC
> >
> >Can we have INTEL_ prefix here?
> >
> >> +};
> >> Yes. Thanks Michal.
>
>
> Anusha
> >> /*
> >> * This structure encapsulates all the data needed during the process
> >> * of fetching, caching, and loading the firmware image into the GuC.
> >> --
> >> 2.7.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-09 12:59 ` Michal Wajdeczko
@ 2016-12-12 14:13 ` Arkadiusz Hiler
2016-12-12 14:21 ` Chris Wilson
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-12 14:13 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
On Fri, Dec 09, 2016 at 01:59:45PM +0100, Michal Wajdeczko wrote:
> On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > This patch will allow for getparams to return the status of the HuC.
> > As the HuC has to be validated by the GuC this patch uses the validated
> > status to show when the HuC is loaded and ready for use. You cannot use
> > the loaded status as with the GuC as the HuC is verified after it is
> > loaded and is not usable until it is verified.
> >
> > v2: removed the forewakes as the registers are already force-woken.
> > (T.Ursulin)
> > v4: rebased.
> > v5: rebased on top of drm-tip.
> > v6: rebased. Removed any reference to intel_huc.h
> >
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
> > drivers/gpu/drm/i915/intel_uc.h | 1 +
> > include/uapi/drm/i915_drm.h | 1 +
> > 4 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 85a47c2..6be06a27 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -49,6 +49,7 @@
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > #include "intel_drv.h"
> > +#include "intel_uc.h"
> >
> > static struct drm_driver driver;
> >
> > @@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > */
> > value = 1;
> > break;
> > + case I915_PARAM_HAS_HUC:
>
> For me this param name does not match returned result which maybe misleading.
> Note that other HAS params return static driver/hw capability, not runtime.
>
> I guess PARAM_HUC_STATUS would be better (0=no huc, 1=pending, 2=ok, -1=failed)
> And you can cache huc status in intel_huc struct and make final modification in
> intel_huc_auth() function to avoid registry read (unless we want to detect later
> crash of the huc using this reg read)
Why should userspace care for those intermediary states? From what I
know (docs and patches from the cover letter) userspace is interested
only in being able to use HuC. If something is not working you have
DebugFS for that exact purpose.
As of cacheing - seems like a good idea to limit reg reads.
> > + value = intel_is_huc_valid(dev_priv);
> > + break;
> > default:
> > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> > index 96fc727..6704cc8 100644
> > --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > @@ -289,3 +289,15 @@ void intel_huc_fini(struct drm_device *dev)
> > huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > }
> >
> > +/**
> > + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> > + * @dev_priv: drm device to check.
> > + *
> > + * This function will return true if the guc has been loaded and
>
> Please change function return type to bool to match this description.
>
> > + * has valid firmware. The simplest way of doing this is to check
> > + * if the HuC has been validated, if so it must have been loaded.
> > + */
> > +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> > +{
> > + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> > +}
> > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> > index 1db8bc2..ccd3f69 100644
> > --- a/drivers/gpu/drm/i915/intel_uc.h
> > +++ b/drivers/gpu/drm/i915/intel_uc.h
> > @@ -226,6 +226,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
> > void intel_huc_init(struct drm_i915_private *dev_priv);
> > void intel_huc_fini(struct drm_device *dev);
> > int intel_huc_load(struct drm_i915_private *dev_priv);
> > +int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> >
> > #endif
> > #endif
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index da32c2f..3e1964c 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
> > * priorities and the driver will attempt to execute batches in priority order.
> > */
> > #define I915_PARAM_HAS_SCHEDULER 41
> > +#define I915_PARAM_HAS_HUC 42
> >
> > typedef struct drm_i915_getparam {
> > __s32 param;
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-12 14:13 ` Arkadiusz Hiler
@ 2016-12-12 14:21 ` Chris Wilson
2016-12-12 14:52 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Chris Wilson @ 2016-12-12 14:21 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: intel-gfx, Michal Wajdeczko
On Mon, Dec 12, 2016 at 03:13:17PM +0100, Arkadiusz Hiler wrote:
> On Fri, Dec 09, 2016 at 01:59:45PM +0100, Michal Wajdeczko wrote:
> > On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
> > > From: Peter Antoine <peter.antoine@intel.com>
> > >
> > > This patch will allow for getparams to return the status of the HuC.
> > > As the HuC has to be validated by the GuC this patch uses the validated
> > > status to show when the HuC is loaded and ready for use. You cannot use
> > > the loaded status as with the GuC as the HuC is verified after it is
> > > loaded and is not usable until it is verified.
> > >
> > > v2: removed the forewakes as the registers are already force-woken.
> > > (T.Ursulin)
> > > v4: rebased.
> > > v5: rebased on top of drm-tip.
> > > v6: rebased. Removed any reference to intel_huc.h
> > >
> > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > > drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
> > > drivers/gpu/drm/i915/intel_uc.h | 1 +
> > > include/uapi/drm/i915_drm.h | 1 +
> > > 4 files changed, 18 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index 85a47c2..6be06a27 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -49,6 +49,7 @@
> > > #include "i915_trace.h"
> > > #include "i915_vgpu.h"
> > > #include "intel_drv.h"
> > > +#include "intel_uc.h"
> > >
> > > static struct drm_driver driver;
> > >
> > > @@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > */
> > > value = 1;
> > > break;
> > > + case I915_PARAM_HAS_HUC:
> >
> > For me this param name does not match returned result which maybe misleading.
> > Note that other HAS params return static driver/hw capability, not runtime.
> >
> > I guess PARAM_HUC_STATUS would be better (0=no huc, 1=pending, 2=ok, -1=failed)
> > And you can cache huc status in intel_huc struct and make final modification in
> > intel_huc_auth() function to avoid registry read (unless we want to detect later
> > crash of the huc using this reg read)
>
> Why should userspace care for those intermediary states? From what I
> know (docs and patches from the cover letter) userspace is interested
> only in being able to use HuC. If something is not working you have
> DebugFS for that exact purpose.
>
> As of cacheing - seems like a good idea to limit reg reads.
Is GETPARAM(HAS_HUC) a hot path? Should we even encourage it?
Are there any other users of intel_huc_is_valid()?
As for userspace simply asking where huc is enabled, we already have
that in the ABI via the module parameter, so you need to justify why
this is preferred (in addition to the available information).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-12 14:21 ` Chris Wilson
@ 2016-12-12 14:52 ` Arkadiusz Hiler
2016-12-12 15:17 ` Chris Wilson
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-12 14:52 UTC (permalink / raw)
To: Chris Wilson, Michal Wajdeczko, intel-gfx
On Mon, Dec 12, 2016 at 02:21:41PM +0000, Chris Wilson wrote:
> On Mon, Dec 12, 2016 at 03:13:17PM +0100, Arkadiusz Hiler wrote:
> > On Fri, Dec 09, 2016 at 01:59:45PM +0100, Michal Wajdeczko wrote:
> > > On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
> > > > From: Peter Antoine <peter.antoine@intel.com>
> > > >
> > > > This patch will allow for getparams to return the status of the HuC.
> > > > As the HuC has to be validated by the GuC this patch uses the validated
> > > > status to show when the HuC is loaded and ready for use. You cannot use
> > > > the loaded status as with the GuC as the HuC is verified after it is
> > > > loaded and is not usable until it is verified.
> > > >
> > > > v2: removed the forewakes as the registers are already force-woken.
> > > > (T.Ursulin)
> > > > v4: rebased.
> > > > v5: rebased on top of drm-tip.
> > > > v6: rebased. Removed any reference to intel_huc.h
> > > >
> > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > > > drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
> > > > drivers/gpu/drm/i915/intel_uc.h | 1 +
> > > > include/uapi/drm/i915_drm.h | 1 +
> > > > 4 files changed, 18 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > index 85a47c2..6be06a27 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -49,6 +49,7 @@
> > > > #include "i915_trace.h"
> > > > #include "i915_vgpu.h"
> > > > #include "intel_drv.h"
> > > > +#include "intel_uc.h"
> > > >
> > > > static struct drm_driver driver;
> > > >
> > > > @@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > > */
> > > > value = 1;
> > > > break;
> > > > + case I915_PARAM_HAS_HUC:
> > >
> > > For me this param name does not match returned result which maybe misleading.
> > > Note that other HAS params return static driver/hw capability, not runtime.
> > >
> > > I guess PARAM_HUC_STATUS would be better (0=no huc, 1=pending, 2=ok, -1=failed)
> > > And you can cache huc status in intel_huc struct and make final modification in
> > > intel_huc_auth() function to avoid registry read (unless we want to detect later
> > > crash of the huc using this reg read)
> >
> > Why should userspace care for those intermediary states? From what I
> > know (docs and patches from the cover letter) userspace is interested
> > only in being able to use HuC. If something is not working you have
> > DebugFS for that exact purpose.
> >
> > As of cacheing - seems like a good idea to limit reg reads.
>
> Is GETPARAM(HAS_HUC) a hot path? Should we even encourage it?
Actually... Good point. HAS_HUC is used once each time you initialise
libva client.
> Are there any other users of intel_huc_is_valid()?
intel_guc_auth_huc() uses
ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
So it can be reused there.
> As for userspace simply asking where huc is enabled, we already have
> that in the ABI via the module parameter, so you need to justify why
> this is preferred (in addition to the available information).
Yeah, we do change the values of module parameters. But a lot of them
are uid 0 only and we have PARAMS for those.
Do anything userspace use those actually? Do we plan to use them instead
of the getparams since now on?
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-12 14:52 ` Arkadiusz Hiler
@ 2016-12-12 15:17 ` Chris Wilson
2016-12-12 15:27 ` Arkadiusz Hiler
2016-12-12 19:20 ` Srivatsa, Anusha
0 siblings, 2 replies; 71+ messages in thread
From: Chris Wilson @ 2016-12-12 15:17 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: intel-gfx, Michal Wajdeczko
On Mon, Dec 12, 2016 at 03:52:05PM +0100, Arkadiusz Hiler wrote:
> On Mon, Dec 12, 2016 at 02:21:41PM +0000, Chris Wilson wrote:
> > As for userspace simply asking where huc is enabled, we already have
> > that in the ABI via the module parameter, so you need to justify why
> > this is preferred (in addition to the available information).
>
> Yeah, we do change the values of module parameters. But a lot of them
> are uid 0 only and we have PARAMS for those.
>
> Do anything userspace use those actually? Do we plan to use them instead
> of the getparams since now on?
I've done both from userspace... I don't really have a preference, once
you have an fd, an ioctl/GETPARAM is trivial. But for quick querying and
reporting of driver state, reading the module parameter is easier. So I
have a tendency to use an ioctl in production code and module parameter
in igt. (And I would say that for one-off validation purposes, i.e. did
hte module actually enable huc?, just check the module parameter. If
userspace is expected to interact and respond to the setting during its
early probe, make it an ioctl so it fits in with the similar code also
being run at that time.)
It is just worth explaining the intended usecase in the cover note, so
that the use can be sanity checked and reflected upon later if need be.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-12 15:17 ` Chris Wilson
@ 2016-12-12 15:27 ` Arkadiusz Hiler
2016-12-12 19:20 ` Srivatsa, Anusha
1 sibling, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-12 15:27 UTC (permalink / raw)
To: Chris Wilson, Michal Wajdeczko, intel-gfx
On Mon, Dec 12, 2016 at 03:17:16PM +0000, Chris Wilson wrote:
> On Mon, Dec 12, 2016 at 03:52:05PM +0100, Arkadiusz Hiler wrote:
> > On Mon, Dec 12, 2016 at 02:21:41PM +0000, Chris Wilson wrote:
> > > As for userspace simply asking where huc is enabled, we already have
> > > that in the ABI via the module parameter, so you need to justify why
> > > this is preferred (in addition to the available information).
> >
> > Yeah, we do change the values of module parameters. But a lot of them
> > are uid 0 only and we have PARAMS for those.
> >
> > Do anything userspace use those actually? Do we plan to use them instead
> > of the getparams since now on?
>
> I've done both from userspace... I don't really have a preference, once
> you have an fd, an ioctl/GETPARAM is trivial. But for quick querying and
> reporting of driver state, reading the module parameter is easier. So I
> have a tendency to use an ioctl in production code and module parameter
> in igt. (And I would say that for one-off validation purposes, i.e. did
> hte module actually enable huc?, just check the module parameter.
Thank you for explaining it :)
> If userspace is expected to interact and respond to the setting
> during its early probe, make it an ioctl so it fits in with the
> similar code also being run at that time.)
Okay. Seems like the scenario Anusha's got.
> It is just worth explaining the intended usecase in the cover note, so
> that the use can be sanity checked and reflected upon later if need be.
> -Chris
The cover letter links patches from the libva which is pretty much a
template usecase, but I agree, it wold be nice if it used
words/pseudocode instead of portions of code from some other project.
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-08 23:02 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support anushasr
2016-12-09 10:56 ` Arkadiusz Hiler
2016-12-09 12:17 ` Michal Wajdeczko
@ 2016-12-12 18:52 ` Tvrtko Ursulin
2016-12-14 15:19 ` Jani Nikula
2 siblings, 1 reply; 71+ messages in thread
From: Tvrtko Ursulin @ 2016-12-12 18:52 UTC (permalink / raw)
To: anushasr, intel-gfx; +Cc: Jani Nikula
Hi all,
Executive decision required below:
On 08/12/2016 23:02, anushasr wrote:
[snip]
> +
> +/**
> + * DOC: HuC Firmware
> + *
> + * Motivation:
> + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can use the firmware
> + * capabilities by adding HuC specific commands to batch buffers.
> + *
> + * Implementation:
> + * The same firmware loader is used as the GuC. However, the actual
> + * loading to HW is deferred until GEM initialization is done.
> + *
> + * Note that HuC firmware loading must be done before GuC loading.
> + */
> +
> +#define SKL_FW_MAJOR 01
> +#define SKL_FW_MINOR 07
> +#define SKL_BLD_NUM 1398
> +
> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> + __stringify(minor) "_" __stringify(bld_num) ".bin"
> +
> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
> + SKL_FW_MINOR, SKL_BLD_NUM)
> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
Daniel & Jani, I understand in the GuC firmware discussions you were
very much in the favour of encoding the full name (major and minor
included) as the fw firmware?
Argument was that we want to in effect claim support only for one
validated firmware binary with one version of i915.
In the case of the HuC we have a very similar situation with two key
differences.
First, there is a build number in the file name as provided by the
firmware team. We know that it will happen that only the build number
changes with some fixes and the minor stays the same. And we know that
the major indicates the interface compatibility.
Secondly, from all I can see, there are no interactions between the
driver and the HuC firmware apart from driver loading it and thats it.
In the light of that I was advocating only using the major in the driver
request fw name in order to improve usability both for developers
(easier to test with different firmwares), and for users (be it
distributions or end users - easier to upgrade the HuC firmware in case
of codec issues by not having to patch and recompile the kernel).
Since I understand this topic has been beaten to death in the past and
there are strong opinions on it, could you just okay (or not) the
current proposal (as in posted patches) which encodes major, minor and
build number in the fw name?
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-12 15:17 ` Chris Wilson
2016-12-12 15:27 ` Arkadiusz Hiler
@ 2016-12-12 19:20 ` Srivatsa, Anusha
1 sibling, 0 replies; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-12 19:20 UTC (permalink / raw)
To: Chris Wilson, Hiler, Arkadiusz; +Cc: intel-gfx, Michal Wajdeczko
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Chris Wilson
>Sent: Monday, December 12, 2016 7:17 AM
>To: Hiler, Arkadiusz <arkadiusz.hiler@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Michal Wajdeczko
><michal.wajdeczko@linux.intel.com>
>Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to
>getparams
>
>On Mon, Dec 12, 2016 at 03:52:05PM +0100, Arkadiusz Hiler wrote:
>> On Mon, Dec 12, 2016 at 02:21:41PM +0000, Chris Wilson wrote:
>> > As for userspace simply asking where huc is enabled, we already have
>> > that in the ABI via the module parameter, so you need to justify why
>> > this is preferred (in addition to the available information).
>>
>> Yeah, we do change the values of module parameters. But a lot of them
>> are uid 0 only and we have PARAMS for those.
>>
>> Do anything userspace use those actually? Do we plan to use them
>> instead of the getparams since now on?
>
>I've done both from userspace... I don't really have a preference, once you have
>an fd, an ioctl/GETPARAM is trivial. But for quick querying and reporting of driver
>state, reading the module parameter is easier. So I have a tendency to use an
>ioctl in production code and module parameter in igt. (And I would say that for
>one-off validation purposes, i.e. did hte module actually enable huc?, just check
>the module parameter. If userspace is expected to interact and respond to the
>setting during its early probe, make it an ioctl so it fits in with the similar code
>also being run at that time.)
>
>It is just worth explaining the intended usecase in the cover note, so that the use
>can be sanity checked and reflected upon later if need be.
>-Chris
>
Thanks for explaining Chris....
Anusha
>Chris Wilson, Intel Open Source Technology Centre
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-08 23:55 ` Chris Wilson
@ 2016-12-13 9:40 ` Arkadiusz Hiler
2016-12-14 1:02 ` Srivatsa, Anusha
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-13 9:40 UTC (permalink / raw)
To: Chris Wilson, anushasr, intel-gfx, Peter Antoine
On Thu, Dec 08, 2016 at 11:55:34PM +0000, Chris Wilson wrote:
> On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > This patch will allow for getparams to return the status of the HuC.
> > As the HuC has to be validated by the GuC this patch uses the validated
> > status to show when the HuC is loaded and ready for use. You cannot use
> > the loaded status as with the GuC as the HuC is verified after it is
> > loaded and is not usable until it is verified.
> >
> > v2: removed the forewakes as the registers are already force-woken.
> > (T.Ursulin)
> > v4: rebased.
> > v5: rebased on top of drm-tip.
> > v6: rebased. Removed any reference to intel_huc.h
> >
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
> > drivers/gpu/drm/i915/intel_uc.h | 1 +
> > include/uapi/drm/i915_drm.h | 1 +
> > 4 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 85a47c2..6be06a27 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -49,6 +49,7 @@
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > #include "intel_drv.h"
> > +#include "intel_uc.h"
> >
> > static struct drm_driver driver;
> >
> > @@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > */
> > value = 1;
> > break;
> > + case I915_PARAM_HAS_HUC:
> > + value = intel_is_huc_valid(dev_priv);
> > + break;
>
> Why did you put it here? It breaks the pattern of case statements.
>
> > default:
> > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> > index 96fc727..6704cc8 100644
> > --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > @@ -289,3 +289,15 @@ void intel_huc_fini(struct drm_device *dev)
> > huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > }
> >
> > +/**
> > + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> > + * @dev_priv: drm device to check.
> > + *
> > + * This function will return true if the guc has been loaded and
> > + * has valid firmware. The simplest way of doing this is to check
> > + * if the HuC has been validated, if so it must have been loaded.
> > + */
> > +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
>
> bool
>
> > +{
> > + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
>
> (brackets (because (brackets)))
>
> But what I really wanted to ask... Does this register access require the
> device to be awake and powered?
Just confirmed that this register indeed requires MEDIA FW.
> -Chris
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-13 9:40 ` Arkadiusz Hiler
@ 2016-12-14 1:02 ` Srivatsa, Anusha
0 siblings, 0 replies; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-14 1:02 UTC (permalink / raw)
To: Hiler, Arkadiusz, Chris Wilson, intel-gfx, Peter Antoine
>-----Original Message-----
>From: Hiler, Arkadiusz
>Sent: Tuesday, December 13, 2016 1:41 AM
>To: Chris Wilson <chris@chris-wilson.co.uk>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>; intel-gfx@lists.freedesktop.org; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to
>getparams
>
>On Thu, Dec 08, 2016 at 11:55:34PM +0000, Chris Wilson wrote:
>> On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
>> > From: Peter Antoine <peter.antoine@intel.com>
>> >
>> > This patch will allow for getparams to return the status of the HuC.
>> > As the HuC has to be validated by the GuC this patch uses the
>> > validated status to show when the HuC is loaded and ready for use.
>> > You cannot use the loaded status as with the GuC as the HuC is
>> > verified after it is loaded and is not usable until it is verified.
>> >
>> > v2: removed the forewakes as the registers are already force-woken.
>> > (T.Ursulin)
>> > v4: rebased.
>> > v5: rebased on top of drm-tip.
>> > v6: rebased. Removed any reference to intel_huc.h
>> >
>> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>> > drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
>> > drivers/gpu/drm/i915/intel_uc.h | 1 +
>> > include/uapi/drm/i915_drm.h | 1 +
>> > 4 files changed, 18 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> > b/drivers/gpu/drm/i915/i915_drv.c index 85a47c2..6be06a27 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.c
>> > +++ b/drivers/gpu/drm/i915/i915_drv.c
>> > @@ -49,6 +49,7 @@
>> > #include "i915_trace.h"
>> > #include "i915_vgpu.h"
>> > #include "intel_drv.h"
>> > +#include "intel_uc.h"
>> >
>> > static struct drm_driver driver;
>> >
>> > @@ -349,6 +350,9 @@ static int i915_getparam(struct drm_device *dev, void
>*data,
>> > */
>> > value = 1;
>> > break;
>> > + case I915_PARAM_HAS_HUC:
>> > + value = intel_is_huc_valid(dev_priv);
>> > + break;
>>
>> Why did you put it here? It breaks the pattern of case statements.
>>
>> > default:
>> > DRM_DEBUG("Unknown parameter %d\n", param->param);
>> > return -EINVAL;
>> > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
>> > b/drivers/gpu/drm/i915/intel_huc_loader.c
>> > index 96fc727..6704cc8 100644
>> > --- a/drivers/gpu/drm/i915/intel_huc_loader.c
>> > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
>> > @@ -289,3 +289,15 @@ void intel_huc_fini(struct drm_device *dev)
>> > huc_fw->fetch_status = UC_FIRMWARE_NONE; }
>> >
>> > +/**
>> > + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
>> > + * @dev_priv: drm device to check.
>> > + *
>> > + * This function will return true if the guc has been loaded and
>> > + * has valid firmware. The simplest way of doing this is to check
>> > + * if the HuC has been validated, if so it must have been loaded.
>> > + */
>> > +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
>>
>> bool
>>
>> > +{
>> > + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
>>
>> (brackets (because (brackets)))
>>
>> But what I really wanted to ask... Does this register access require
>> the device to be awake and powered?
>
>Just confirmed that this register indeed requires MEDIA FW.
Thanks Arek.
>> -Chris
>
>--
>Cheers,
>Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-12 18:52 ` Tvrtko Ursulin
@ 2016-12-14 15:19 ` Jani Nikula
2016-12-14 15:24 ` Parenteau, Paul A
0 siblings, 1 reply; 71+ messages in thread
From: Jani Nikula @ 2016-12-14 15:19 UTC (permalink / raw)
To: Tvrtko Ursulin, anushasr, intel-gfx
On Mon, 12 Dec 2016, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> Hi all,
>
> Executive decision required below:
>
> On 08/12/2016 23:02, anushasr wrote:
>
> [snip]
>
>> +
>> +/**
>> + * DOC: HuC Firmware
>> + *
>> + * Motivation:
>> + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
>> + * Efficiency Video Coding) operations. Userspace can use the firmware
>> + * capabilities by adding HuC specific commands to batch buffers.
>> + *
>> + * Implementation:
>> + * The same firmware loader is used as the GuC. However, the actual
>> + * loading to HW is deferred until GEM initialization is done.
>> + *
>> + * Note that HuC firmware loading must be done before GuC loading.
>> + */
>> +
>> +#define SKL_FW_MAJOR 01
>> +#define SKL_FW_MINOR 07
>> +#define SKL_BLD_NUM 1398
>> +
>> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
>> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>> + __stringify(minor) "_" __stringify(bld_num) ".bin"
>> +
>> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
>> + SKL_FW_MINOR, SKL_BLD_NUM)
>> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>
> Daniel & Jani, I understand in the GuC firmware discussions you were
> very much in the favour of encoding the full name (major and minor
> included) as the fw firmware?
>
> Argument was that we want to in effect claim support only for one
> validated firmware binary with one version of i915.
>
> In the case of the HuC we have a very similar situation with two key
> differences.
>
> First, there is a build number in the file name as provided by the
> firmware team. We know that it will happen that only the build number
> changes with some fixes and the minor stays the same. And we know that
> the major indicates the interface compatibility.
>
> Secondly, from all I can see, there are no interactions between the
> driver and the HuC firmware apart from driver loading it and thats it.
>
> In the light of that I was advocating only using the major in the driver
> request fw name in order to improve usability both for developers
> (easier to test with different firmwares), and for users (be it
> distributions or end users - easier to upgrade the HuC firmware in case
> of codec issues by not having to patch and recompile the kernel).
>
> Since I understand this topic has been beaten to death in the past and
> there are strong opinions on it, could you just okay (or not) the
> current proposal (as in posted patches) which encodes major, minor and
> build number in the fw name?
The question is the same as it ever was, can you absolutely guarantee a
new firmware version (even if just a build number bump) will not cause
regressions? Note that we'll probably only have resources to test the
latest kernel against the latest firmware, but accepting future firmware
versions means even stable kernels will start using the new firmware
versions after linux-firmware updates. We also can't easily
retroactively prevent this from happening even if we find out that there
will be breakage.
I still think we should only accept one firmware version. If we (or
someone else) has the resources to test against older kernels, commits
to enable newer firmware versions can be backported to stable.
I would love to be able to look at the firmware sources and say, oh,
there are no interactions with the kernel whatsoever, but you know how
that is. I don't know if there are interactions. I don't know if future
blobs will have interactions, and break everything if the kernel doesn't
do something the black box expects.
If you want to help developers test various firmware versions, I suggest
the same thing I suggested the last time: add an _unsafe module
parameter to specify the firmware filename/version to load.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-12-14 15:19 ` Jani Nikula
@ 2016-12-14 15:24 ` Parenteau, Paul A
0 siblings, 0 replies; 71+ messages in thread
From: Parenteau, Paul A @ 2016-12-14 15:24 UTC (permalink / raw)
To: Nikula, Jani, Tvrtko Ursulin, Srivatsa, Anusha, intel-gfx
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Jani Nikula
>Sent: Wednesday, December 14, 2016 7:20 AM
>To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>On Mon, 12 Dec 2016, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> Hi all,
>>
>> Executive decision required below:
>>
>> On 08/12/2016 23:02, anushasr wrote:
>>
>> [snip]
>>
>>> +
>>> +/**
>>> + * DOC: HuC Firmware
>>> + *
>>> + * Motivation:
>>> + * GEN9 introduces a new dedicated firmware for usage in media HEVC
>>> +(High
>>> + * Efficiency Video Coding) operations. Userspace can use the
>>> +firmware
>>> + * capabilities by adding HuC specific commands to batch buffers.
>>> + *
>>> + * Implementation:
>>> + * The same firmware loader is used as the GuC. However, the actual
>>> + * loading to HW is deferred until GEM initialization is done.
>>> + *
>>> + * Note that HuC firmware loading must be done before GuC loading.
>>> + */
>>> +
>>> +#define SKL_FW_MAJOR 01
>>> +#define SKL_FW_MINOR 07
>>> +#define SKL_BLD_NUM 1398
>>> +
>>> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
>>> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>>> + __stringify(minor) "_" __stringify(bld_num) ".bin"
>>> +
>>> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
>>> + SKL_FW_MINOR, SKL_BLD_NUM)
>>> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>>
>> Daniel & Jani, I understand in the GuC firmware discussions you were
>> very much in the favour of encoding the full name (major and minor
>> included) as the fw firmware?
>>
>> Argument was that we want to in effect claim support only for one
>> validated firmware binary with one version of i915.
>>
>> In the case of the HuC we have a very similar situation with two key
>> differences.
>>
>> First, there is a build number in the file name as provided by the
>> firmware team. We know that it will happen that only the build number
>> changes with some fixes and the minor stays the same. And we know that
>> the major indicates the interface compatibility.
>>
>> Secondly, from all I can see, there are no interactions between the
>> driver and the HuC firmware apart from driver loading it and thats it.
>>
>> In the light of that I was advocating only using the major in the
>> driver request fw name in order to improve usability both for
>> developers (easier to test with different firmwares), and for users
>> (be it distributions or end users - easier to upgrade the HuC firmware
>> in case of codec issues by not having to patch and recompile the kernel).
>>
>> Since I understand this topic has been beaten to death in the past and
>> there are strong opinions on it, could you just okay (or not) the
>> current proposal (as in posted patches) which encodes major, minor and
>> build number in the fw name?
>
>The question is the same as it ever was, can you absolutely guarantee a new
>firmware version (even if just a build number bump) will not cause regressions?
>Note that we'll probably only have resources to test the latest kernel against the
>latest firmware, but accepting future firmware versions means even stable
>kernels will start using the new firmware versions after linux-firmware updates.
>We also can't easily retroactively prevent this from happening even if we find
>out that there will be breakage.
>
>I still think we should only accept one firmware version. If we (or someone else)
>has the resources to test against older kernels, commits to enable newer
>firmware versions can be backported to stable.
>
I agree with Jani's position here. We have to keep some controls to the combinations of FW and kernels so we know what works. At least until FW matures in the future.
>
>I would love to be able to look at the firmware sources and say, oh, there are no
>interactions with the kernel whatsoever, but you know how that is. I don't know
>if there are interactions. I don't know if future blobs will have interactions, and
>break everything if the kernel doesn't do something the black box expects.
>
>If you want to help developers test various firmware versions, I suggest the same
>thing I suggested the last time: add an _unsafe module parameter to specify the
>firmware filename/version to load.
>
>BR,
>Jani.
>
>
>--
>Jani Nikula, Intel Open Source Technology Center
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2017-01-14 1:17 [PATCH 0/8] " Anusha Srivatsa
@ 2017-01-14 1:17 ` Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2017-01-14 1:17 UTC (permalink / raw)
To: intel-gfx
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v3: rebased on top of drm-tip. Removed any reference to intel_huc.h
v4: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v5: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7a0b49..49a927a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+ case I915_PARAM_HUC_STATUS:
+ /* The register is already force-woken. We dont need
+ * any rpm here
+ */
+ value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
* earlier versions as 0, in effect their value is undefined as
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2017-01-13 18:08 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2017-01-13 18:08 ` Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2017-01-13 18:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v3: rebased on top of drm-tip. Removed any reference to intel_huc.h
v4: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v5: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7a0b49..49a927a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+ case I915_PARAM_HUC_STATUS:
+ /* The register is already force-woken. We dont need
+ * any rpm here
+ */
+ value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
* earlier versions as 0, in effect their value is undefined as
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
@ 2017-01-13 17:07 Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2017-01-13 17:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v3: rebased on top of drm-tip. Removed any reference to intel_huc.h
v4: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v5: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7a0b49..49a927a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+ case I915_PARAM_HUC_STATUS:
+ /* The register is already force-woken. We dont need
+ * any rpm here
+ */
+ value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
* earlier versions as 0, in effect their value is undefined as
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2017-01-04 14:55 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2017-01-04 14:55 ` Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2017-01-04 14:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased on top of drm-tip.
v6: rebased. Removed any reference to intel_huc.h
v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v8: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.
v9: rebased.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
include/uapi/drm/i915_drm.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c9f71e0..723442c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+ case I915_PARAM_HUC_STATUS:
+ /* The register is already force-woken. We dont need
+ * any rpm here
+ */
+ value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
* earlier versions as 0, in effect their value is undefined as
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 57fc48b..af75d1d 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -281,4 +281,3 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
}
-
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2017-01-04 13:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2017-01-04 13:27 ` Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2017-01-04 13:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased on top of drm-tip.
v6: rebased. Removed any reference to intel_huc.h
v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v8: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.
v9: rebased.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
include/uapi/drm/i915_drm.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c9f71e0..723442c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+ case I915_PARAM_HUC_STATUS:
+ /* The register is already force-woken. We dont need
+ * any rpm here
+ */
+ value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
* earlier versions as 0, in effect their value is undefined as
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 051e7ba..d0a7547 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -281,4 +281,3 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
}
-
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-22 23:12 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
@ 2016-12-23 14:33 ` Arkadiusz Hiler
0 siblings, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-23 14:33 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Peter Antoine
On Thu, Dec 22, 2016 at 03:12:24PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased on top of drm-tip.
> v6: rebased. Removed any reference to intel_huc.h
> v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> Remove intel_is_huc_valid() since it is used only in one place.
> Put the case of I915_PARAM_HAS_HUC() in the right place.
> v8: rebased. Add a comment to specify that I915_READ(reg)
> does not read garbage value. The register HUC_STATUS2 is force
> woken and no rpm is needed.
>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Where is your s-o-b?
other than that:
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-22 23:12 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2016-12-22 23:12 ` Anusha Srivatsa
2016-12-23 14:33 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Anusha Srivatsa @ 2016-12-22 23:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased on top of drm-tip.
v6: rebased. Removed any reference to intel_huc.h
v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v8: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
include/uapi/drm/i915_drm.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 85a47c2..c4f0620 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+ case I915_PARAM_HUC_STATUS:
+ /* The register is already force-woken. We dont need
+ * any rpm here
+ */
+ value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
* earlier versions as 0, in effect their value is undefined as
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 75f3dc5..dd42676 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -284,4 +284,3 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
}
-
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-16 18:46 ` Chris Wilson
@ 2016-12-16 18:55 ` Srivatsa, Anusha
0 siblings, 0 replies; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-16 18:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
>-----Original Message-----
>From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
>Sent: Friday, December 16, 2016 10:47 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: Hiler, Arkadiusz <arkadiusz.hiler@intel.com>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to
>getparams
>
>On Fri, Dec 16, 2016 at 06:31:46PM +0000, Srivatsa, Anusha wrote:
>>
>>
>> >-----Original Message-----
>> >From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
>> >Sent: Friday, December 16, 2016 8:31 AM
>> >To: Hiler, Arkadiusz <arkadiusz.hiler@intel.com>
>> >Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
>> >gfx@lists.freedesktop.org
>> >Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC
>> >status to getparams
>> >
>> >On Fri, Dec 16, 2016 at 05:21:38PM +0100, Arkadiusz Hiler wrote:
>> >> On Fri, Dec 16, 2016 at 04:12:36PM +0000, Chris Wilson wrote:
>> >> > On Fri, Dec 16, 2016 at 03:43:46PM +0100, Arkadiusz Hiler wrote:
>> >> > > On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
>> >> > > > On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
>> >> > > > > From: Peter Antoine <peter.antoine@intel.com>
>> >> > > > >
>> >> > > > > This patch will allow for getparams to return the status of the HuC.
>> >> > > > > As the HuC has to be validated by the GuC this patch uses
>> >> > > > > the validated status to show when the HuC is loaded and
>> >> > > > > ready for use. You cannot use the loaded status as with the
>> >> > > > > GuC as the HuC is verified after it is loaded and is not usable until it is
>verified.
>> >> > > > >
>> >> > > > > v2: removed the forewakes as the registers are already force-woken.
>> >> > > > > (T.Ursulin)
>> >> > > > > v4: rebased.
>> >> > > > > v5: rebased on top of drm-tip.
>> >> > > > > v6: rebased. Removed any reference to intel_huc.h
>> >> > > > > v7: rebased. Rename I915_PARAM_HAS_HUC to
>> >I915_PARAM_HUC_STATUS.
>> >> > > > > Remove intel_is_huc_valid() since it is used only in one place.
>> >> > > > > Put the case of I915_PARAM_HAS_HUC() in the right place.
>> >> > > > >
>> >> > > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> >> > > > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>> >> > > > > ---
>> >> > > > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>> >> > > > > drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
>> >> > > > > include/uapi/drm/i915_drm.h | 1 +
>> >> > > > > 3 files changed, 5 insertions(+), 1 deletion(-)
>> >> > > > >
>> >> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> >> > > > > b/drivers/gpu/drm/i915/i915_drv.c index 85a47c2..0bc016d
>> >> > > > > 100644
>> >> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
>> >> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
>> >> > > > > @@ -49,6 +49,7 @@
>> >> > > > > #include "i915_trace.h"
>> >> > > > > #include "i915_vgpu.h"
>> >> > > > > #include "intel_drv.h"
>> >> > > > > +#include "intel_uc.h"
>> >> > > > >
>> >> > > > > static struct drm_driver driver;
>> >> > > > >
>> >> > > > > @@ -315,6 +316,9 @@ static int i915_getparam(struct
>> >> > > > > drm_device
>> >*dev, void *data,
>> >> > > > > case I915_PARAM_MIN_EU_IN_POOL:
>> >> > > > > value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
>> >> > > > > break;
>> >> > > > > + case I915_PARAM_HUC_STATUS:
>> >> > > > > + value = I915_READ(HUC_STATUS2) &
>> >HUC_FW_VERIFIED;
>> >> > > >
>> >> > > > Same question as last time: does the device need to be awake?
>> >> > > > We know is one of the GT power wells, so presumably we need
>> >> > > > an rpm_get/rpm_put as well to access the register.
>> >> > > > -Chris
>> >> > >
>> >> > > I get:
>> >> > >
>> >> > > [ 1588.570174] [drm:i915_huc_load_status_info [i915]]
>> >> > > HUC_STATUS2 PRE 24704 [ 1588.571285]
>> >> > > [drm:intel_runtime_suspend [i915]] Suspending device [
>> >> > > 1588.575768] [drm:intel_runtime_suspend [i915]] Device
>> >> > > suspended [ 1588.577156] [drm:i915_huc_load_status_info [i915]]
>> >> > > HUC_STATUS2 POST 24704 [ 1588.578259] [drm:intel_runtime_resume
>> >> > > [i915]] Resuming device
>> >> > >
>> >> > > consistently from:
>> >> > >
>> >> > > value = I915_READ(HUC_STATUS2);
>> >> > > DRM_DEBUG_DRIVER("HUC_STATUS2 PRE %d\n", value);
>> >> > > i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
>> >> > >
>> >> > > value = I915_READ(HUC_STATUS2);
>> >> > > DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
>> >> > > i915_pm_ops.runtime_resume(dev_priv->drm.dev);
>> >> >
>> >> > Also do the test with i915.mmio_debug=9999 -Chris
>> >>
>> >> Same effect. Works.
>> Thanks Arek for confirming.
>>
>> >Ok, then just mark up that we don't need rpm here so that we don't
>> >freak out in future scans for mmio access outside of rpm.
>> >-Chris
>> Chris, v2 as changed by Tvrtko suggests that forcewakes are removed since the
>register is force waken. Are you suggesting that adding that rpm not being
>required in the commit message will make things much more clearer?
>
>No, if you are eschewing taking rpm around mmio access, I want that
>commented upon in the code so that it is visible the next time we do an audit for
>rpm abuse/misuse.
Ah! Got it. Thanks.
Cheers,
Anusha
>-Chris
>
>--
>Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-16 18:31 ` Srivatsa, Anusha
@ 2016-12-16 18:46 ` Chris Wilson
2016-12-16 18:55 ` Srivatsa, Anusha
0 siblings, 1 reply; 71+ messages in thread
From: Chris Wilson @ 2016-12-16 18:46 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx
On Fri, Dec 16, 2016 at 06:31:46PM +0000, Srivatsa, Anusha wrote:
>
>
> >-----Original Message-----
> >From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> >Sent: Friday, December 16, 2016 8:31 AM
> >To: Hiler, Arkadiusz <arkadiusz.hiler@intel.com>
> >Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> >gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to
> >getparams
> >
> >On Fri, Dec 16, 2016 at 05:21:38PM +0100, Arkadiusz Hiler wrote:
> >> On Fri, Dec 16, 2016 at 04:12:36PM +0000, Chris Wilson wrote:
> >> > On Fri, Dec 16, 2016 at 03:43:46PM +0100, Arkadiusz Hiler wrote:
> >> > > On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
> >> > > > On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> >> > > > > From: Peter Antoine <peter.antoine@intel.com>
> >> > > > >
> >> > > > > This patch will allow for getparams to return the status of the HuC.
> >> > > > > As the HuC has to be validated by the GuC this patch uses the
> >> > > > > validated status to show when the HuC is loaded and ready for
> >> > > > > use. You cannot use the loaded status as with the GuC as the
> >> > > > > HuC is verified after it is loaded and is not usable until it is verified.
> >> > > > >
> >> > > > > v2: removed the forewakes as the registers are already force-woken.
> >> > > > > (T.Ursulin)
> >> > > > > v4: rebased.
> >> > > > > v5: rebased on top of drm-tip.
> >> > > > > v6: rebased. Removed any reference to intel_huc.h
> >> > > > > v7: rebased. Rename I915_PARAM_HAS_HUC to
> >I915_PARAM_HUC_STATUS.
> >> > > > > Remove intel_is_huc_valid() since it is used only in one place.
> >> > > > > Put the case of I915_PARAM_HAS_HUC() in the right place.
> >> > > > >
> >> > > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> >> > > > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> >> > > > > ---
> >> > > > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> >> > > > > drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> >> > > > > include/uapi/drm/i915_drm.h | 1 +
> >> > > > > 3 files changed, 5 insertions(+), 1 deletion(-)
> >> > > > >
> >> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> >> > > > > b/drivers/gpu/drm/i915/i915_drv.c index 85a47c2..0bc016d
> >> > > > > 100644
> >> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> >> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> >> > > > > @@ -49,6 +49,7 @@
> >> > > > > #include "i915_trace.h"
> >> > > > > #include "i915_vgpu.h"
> >> > > > > #include "intel_drv.h"
> >> > > > > +#include "intel_uc.h"
> >> > > > >
> >> > > > > static struct drm_driver driver;
> >> > > > >
> >> > > > > @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device
> >*dev, void *data,
> >> > > > > case I915_PARAM_MIN_EU_IN_POOL:
> >> > > > > value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> >> > > > > break;
> >> > > > > + case I915_PARAM_HUC_STATUS:
> >> > > > > + value = I915_READ(HUC_STATUS2) &
> >HUC_FW_VERIFIED;
> >> > > >
> >> > > > Same question as last time: does the device need to be awake? We
> >> > > > know is one of the GT power wells, so presumably we need an
> >> > > > rpm_get/rpm_put as well to access the register.
> >> > > > -Chris
> >> > >
> >> > > I get:
> >> > >
> >> > > [ 1588.570174] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2
> >> > > PRE 24704 [ 1588.571285] [drm:intel_runtime_suspend [i915]]
> >> > > Suspending device [ 1588.575768] [drm:intel_runtime_suspend
> >> > > [i915]] Device suspended [ 1588.577156]
> >> > > [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 POST 24704 [
> >> > > 1588.578259] [drm:intel_runtime_resume [i915]] Resuming device
> >> > >
> >> > > consistently from:
> >> > >
> >> > > value = I915_READ(HUC_STATUS2);
> >> > > DRM_DEBUG_DRIVER("HUC_STATUS2 PRE %d\n", value);
> >> > > i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
> >> > >
> >> > > value = I915_READ(HUC_STATUS2);
> >> > > DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
> >> > > i915_pm_ops.runtime_resume(dev_priv->drm.dev);
> >> >
> >> > Also do the test with i915.mmio_debug=9999 -Chris
> >>
> >> Same effect. Works.
> Thanks Arek for confirming.
>
> >Ok, then just mark up that we don't need rpm here so that we don't freak out in
> >future scans for mmio access outside of rpm.
> >-Chris
> Chris, v2 as changed by Tvrtko suggests that forcewakes are removed since the register is force waken. Are you suggesting that adding that rpm not being required in the commit message will make things much more clearer?
No, if you are eschewing taking rpm around mmio access, I want that
commented upon in the code so that it is visible the next time we do an
audit for rpm abuse/misuse.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-16 16:30 ` Chris Wilson
@ 2016-12-16 18:31 ` Srivatsa, Anusha
2016-12-16 18:46 ` Chris Wilson
0 siblings, 1 reply; 71+ messages in thread
From: Srivatsa, Anusha @ 2016-12-16 18:31 UTC (permalink / raw)
To: Chris Wilson, Hiler, Arkadiusz; +Cc: intel-gfx
>-----Original Message-----
>From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
>Sent: Friday, December 16, 2016 8:31 AM
>To: Hiler, Arkadiusz <arkadiusz.hiler@intel.com>
>Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
>gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to
>getparams
>
>On Fri, Dec 16, 2016 at 05:21:38PM +0100, Arkadiusz Hiler wrote:
>> On Fri, Dec 16, 2016 at 04:12:36PM +0000, Chris Wilson wrote:
>> > On Fri, Dec 16, 2016 at 03:43:46PM +0100, Arkadiusz Hiler wrote:
>> > > On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
>> > > > On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
>> > > > > From: Peter Antoine <peter.antoine@intel.com>
>> > > > >
>> > > > > This patch will allow for getparams to return the status of the HuC.
>> > > > > As the HuC has to be validated by the GuC this patch uses the
>> > > > > validated status to show when the HuC is loaded and ready for
>> > > > > use. You cannot use the loaded status as with the GuC as the
>> > > > > HuC is verified after it is loaded and is not usable until it is verified.
>> > > > >
>> > > > > v2: removed the forewakes as the registers are already force-woken.
>> > > > > (T.Ursulin)
>> > > > > v4: rebased.
>> > > > > v5: rebased on top of drm-tip.
>> > > > > v6: rebased. Removed any reference to intel_huc.h
>> > > > > v7: rebased. Rename I915_PARAM_HAS_HUC to
>I915_PARAM_HUC_STATUS.
>> > > > > Remove intel_is_huc_valid() since it is used only in one place.
>> > > > > Put the case of I915_PARAM_HAS_HUC() in the right place.
>> > > > >
>> > > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> > > > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>> > > > > ---
>> > > > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>> > > > > drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
>> > > > > include/uapi/drm/i915_drm.h | 1 +
>> > > > > 3 files changed, 5 insertions(+), 1 deletion(-)
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> > > > > b/drivers/gpu/drm/i915/i915_drv.c index 85a47c2..0bc016d
>> > > > > 100644
>> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
>> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
>> > > > > @@ -49,6 +49,7 @@
>> > > > > #include "i915_trace.h"
>> > > > > #include "i915_vgpu.h"
>> > > > > #include "intel_drv.h"
>> > > > > +#include "intel_uc.h"
>> > > > >
>> > > > > static struct drm_driver driver;
>> > > > >
>> > > > > @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device
>*dev, void *data,
>> > > > > case I915_PARAM_MIN_EU_IN_POOL:
>> > > > > value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
>> > > > > break;
>> > > > > + case I915_PARAM_HUC_STATUS:
>> > > > > + value = I915_READ(HUC_STATUS2) &
>HUC_FW_VERIFIED;
>> > > >
>> > > > Same question as last time: does the device need to be awake? We
>> > > > know is one of the GT power wells, so presumably we need an
>> > > > rpm_get/rpm_put as well to access the register.
>> > > > -Chris
>> > >
>> > > I get:
>> > >
>> > > [ 1588.570174] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2
>> > > PRE 24704 [ 1588.571285] [drm:intel_runtime_suspend [i915]]
>> > > Suspending device [ 1588.575768] [drm:intel_runtime_suspend
>> > > [i915]] Device suspended [ 1588.577156]
>> > > [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 POST 24704 [
>> > > 1588.578259] [drm:intel_runtime_resume [i915]] Resuming device
>> > >
>> > > consistently from:
>> > >
>> > > value = I915_READ(HUC_STATUS2);
>> > > DRM_DEBUG_DRIVER("HUC_STATUS2 PRE %d\n", value);
>> > > i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
>> > >
>> > > value = I915_READ(HUC_STATUS2);
>> > > DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
>> > > i915_pm_ops.runtime_resume(dev_priv->drm.dev);
>> >
>> > Also do the test with i915.mmio_debug=9999 -Chris
>>
>> Same effect. Works.
Thanks Arek for confirming.
>Ok, then just mark up that we don't need rpm here so that we don't freak out in
>future scans for mmio access outside of rpm.
>-Chris
Chris, v2 as changed by Tvrtko suggests that forcewakes are removed since the register is force waken. Are you suggesting that adding that rpm not being required in the commit message will make things much more clearer?
Anusha
>
>--
>Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-16 16:21 ` Arkadiusz Hiler
@ 2016-12-16 16:30 ` Chris Wilson
2016-12-16 18:31 ` Srivatsa, Anusha
0 siblings, 1 reply; 71+ messages in thread
From: Chris Wilson @ 2016-12-16 16:30 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: intel-gfx
On Fri, Dec 16, 2016 at 05:21:38PM +0100, Arkadiusz Hiler wrote:
> On Fri, Dec 16, 2016 at 04:12:36PM +0000, Chris Wilson wrote:
> > On Fri, Dec 16, 2016 at 03:43:46PM +0100, Arkadiusz Hiler wrote:
> > > On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
> > > > On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> > > > > From: Peter Antoine <peter.antoine@intel.com>
> > > > >
> > > > > This patch will allow for getparams to return the status of the HuC.
> > > > > As the HuC has to be validated by the GuC this patch uses the validated
> > > > > status to show when the HuC is loaded and ready for use. You cannot use
> > > > > the loaded status as with the GuC as the HuC is verified after it is
> > > > > loaded and is not usable until it is verified.
> > > > >
> > > > > v2: removed the forewakes as the registers are already force-woken.
> > > > > (T.Ursulin)
> > > > > v4: rebased.
> > > > > v5: rebased on top of drm-tip.
> > > > > v6: rebased. Removed any reference to intel_huc.h
> > > > > v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> > > > > Remove intel_is_huc_valid() since it is used only in one place.
> > > > > Put the case of I915_PARAM_HAS_HUC() in the right place.
> > > > >
> > > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > > > > drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> > > > > include/uapi/drm/i915_drm.h | 1 +
> > > > > 3 files changed, 5 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > > index 85a47c2..0bc016d 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > > @@ -49,6 +49,7 @@
> > > > > #include "i915_trace.h"
> > > > > #include "i915_vgpu.h"
> > > > > #include "intel_drv.h"
> > > > > +#include "intel_uc.h"
> > > > >
> > > > > static struct drm_driver driver;
> > > > >
> > > > > @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > > > case I915_PARAM_MIN_EU_IN_POOL:
> > > > > value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> > > > > break;
> > > > > + case I915_PARAM_HUC_STATUS:
> > > > > + value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> > > >
> > > > Same question as last time: does the device need to be awake? We know is
> > > > one of the GT power wells, so presumably we need an rpm_get/rpm_put as
> > > > well to access the register.
> > > > -Chris
> > >
> > > I get:
> > >
> > > [ 1588.570174] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 PRE 24704
> > > [ 1588.571285] [drm:intel_runtime_suspend [i915]] Suspending device
> > > [ 1588.575768] [drm:intel_runtime_suspend [i915]] Device suspended
> > > [ 1588.577156] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 POST 24704
> > > [ 1588.578259] [drm:intel_runtime_resume [i915]] Resuming device
> > >
> > > consistently from:
> > >
> > > value = I915_READ(HUC_STATUS2);
> > > DRM_DEBUG_DRIVER("HUC_STATUS2 PRE %d\n", value);
> > > i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
> > >
> > > value = I915_READ(HUC_STATUS2);
> > > DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
> > > i915_pm_ops.runtime_resume(dev_priv->drm.dev);
> >
> > Also do the test with i915.mmio_debug=9999
> > -Chris
>
> Same effect. Works.
Ok, then just mark up that we don't need rpm here so that we don't freak
out in future scans for mmio access outside of rpm.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-16 16:12 ` Chris Wilson
@ 2016-12-16 16:21 ` Arkadiusz Hiler
2016-12-16 16:30 ` Chris Wilson
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-16 16:21 UTC (permalink / raw)
To: Chris Wilson, anushasr, intel-gfx
On Fri, Dec 16, 2016 at 04:12:36PM +0000, Chris Wilson wrote:
> On Fri, Dec 16, 2016 at 03:43:46PM +0100, Arkadiusz Hiler wrote:
> > On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
> > > On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> > > > From: Peter Antoine <peter.antoine@intel.com>
> > > >
> > > > This patch will allow for getparams to return the status of the HuC.
> > > > As the HuC has to be validated by the GuC this patch uses the validated
> > > > status to show when the HuC is loaded and ready for use. You cannot use
> > > > the loaded status as with the GuC as the HuC is verified after it is
> > > > loaded and is not usable until it is verified.
> > > >
> > > > v2: removed the forewakes as the registers are already force-woken.
> > > > (T.Ursulin)
> > > > v4: rebased.
> > > > v5: rebased on top of drm-tip.
> > > > v6: rebased. Removed any reference to intel_huc.h
> > > > v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> > > > Remove intel_is_huc_valid() since it is used only in one place.
> > > > Put the case of I915_PARAM_HAS_HUC() in the right place.
> > > >
> > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > > > drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> > > > include/uapi/drm/i915_drm.h | 1 +
> > > > 3 files changed, 5 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > index 85a47c2..0bc016d 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -49,6 +49,7 @@
> > > > #include "i915_trace.h"
> > > > #include "i915_vgpu.h"
> > > > #include "intel_drv.h"
> > > > +#include "intel_uc.h"
> > > >
> > > > static struct drm_driver driver;
> > > >
> > > > @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > > case I915_PARAM_MIN_EU_IN_POOL:
> > > > value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> > > > break;
> > > > + case I915_PARAM_HUC_STATUS:
> > > > + value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> > >
> > > Same question as last time: does the device need to be awake? We know is
> > > one of the GT power wells, so presumably we need an rpm_get/rpm_put as
> > > well to access the register.
> > > -Chris
> >
> > I get:
> >
> > [ 1588.570174] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 PRE 24704
> > [ 1588.571285] [drm:intel_runtime_suspend [i915]] Suspending device
> > [ 1588.575768] [drm:intel_runtime_suspend [i915]] Device suspended
> > [ 1588.577156] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 POST 24704
> > [ 1588.578259] [drm:intel_runtime_resume [i915]] Resuming device
> >
> > consistently from:
> >
> > value = I915_READ(HUC_STATUS2);
> > DRM_DEBUG_DRIVER("HUC_STATUS2 PRE %d\n", value);
> > i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
> >
> > value = I915_READ(HUC_STATUS2);
> > DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
> > i915_pm_ops.runtime_resume(dev_priv->drm.dev);
>
> Also do the test with i915.mmio_debug=9999
> -Chris
Same effect. Works.
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-16 14:43 ` Arkadiusz Hiler
@ 2016-12-16 16:12 ` Chris Wilson
2016-12-16 16:21 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Chris Wilson @ 2016-12-16 16:12 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: intel-gfx, Peter Antoine
On Fri, Dec 16, 2016 at 03:43:46PM +0100, Arkadiusz Hiler wrote:
> On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
> > On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> > > From: Peter Antoine <peter.antoine@intel.com>
> > >
> > > This patch will allow for getparams to return the status of the HuC.
> > > As the HuC has to be validated by the GuC this patch uses the validated
> > > status to show when the HuC is loaded and ready for use. You cannot use
> > > the loaded status as with the GuC as the HuC is verified after it is
> > > loaded and is not usable until it is verified.
> > >
> > > v2: removed the forewakes as the registers are already force-woken.
> > > (T.Ursulin)
> > > v4: rebased.
> > > v5: rebased on top of drm-tip.
> > > v6: rebased. Removed any reference to intel_huc.h
> > > v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> > > Remove intel_is_huc_valid() since it is used only in one place.
> > > Put the case of I915_PARAM_HAS_HUC() in the right place.
> > >
> > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > > drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> > > include/uapi/drm/i915_drm.h | 1 +
> > > 3 files changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index 85a47c2..0bc016d 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -49,6 +49,7 @@
> > > #include "i915_trace.h"
> > > #include "i915_vgpu.h"
> > > #include "intel_drv.h"
> > > +#include "intel_uc.h"
> > >
> > > static struct drm_driver driver;
> > >
> > > @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > case I915_PARAM_MIN_EU_IN_POOL:
> > > value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> > > break;
> > > + case I915_PARAM_HUC_STATUS:
> > > + value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> >
> > Same question as last time: does the device need to be awake? We know is
> > one of the GT power wells, so presumably we need an rpm_get/rpm_put as
> > well to access the register.
> > -Chris
>
> I get:
>
> [ 1588.570174] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 PRE 24704
> [ 1588.571285] [drm:intel_runtime_suspend [i915]] Suspending device
> [ 1588.575768] [drm:intel_runtime_suspend [i915]] Device suspended
> [ 1588.577156] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 POST 24704
> [ 1588.578259] [drm:intel_runtime_resume [i915]] Resuming device
>
> consistently from:
>
> value = I915_READ(HUC_STATUS2);
> DRM_DEBUG_DRIVER("HUC_STATUS2 PRE %d\n", value);
> i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
>
> value = I915_READ(HUC_STATUS2);
> DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
> i915_pm_ops.runtime_resume(dev_priv->drm.dev);
Also do the test with i915.mmio_debug=9999
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-15 22:29 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
2016-12-15 22:42 ` Chris Wilson
@ 2016-12-16 16:00 ` Arkadiusz Hiler
1 sibling, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-16 16:00 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Peter Antoine
On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased on top of drm-tip.
> v6: rebased. Removed any reference to intel_huc.h
> v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> Remove intel_is_huc_valid() since it is used only in one place.
> Put the case of I915_PARAM_HAS_HUC() in the right place.
>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
You've retained my rb without asking me.
With the changes you've made and confirmation that MEDIA FW that
I915_READ() assumes:
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> include/uapi/drm/i915_drm.h | 1 +
> 3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 85a47c2..0bc016d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_uc.h"
>
> static struct drm_driver driver;
>
> @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_MIN_EU_IN_POOL:
> value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> break;
> + case I915_PARAM_HUC_STATUS:
> + value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> + break;
> case I915_PARAM_MMAP_GTT_VERSION:
> /* Though we've started our numbering from 1, and so class all
> * earlier versions as 0, in effect their value is undefined as
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index d8c5266..b06a613 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -288,4 +288,3 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
> }
> -
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index da32c2f..57093b4 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
> * priorities and the driver will attempt to execute batches in priority order.
> */
> #define I915_PARAM_HAS_SCHEDULER 41
> +#define I915_PARAM_HUC_STATUS 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-15 22:42 ` Chris Wilson
@ 2016-12-16 14:43 ` Arkadiusz Hiler
2016-12-16 16:12 ` Chris Wilson
0 siblings, 1 reply; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-16 14:43 UTC (permalink / raw)
To: Chris Wilson, anushasr, intel-gfx, Peter Antoine
On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
> On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > This patch will allow for getparams to return the status of the HuC.
> > As the HuC has to be validated by the GuC this patch uses the validated
> > status to show when the HuC is loaded and ready for use. You cannot use
> > the loaded status as with the GuC as the HuC is verified after it is
> > loaded and is not usable until it is verified.
> >
> > v2: removed the forewakes as the registers are already force-woken.
> > (T.Ursulin)
> > v4: rebased.
> > v5: rebased on top of drm-tip.
> > v6: rebased. Removed any reference to intel_huc.h
> > v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> > Remove intel_is_huc_valid() since it is used only in one place.
> > Put the case of I915_PARAM_HAS_HUC() in the right place.
> >
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> > include/uapi/drm/i915_drm.h | 1 +
> > 3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 85a47c2..0bc016d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -49,6 +49,7 @@
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > #include "intel_drv.h"
> > +#include "intel_uc.h"
> >
> > static struct drm_driver driver;
> >
> > @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > case I915_PARAM_MIN_EU_IN_POOL:
> > value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> > break;
> > + case I915_PARAM_HUC_STATUS:
> > + value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>
> Same question as last time: does the device need to be awake? We know is
> one of the GT power wells, so presumably we need an rpm_get/rpm_put as
> well to access the register.
> -Chris
I get:
[ 1588.570174] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 PRE 24704
[ 1588.571285] [drm:intel_runtime_suspend [i915]] Suspending device
[ 1588.575768] [drm:intel_runtime_suspend [i915]] Device suspended
[ 1588.577156] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 POST 24704
[ 1588.578259] [drm:intel_runtime_resume [i915]] Resuming device
consistently from:
value = I915_READ(HUC_STATUS2);
DRM_DEBUG_DRIVER("HUC_STATUS2 PRE %d\n", value);
i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
value = I915_READ(HUC_STATUS2);
DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
i915_pm_ops.runtime_resume(dev_priv->drm.dev);
> --
> Chris Wilson, Intel Open Source Technology Centre
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-15 22:29 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
@ 2016-12-15 22:42 ` Chris Wilson
2016-12-16 14:43 ` Arkadiusz Hiler
2016-12-16 16:00 ` Arkadiusz Hiler
1 sibling, 1 reply; 71+ messages in thread
From: Chris Wilson @ 2016-12-15 22:42 UTC (permalink / raw)
To: anushasr; +Cc: intel-gfx, Peter Antoine
On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased on top of drm-tip.
> v6: rebased. Removed any reference to intel_huc.h
> v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> Remove intel_is_huc_valid() since it is used only in one place.
> Put the case of I915_PARAM_HAS_HUC() in the right place.
>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> include/uapi/drm/i915_drm.h | 1 +
> 3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 85a47c2..0bc016d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_uc.h"
>
> static struct drm_driver driver;
>
> @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_MIN_EU_IN_POOL:
> value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> break;
> + case I915_PARAM_HUC_STATUS:
> + value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
Same question as last time: does the device need to be awake? We know is
one of the GT power wells, so presumably we need an rpm_get/rpm_put as
well to access the register.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-12-15 22:29 [PATCH 0/8] HuC Loading Patches anushasr
@ 2016-12-15 22:29 ` anushasr
2016-12-15 22:42 ` Chris Wilson
2016-12-16 16:00 ` Arkadiusz Hiler
0 siblings, 2 replies; 71+ messages in thread
From: anushasr @ 2016-12-15 22:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased on top of drm-tip.
v6: rebased. Removed any reference to intel_huc.h
v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
include/uapi/drm/i915_drm.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 85a47c2..0bc016d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
static struct drm_driver driver;
@@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+ case I915_PARAM_HUC_STATUS:
+ value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
* earlier versions as 0, in effect their value is undefined as
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index d8c5266..b06a613 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -288,4 +288,3 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
}
-
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-11-30 23:31 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
@ 2016-12-01 13:07 ` Arkadiusz Hiler
0 siblings, 0 replies; 71+ messages in thread
From: Arkadiusz Hiler @ 2016-12-01 13:07 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Wed, Nov 30, 2016 at 03:31:34PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased on top of drm-tip.
>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 5 +++++
> drivers/gpu/drm/i915/intel_huc.h | 1 +
> drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 075d9ce..75a3e24 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,8 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_uc.h"
> +#include "intel_huc.h"
>
> static struct drm_driver driver;
>
> @@ -350,6 +352,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> */
> value = 1;
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 1dd18c5..1b67311 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -39,4 +39,5 @@ struct intel_huc {
> void intel_huc_init(struct drm_device *dev);
> void intel_huc_fini(struct drm_device *dev);
> int intel_huc_load(struct drm_device *dev);
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 20526a4..e18de0f6 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -292,3 +292,15 @@ void intel_huc_fini(struct drm_device *dev)
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
>
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bdfc688..397b47d 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
> * priorities and the driver will attempt to execute batches in priority order.
> */
> #define I915_PARAM_HAS_SCHEDULER 41
> +#define I915_PARAM_HAS_HUC 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2016-11-30 23:31 ` Anusha Srivatsa
2016-12-01 13:07 ` Arkadiusz Hiler
0 siblings, 1 reply; 71+ messages in thread
From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased on top of drm-tip.
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
drivers/gpu/drm/i915/intel_huc.h | 1 +
drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 075d9ce..75a3e24 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,8 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_uc.h"
+#include "intel_huc.h"
static struct drm_driver driver;
@@ -350,6 +352,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 1dd18c5..1b67311 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -39,4 +39,5 @@ struct intel_huc {
void intel_huc_init(struct drm_device *dev);
void intel_huc_fini(struct drm_device *dev);
int intel_huc_load(struct drm_device *dev);
+int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 20526a4..e18de0f6 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -292,3 +292,15 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bdfc688..397b47d 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
* priorities and the driver will attempt to execute batches in priority order.
*/
#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-11-23 22:27 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
@ 2016-11-24 1:35 ` Jeff McGee
0 siblings, 0 replies; 71+ messages in thread
From: Jeff McGee @ 2016-11-24 1:35 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Peter Antoine
On Wed, Nov 23, 2016 at 02:27:43PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased.
> v6: rebased.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_huc.h | 1 +
> drivers/gpu/drm/i915/intel_huc_loader.c | 13 +++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b893e67..f2d5b0f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,8 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_guc.h"
> +#include "intel_huc.h"
>
> static struct drm_driver driver;
>
> @@ -350,6 +352,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> */
> value = 1;
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> @@ -603,6 +608,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> if (ret)
> goto cleanup_irq;
>
> + intel_huc_init(dev);
As we discussed, this needs to be in patch 3.
> intel_guc_init(dev);
>
> ret = i915_gem_init(dev);
> @@ -630,6 +636,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> i915_gem_fini(dev_priv);
> cleanup_irq:
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> drm_irq_uninstall(dev);
> intel_teardown_gmbus(dev);
> @@ -1325,6 +1332,7 @@ void i915_driver_unload(struct drm_device *dev)
> /* Flush any outstanding unpin_work. */
> drain_workqueue(dev_priv->wq);
>
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> i915_gem_fini(dev_priv);
> intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 3ce0299..2e150be 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -39,4 +39,5 @@ struct intel_huc {
> void intel_huc_init(struct drm_device *dev);
> void intel_huc_fini(struct drm_device *dev);
> int intel_huc_load(struct drm_device *dev);
> +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 3a2555e..8c3993b 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -291,3 +291,16 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bdfc688..0a9dac4 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -390,6 +390,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_HAS_POOLED_EU 38
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> +#define I915_PARAM_HAS_HUC 42
>
> /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
> * priorities and the driver will attempt to execute batches in priority order.
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-11-23 22:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2016-11-23 22:27 ` Anusha Srivatsa
2016-11-24 1:35 ` Jeff McGee
0 siblings, 1 reply; 71+ messages in thread
From: Anusha Srivatsa @ 2016-11-23 22:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased.
v6: rebased.
v7: rebased.
v8: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 8 ++++++++
drivers/gpu/drm/i915/intel_huc.h | 1 +
drivers/gpu/drm/i915/intel_huc_loader.c | 13 +++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b893e67..f2d5b0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,8 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_guc.h"
+#include "intel_huc.h"
static struct drm_driver driver;
@@ -350,6 +352,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
@@ -603,6 +608,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
+ intel_huc_init(dev);
intel_guc_init(dev);
ret = i915_gem_init(dev);
@@ -630,6 +636,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1325,6 +1332,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
+ intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 3ce0299..2e150be 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -39,4 +39,5 @@ struct intel_huc {
void intel_huc_init(struct drm_device *dev);
void intel_huc_fini(struct drm_device *dev);
int intel_huc_load(struct drm_device *dev);
+extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 3a2555e..8c3993b 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -291,3 +291,16 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bdfc688..0a9dac4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -390,6 +390,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_POOLED_EU 38
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
+#define I915_PARAM_HAS_HUC 42
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
* priorities and the driver will attempt to execute batches in priority order.
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-11-11 0:15 [PATCH v4 0/8] HuC Loading Patches Anusha Srivatsa
@ 2016-11-11 0:15 ` Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2016-11-11 0:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased.
v6: rebased.
v7: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 8 ++++++++
drivers/gpu/drm/i915/intel_huc.h | 1 +
drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0213a30..52a1941 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,8 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_guc.h"
+#include "intel_huc.h"
static struct drm_driver driver;
@@ -346,6 +348,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
@@ -599,6 +604,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
+ intel_huc_init(dev);
intel_guc_init(dev);
ret = i915_gem_init(dev);
@@ -626,6 +632,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1313,6 +1320,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
+ intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 3ce0299..2e150be 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -39,4 +39,5 @@ struct intel_huc {
void intel_huc_init(struct drm_device *dev);
void intel_huc_fini(struct drm_device *dev);
int intel_huc_load(struct drm_device *dev);
+extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index dab64ba..c6eec5b 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -292,3 +292,17 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
+
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 03725fe..aa7667e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_POOLED_EU 38
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-11-09 18:51 [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
@ 2016-11-09 18:51 ` Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2016-11-09 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased.
v6: rebased.
v7: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
drivers/gpu/drm/i915/intel_huc.h | 1 +
drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aa44d8d..52a1941 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,8 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_guc.h"
+#include "intel_huc.h"
static struct drm_driver driver;
@@ -346,6 +348,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 3ce0299..2e150be 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -39,4 +39,5 @@ struct intel_huc {
void intel_huc_init(struct drm_device *dev);
void intel_huc_fini(struct drm_device *dev);
int intel_huc_load(struct drm_device *dev);
+extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index a388437..df149b7 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -290,3 +290,17 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
+
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 03725fe..aa7667e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_POOLED_EU 38
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-13 21:47 ` Jeff McGee
@ 2016-10-17 6:48 ` Daniel Vetter
0 siblings, 0 replies; 71+ messages in thread
From: Daniel Vetter @ 2016-10-17 6:48 UTC (permalink / raw)
To: Jeff McGee; +Cc: intel-gfx
On Thu, Oct 13, 2016 at 02:47:32PM -0700, Jeff McGee wrote:
> On Mon, Oct 03, 2016 at 11:43:02AM -0700, Anusha Srivatsa wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > This patch will allow for getparams to return the status of the HuC.
> > As the HuC has to be validated by the GuC this patch uses the validated
> > status to show when the HuC is loaded and ready for use. You cannot use
> > the loaded status as with the GuC as the HuC is verified after it is
> > loaded and is not usable until it is verified.
> >
> > v2: removed the forewakes as the registers are already force-woken.
> > (T.Ursulin)
> > v4: rebased.
> > v5: rebased.
> >
> > Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > drivers/gpu/drm/i915/intel_huc.h | 2 +-
> > drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
> > include/uapi/drm/i915_drm.h | 1 +
> > 4 files changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index ff1c18d..0d7b290 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -49,6 +49,7 @@
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > #include "intel_drv.h"
> > +#include "intel_huc.h"
> > #include "intel_guc.h"
> >
> > static struct drm_driver driver;
> > @@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > case I915_PARAM_HAS_GUC:
> > value = intel_is_guc_valid(dev_priv);
> > break;
> > + case I915_PARAM_HAS_HUC:
> > + value = intel_is_huc_valid(dev_priv);
> > + break;
> > default:
> > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> > index 946caa7..5eac625 100644
> > --- a/drivers/gpu/drm/i915/intel_huc.h
> > +++ b/drivers/gpu/drm/i915/intel_huc.h
> > @@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
> > extern int intel_huc_load(struct drm_device *dev);
> > extern void intel_huc_auth(struct drm_device *dev);
> > extern void intel_huc_fini(struct drm_device *dev);
> > -
> > +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> > #endif
> > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> > index 87a6948..d574183 100644
> > --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > @@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
> >
> > huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > }
> > +
> > +/**
> > + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> > + * @dev_priv: drm device to check.
> > + *
> > + * This function will return true if the guc has been loaded and
> > + * has valid firmware. The simplest way of doing this is to check
> > + * if the HuC has been validated, if so it must have been loaded.
> > + */
> > +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> I'm still unclear on the 'intel' vs. 'i915' prefix usage. But it seems
> that intel prefixed functions accept drm_device instead of drm_i915_private.
intel_ is core and modeset, i915_ is gem stuff. mostly. Absolutely nothing
to do with drm_device vs. drm_i915_private, that should only be a question
of whether it's a drm vfunc or an internal one (we're transitioning to
that pattern, so atm it's a bit a mess).
> Also, need to see the userspace usage of this new GETPARAM.
+1 ;-)
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-03 18:43 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-10-05 20:51 ` Rodrigo Vivi
@ 2016-10-13 21:47 ` Jeff McGee
2016-10-17 6:48 ` Daniel Vetter
1 sibling, 1 reply; 71+ messages in thread
From: Jeff McGee @ 2016-10-13 21:47 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 03, 2016 at 11:43:02AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc.h | 2 +-
> drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ff1c18d..0d7b290 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_huc.h"
> #include "intel_guc.h"
>
> static struct drm_driver driver;
> @@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_HAS_GUC:
> value = intel_is_guc_valid(dev_priv);
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 946caa7..5eac625 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
> extern int intel_huc_load(struct drm_device *dev);
> extern void intel_huc_auth(struct drm_device *dev);
> extern void intel_huc_fini(struct drm_device *dev);
> -
> +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 87a6948..d574183 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
I'm still unclear on the 'intel' vs. 'i915' prefix usage. But it seems
that intel prefixed functions accept drm_device instead of drm_i915_private.
Also, need to see the userspace usage of this new GETPARAM.
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> +
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 629fb5e..d236520 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -389,6 +389,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> #define I915_PARAM_HAS_GUC 41
> +#define I915_PARAM_HAS_HUC 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-03 18:43 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
@ 2016-10-05 20:51 ` Rodrigo Vivi
2016-10-13 21:47 ` Jeff McGee
1 sibling, 0 replies; 71+ messages in thread
From: Rodrigo Vivi @ 2016-10-05 20:51 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Mon, Oct 03, 2016 at 11:43:02AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc.h | 2 +-
> drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ff1c18d..0d7b290 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_huc.h"
> #include "intel_guc.h"
>
> static struct drm_driver driver;
> @@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_HAS_GUC:
> value = intel_is_guc_valid(dev_priv);
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 946caa7..5eac625 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
> extern int intel_huc_load(struct drm_device *dev);
> extern void intel_huc_auth(struct drm_device *dev);
> extern void intel_huc_fini(struct drm_device *dev);
> -
> +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 87a6948..d574183 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> +
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 629fb5e..d236520 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -389,6 +389,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> #define I915_PARAM_HAS_GUC 41
> +#define I915_PARAM_HAS_HUC 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2016-10-03 18:43 ` Anusha Srivatsa
2016-10-05 20:51 ` Rodrigo Vivi
2016-10-13 21:47 ` Jeff McGee
0 siblings, 2 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:43 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/intel_huc.h | 2 +-
drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ff1c18d..0d7b290 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_huc.h"
#include "intel_guc.h"
static struct drm_driver driver;
@@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_GUC:
value = intel_is_guc_valid(dev_priv);
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 946caa7..5eac625 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
extern int intel_huc_load(struct drm_device *dev);
extern void intel_huc_auth(struct drm_device *dev);
extern void intel_huc_fini(struct drm_device *dev);
-
+extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 87a6948..d574183 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
+
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 629fb5e..d236520 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -389,6 +389,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
#define I915_PARAM_HAS_GUC 41
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-09-29 18:03 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2016-09-29 18:04 ` Anusha Srivatsa
0 siblings, 0 replies; 71+ messages in thread
From: Anusha Srivatsa @ 2016-09-29 18:04 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5:rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/intel_huc.h | 2 +-
drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ff1c18d..0d7b290 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_huc.h"
#include "intel_guc.h"
static struct drm_driver driver;
@@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_GUC:
value = intel_is_guc_valid(dev_priv);
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 946caa7..5eac625 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
extern int intel_huc_load(struct drm_device *dev);
extern void intel_huc_auth(struct drm_device *dev);
extern void intel_huc_fini(struct drm_device *dev);
-
+extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 87a6948..d574183 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
+
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 629fb5e..d236520 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -389,6 +389,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
#define I915_PARAM_HAS_GUC 41
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 71+ messages in thread
end of thread, other threads:[~2017-01-14 1:20 UTC | newest]
Thread overview: 71+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr
2016-12-08 23:02 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general anushasr
2016-12-09 8:58 ` Arkadiusz Hiler
2016-12-09 11:28 ` Michal Wajdeczko
2016-12-09 11:49 ` Arkadiusz Hiler
2016-12-09 13:06 ` Michal Wajdeczko
2016-12-09 13:09 ` Arkadiusz Hiler
2016-12-09 19:34 ` Srivatsa, Anusha
2016-12-08 23:02 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC anushasr
2016-12-09 9:20 ` Arkadiusz Hiler
2016-12-09 11:55 ` Michal Wajdeczko
2016-12-09 21:42 ` Srivatsa, Anusha
2016-12-12 11:56 ` Arkadiusz Hiler
2016-12-08 23:02 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support anushasr
2016-12-09 10:56 ` Arkadiusz Hiler
2016-12-09 11:10 ` Chris Wilson
2016-12-09 11:34 ` Arkadiusz Hiler
2016-12-09 12:19 ` Arkadiusz Hiler
2016-12-09 12:17 ` Michal Wajdeczko
2016-12-09 23:56 ` Srivatsa, Anusha
2016-12-12 11:50 ` Arkadiusz Hiler
2016-12-12 18:52 ` Tvrtko Ursulin
2016-12-14 15:19 ` Jani Nikula
2016-12-14 15:24 ` Parenteau, Paul A
2016-12-08 23:02 ` [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support anushasr
2016-12-08 23:02 ` [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support anushasr
2016-12-08 23:02 ` [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check anushasr
2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr
2016-12-09 10:22 ` Arkadiusz Hiler
2016-12-09 12:36 ` Michal Wajdeczko
2016-12-11 0:03 ` Srivatsa, Anusha
2016-12-08 23:02 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
2016-12-08 23:55 ` Chris Wilson
2016-12-13 9:40 ` Arkadiusz Hiler
2016-12-14 1:02 ` Srivatsa, Anusha
2016-12-09 12:59 ` Michal Wajdeczko
2016-12-12 14:13 ` Arkadiusz Hiler
2016-12-12 14:21 ` Chris Wilson
2016-12-12 14:52 ` Arkadiusz Hiler
2016-12-12 15:17 ` Chris Wilson
2016-12-12 15:27 ` Arkadiusz Hiler
2016-12-12 19:20 ` Srivatsa, Anusha
2016-12-08 23:45 ` ✓ Fi.CI.BAT: success for HuC Loading Patches Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-01-14 1:17 [PATCH 0/8] " Anusha Srivatsa
2017-01-14 1:17 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2017-01-13 18:08 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2017-01-13 18:08 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2017-01-13 17:07 Anusha Srivatsa
2017-01-04 14:55 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2017-01-04 14:55 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2017-01-04 13:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2017-01-04 13:27 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-12-22 23:12 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2016-12-22 23:12 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-12-23 14:33 ` Arkadiusz Hiler
2016-12-15 22:29 [PATCH 0/8] HuC Loading Patches anushasr
2016-12-15 22:29 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams anushasr
2016-12-15 22:42 ` Chris Wilson
2016-12-16 14:43 ` Arkadiusz Hiler
2016-12-16 16:12 ` Chris Wilson
2016-12-16 16:21 ` Arkadiusz Hiler
2016-12-16 16:30 ` Chris Wilson
2016-12-16 18:31 ` Srivatsa, Anusha
2016-12-16 18:46 ` Chris Wilson
2016-12-16 18:55 ` Srivatsa, Anusha
2016-12-16 16:00 ` Arkadiusz Hiler
2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2016-11-30 23:31 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-12-01 13:07 ` Arkadiusz Hiler
2016-11-23 22:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2016-11-23 22:27 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-11-24 1:35 ` Jeff McGee
2016-11-11 0:15 [PATCH v4 0/8] HuC Loading Patches Anusha Srivatsa
2016-11-11 0:15 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-11-09 18:51 [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
2016-11-09 18:51 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2016-10-03 18:43 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-10-05 20:51 ` Rodrigo Vivi
2016-10-13 21:47 ` Jeff McGee
2016-10-17 6:48 ` Daniel Vetter
2016-09-29 18:03 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2016-09-29 18:04 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
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