[PATCH 1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.

[PATCH 1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Rodrigo Vivi]

Coffee Lake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.

It is Gen9 graphics based platform on top of CNP PCH.

Let's start by adding the platform definition based on previous
platforms but yet as preliminary_hw_support.

On following patches we will start adding PCI IDs and the
platform specific changes.

v2: Also add BS2 ring that is present on GT3. As on KBL, according
    spec: "GT3 also has additional media blocks with second instance
    of VEBox and VDBox each", i.e. BSD2 ring in our case. Noticed
    when reviewing PCI ID patches.

v3: CFL_PLATFORM instead for CFL_FEATURES because it contains
    Platform information and no new features when compared to
    BDW_FEATURES definition.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c31c0cf..2f20e87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -826,6 +826,7 @@ enum intel_platform {
 	INTEL_BROXTON,
 	INTEL_KABYLAKE,
 	INTEL_GEMINILAKE,
+	INTEL_COFFEELAKE,
 	INTEL_MAX_PLATFORMS
 };
 
@@ -2768,6 +2769,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
 #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
 #define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv)	((dev_priv)->info.platform == INTEL_COFFEELAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f940e48..89f71e0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -425,6 +425,22 @@
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
+#define CFL_PLATFORM \
+	.is_alpha_support = 1, \
+	BDW_FEATURES, \
+	.gen = 9, \
+	.platform = INTEL_COFFEELAKE, \
+	.ddb_size = 896
+
+static const struct intel_device_info intel_coffeelake_info = {
+	CFL_PLATFORM,
+};
+
+static const struct intel_device_info intel_coffeelake_gt3_info = {
+	CFL_PLATFORM,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3718341..acc746f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -51,6 +51,7 @@
 	PLATFORM_NAME(BROXTON),
 	PLATFORM_NAME(KABYLAKE),
 	PLATFORM_NAME(GEMINILAKE),
+	PLATFORM_NAME(COFFEELAKE),
 };
 #undef PLATFORM_NAME
 
-- 
1.9.1

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[PATCH 2/5] drm/i915/cfl: Coffee Lake uses CNP PCH.

[Rodrigo Vivi]

So let's force it on the virtual detection.

Also it is still the only silicon for now on this PCH,
so WARN otherwise.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6ca99de..ed051a6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -139,6 +139,8 @@ static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 		ret = PCH_SPT;
 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
+	} else if (IS_COFFEELAKE(dev_priv)) {
+		ret = PCH_CNP;
 	}
 
 	return ret;
@@ -222,9 +224,11 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+				WARN_ON(!IS_COFFEELAKE(dev_priv));
 			} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
+				WARN_ON(!IS_COFFEELAKE(dev_priv));
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
-- 
1.9.1

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[PATCH 3/5] drm/i915/cfl: Basic DDI plumbing for Coffee Lake.

[Rodrigo Vivi]

All here is pretty much like Kabylake.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8bac628..5b5bee6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 		}
 	}
 
-	if (IS_KABYLAKE(dev_priv))
+	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		return kbl_get_buf_trans_dp(dev_priv, n_entries);
 	else
 		return skl_get_buf_trans_dp(dev_priv, n_entries);
@@ -485,7 +485,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 			   int *n_entries)
 {
-	if (IS_KABYLAKE(dev_priv)) {
+	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 		return kbl_get_buf_trans_dp(dev_priv, n_entries);
 	} else if (IS_SKYLAKE(dev_priv)) {
 		return skl_get_buf_trans_dp(dev_priv, n_entries);
@@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
 		if (dp_iboost) {
 			iboost = dp_iboost;
 		} else {
-			if (IS_KABYLAKE(dev_priv))
+			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
 									&n_entries);
 			else
-- 
1.9.1

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[PATCH 4/5] drm/i915/cfl: Introduce Display workarounds for Coffee Lake.

[Rodrigo Vivi]

The whole Display engine for Coffee Lake is pretty much
identical to the Kabylake. For this reason let's reuse
all display related production workardounds here even though
CFL is not explicit listed at Display workarounds page at Spec.

Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aa9d8ce..98aeba9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3549,7 +3549,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
 static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	if (IS_KABYLAKE(dev_priv))
+	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		return true;
 
 	if (IS_SKYLAKE(dev_priv) &&
@@ -4459,8 +4459,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		  fb->modifier == I915_FORMAT_MOD_Yf_TILED;
 	x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
 
-	/* Display WA #1141: kbl. */
-	if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
+	/* Display WA #1141: kbl,cfl */
+	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
+	    dev_priv->ipc_enabled)
 		latency += 4;
 
 	if (apply_memory_bw_wa && x_tiled)
@@ -8312,7 +8313,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
 		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
 			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-	/* WaFbcNukeOnHostModify:kbl */
+	/* WaFbcNukeOnHostModify:kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
@@ -8780,7 +8781,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_SKYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
-	else if (IS_KABYLAKE(dev_priv))
+	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
 	else if (IS_BROXTON(dev_priv))
 		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
-- 
1.9.1

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[PATCH 5/5] drm/i915/cfl: Introduce Coffee Lake workardounds.

[Rodrigo Vivi]

Coffee Lake inherit most of Kabylake production
workardounds.

Only difference identified so far is:
- WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c    |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c | 75 +++++++++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_pm.c        | 10 ++---
 3 files changed, 61 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4ff854e..8e055b1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1884,7 +1884,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
-	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
 	if (IS_BROADWELL(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
 	else if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index bc38bd1..630ff6e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -814,24 +814,24 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
-	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */
+	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
 
-	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */
+	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 
-	/* WaDisableKillLogic:bxt,skl,kbl */
+	/* WaDisableKillLogic:bxt,skl,kbl,cfl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   ECOCHK_DIS_TLB);
 
-	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */
-	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */
+	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
+	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  FLOW_CONTROL_ENABLE |
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
+	/* Syncing dependencies between camera and graphics:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
@@ -851,18 +851,18 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 		 */
 	}
 
-	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk */
-	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
+	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
+	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 			  GEN9_ENABLE_YV12_BUGFIX |
 			  GEN9_ENABLE_GPGPU_PREEMPTION);
 
-	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */
-	/* WaDisablePartialResolveInVc:skl,bxt,kbl */
+	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
+	/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 
-	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */
+	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
@@ -871,7 +871,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 				  PIXEL_MASK_CAMMING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
 			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
@@ -889,39 +889,40 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 	 * a TLB invalidation occurs during a PSD flush.
 	 */
 
-	/* WaForceEnableNonCoherent:skl,bxt,kbl */
+	/* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
 			  HDC_FORCE_NON_COHERENT);
 
-	/* WaDisableHDCInvalidation:skl,bxt,kbl */
+	/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   BDW_DISABLE_HDC_INVALIDATION);
 
-	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
+	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
 	if (IS_SKYLAKE(dev_priv) ||
 	    IS_KABYLAKE(dev_priv) ||
+	    IS_COFFEELAKE(dev_priv)||
 	    IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 				  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
-	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */
+	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
-	/* WaOCLCoherentLineFlush:skl,bxt,kbl */
+	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */
+	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
 	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
 	if (ret)
 		return ret;
 
-	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
+	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
 	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 	if (ret)
 		return ret;
 
-	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */
+	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
 	if (ret)
 		return ret;
@@ -1140,6 +1141,38 @@ static int glk_init_workarounds(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static int cfl_init_workarounds(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	int ret;
+
+	ret = gen9_init_workarounds(engine);
+	if (ret)
+		return ret;
+
+	/* WaEnableGapsTsvCreditFix:cfl */
+	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+				   GEN9_GAPS_TSV_CREDIT_DISABLE));
+
+	/* WaToEnableHwFixForPushConstHWBug:cfl */
+	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
+	/* WaDisableGafsUnitClkGating:cfl */
+	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableSbeCacheDispatchPortSharing:cfl */
+	WA_SET_BIT_MASKED(
+		GEN7_HALF_SLICE_CHICKEN1,
+		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
+	/* WaInPlaceDecompressionHang:cfl */
+	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+	return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
@@ -1162,6 +1195,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
 		err = kbl_init_workarounds(engine);
 	else if (IS_GEMINILAKE(dev_priv))
 		err =  glk_init_workarounds(engine);
+	else if (IS_COFFEELAKE(dev_priv))
+		err = cfl_init_workarounds(engine);
 	else
 		err = 0;
 	if (err)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 98aeba9..0aed13d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -58,24 +58,24 @@
 
 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
 	I915_WRITE(CHICKEN_PAR1_1,
 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
 	I915_WRITE(GEN8_CONFIG0,
 		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
 
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(GEN8_CHICKEN_DCPR_1,
 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
-	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
-	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
+	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
+	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS |
 		   DISP_FBC_MEMORY_WAKE);
 
-	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
+	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
 }
-- 
1.9.1

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Re: [PATCH 1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Srivatsa, Anusha]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Tuesday, June 6, 2017 12:20 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Subject: [PATCH 1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.
>
>Coffee Lake is a Intel® Processor containing Intel® HD Graphics following
>Kabylake.
>
>It is Gen9 graphics based platform on top of CNP PCH.
>
>Let's start by adding the platform definition based on previous platforms but yet
>as preliminary_hw_support.
>
>On following patches we will start adding PCI IDs and the platform specific
>changes.
>
>v2: Also add BS2 ring that is present on GT3. As on KBL, according
>    spec: "GT3 also has additional media blocks with second instance
>    of VEBox and VDBox each", i.e. BSD2 ring in our case. Noticed
>    when reviewing PCI ID patches.
>
>v3: CFL_PLATFORM instead for CFL_FEATURES because it contains
>    Platform information and no new features when compared to
>    BDW_FEATURES definition.
>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> drivers/gpu/drm/i915/i915_drv.h          |  2 ++
> drivers/gpu/drm/i915/i915_pci.c          | 16 ++++++++++++++++
> drivers/gpu/drm/i915/intel_device_info.c |  1 +
> 3 files changed, 19 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index c31c0cf..2f20e87 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -826,6 +826,7 @@ enum intel_platform {
> 	INTEL_BROXTON,
> 	INTEL_KABYLAKE,
> 	INTEL_GEMINILAKE,
>+	INTEL_COFFEELAKE,
> 	INTEL_MAX_PLATFORMS
> };
>
>@@ -2768,6 +2769,7 @@ static inline struct scatterlist *__sg_next(struct
>scatterlist *sg)
> #define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
> #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
> #define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform ==
>INTEL_GEMINILAKE)
>+#define IS_COFFEELAKE(dev_priv)	((dev_priv)->info.platform ==
>INTEL_COFFEELAKE)
> #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index f940e48..89f71e0 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -425,6 +425,22 @@
> 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
>BSD2_RING,  };
>
>+#define CFL_PLATFORM \
>+	.is_alpha_support = 1, \
>+	BDW_FEATURES, \
>+	.gen = 9, \
>+	.platform = INTEL_COFFEELAKE, \
>+	.ddb_size = 896
>+
>+static const struct intel_device_info intel_coffeelake_info = {
>+	CFL_PLATFORM,
>+};
>+
>+static const struct intel_device_info intel_coffeelake_gt3_info = {
>+	CFL_PLATFORM,
>+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
>+BSD2_RING, };
>+
> /*
>  * Make sure any device matches here are from most specific to most
>  * general.  For example, since the Quanta match is based on the subsystem diff -
>-git a/drivers/gpu/drm/i915/intel_device_info.c
>b/drivers/gpu/drm/i915/intel_device_info.c
>index 3718341..acc746f 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -51,6 +51,7 @@
> 	PLATFORM_NAME(BROXTON),
> 	PLATFORM_NAME(KABYLAKE),
> 	PLATFORM_NAME(GEMINILAKE),
>+	PLATFORM_NAME(COFFEELAKE),
> };
> #undef PLATFORM_NAME
>
>--
>1.9.1

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✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/cfl: Introduce Coffee Lake platform definition.
URL   : https://patchwork.freedesktop.org/series/25352/
State : success

== Summary ==

Series 25352v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25352/revisions/1/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                fail       -> PASS       (fi-snb-2600) fdo#100007
Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                dmesg-warn -> PASS       (fi-kbl-7560u) fdo#101022
Test kms_busy:
        Subgroup basic-flip-default-b:
                dmesg-warn -> PASS       (fi-skl-6700hq) fdo#101144 +2
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-skl-6700hq) fdo#101154 +7
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (fi-skl-6700hq) fdo#100461

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#101022 https://bugs.freedesktop.org/show_bug.cgi?id=101022
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#101154 https://bugs.freedesktop.org/show_bug.cgi?id=101154
fdo#100461 https://bugs.freedesktop.org/show_bug.cgi?id=100461

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time:445s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time:432s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time:573s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time:506s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time:484s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:484s
fi-glk-2a        total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time:587s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:427s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:415s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time:421s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:496s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:459s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:469s
fi-kbl-7560u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:568s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:456s
fi-skl-6700hq    total:278  pass:239  dwarn:0   dfail:1   fail:17  skip:21  time:427s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time:466s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:507s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time:438s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:539s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time:406s

9458d5928c9c2731fe32329ba2219d642b1f81f2 drm-tip: 2017y-06m-06d-16h-35m-12s UTC integration manifest
f330c57 drm/i915/cfl: Introduce Coffee Lake workardounds.
30cc9d5 drm/i915/cfl: Introduce Display workarounds for Coffee Lake.
5e533e9 drm/i915/cfl: Basic DDI plumbing for Coffee Lake.
d9a5e5e drm/i915/cfl: Coffee Lake uses CNP PCH.
eb9198b drm/i915/cfl: Introduce Coffee Lake platform definition.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4892/
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Re: [PATCH 2/5] drm/i915/cfl: Coffee Lake uses CNP PCH.

[Pandiyan, Dhinakaran]

On Tue, 2017-06-06 at 12:19 -0700, Rodrigo Vivi wrote:
> So let's force it on the virtual detection.
> 
> Also it is still the only silicon for now on this PCH,
> so WARN otherwise.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6ca99de..ed051a6e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -139,6 +139,8 @@ static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
>  	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>  		ret = PCH_SPT;
>  		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
> +	} else if (IS_COFFEELAKE(dev_priv)) {
> +		ret = PCH_CNP;

nit: You missed the debug logging.


>  	}
>  
>  	return ret;
> @@ -222,9 +224,11 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
>  			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_CNP;
>  				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
> +				WARN_ON(!IS_COFFEELAKE(dev_priv));
>  			} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_CNP;
>  				DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
> +				WARN_ON(!IS_COFFEELAKE(dev_priv));
>  			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
>  				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
>  				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&

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Re: [PATCH 3/5] drm/i915/cfl: Basic DDI plumbing for Coffee Lake.

[Pandiyan, Dhinakaran]

On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> All here is pretty much like Kabylake.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 8bac628..5b5bee6 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
>  		}
>  	}
>  

I don't see the corresponding change in the caller
intel_ddi_get_buf_trans_edp(). 


> -	if (IS_KABYLAKE(dev_priv))
> +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
>  	else
>  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> @@ -485,7 +485,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
>  			   int *n_entries)
>  {
> -	if (IS_KABYLAKE(dev_priv)) {
> +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {

What SKU's are being supported here? Anusha's sent patches for U, H and
S. I see distinct ddi_translation definitions for KBL U SKU's but I see
them missing for CFL in the callee kbl_get_buf_trans_dp. 


-DK


>  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
>  	} else if (IS_SKYLAKE(dev_priv)) {
>  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> @@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
>  		if (dp_iboost) {
>  			iboost = dp_iboost;
>  		} else {
> -			if (IS_KABYLAKE(dev_priv))
> +			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
>  									&n_entries);
>  			else

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Re: [PATCH 4/5] drm/i915/cfl: Introduce Display workarounds for Coffee Lake.

[Pandiyan, Dhinakaran]

On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> The whole Display engine for Coffee Lake is pretty much
> identical to the Kabylake. For this reason let's reuse
> all display related production workardounds here even though

Are these all the display workarounds we have or is this patch just for
PM related ones?

> CFL is not explicit listed at Display workarounds page at Spec.
> 
> Cc: Arthur Runyan <arthur.j.runyan@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index aa9d8ce..98aeba9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3549,7 +3549,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
>  static bool
>  intel_has_sagv(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_KABYLAKE(dev_priv))
> +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  		return true;
>  
>  	if (IS_SKYLAKE(dev_priv) &&
> @@ -4459,8 +4459,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  		  fb->modifier == I915_FORMAT_MOD_Yf_TILED;
>  	x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
>  
> -	/* Display WA #1141: kbl. */
> -	if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
> +	/* Display WA #1141: kbl,cfl */
> +	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
> +	    dev_priv->ipc_enabled)

I am not sure about this, bspec does not say whether it applies to CFL
or not. So unless we get more clarification, makes sense to go with
this.

I have audited all occurrences of KBL special cases in this file,
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

>  		latency += 4;
>  
>  	if (apply_memory_bw_wa && x_tiled)
> @@ -8312,7 +8313,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
>  		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>  
> -	/* WaFbcNukeOnHostModify:kbl */
> +	/* WaFbcNukeOnHostModify:kbl,cfl */
>  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
> @@ -8780,7 +8781,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_SKYLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> -	else if (IS_KABYLAKE(dev_priv))
> +	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
>  	else if (IS_BROXTON(dev_priv))
>  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;

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Re: [PATCH 4/5] drm/i915/cfl: Introduce Display workarounds for Coffee Lake.

[Vivi, Rodrigo]

On Wed, 2017-06-07 at 18:44 +0000, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > The whole Display engine for Coffee Lake is pretty much
> > identical to the Kabylake. For this reason let's reuse
> > all display related production workardounds here even though
> 
> Are these all the display workarounds we have or is this patch just for
> PM related ones?

All this are Display W/a but needed on pm init... Maybe they would
deserve a better and more clear place in our code like in intel_display
that gets called on the right time... not sure, but anyways for a follow
up patch.

But I just noticed not all of Display W/a are here as well. I need to
move all other intel_pm.c changes from  drm/i915/cfl: Introduce Coffee
Lake workardounds. to this patch :/ and also rename that patch to GT
workarounds.

I hope to still count with your rv-b here.


> 
> > CFL is not explicit listed at Display workarounds page at Spec.

CFL Display is identical to KBL, this is why the spec has no specific
mention about CFL. Only page that is apparently updated is the
configuration SKUs with the IDs.

> > 
> > Cc: Arthur Runyan <arthur.j.runyan@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 11 ++++++-----
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index aa9d8ce..98aeba9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3549,7 +3549,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
> >  static bool
> >  intel_has_sagv(struct drm_i915_private *dev_priv)
> >  {
> > -	if (IS_KABYLAKE(dev_priv))
> > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  		return true;
> >  
> >  	if (IS_SKYLAKE(dev_priv) &&
> > @@ -4459,8 +4459,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> >  		  fb->modifier == I915_FORMAT_MOD_Yf_TILED;
> >  	x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
> >  
> > -	/* Display WA #1141: kbl. */
> > -	if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
> > +	/* Display WA #1141: kbl,cfl */
> > +	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
> > +	    dev_priv->ipc_enabled)
> 
> I am not sure about this, bspec does not say whether it applies to CFL
> or not. So unless we get more clarification, makes sense to go with
> this.

yep, let's consider all same as KBL. If something changes later we
follow up with updates in the code.

> 
> I have audited all occurrences of KBL special cases in this file,
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> 
> >  		latency += 4;
> >  
> >  	if (apply_memory_bw_wa && x_tiled)
> > @@ -8312,7 +8313,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> >  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> >  
> > -	/* WaFbcNukeOnHostModify:kbl */
> > +	/* WaFbcNukeOnHostModify:kbl,cfl */
> >  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> > @@ -8780,7 +8781,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> >  {
> >  	if (IS_SKYLAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> > -	else if (IS_KABYLAKE(dev_priv))
> > +	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> >  	else if (IS_BROXTON(dev_priv))
> >  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> 

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Re: [PATCH 3/5] drm/i915/cfl: Basic DDI plumbing for Coffee Lake.

[Vivi, Rodrigo]

On Wed, 2017-06-07 at 18:04 +0000, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > All here is pretty much like Kabylake.
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 8bac628..5b5bee6 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
> >  		}
> >  	}
> >  
> 
> I don't see the corresponding change in the caller
> intel_ddi_get_buf_trans_edp(). 
> 
> 
> > -	if (IS_KABYLAKE(dev_priv))
> > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
> >  	else
> >  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> > @@ -485,7 +485,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> >  intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> >  			   int *n_entries)
> >  {
> > -	if (IS_KABYLAKE(dev_priv)) {
> > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
> 
> What SKU's are being supported here? Anusha's sent patches for U, H and
> S. I see distinct ddi_translation definitions for KBL U SKU's but I see
> them missing for CFL in the callee kbl_get_buf_trans_dp. 

good catch! CFL-U is same as KBL-U and according to hardware engineers
should start with same translation table. If something changes in the
future we update here.

I will rebase and put this patch on top of PCI ID ones so I reuse the
Anusha's definition to get CFL-U.

> 
> 
> -DK
> 
> 
> >  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
> >  	} else if (IS_SKYLAKE(dev_priv)) {
> >  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> > @@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
> >  		if (dp_iboost) {
> >  			iboost = dp_iboost;
> >  		} else {
> > -			if (IS_KABYLAKE(dev_priv))
> > +			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
> >  									&n_entries);
> >  			else
> 

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Re: [PATCH 4/5] drm/i915/cfl: Introduce Display workarounds for Coffee Lake.

[Pandiyan, Dhinakaran]

On Wed, 2017-06-07 at 21:52 +0000, Vivi, Rodrigo wrote:
> On Wed, 2017-06-07 at 18:44 +0000, Pandiyan, Dhinakaran wrote:
> > On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > > The whole Display engine for Coffee Lake is pretty much
> > > identical to the Kabylake. For this reason let's reuse
> > > all display related production workardounds here even though
> > 
> > Are these all the display workarounds we have or is this patch just for
> > PM related ones?
> 
> All this are Display W/a but needed on pm init... Maybe they would
> deserve a better and more clear place in our code like in intel_display
> that gets called on the right time... not sure, but anyways for a follow
> up patch.
> 
> But I just noticed not all of Display W/a are here as well. I need to
> move all other intel_pm.c changes from  drm/i915/cfl: Introduce Coffee
> Lake workardounds. to this patch :/ and also rename that patch to GT
> workarounds.

I noticed that in patch 5/5 and had a half-written email with comments
for that.

> 
> I hope to still count with your rv-b here.

Sure, please move the intel_pm.c hunk from 5/5 to this patch and retain
the R-B.

-DK

> 
> 
> > 
> > > CFL is not explicit listed at Display workarounds page at Spec.
> 
> CFL Display is identical to KBL, this is why the spec has no specific
> mention about CFL. Only page that is apparently updated is the
> configuration SKUs with the IDs.
> 
> > > 
> > > Cc: Arthur Runyan <arthur.j.runyan@intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 11 ++++++-----
> > >  1 file changed, 6 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index aa9d8ce..98aeba9 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3549,7 +3549,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
> > >  static bool
> > >  intel_has_sagv(struct drm_i915_private *dev_priv)
> > >  {
> > > -	if (IS_KABYLAKE(dev_priv))
> > > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > >  		return true;
> > >  
> > >  	if (IS_SKYLAKE(dev_priv) &&
> > > @@ -4459,8 +4459,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > >  		  fb->modifier == I915_FORMAT_MOD_Yf_TILED;
> > >  	x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
> > >  
> > > -	/* Display WA #1141: kbl. */
> > > -	if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
> > > +	/* Display WA #1141: kbl,cfl */
> > > +	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
> > > +	    dev_priv->ipc_enabled)
> > 
> > I am not sure about this, bspec does not say whether it applies to CFL
> > or not. So unless we get more clarification, makes sense to go with
> > this.
> 
> yep, let's consider all same as KBL. If something changes later we
> follow up with updates in the code.
> 
> > 
> > I have audited all occurrences of KBL special cases in this file,
> > Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> > 
> > >  		latency += 4;
> > >  
> > >  	if (apply_memory_bw_wa && x_tiled)
> > > @@ -8312,7 +8313,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> > >  		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > >  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> > >  
> > > -	/* WaFbcNukeOnHostModify:kbl */
> > > +	/* WaFbcNukeOnHostModify:kbl,cfl */
> > >  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> > >  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> > >  }
> > > @@ -8780,7 +8781,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> > >  {
> > >  	if (IS_SKYLAKE(dev_priv))
> > >  		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> > > -	else if (IS_KABYLAKE(dev_priv))
> > > +	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > >  		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> > >  	else if (IS_BROXTON(dev_priv))
> > >  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> > 
> 

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Re: [PATCH 3/5] drm/i915/cfl: Basic DDI plumbing for Coffee Lake.

[Pandiyan, Dhinakaran]

On Wed, 2017-06-07 at 21:53 +0000, Vivi, Rodrigo wrote:
> On Wed, 2017-06-07 at 18:04 +0000, Pandiyan, Dhinakaran wrote:
> > On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > > All here is pretty much like Kabylake.
> > > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > index 8bac628..5b5bee6 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
> > >  		}
> > >  	}
> > >  
> > 
> > I don't see the corresponding change in the caller
> > intel_ddi_get_buf_trans_edp(). 
> > 
^How about this?

intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
                            int *n_entries)
{
        if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
                return skl_get_buf_trans_edp(dev_priv, n_entries);


> > 
> > > -	if (IS_KABYLAKE(dev_priv))
> > > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > >  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
> > >  	else
> > >  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> > > @@ -485,7 +485,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> > >  intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> > >  			   int *n_entries)
> > >  {
> > > -	if (IS_KABYLAKE(dev_priv)) {
> > > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
> > 
> > What SKU's are being supported here? Anusha's sent patches for U, H and
> > S. I see distinct ddi_translation definitions for KBL U SKU's but I see
> > them missing for CFL in the callee kbl_get_buf_trans_dp. 
> 
> good catch! CFL-U is same as KBL-U and according to hardware engineers
> should start with same translation table. If something changes in the
> future we update here.
> 
> I will rebase and put this patch on top of PCI ID ones so I reuse the
> Anusha's definition to get CFL-U.
> 
> > 
> > 
> > -DK
> > 
> > 
> > >  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
> > >  	} else if (IS_SKYLAKE(dev_priv)) {
> > >  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> > > @@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
> > >  		if (dp_iboost) {
> > >  			iboost = dp_iboost;
> > >  		} else {
> > > -			if (IS_KABYLAKE(dev_priv))
> > > +			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > >  				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
> > >  									&n_entries);
> > >  			else
> > 
> 

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Re: [PATCH 3/5] drm/i915/cfl: Basic DDI plumbing for Coffee Lake.

[Vivi, Rodrigo]

On Wed, 2017-06-07 at 22:06 +0000, Pandiyan, Dhinakaran wrote:
> On Wed, 2017-06-07 at 21:53 +0000, Vivi, Rodrigo wrote:
> > On Wed, 2017-06-07 at 18:04 +0000, Pandiyan, Dhinakaran wrote:
> > > On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > > > All here is pretty much like Kabylake.
> > > > 
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> > > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > > index 8bac628..5b5bee6 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > @@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
> > > >  		}
> > > >  	}
> > > >  
> > > 
> > > I don't see the corresponding change in the caller
> > > intel_ddi_get_buf_trans_edp(). 
> > > 
> ^How about this?
> 
> intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
>                             int *n_entries)
> {
>         if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
>                 return skl_get_buf_trans_edp(dev_priv, n_entries);

ouch!!!

I will include this...

> 
> 
> > > 
> > > > -	if (IS_KABYLAKE(dev_priv))
> > > > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > > >  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
> > > >  	else
> > > >  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> > > > @@ -485,7 +485,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> > > >  intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> > > >  			   int *n_entries)
> > > >  {
> > > > -	if (IS_KABYLAKE(dev_priv)) {
> > > > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
> > > 
> > > What SKU's are being supported here? Anusha's sent patches for U, H and
> > > S. I see distinct ddi_translation definitions for KBL U SKU's but I see
> > > them missing for CFL in the callee kbl_get_buf_trans_dp. 
> > 
> > good catch! CFL-U is same as KBL-U and according to hardware engineers
> > should start with same translation table. If something changes in the
> > future we update here.
> > 
> > I will rebase and put this patch on top of PCI ID ones so I reuse the
> > Anusha's definition to get CFL-U.
> > 
> > > 
> > > 
> > > -DK
> > > 
> > > 
> > > >  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
> > > >  	} else if (IS_SKYLAKE(dev_priv)) {
> > > >  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> > > > @@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
> > > >  		if (dp_iboost) {
> > > >  			iboost = dp_iboost;
> > > >  		} else {
> > > > -			if (IS_KABYLAKE(dev_priv))
> > > > +			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > > >  				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
> > > >  									&n_entries);
> > > >  			else
> > > 
> > 
> 

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Re: [PATCH 5/5] drm/i915/cfl: Introduce Coffee Lake workardounds.

[Pandiyan, Dhinakaran]

On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> Coffee Lake inherit most of Kabylake production
> workardounds.
> 
> Only difference identified so far is:
> - WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c    |  2 +-
>  drivers/gpu/drm/i915/intel_engine_cs.c | 75 +++++++++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_pm.c        | 10 ++---
>  3 files changed, 61 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4ff854e..8e055b1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1884,7 +1884,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>  	 * called on driver load and after a GPU reset, so you can place
>  	 * workarounds here even if they get overwritten by GPU reset.
>  	 */
> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
>  	if (IS_BROADWELL(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>  	else if (IS_CHERRYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bc38bd1..630ff6e 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -814,24 +814,24 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	int ret;
>  
> -	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */
> +	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
>  
> -	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */
> +	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
>  		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
>  
> -	/* WaDisableKillLogic:bxt,skl,kbl */
> +	/* WaDisableKillLogic:bxt,skl,kbl,cfl */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  		   ECOCHK_DIS_TLB);
>  
> -	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */
> -	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */
> +	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
> +	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  FLOW_CONTROL_ENABLE |
>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>  
> -	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
> +	/* Syncing dependencies between camera and graphics:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>  			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>  
> @@ -851,18 +851,18 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  		 */
>  	}
>  
> -	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk */
> -	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> +	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
> +	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
>  			  GEN9_ENABLE_YV12_BUGFIX |
>  			  GEN9_ENABLE_GPGPU_PREEMPTION);
>  
> -	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */
> -	/* WaDisablePartialResolveInVc:skl,bxt,kbl */
> +	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
> +	/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
>  					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
>  
> -	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */
> +	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
>  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
>  			  GEN9_CCS_TLB_PREFETCH_ENABLE);
>  
> @@ -871,7 +871,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
>  				  PIXEL_MASK_CAMMING_DISABLE);
>  
> -	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
> +	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
>  			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
> @@ -889,39 +889,40 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	 * a TLB invalidation occurs during a PSD flush.
>  	 */
>  
> -	/* WaForceEnableNonCoherent:skl,bxt,kbl */
> +	/* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_NON_COHERENT);
>  
> -	/* WaDisableHDCInvalidation:skl,bxt,kbl */
> +	/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  		   BDW_DISABLE_HDC_INVALIDATION);
>  
> -	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
> +	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
>  	if (IS_SKYLAKE(dev_priv) ||
>  	    IS_KABYLAKE(dev_priv) ||
> +	    IS_COFFEELAKE(dev_priv)||

GEN9_BC?


>  	    IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
>  		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>  				  GEN8_SAMPLER_POWER_BYPASS_DIS);
>  
> -	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */
> +	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>  
> -	/* WaOCLCoherentLineFlush:skl,bxt,kbl */
> +	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>  
> -	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */
> +	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>  	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>  	if (ret)
>  		return ret;
>  
> -	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
> +	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
>  	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
>  	if (ret)
>  		return ret;
>  
> -	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */
> +	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
>  	ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
>  	if (ret)
>  		return ret;
> @@ -1140,6 +1141,38 @@ static int glk_init_workarounds(struct intel_engine_cs *engine)
>  	return 0;
>  }
>  
> +static int cfl_init_workarounds(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	int ret;
> +
> +	ret = gen9_init_workarounds(engine);
> +	if (ret)
> +		return ret;
> +
> +	/* WaEnableGapsTsvCreditFix:cfl */
> +	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> +				   GEN9_GAPS_TSV_CREDIT_DISABLE));
> +
> +	/* WaToEnableHwFixForPushConstHWBug:cfl */
> +	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> +			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> +
> +	/* WaDisableGafsUnitClkGating:cfl */
> +	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaDisableSbeCacheDispatchPortSharing:cfl */
> +	WA_SET_BIT_MASKED(
> +		GEN7_HALF_SLICE_CHICKEN1,
> +		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> +
> +	/* WaInPlaceDecompressionHang:cfl */
> +	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
> +		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> +	return 0;
> +}
> +
>  int init_workarounds_ring(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> @@ -1162,6 +1195,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
>  		err = kbl_init_workarounds(engine);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		err =  glk_init_workarounds(engine);
> +	else if (IS_COFFEELAKE(dev_priv))
> +		err = cfl_init_workarounds(engine);
>  	else
>  		err = 0;
>  	if (err)

Noting a couple of things that will change in the next version.
1) Commit message and title change to clarify these are GT workarounds.
2) The hunk below moves to patch 4/5. 


I am unable review the workarounds themselves, will leave it for someone
who is competent in this area to do it.


> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 98aeba9..0aed13d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -58,24 +58,24 @@
>  
>  static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
> +	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
>  	I915_WRITE(CHICKEN_PAR1_1,
>  		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>  
>  	I915_WRITE(GEN8_CONFIG0,
>  		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
>  
> -	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
> +	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>  
> -	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> -	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
> +	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
> +	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS |
>  		   DISP_FBC_MEMORY_WAKE);
>  
> -	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
> +	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_DISABLE_DUMMY0);
>  }

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Re: [PATCH 5/5] drm/i915/cfl: Introduce Coffee Lake workardounds.

[Mika Kuoppala]

Rodrigo Vivi <rodrigo.vivi@intel.com> writes:

> Coffee Lake inherit most of Kabylake production
> workardounds.
>
> Only difference identified so far is:
> - WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c    |  2 +-
>  drivers/gpu/drm/i915/intel_engine_cs.c | 75 +++++++++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_pm.c        | 10 ++---
>  3 files changed, 61 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4ff854e..8e055b1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1884,7 +1884,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>  	 * called on driver load and after a GPU reset, so you can place
>  	 * workarounds here even if they get overwritten by GPU reset.
>  	 */
> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
>  	if (IS_BROADWELL(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>  	else if (IS_CHERRYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bc38bd1..630ff6e 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -814,24 +814,24 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	int ret;
>  
> -	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */
> +	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
>  
> -	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */
> +	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
>  		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
>  
> -	/* WaDisableKillLogic:bxt,skl,kbl */
> +	/* WaDisableKillLogic:bxt,skl,kbl,cfl */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  		   ECOCHK_DIS_TLB);
>

I couldn't find reference to this in anywhere. So I
would suggest excluding it, unless you have better sources :)


> -	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */
> -	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */
> +	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
> +	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  FLOW_CONTROL_ENABLE |
>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>  
> -	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
> +	/* Syncing dependencies between camera and graphics:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>  			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>

Bspec says that should be disabled for skl+. Bspec is outdated?

> @@ -851,18 +851,18 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  		 */
>  	}
>  
> -	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk */
> -	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> +	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
> +	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
>  			  GEN9_ENABLE_YV12_BUGFIX |
>  			  GEN9_ENABLE_GPGPU_PREEMPTION);
>  
> -	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */
> -	/* WaDisablePartialResolveInVc:skl,bxt,kbl */
> +	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
> +	/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
>  					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
>  
> -	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */
> +	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
>  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
>  			  GEN9_CCS_TLB_PREFETCH_ENABLE);
>  
> @@ -871,7 +871,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
>  				  PIXEL_MASK_CAMMING_DISABLE);
>  
> -	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
> +	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
>  			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
> @@ -889,39 +889,40 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	 * a TLB invalidation occurs during a PSD flush.
>  	 */
>  
> -	/* WaForceEnableNonCoherent:skl,bxt,kbl */
> +	/* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_NON_COHERENT);
>  
> -	/* WaDisableHDCInvalidation:skl,bxt,kbl */
> +	/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  		   BDW_DISABLE_HDC_INVALIDATION);
>

The two above are not mentioned with cfl. But the comment and
history of these workarounds speaks volumes, so I agree with these.

> -	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
> +	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
>  	if (IS_SKYLAKE(dev_priv) ||
>  	    IS_KABYLAKE(dev_priv) ||
> +	    IS_COFFEELAKE(dev_priv)||
>  	    IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
>  		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>  				  GEN8_SAMPLER_POWER_BYPASS_DIS);
>  
> -	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */
> +	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>  
> -	/* WaOCLCoherentLineFlush:skl,bxt,kbl */
> +	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>

For me it seems that the workaround name has changed:
WaPipelineFlushCoherentLines. Should be carried to cfl.

> -	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */
> +	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>  	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>  	if (ret)
>  		return ret;
>  
> -	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
> +	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
>  	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
>  	if (ret)
>  		return ret;
>  
> -	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */
> +	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
>  	ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
>  	if (ret)
>  		return ret;
> @@ -1140,6 +1141,38 @@ static int glk_init_workarounds(struct intel_engine_cs *engine)
>  	return 0;
>  }
>  
> +static int cfl_init_workarounds(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	int ret;
> +
> +	ret = gen9_init_workarounds(engine);
> +	if (ret)
> +		return ret;
> +
> +	/* WaEnableGapsTsvCreditFix:cfl */
> +	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> +				   GEN9_GAPS_TSV_CREDIT_DISABLE));
> +
> +	/* WaToEnableHwFixForPushConstHWBug:cfl */
> +	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> +			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> +
> +	/* WaDisableGafsUnitClkGating:cfl */
> +	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaDisableSbeCacheDispatchPortSharing:cfl */
> +	WA_SET_BIT_MASKED(
> +		GEN7_HALF_SLICE_CHICKEN1,
> +		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> +
> +	/* WaInPlaceDecompressionHang:cfl */
> +	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
> +		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> +	return 0;
> +}
> +
>  int init_workarounds_ring(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> @@ -1162,6 +1195,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
>  		err = kbl_init_workarounds(engine);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		err =  glk_init_workarounds(engine);
> +	else if (IS_COFFEELAKE(dev_priv))
> +		err = cfl_init_workarounds(engine);
>  	else
>  		err = 0;
>  	if (err)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 98aeba9..0aed13d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -58,24 +58,24 @@
>  
>  static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
> +	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
>  	I915_WRITE(CHICKEN_PAR1_1,
>  		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>  
>  	I915_WRITE(GEN8_CONFIG0,
>  		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
>  
> -	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
> +	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>  
> -	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> -	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
> +	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
> +	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS |
>  		   DISP_FBC_MEMORY_WAKE);
>  
> -	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
> +	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */

I haven't rummaged around what new we might be missing. So
we should do a second pass after month or two.

With WaDisableKillLogic and GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
double checked.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>


>  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_DISABLE_DUMMY0);
>  }
> -- 
> 1.9.1
>
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