* [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP
@ 2018-07-31 21:06 Manasi Navare
2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
` (30 more replies)
0 siblings, 31 replies; 73+ messages in thread
From: Manasi Navare @ 2018-07-31 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Cc: dri-devel@lists.freedesktop.org
VESA has developed an industry standard Display Stream Compression(DSC)
for interoperable, visually lossless compression over display links to
address the needs for higher resolution displays.
This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels.
This implementation is based on VESA DP 1.4 and DSC specifications.
These patches have been validated on 1080p eDP 1.4 panel with DSC support
and FPGA based DP 1.4 sink device.
This patch series fixes some CI warnings from prev series:
https://patchwork.freedesktop.org/series/47461/
Gaurav K Singh (6):
drm/dsc: Define VESA Display Stream Compression Capabilities
drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
drm/i915/dsc: Define & Compute VESA DSC params
drm/i915/dsc: Compute Rate Control parameters for DSC
drm/i915/dp: Enable/Disable DSC in DP Sink
drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
Manasi Navare (15):
drm/dp: Add DP DSC DPCD receiver capability size define and missing
SHIFT
drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP
Init
drm/dp: DRM DP helper/macros to get DP sink DSC parameters
drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
drm/i915/dp: Validate modes using max Output BPP and slice count when
DSC supported
drm/dp: Define payload size for DP SDP PPS packet
drm/dsc: Define Display Stream Compression PPS infoframe
drm/dsc: Add helpers for DSC picture parameter set infoframes
drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
drm/i915/dp: Compute DSC pipe config in atomic check
drm/i915/dp: Do not enable PSR2 if DSC is enabled
drm/i915/dp: Configure i915 Picture parameter Set registers during DSC
enabling
drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
drm/i915/dp: Configure Display stream splitter registers during DSC
enable
Srivatsa, Anusha (2):
drm/dsc: Define Rate Control values that do not change over
configurations
drm/i915/icl: Add Display Stream Splitter control registers
Documentation/gpu/drm-kms-helpers.rst | 12 +
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dp_helper.c | 89 +++
drivers/gpu/drm/drm_dsc.c | 221 +++++++
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_reg.h | 34 ++
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_display.c | 39 +-
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 326 +++++++++-
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 21 +
drivers/gpu/drm/i915/intel_hdmi.c | 23 +-
drivers/gpu/drm/i915/intel_psr.c | 10 +
drivers/gpu/drm/i915/intel_vdsc.c | 1088 +++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 40 ++
include/drm/drm_dsc.h | 506 +++++++++++++++
18 files changed, 2400 insertions(+), 29 deletions(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
create mode 100644 include/drm/drm_dsc.h
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread* [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare @ 2018-07-31 21:06 ` Manasi Navare 2018-07-31 22:17 ` Srivatsa, Anusha 2018-07-31 21:06 ` [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare ` (29 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:06 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel This patch defines the DP DSC receiver capability size that gives total number of DP DSC DPCD registers. This also adds a missing #defines for DP DSC support missed in the commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") v3: * MIN_SLICE_WIDTH = 2560 (Anusha) * Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 v2: * Add SHIFT define and DECOMPRESSION_EN define misse din prev patch Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- include/drm/drm_dp_helper.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 05cc31b..eb0d86c 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -230,6 +230,8 @@ #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -278,6 +280,8 @@ # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) #define DP_DSC_MAX_SLICE_WIDTH 0x06C +#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 +#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 #define DP_DSC_SLICE_CAP_2 0x06D # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) @@ -476,6 +480,7 @@ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ +# define DP_DECOMPRESSION_EN (1 << 0) #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) @@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE 0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* RE: [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare @ 2018-07-31 22:17 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-07-31 22:17 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx; +Cc: dri-devel, Singh, Gaurav K >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; dri- >devel@lists.freedesktop.org; Jani Nikula <jani.nikula@linux.intel.com>; Ville >Syrjala <ville.syrjala@linux.intel.com>; Srivatsa, Anusha ><anusha.srivatsa@intel.com>; Singh, Gaurav K <gaurav.k.singh@intel.com> >Subject: [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size >define and missing SHIFT > >This patch defines the DP DSC receiver capability size that gives total number of >DP DSC DPCD registers. >This also adds a missing #defines for DP DSC support missed in the commit id >(ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") > >v3: >* MIN_SLICE_WIDTH = 2560 (Anusha) >* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 >v2: >* Add SHIFT define and DECOMPRESSION_EN define misse din prev patch ^^^ "missed in previous" >Cc: dri-devel@lists.freedesktop.org >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Other than the typo, the patch looks good. Checked with Spec. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > include/drm/drm_dp_helper.h | 6 ++++++ > 1 file changed, 6 insertions(+) > >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index >05cc31b..eb0d86c 100644 >--- a/include/drm/drm_dp_helper.h >+++ b/include/drm/drm_dp_helper.h >@@ -230,6 +230,8 @@ > #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ > > #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ >+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define >+DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 > > #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 > # define DP_DSC_RGB (1 << 0) >@@ -278,6 +280,8 @@ > # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) > > #define DP_DSC_MAX_SLICE_WIDTH 0x06C >+#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 >+#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 > > #define DP_DSC_SLICE_CAP_2 0x06D > # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) >@@ -476,6 +480,7 @@ > # define DP_AUX_FRAME_SYNC_VALID (1 << 0) > > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ >+# define DP_DECOMPRESSION_EN (1 << 0) > > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > # define DP_PSR_ENABLE (1 << 0) >@@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 >link_status[DP_LINK_STATUS_SI > > #define DP_BRANCH_OUI_HEADER_SIZE 0xc > #define DP_RECEIVER_CAP_SIZE 0xf >+#define DP_DSC_RECEIVER_CAP_SIZE 0xf > #define EDP_PSR_RECEIVER_CAP_SIZE 2 > #define EDP_DISPLAY_CTL_CAP_SIZE 3 > >-- >2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare 2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare @ 2018-07-31 21:06 ` Manasi Navare 2018-07-31 22:32 ` Srivatsa, Anusha 2018-09-11 11:22 ` Singh, Gaurav K 2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare ` (28 subsequent siblings) 30 siblings, 2 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:06 UTC (permalink / raw) To: intel-gfx; +Cc: Daniel Vetter DSC is supported on eDP starting GEN 10 display and on DP starting GEN 11. This patch implements the discovery phase of DSC. On hotplug, source reads the DSC DPCD register set (0x00060 - 0x006F) to read the decompression capabilities of the sink device. This entire block of registers is cached in intel_dp so that capability information can be used during DSC configuration phase during compute_config phase of the modeset. For eDP, this caching happens during the eDP initialization. This caching is done only for eDP and DP rev >= 1.4 v5: * Fix the block comment (Gaurav) * Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha) v4: * Cache these only for Gen >= 11 v3: * Remove the dsc_sink_support field in intel_dp (Jani N) v2: * Clear the cached registers on hotplug always (Jani N) * Combine the eDP and DP caching in same function (Jani N) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 32 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8e0e14b..afa4e2d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3877,6 +3877,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp) return intel_dp->dpcd[DP_DPCD_REV] != 0; } +static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) +{ + /* + *Clear the cached register set to avoid using stale values + * for the sinks that do not support DSC. + */ + memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + + /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || + intel_dp->edp_dpcd[0] >= DP_EDP_14) { + if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, + intel_dp->dsc_dpcd, + sizeof(intel_dp->dsc_dpcd)) < 0) + DRM_ERROR("Failed to read DPCD register 0x%x\n", + DP_DSC_SUPPORT); + + DRM_DEBUG_KMS("DSC DPCD: %*ph\n", + (int)sizeof(intel_dp->dsc_dpcd), + intel_dp->dsc_dpcd); + } +} + static bool intel_edp_init_dpcd(struct intel_dp *intel_dp) { @@ -3953,6 +3976,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) intel_dp_set_common_rates(intel_dp); + /* Read the eDP DSC DPCD registers */ + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + intel_dp_get_dsc_sink_cap(intel_dp); + return true; } @@ -4944,6 +4971,7 @@ intel_dp_long_pulse(struct intel_connector *connector) if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); + memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); if (intel_dp->is_mst) { DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", @@ -4969,6 +4997,10 @@ intel_dp_long_pulse(struct intel_connector *connector) intel_dp_print_rates(intel_dp); + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ + if (INTEL_GEN(dev_priv) >= 11) + intel_dp_get_dsc_sink_cap(intel_dp); + drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd)); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 99a5f5b..29abe7a 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1070,6 +1070,7 @@ struct intel_dp { uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; + u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; /* source rates */ int num_source_rates; const int *source_rates; -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 2018-07-31 21:06 ` [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare @ 2018-07-31 22:32 ` Srivatsa, Anusha 2018-09-11 11:22 ` Singh, Gaurav K 1 sibling, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-07-31 22:32 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx; +Cc: Daniel Vetter >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; Daniel >Vetter <daniel.vetter@ffwll.ch>; Srivatsa, Anusha <anusha.srivatsa@intel.com>; >Singh, Gaurav K <gaurav.k.singh@intel.com> >Subject: [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set >on Hotplug/eDP Init > >DSC is supported on eDP starting GEN 10 display and on DP starting GEN 11. >This patch implements the discovery phase of DSC. On hotplug, source reads the >DSC DPCD register set (0x00060 - 0x006F) to read the decompression capabilities >of the sink device. A sentence telling that DSC on eDP is supported on Geminilake would be more clear. In the code below, we check if it is gen10 or GLK. The commit message speaks of DSC support only for Gen10+ for eDP and Gen 11+ for DP. Implementation looks good. >This entire block of registers is cached in intel_dp so that capability information >can be used during DSC configuration phase during compute_config phase of the >modeset. >For eDP, this caching happens during the eDP initialization. >This caching is done only for eDP and DP rev >= 1.4 > >v5: >* Fix the block comment (Gaurav) >* Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha) >v4: >* Cache these only for Gen >= 11 >v3: >* Remove the dsc_sink_support field in intel_dp (Jani N) >v2: >* Clear the cached registers on hotplug always (Jani N) >* Combine the eDP and DP caching in same function (Jani N) > >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Daniel Vetter <daniel.vetter@ffwll.ch> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/intel_dp.c | 32 ++++++++++++++++++++++++++++++++ >drivers/gpu/drm/i915/intel_drv.h | 1 + > 2 files changed, 33 insertions(+) > >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >index 8e0e14b..afa4e2d 100644 >--- a/drivers/gpu/drm/i915/intel_dp.c >+++ b/drivers/gpu/drm/i915/intel_dp.c >@@ -3877,6 +3877,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp) > return intel_dp->dpcd[DP_DPCD_REV] != 0; } > >+static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) { >+ /* >+ *Clear the cached register set to avoid using stale values >+ * for the sinks that do not support DSC. >+ */ >+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); >+ >+ /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ >+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || >+ intel_dp->edp_dpcd[0] >= DP_EDP_14) { >+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, >+ intel_dp->dsc_dpcd, >+ sizeof(intel_dp->dsc_dpcd)) < 0) >+ DRM_ERROR("Failed to read DPCD register 0x%x\n", >+ DP_DSC_SUPPORT); >+ >+ DRM_DEBUG_KMS("DSC DPCD: %*ph\n", >+ (int)sizeof(intel_dp->dsc_dpcd), >+ intel_dp->dsc_dpcd); >+ } >+} >+ > static bool > intel_edp_init_dpcd(struct intel_dp *intel_dp) { @@ -3953,6 +3976,10 @@ >intel_edp_init_dpcd(struct intel_dp *intel_dp) > > intel_dp_set_common_rates(intel_dp); > >+ /* Read the eDP DSC DPCD registers */ >+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) >+ intel_dp_get_dsc_sink_cap(intel_dp); >+ > return true; > } > >@@ -4944,6 +4971,7 @@ intel_dp_long_pulse(struct intel_connector >*connector) > > if (status == connector_status_disconnected) { > memset(&intel_dp->compliance, 0, sizeof(intel_dp- >>compliance)); >+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > if (intel_dp->is_mst) { > DRM_DEBUG_KMS("MST device may have disappeared >%d vs %d\n", @@ -4969,6 +4997,10 @@ intel_dp_long_pulse(struct >intel_connector *connector) > > intel_dp_print_rates(intel_dp); > >+ /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ >+ if (INTEL_GEN(dev_priv) >= 11) >+ intel_dp_get_dsc_sink_cap(intel_dp); >+ > drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, > drm_dp_is_branch(intel_dp->dpcd)); > >diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >index 99a5f5b..29abe7a 100644 >--- a/drivers/gpu/drm/i915/intel_drv.h >+++ b/drivers/gpu/drm/i915/intel_drv.h >@@ -1070,6 +1070,7 @@ struct intel_dp { > uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; > uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; > uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; >+ u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; > /* source rates */ > int num_source_rates; > const int *source_rates; >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 2018-07-31 21:06 ` [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare 2018-07-31 22:32 ` Srivatsa, Anusha @ 2018-09-11 11:22 ` Singh, Gaurav K 1 sibling, 0 replies; 73+ messages in thread From: Singh, Gaurav K @ 2018-09-11 11:22 UTC (permalink / raw) To: Manasi Navare, intel-gfx; +Cc: Daniel Vetter On 8/1/2018 2:36 AM, Manasi Navare wrote: > DSC is supported on eDP starting GEN 10 display and on DP starting > GEN 11. > This patch implements the discovery phase of DSC. On hotplug, > source reads the DSC DPCD register set (0x00060 - 0x006F) to Please correct it to 0x0006F in order to match the spec > read the decompression capabilities of the sink device. > This entire block of registers is cached in intel_dp so that > capability information can be used during DSC configuration > phase during compute_config phase of the modeset. > For eDP, this caching happens during the eDP initialization. > This caching is done only for eDP and DP rev >= 1.4 > > v5: > * Fix the block comment (Gaurav) > * Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha) > v4: > * Cache these only for Gen >= 11 > v3: > * Remove the dsc_sink_support field in intel_dp (Jani N) > v2: > * Clear the cached registers on hotplug always (Jani N) > * Combine the eDP and DP caching in same function (Jani N) > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Except the above comment, this patch looks good to me.. Reviewed-by: Gaurav K Singh<gaurav.k.singh@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 32 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_drv.h | 1 + > 2 files changed, 33 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 8e0e14b..afa4e2d 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3877,6 +3877,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp) > return intel_dp->dpcd[DP_DPCD_REV] != 0; > } > > +static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) > +{ > + /* > + *Clear the cached register set to avoid using stale values > + * for the sinks that do not support DSC. > + */ > + memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > + > + /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ > + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || > + intel_dp->edp_dpcd[0] >= DP_EDP_14) { > + if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, > + intel_dp->dsc_dpcd, > + sizeof(intel_dp->dsc_dpcd)) < 0) > + DRM_ERROR("Failed to read DPCD register 0x%x\n", > + DP_DSC_SUPPORT); > + > + DRM_DEBUG_KMS("DSC DPCD: %*ph\n", > + (int)sizeof(intel_dp->dsc_dpcd), > + intel_dp->dsc_dpcd); > + } > +} > + > static bool > intel_edp_init_dpcd(struct intel_dp *intel_dp) > { > @@ -3953,6 +3976,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) > > intel_dp_set_common_rates(intel_dp); > > + /* Read the eDP DSC DPCD registers */ > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > + intel_dp_get_dsc_sink_cap(intel_dp); > + > return true; > } > > @@ -4944,6 +4971,7 @@ intel_dp_long_pulse(struct intel_connector *connector) > > if (status == connector_status_disconnected) { > memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); > + memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > if (intel_dp->is_mst) { > DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", > @@ -4969,6 +4997,10 @@ intel_dp_long_pulse(struct intel_connector *connector) > > intel_dp_print_rates(intel_dp); > > + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > + if (INTEL_GEN(dev_priv) >= 11) > + intel_dp_get_dsc_sink_cap(intel_dp); > + > drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, > drm_dp_is_branch(intel_dp->dpcd)); > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 99a5f5b..29abe7a 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1070,6 +1070,7 @@ struct intel_dp { > uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; > uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; > uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; > + u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; > /* source rates */ > int num_source_rates; > const int *source_rates; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare 2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare 2018-07-31 21:06 ` [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare @ 2018-07-31 21:06 ` Manasi Navare 2018-07-31 23:33 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare ` (27 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:06 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel This patch adds inline functions and helpers for obtaining DP sink's supported DSC parameters like DSC sink support, eDP compressed BPP supported, maximum slice count supported by the sink devices, DSC line buffer bit depth supported on DP sink, DSC sink maximum color depth by parsing corresponding DPCD registers. v4: * Add helper to give line buf bit depth (Manasi) v3: * Use SLICE_CAP_2 for DP (Anusha) v2: * Add DSC sink support macro (Jani N) Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 89 +++++++++++++++++++++++++++++++++++++++++ include/drm/drm_dp_helper.h | 30 ++++++++++++++ 2 files changed, 119 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 0cccbcb..7dc61d1 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1336,3 +1336,92 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, return 0; } EXPORT_SYMBOL(drm_dp_read_desc); + +/** + * DRM DP Helpers for DSC + */ +u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], + bool is_edp) +{ + u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; + + if (is_edp) { + /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ + if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) + return 4; + if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) + return 2; + if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) + return 1; + } else { + /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ + u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; + + if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) + return 24; + if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) + return 20; + if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) + return 16; + if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) + return 12; + if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) + return 10; + if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) + return 8; + if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) + return 6; + if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) + return 4; + if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) + return 2; + if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) + return 1; + } + + return 0; +} +EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); + +u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; + + switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { + case DP_DSC_LINE_BUF_BIT_DEPTH_9: + return 9; + case DP_DSC_LINE_BUF_BIT_DEPTH_10: + return 10; + case DP_DSC_LINE_BUF_BIT_DEPTH_11: + return 11; + case DP_DSC_LINE_BUF_BIT_DEPTH_12: + return 12; + case DP_DSC_LINE_BUF_BIT_DEPTH_13: + return 13; + case DP_DSC_LINE_BUF_BIT_DEPTH_14: + return 14; + case DP_DSC_LINE_BUF_BIT_DEPTH_15: + return 15; + case DP_DSC_LINE_BUF_BIT_DEPTH_16: + return 16; + case DP_DSC_LINE_BUF_BIT_DEPTH_8: + return 8; + } + + return 0; +} +EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); + +u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + switch (dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]) { + case DP_DSC_12_BPC: + return 12; + case DP_DSC_10_BPC: + return 10; + case DP_DSC_8_BPC: + return 8; + } + return 0; +} +EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index eb0d86c..8c1dbca 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1064,6 +1064,36 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; } +/* DP/eDP DSC support */ +u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], + bool is_edp); +u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); +u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]); + +static inline bool +drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & + DP_DSC_DECOMPRESSION_IS_SUPPORTED; +} + +static inline u16 +drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | + (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & + DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << + DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); +} + +static inline u32 +drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + /* Max Slicewidth = Number of Pixels * 320 */ + return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * + DP_DSC_SLICE_WIDTH_MULTIPLIER; +} + /* * DisplayPort AUX channel */ -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters 2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare @ 2018-07-31 23:33 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-07-31 23:33 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx; +Cc: dri-devel >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K ><gaurav.k.singh@intel.com>; dri-devel@lists.freedesktop.org; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com> >Subject: [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC >parameters > >This patch adds inline functions and helpers for obtaining DP sink's supported DSC >parameters like DSC sink support, eDP compressed BPP supported, maximum slice >count supported by the sink devices, DSC line buffer bit depth supported on DP >sink, DSC sink maximum color depth by parsing corresponding DPCD registers. > >v4: >* Add helper to give line buf bit depth (Manasi) >v3: >* Use SLICE_CAP_2 for DP (Anusha) >v2: >* Add DSC sink support macro (Jani N) > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Cc: dri-devel@lists.freedesktop.org >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/drm_dp_helper.c | 89 >+++++++++++++++++++++++++++++++++++++++++ > include/drm/drm_dp_helper.h | 30 ++++++++++++++ > 2 files changed, 119 insertions(+) > >diff --git a/drivers/gpu/drm/drm_dp_helper.c >b/drivers/gpu/drm/drm_dp_helper.c index 0cccbcb..7dc61d1 100644 >--- a/drivers/gpu/drm/drm_dp_helper.c >+++ b/drivers/gpu/drm/drm_dp_helper.c >@@ -1336,3 +1336,92 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, >struct drm_dp_desc *desc, > return 0; > } > EXPORT_SYMBOL(drm_dp_read_desc); >+ >+/** >+ * DRM DP Helpers for DSC >+ */ >+u8 drm_dp_dsc_sink_max_slice_count(const u8 >dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], >+ bool is_edp) >+{ >+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; >+ >+ if (is_edp) { >+ /* For eDP, register DSC_SLICE_CAPABILITIES_1 NIT : the actual register is DSC_SLICE_CAP_1 gives slice count >*/ >+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) >+ return 4; >+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) >+ return 2; >+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) >+ return 1; >+ } else { >+ /* For DP, use values from DSC_SLICE_CAP_1 and >DSC_SLICE_CAP2 */ ^^^ DSC_SLICE_CAP_2 >+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - >DP_DSC_SUPPORT]; >+ >+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) >+ return 24; >+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) >+ return 20; >+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) >+ return 16; >+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) >+ return 12; >+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) >+ return 10; >+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) >+ return 8; >+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) >+ return 6; >+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) >+ return 4; >+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) >+ return 2; >+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) >+ return 1; >+ } >+ >+ return 0; >+} >+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); >+ >+u8 drm_dp_dsc_sink_line_buf_depth(const u8 >+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) >+{ >+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - >+DP_DSC_SUPPORT]; >+ >+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { >+ case DP_DSC_LINE_BUF_BIT_DEPTH_9: >+ return 9; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_10: >+ return 10; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_11: >+ return 11; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_12: >+ return 12; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_13: >+ return 13; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_14: >+ return 14; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_15: >+ return 15; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_16: >+ return 16; >+ case DP_DSC_LINE_BUF_BIT_DEPTH_8: >+ return 8; >+ } >+ >+ return 0; >+} >+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); >+ >+u8 drm_dp_dsc_sink_max_color_depth(const u8 >+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) >+{ >+ switch (dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - >DP_DSC_SUPPORT]) { >+ case DP_DSC_12_BPC: >+ return 12; >+ case DP_DSC_10_BPC: >+ return 10; >+ case DP_DSC_8_BPC: >+ return 8; >+ } >+ return 0; >+} >+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth); >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index >eb0d86c..8c1dbca 100644 >--- a/include/drm/drm_dp_helper.h >+++ b/include/drm/drm_dp_helper.h >@@ -1064,6 +1064,36 @@ drm_dp_is_branch(const u8 >dpcd[DP_RECEIVER_CAP_SIZE]) > return dpcd[DP_DOWNSTREAMPORT_PRESENT] & >DP_DWN_STRM_PORT_PRESENT; } > >+/* DP/eDP DSC support */ >+u8 drm_dp_dsc_sink_max_slice_count(const u8 >dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], >+ bool is_edp); >+u8 drm_dp_dsc_sink_line_buf_depth(const u8 >+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); >+u8 drm_dp_dsc_sink_max_color_depth(const u8 >+dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]); >+ >+static inline bool >+drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) >+{ >+ return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & >+ DP_DSC_DECOMPRESSION_IS_SUPPORTED; >+} >+ >+static inline u16 >+drm_edp_dsc_sink_output_bpp(const u8 >+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) >+{ >+ return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - >DP_DSC_SUPPORT] | >+ (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - >DP_DSC_SUPPORT] & >+ DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << >+ DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); >+} >+ >+static inline u32 >+drm_dp_dsc_sink_max_slice_width(const u8 >+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) >+{ >+ /* Max Slicewidth = Number of Pixels * 320 */ >+ return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * >+ DP_DSC_SLICE_WIDTH_MULTIPLIER; >+} >+ > /* > * DisplayPort AUX channel > */ >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (2 preceding siblings ...) 2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-17 19:21 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare ` (26 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Dhinakaran Pandiyan This patch adds helpers for calculating the maximum compressed BPP supported with small joiner. This also adds a helper for calculating the slice count in case of small joiner. These are inside intel_dp since they take into account hardware limitations. v5: * Get the max slice width from DPCD * Check against Min_Slice_width of 2560 (Anusha) v4: * #defines for PPR in slice count helper (Gaurav) v3: * Simply logic for bpp (DK) * Limit the valid slice count by max supported by Sink (Manasi) v2: * Change the small joiner RAM buffer constant as bspec changed (Manasi) * rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha) Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 104 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 4 ++ 2 files changed, 108 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index afa4e2d..ec2af43 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -45,6 +45,17 @@ #define DP_DPRX_ESI_LEN 14 +/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */ +#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440 + +/* DP DSC throughput values used for slice count calculations KPixels/s */ +#define DP_DSC_PEAK_PIXEL_RATE 2720000 +#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 +#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 + +/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */ +#define DP_DSC_FEC_OVERHEAD_FACTOR 976 + /* Compliance test status bits */ #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) @@ -93,6 +104,14 @@ static const struct dp_link_dpll chv_dpll[] = { { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, }; +/* Constants for DP DSC configurations */ +static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; + +/* With Single pipe configuration, HW is capable of supporting maximum + * of 4 slices per line. + */ +static const u8 valid_dsc_slicecount[] = {1, 2, 4}; + /** * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) * @intel_dp: DP struct @@ -4087,6 +4106,91 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) DP_DPRX_ESI_LEN; } +uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, + int mode_clock, int mode_hdisplay) +{ + u16 bits_per_pixel, max_bpp_small_joiner_ram; + int i; + + /* + * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* + * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP) + * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1, + * for MST -> TimeSlotsPerMTP has to be calculated + */ + bits_per_pixel = (link_clock * lane_count * 8 * + DP_DSC_FEC_OVERHEAD_FACTOR) / + (mode_clock * 1000); + + /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ + max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / + mode_hdisplay; + + /* + * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW + * check, output bpp from small joiner RAM check) + */ + bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); + + /* Error out if the max bpp is less than smallest allowed valid bpp */ + if (bits_per_pixel < valid_dsc_bpp[0]) { + DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel); + return 0; + } + + /* Find the nearest match in the array of known BPPs from VESA */ + for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { + if (bits_per_pixel < valid_dsc_bpp[i + 1]) + break; + } + bits_per_pixel = valid_dsc_bpp[i]; + + /* + * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, + * fractional part is 0 + */ + return bits_per_pixel << 4; +} + +uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, + int mode_hdisplay) +{ + u8 min_slice_count, i; + int max_slice_width; + + if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) + min_slice_count = DIV_ROUND_UP(mode_clock, + DP_DSC_MAX_ENC_THROUGHPUT_0); + else + min_slice_count = DIV_ROUND_UP(mode_clock, + DP_DSC_MAX_ENC_THROUGHPUT_1); + + max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); + if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { + DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n", + max_slice_width); + return 0; + } + /* Also take into account max slice width */ + min_slice_count = min_t(uint8_t, min_slice_count, + DIV_ROUND_UP(mode_hdisplay, + max_slice_width)); + + /* Find the closest match to the valid slice count values */ + for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { + if (valid_dsc_slicecount[i] > + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, + false)) + break; + if (min_slice_count <= valid_dsc_slicecount[i]) + return valid_dsc_slicecount[i]; + } + + DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count); + return 0; +} + static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { int status = 0; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 29abe7a..68b2401 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1735,6 +1735,10 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); bool intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); +uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, + int mode_clock, int mode_hdisplay); +uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, + int mode_hdisplay); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC 2018-07-31 21:07 ` [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare @ 2018-08-17 19:21 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-17 19:21 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx; +Cc: Pandiyan, Dhinakaran >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K ><gaurav.k.singh@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>; Ville >Syrjala <ville.syrjala@linux.intel.com>; Srivatsa, Anusha ><anusha.srivatsa@intel.com>; Pandiyan, Dhinakaran ><dhinakaran.pandiyan@intel.com> >Subject: [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and >Slice Count for DSC > >This patch adds helpers for calculating the maximum compressed BPP supported >with small joiner. >This also adds a helper for calculating the slice count in case of small joiner. >These are inside intel_dp since they take into account hardware limitations. > >v5: >* Get the max slice width from DPCD >* Check against Min_Slice_width of 2560 (Anusha) >v4: >* #defines for PPR in slice count helper (Gaurav) >v3: >* Simply logic for bpp (DK) >* Limit the valid slice count by max supported by Sink (Manasi) >v2: >* Change the small joiner RAM buffer constant as bspec changed (Manasi) >* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha) > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Looks good. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/intel_dp.c | 104 >+++++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_drv.h | 4 ++ > 2 files changed, 108 insertions(+) > >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >index afa4e2d..ec2af43 100644 >--- a/drivers/gpu/drm/i915/intel_dp.c >+++ b/drivers/gpu/drm/i915/intel_dp.c >@@ -45,6 +45,17 @@ > > #define DP_DPRX_ESI_LEN 14 > >+/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */ >+#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440 >+ >+/* DP DSC throughput values used for slice count calculations KPixels/s */ >+#define DP_DSC_PEAK_PIXEL_RATE 2720000 >+#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 >+#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 >+ >+/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */ >+#define DP_DSC_FEC_OVERHEAD_FACTOR 976 >+ > /* Compliance test status bits */ > #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 > #define INTEL_DP_RESOLUTION_PREFERRED (1 << >INTEL_DP_RESOLUTION_SHIFT_MASK) >@@ -93,6 +104,14 @@ static const struct dp_link_dpll chv_dpll[] = { > { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, }; > >+/* Constants for DP DSC configurations */ static const u8 >+valid_dsc_bpp[] = {6, 8, 10, 12, 15}; >+ >+/* With Single pipe configuration, HW is capable of supporting maximum >+ * of 4 slices per line. >+ */ >+static const u8 valid_dsc_slicecount[] = {1, 2, 4}; >+ > /** > * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or >PCH) > * @intel_dp: DP struct >@@ -4087,6 +4106,91 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, >u8 *sink_irq_vector) > DP_DPRX_ESI_LEN; > } > >+uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, >+ int mode_clock, int mode_hdisplay) { >+ u16 bits_per_pixel, max_bpp_small_joiner_ram; >+ int i; >+ >+ /* >+ * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* >+ * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP) >+ * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1, >+ * for MST -> TimeSlotsPerMTP has to be calculated >+ */ >+ bits_per_pixel = (link_clock * lane_count * 8 * >+ DP_DSC_FEC_OVERHEAD_FACTOR) / >+ (mode_clock * 1000); >+ >+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ >+ max_bpp_small_joiner_ram = >DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / >+ mode_hdisplay; >+ >+ /* >+ * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW >+ * check, output bpp from small joiner RAM check) >+ */ >+ bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); >+ >+ /* Error out if the max bpp is less than smallest allowed valid bpp */ >+ if (bits_per_pixel < valid_dsc_bpp[0]) { >+ DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel); >+ return 0; >+ } >+ >+ /* Find the nearest match in the array of known BPPs from VESA */ >+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { >+ if (bits_per_pixel < valid_dsc_bpp[i + 1]) >+ break; >+ } >+ bits_per_pixel = valid_dsc_bpp[i]; >+ >+ /* >+ * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, >+ * fractional part is 0 >+ */ >+ return bits_per_pixel << 4; >+} >+ >+uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, >+ int mode_clock, >+ int mode_hdisplay) >+{ >+ u8 min_slice_count, i; >+ int max_slice_width; >+ >+ if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) >+ min_slice_count = DIV_ROUND_UP(mode_clock, >+ >DP_DSC_MAX_ENC_THROUGHPUT_0); >+ else >+ min_slice_count = DIV_ROUND_UP(mode_clock, >+ >DP_DSC_MAX_ENC_THROUGHPUT_1); >+ >+ max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp- >>dsc_dpcd); >+ if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { >+ DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink >device\n", >+ max_slice_width); >+ return 0; >+ } >+ /* Also take into account max slice width */ >+ min_slice_count = min_t(uint8_t, min_slice_count, >+ DIV_ROUND_UP(mode_hdisplay, >+ max_slice_width)); >+ >+ /* Find the closest match to the valid slice count values */ >+ for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { >+ if (valid_dsc_slicecount[i] > >+ drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, >+ false)) >+ break; >+ if (min_slice_count <= valid_dsc_slicecount[i]) >+ return valid_dsc_slicecount[i]; >+ } >+ >+ DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count); >+ return 0; >+} >+ > static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { > int status = 0; >diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >index 29abe7a..68b2401 100644 >--- a/drivers/gpu/drm/i915/intel_drv.h >+++ b/drivers/gpu/drm/i915/intel_drv.h >@@ -1735,6 +1735,10 @@ bool intel_dp_source_supports_hbr2(struct intel_dp >*intel_dp); bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); bool >intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t >link_status[DP_LINK_STATUS_SIZE]); >+uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, >+ int mode_clock, int mode_hdisplay); uint8_t >+intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, >+ int mode_hdisplay); > > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (3 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-17 19:20 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare ` (25 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx When DSC is supported we need to validate the modes based on the maximum supported compressed BPP and maximum supported slice count. This allows us to allow the modes with pixel clock greater than the available link BW as long as it meets the compressed BPP and slice count requirements. v3: * Use the macro for dsc sink support (Jani N) v2: * Properly comment why we are right shifting the bpp value (Anusha) Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ec2af43..8459d74 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -612,9 +612,12 @@ intel_dp_mode_valid(struct drm_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_connector *intel_connector = to_intel_connector(connector); struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; + struct drm_i915_private *dev_priv = to_i915(connector->dev); int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk; + uint16_t dsc_max_output_bpp = 0; + uint8_t dsc_slice_count = 0; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; @@ -637,7 +640,29 @@ intel_dp_mode_valid(struct drm_connector *connector, max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); mode_rate = intel_dp_link_required(target_clock, 18); - if (mode_rate > max_rate || target_clock > max_dotclk) + /* + * Output bpp is stored in 6.4 format so right shift by 4 to get the + * integer value since we support only integer values of bpp. + */ + if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + if (intel_dp_is_edp(intel_dp)) { + dsc_max_output_bpp = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; + dsc_slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, + true); + } else { + dsc_max_output_bpp = intel_dp_dsc_get_output_bpp(max_link_clock, + max_lanes, + target_clock, + mode->hdisplay) >> 4; + dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, + target_clock, + mode->hdisplay); + } + } + + if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || + target_clock > max_dotclk) return MODE_CLOCK_HIGH; if (mode->clock < 10000) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 2018-07-31 21:07 ` [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare @ 2018-08-17 19:20 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-17 19:20 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K ><gaurav.k.singh@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>; Ville >Syrjala <ville.syrjala@linux.intel.com>; Srivatsa, Anusha ><anusha.srivatsa@intel.com> >Subject: [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP >and slice count when DSC supported > >When DSC is supported we need to validate the modes based on the maximum >supported compressed BPP and maximum supported slice count. >This allows us to allow the modes with pixel clock greater than the available link >BW as long as it meets the compressed BPP and slice count requirements. > >v3: >* Use the macro for dsc sink support (Jani N) >v2: >* Properly comment why we are right shifting the bpp value (Anusha) > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa<anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >index ec2af43..8459d74 100644 >--- a/drivers/gpu/drm/i915/intel_dp.c >+++ b/drivers/gpu/drm/i915/intel_dp.c >@@ -612,9 +612,12 @@ intel_dp_mode_valid(struct drm_connector *connector, > struct intel_dp *intel_dp = intel_attached_dp(connector); > struct intel_connector *intel_connector = >to_intel_connector(connector); > struct drm_display_mode *fixed_mode = intel_connector- >>panel.fixed_mode; >+ struct drm_i915_private *dev_priv = to_i915(connector->dev); > int target_clock = mode->clock; > int max_rate, mode_rate, max_lanes, max_link_clock; > int max_dotclk; >+ uint16_t dsc_max_output_bpp = 0; >+ uint8_t dsc_slice_count = 0; > > if (mode->flags & DRM_MODE_FLAG_DBLSCAN) > return MODE_NO_DBLESCAN; >@@ -637,7 +640,29 @@ intel_dp_mode_valid(struct drm_connector *connector, > max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); > mode_rate = intel_dp_link_required(target_clock, 18); > >- if (mode_rate > max_rate || target_clock > max_dotclk) >+ /* >+ * Output bpp is stored in 6.4 format so right shift by 4 to get the >+ * integer value since we support only integer values of bpp. >+ */ >+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && >+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { >+ if (intel_dp_is_edp(intel_dp)) { >+ dsc_max_output_bpp = >drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; >+ dsc_slice_count = >drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, >+ true); >+ } else { >+ dsc_max_output_bpp = >intel_dp_dsc_get_output_bpp(max_link_clock, >+ >max_lanes, >+ >target_clock, >+ mode- >>hdisplay) >> 4; >+ dsc_slice_count = >intel_dp_dsc_get_slice_count(intel_dp, >+ >target_clock, >+ mode- >>hdisplay); >+ } >+ } >+ >+ if ((mode_rate > max_rate && !(dsc_max_output_bpp && >dsc_slice_count)) || >+ target_clock > max_dotclk) > return MODE_CLOCK_HIGH; > if (mode->clock < 10000) >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (4 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare ` (24 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Anusha Srivatsa, Manasi Navare, dri-devel, Gaurav K Singh DP 1.4 spec defines DP secondary data packet for DSC picture parameter set. This patch defines its payload size according to the DP 1.4 specification. Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> --- include/drm/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8c1dbca..0cf2407 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -998,6 +998,7 @@ struct dp_sdp_header { #define EDP_SDP_HEADER_REVISION_MASK 0x1F #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F +#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F struct edp_vsc_psr { struct dp_sdp_header sdp_header; -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (5 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-17 19:31 ` Srivatsa, Anusha 2018-08-23 19:40 ` Harry Wentland 2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare ` (23 subsequent siblings) 30 siblings, 2 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Anusha Srivatsa, Manasi Navare, dri-devel, Gaurav K Singh This patch defines a new header file for all the DSC 1.2 structures and creates a structure for PPS infoframe which will be used to send picture parameter set secondary data packet for display stream compression. All the PPS infoframe syntax elements are taken from DSC 1.2 specification from VESA. Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- include/drm/drm_dsc.h | 365 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 365 insertions(+) create mode 100644 include/drm/drm_dsc.h diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h new file mode 100644 index 0000000..678e8e6 --- /dev/null +++ b/include/drm/drm_dsc.h @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2018 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Manasi Navare <manasi.d.navare@intel.com> + */ + +#ifndef DRM_DSC_H_ +#define DRM_DSC_H_ + +#include <drm/drm_dp_helper.h> + +/* VESA Display Stream Compression DSC 1.2 constants */ +#define DSC_NUM_BUF_RANGES 15 + +/** + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set + * + * The VESA DSC standard defines picture parameter set (PPS) which display + * stream compression encoders must communicate to decoders. + * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in + * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. + * The PPS fields that span over more than a byte should be stored in Big Endian + * format. + */ +struct picture_parameter_set { + /** + * @dsc_version: + * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC + * PPS0[7:4] - dsc_version_major: Contains major version of DSC + */ + u8 dsc_version; + /** + * @pps_identifier: + * PPS1[7:0] - Application specific identifier that can be + * used to differentiate between different PPS tables. + */ + u8 pps_identifier; + /** + * @pps_reserved: + * PPS2[7:0]- RESERVED Byte + */ + u8 pps_reserved; + /** + * @pps_3: + * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to + * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, + * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, + * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. + * PPS3[7:4] - bits_per_component: Bits per component for the original + * pixels of the encoded picture. + * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) + * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also + * allowed only when dsc_minor_version = 0x2) + */ + u8 pps_3; + /** + * @pps_4: + * PPS4[1:0] -These are the most significant 2 bits of + * compressed BPP bits_per_pixel[9:0] syntax element. + * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled + * PPS4[3] - simple_422: Indicates if decoder drops samples to + * reconstruct the 4:2:2 picture. + * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is + * active. + * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any + * groups in picture + * PPS4[7:6] - Reseved bits + */ + u8 pps_4; + /** + * @bits_per_pixel_low: + * PPS5[7:0] - This indicates the lower significant 8 bits of + * the compressed BPP bits_per_pixel[9:0] element. + */ + u8 bits_per_pixel_low; + /** + * @pic_height: + * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows + * within the raster. + */ + __be16 pic_height; + /** + * @pic_width: + * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within + * the raster. + */ + __be16 pic_width; + /** + * @slice_height: + * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. + */ + __be16 slice_height; + /** + * @slice_width: + * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. + */ + __be16 slice_width; + /** + * @chunk_size: + * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks + * that are used for slice multiplexing. + */ + __be16 chunk_size; + /** + * @initial_xmit_delay_high: + * PPS16[1:0] - Most Significant two bits of initial transmission delay. + * It specifies the number of pixel times that the encoder waits before + * transmitting data from its rate buffer. + * PPS16[7:2] - Reserved + */ + u8 initial_xmit_delay_high; + /** + * @initial_xmit_delay_low: + * PPS17[7:0] - Least significant 8 bits of initial transmission delay. + */ + u8 initial_xmit_delay_low; + /** + * @initial_dec_delay: + * + * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number + * of pixel times that the decoder accumulates data in its rate buffer + * before starting to decode and output pixels. + */ + __be16 initial_dec_delay; + /** + * @pps20_reserved: + * + * PPS20[7:0] - Reserved + */ + u8 pps20_reserved; + /** + * @initial_scale_value: + * PPS21[5:0] - Initial rcXformScale factor used at beginning + * of a slice. + * PPS21[7:6] - Reserved + */ + u8 initial_scale_value; + /** + * @scale_increment_interval: + * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing + * the rcXformScale factor at end of a slice. + */ + __be16 scale_increment_interval; + /** + * @scale_decrement_interval_high: + * PPS24[3:0] - Higher 4 bits indicating number of group times between + * decrementing the rcXformScale factor at beginning of a slice. + * PPS24[7:4] - Reserved + */ + u8 scale_decrement_interval_high; + /** + * @scale_decrement_interval_low: + * PPS25[7:0] - Lower 8 bits of scale decrement interval + */ + u8 scale_decrement_interval_low; + /** + * @pps26_reserved: + * PPS26[7:0] + */ + u8 pps26_reserved; + /** + * @first_line_bpg_offset: + * PPS27[4:0] - Number of additional bits that are allocated + * for each group on first line of a slice. + * PPS27[7:5] - Reserved + */ + u8 first_line_bpg_offset; + /** + * @nfl_bpg_offset: + * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits + * deallocated for each group for groups after the first line of slice. + */ + __be16 nfl_bpg_offset; + /** + * @slice_bpg_offset: + * PPS30, PPS31[7:0] - Number of bits that are deallocated for each + * group to enforce the slice constraint. + */ + __be16 slice_bpg_offset; + /** + * @initial_offset: + * PPS32,33[7:0] - Initial value for rcXformOffset + */ + __be16 initial_offset; + /** + * @final_offset: + * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset + */ + __be16 final_offset; + /** + * @flatness_min_qp: + * PPS36[4:0] - Minimum QP at which flatness is signaled and + * flatness QP adjustment is made. + * PPS36[7:5] - Reserved + */ + u8 flatness_min_qp; + /** + * @flatness_max_qp: + * PPS37[4:0] - Max QP at which flatness is signalled and + * the flatness adjustment is made. + * PPS37[7:5] - Reserved + */ + u8 flatness_max_qp; + /** + * @rc_model_size: + * PPS38,39[7:0] - Number of bits within RC Model. + */ + __be16 rc_model_size; + /** + * @rc_edge_factor: + * PPS40[3:0] - Ratio of current activity vs, previous + * activity to determine presence of edge. + * PPS40[7:4] - Reserved + */ + u8 rc_edge_factor; + /** + * @rc_quant_incr_limit0: + * PPS41[4:0] - QP threshold used in short term RC + * PPS41[7:5] - Reserved + */ + u8 rc_quant_incr_limit0; + /** + * @rc_quant_incr_limit1: + * PPS42[4:0] - QP threshold used in short term RC + * PPS42[7:5] - Reserved + */ + u8 rc_quant_incr_limit1; + /** + * @rc_tgt_offset: + * PPS43[3:0] - Lower end of the variability range around the target + * bits per group that is allowed by short term RC. + * PPS43[7:4]- Upper end of the variability range around the target + * bits per group that i allowed by short term rc. + */ + u8 rc_tgt_offset; + /** + * @rc_buf_thresh: + * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for + * the 15 ranges defined by 14 thresholds. + */ + u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; + /** + * @rc_range_parameters: + * PPS58[7:0] - PPS87[7:0] + * Parameters that correspond to each of the 15 ranges. + */ + __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; + /** + * @native_422_420: + * PPS88[0] - 0 = Native 4:2:2 not used + * 1 = Native 4:2:2 used + * PPS88[1] - 0 = Native 4:2:0 not use + * 1 = Native 4:2:0 used + * PPS88[7:2] - Reserved 6 bits + */ + u8 native_422_420; + /** + * @second_line_bpg_offset: + * PPS89[4:0] - Additional bits/group budget for the + * second line of a slice in Native 4:2:0 mode. + * Set to 0 if DSC minor version is 1 or native420 is 0. + * PPS89[7:5] - Reserved + */ + u8 second_line_bpg_offset; + /** + * @nsl_bpg_offset: + * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated + * for each group that is not in the second line of a slice. + */ + __be16 nsl_bpg_offset; + /** + * @second_line_offset_adj: + * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second + * line in Native 4:2:0 mode. + */ + __be16 second_line_offset_adj; + /** + * @pps_long_94_reserved: + * PPS 94, 95, 96, 97 - Reserved + */ + u32 pps_long_94_reserved; + /** + * @pps_long_98_reserved: + * PPS 98, 99, 100, 101 - Reserved + */ + u32 pps_long_98_reserved; + /** + * @pps_long_102_reserved: + * PPS 102, 103, 104, 105 - Reserved + */ + u32 pps_long_102_reserved; + /** + * @pps_long_106_reserved: + * PPS 106, 107, 108, 109 - reserved + */ + u32 pps_long_106_reserved; + /** + * @pps_long_110_reserved: + * PPS 110, 111, 112, 113 - reserved + */ + u32 pps_long_110_reserved; + /** + * @pps_long_114_reserved: + * PPS 114 - 117 - reserved + */ + u32 pps_long_114_reserved; + /** + * @pps_long_118_reserved: + * PPS 118 - 121 - reserved + */ + u32 pps_long_118_reserved; + /** + * @pps_long_122_reserved: + * PPS 122- 125 - reserved + */ + u32 pps_long_122_reserved; + /** + * @pps_short_126_reserved: + * PPS 126, 127 - reserved + */ + __be16 pps_short_126_reserved; +}; + +/** + * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter + * Set Metadata + * + * This structure represents the DSC PPS infoframe required to send the Picture + * Parameter Set metadata required before enabling VESA Display Stream + * Compression. This is based on the DP Secondary Data Packet structure and + * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload. + * + * @pps_header: + * + * Header for PPS as per DP SDP header format + * + * @pps_payload: + * + * PPS payload fields as per DSC specification Table 4-1 + */ +struct drm_dsc_pps_infoframe { + struct dp_sdp_header pps_header; + struct picture_parameter_set pps_payload; +} __packed; + +#endif /* _DRM_DSC_H_ */ -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe 2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare @ 2018-08-17 19:31 ` Srivatsa, Anusha 2018-08-23 20:08 ` Manasi Navare 2018-08-23 19:40 ` Harry Wentland 1 sibling, 1 reply; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-17 19:31 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx; +Cc: Harry Wentland, dri-devel This patch needs to now incorporate the newly added slice_row_per_frame parameter in PPS_16. Anusha >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K ><gaurav.k.singh@intel.com>; dri-devel@lists.freedesktop.org; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Harry Wentland ><harry.wentland@amd.com> >Subject: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS >infoframe > >This patch defines a new header file for all the DSC 1.2 structures and creates a >structure for PPS infoframe which will be used to send picture parameter set >secondary data packet for display stream compression. >All the PPS infoframe syntax elements are taken from DSC 1.2 specification from >VESA. > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Cc: dri-devel@lists.freedesktop.org >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Cc: Harry Wentland <harry.wentland@amd.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> >--- > include/drm/drm_dsc.h | 365 >++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 365 insertions(+) > create mode 100644 include/drm/drm_dsc.h > >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h new file mode >100644 index 0000000..678e8e6 >--- /dev/null >+++ b/include/drm/drm_dsc.h >@@ -0,0 +1,365 @@ >+/* >+ * Copyright (C) 2018 Intel Corp. >+ * >+ * Permission is hereby granted, free of charge, to any person >+obtaining a >+ * copy of this software and associated documentation files (the >+"Software"), >+ * to deal in the Software without restriction, including without >+limitation >+ * the rights to use, copy, modify, merge, publish, distribute, >+sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom >+the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be >+included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >+EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >+MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO >EVENT >+SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, >+DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR >+OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE >USE >+OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: >+ * Manasi Navare <manasi.d.navare@intel.com> */ >+ >+#ifndef DRM_DSC_H_ >+#define DRM_DSC_H_ >+ >+#include <drm/drm_dp_helper.h> >+ >+/* VESA Display Stream Compression DSC 1.2 constants */ >+#define DSC_NUM_BUF_RANGES 15 >+ >+/** >+ * struct picture_parameter_set - Represents 128 bytes of Picture >+Parameter Set >+ * >+ * The VESA DSC standard defines picture parameter set (PPS) which >+display >+ * stream compression encoders must communicate to decoders. >+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The >+fields in >+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. >+ * The PPS fields that span over more than a byte should be stored in >+Big Endian >+ * format. >+ */ >+struct picture_parameter_set { >+ /** >+ * @dsc_version: >+ * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC >+ * PPS0[7:4] - dsc_version_major: Contains major version of DSC >+ */ >+ u8 dsc_version; >+ /** >+ * @pps_identifier: >+ * PPS1[7:0] - Application specific identifier that can be >+ * used to differentiate between different PPS tables. >+ */ >+ u8 pps_identifier; >+ /** >+ * @pps_reserved: >+ * PPS2[7:0]- RESERVED Byte >+ */ >+ u8 pps_reserved; >+ /** >+ * @pps_3: >+ * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to >+ * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, >+ * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, >+ * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. >+ * PPS3[7:4] - bits_per_component: Bits per component for the original >+ * pixels of the encoded picture. >+ * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) >+ * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also >+ * allowed only when dsc_minor_version = 0x2) >+ */ >+ u8 pps_3; >+ /** >+ * @pps_4: >+ * PPS4[1:0] -These are the most significant 2 bits of >+ * compressed BPP bits_per_pixel[9:0] syntax element. >+ * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled >+ * PPS4[3] - simple_422: Indicates if decoder drops samples to >+ * reconstruct the 4:2:2 picture. >+ * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is >+ * active. >+ * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any >+ * groups in picture >+ * PPS4[7:6] - Reseved bits >+ */ >+ u8 pps_4; >+ /** >+ * @bits_per_pixel_low: >+ * PPS5[7:0] - This indicates the lower significant 8 bits of >+ * the compressed BPP bits_per_pixel[9:0] element. >+ */ >+ u8 bits_per_pixel_low; >+ /** >+ * @pic_height: >+ * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows >+ * within the raster. >+ */ >+ __be16 pic_height; >+ /** >+ * @pic_width: >+ * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within >+ * the raster. >+ */ >+ __be16 pic_width; >+ /** >+ * @slice_height: >+ * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. >+ */ >+ __be16 slice_height; >+ /** >+ * @slice_width: >+ * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. >+ */ >+ __be16 slice_width; >+ /** >+ * @chunk_size: >+ * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks >+ * that are used for slice multiplexing. >+ */ >+ __be16 chunk_size; >+ /** >+ * @initial_xmit_delay_high: >+ * PPS16[1:0] - Most Significant two bits of initial transmission delay. >+ * It specifies the number of pixel times that the encoder waits before >+ * transmitting data from its rate buffer. >+ * PPS16[7:2] - Reserved >+ */ >+ u8 initial_xmit_delay_high; >+ /** >+ * @initial_xmit_delay_low: >+ * PPS17[7:0] - Least significant 8 bits of initial transmission delay. >+ */ >+ u8 initial_xmit_delay_low; >+ /** >+ * @initial_dec_delay: >+ * >+ * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number >+ * of pixel times that the decoder accumulates data in its rate buffer >+ * before starting to decode and output pixels. >+ */ >+ __be16 initial_dec_delay; >+ /** >+ * @pps20_reserved: >+ * >+ * PPS20[7:0] - Reserved >+ */ >+ u8 pps20_reserved; >+ /** >+ * @initial_scale_value: >+ * PPS21[5:0] - Initial rcXformScale factor used at beginning >+ * of a slice. >+ * PPS21[7:6] - Reserved >+ */ >+ u8 initial_scale_value; >+ /** >+ * @scale_increment_interval: >+ * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing >+ * the rcXformScale factor at end of a slice. >+ */ >+ __be16 scale_increment_interval; >+ /** >+ * @scale_decrement_interval_high: >+ * PPS24[3:0] - Higher 4 bits indicating number of group times between >+ * decrementing the rcXformScale factor at beginning of a slice. >+ * PPS24[7:4] - Reserved >+ */ >+ u8 scale_decrement_interval_high; >+ /** >+ * @scale_decrement_interval_low: >+ * PPS25[7:0] - Lower 8 bits of scale decrement interval >+ */ >+ u8 scale_decrement_interval_low; >+ /** >+ * @pps26_reserved: >+ * PPS26[7:0] >+ */ >+ u8 pps26_reserved; >+ /** >+ * @first_line_bpg_offset: >+ * PPS27[4:0] - Number of additional bits that are allocated >+ * for each group on first line of a slice. >+ * PPS27[7:5] - Reserved >+ */ >+ u8 first_line_bpg_offset; >+ /** >+ * @nfl_bpg_offset: >+ * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits >+ * deallocated for each group for groups after the first line of slice. >+ */ >+ __be16 nfl_bpg_offset; >+ /** >+ * @slice_bpg_offset: >+ * PPS30, PPS31[7:0] - Number of bits that are deallocated for each >+ * group to enforce the slice constraint. >+ */ >+ __be16 slice_bpg_offset; >+ /** >+ * @initial_offset: >+ * PPS32,33[7:0] - Initial value for rcXformOffset >+ */ >+ __be16 initial_offset; >+ /** >+ * @final_offset: >+ * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset >+ */ >+ __be16 final_offset; >+ /** >+ * @flatness_min_qp: >+ * PPS36[4:0] - Minimum QP at which flatness is signaled and >+ * flatness QP adjustment is made. >+ * PPS36[7:5] - Reserved >+ */ >+ u8 flatness_min_qp; >+ /** >+ * @flatness_max_qp: >+ * PPS37[4:0] - Max QP at which flatness is signalled and >+ * the flatness adjustment is made. >+ * PPS37[7:5] - Reserved >+ */ >+ u8 flatness_max_qp; >+ /** >+ * @rc_model_size: >+ * PPS38,39[7:0] - Number of bits within RC Model. >+ */ >+ __be16 rc_model_size; >+ /** >+ * @rc_edge_factor: >+ * PPS40[3:0] - Ratio of current activity vs, previous >+ * activity to determine presence of edge. >+ * PPS40[7:4] - Reserved >+ */ >+ u8 rc_edge_factor; >+ /** >+ * @rc_quant_incr_limit0: >+ * PPS41[4:0] - QP threshold used in short term RC >+ * PPS41[7:5] - Reserved >+ */ >+ u8 rc_quant_incr_limit0; >+ /** >+ * @rc_quant_incr_limit1: >+ * PPS42[4:0] - QP threshold used in short term RC >+ * PPS42[7:5] - Reserved >+ */ >+ u8 rc_quant_incr_limit1; >+ /** >+ * @rc_tgt_offset: >+ * PPS43[3:0] - Lower end of the variability range around the target >+ * bits per group that is allowed by short term RC. >+ * PPS43[7:4]- Upper end of the variability range around the target >+ * bits per group that i allowed by short term rc. >+ */ >+ u8 rc_tgt_offset; >+ /** >+ * @rc_buf_thresh: >+ * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for >+ * the 15 ranges defined by 14 thresholds. >+ */ >+ u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; >+ /** >+ * @rc_range_parameters: >+ * PPS58[7:0] - PPS87[7:0] >+ * Parameters that correspond to each of the 15 ranges. >+ */ >+ __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; >+ /** >+ * @native_422_420: >+ * PPS88[0] - 0 = Native 4:2:2 not used >+ * 1 = Native 4:2:2 used >+ * PPS88[1] - 0 = Native 4:2:0 not use >+ * 1 = Native 4:2:0 used >+ * PPS88[7:2] - Reserved 6 bits >+ */ >+ u8 native_422_420; >+ /** >+ * @second_line_bpg_offset: >+ * PPS89[4:0] - Additional bits/group budget for the >+ * second line of a slice in Native 4:2:0 mode. >+ * Set to 0 if DSC minor version is 1 or native420 is 0. >+ * PPS89[7:5] - Reserved >+ */ >+ u8 second_line_bpg_offset; >+ /** >+ * @nsl_bpg_offset: >+ * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated >+ * for each group that is not in the second line of a slice. >+ */ >+ __be16 nsl_bpg_offset; >+ /** >+ * @second_line_offset_adj: >+ * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second >+ * line in Native 4:2:0 mode. >+ */ >+ __be16 second_line_offset_adj; >+ /** >+ * @pps_long_94_reserved: >+ * PPS 94, 95, 96, 97 - Reserved >+ */ >+ u32 pps_long_94_reserved; >+ /** >+ * @pps_long_98_reserved: >+ * PPS 98, 99, 100, 101 - Reserved >+ */ >+ u32 pps_long_98_reserved; >+ /** >+ * @pps_long_102_reserved: >+ * PPS 102, 103, 104, 105 - Reserved >+ */ >+ u32 pps_long_102_reserved; >+ /** >+ * @pps_long_106_reserved: >+ * PPS 106, 107, 108, 109 - reserved >+ */ >+ u32 pps_long_106_reserved; >+ /** >+ * @pps_long_110_reserved: >+ * PPS 110, 111, 112, 113 - reserved >+ */ >+ u32 pps_long_110_reserved; >+ /** >+ * @pps_long_114_reserved: >+ * PPS 114 - 117 - reserved >+ */ >+ u32 pps_long_114_reserved; >+ /** >+ * @pps_long_118_reserved: >+ * PPS 118 - 121 - reserved >+ */ >+ u32 pps_long_118_reserved; >+ /** >+ * @pps_long_122_reserved: >+ * PPS 122- 125 - reserved >+ */ >+ u32 pps_long_122_reserved; >+ /** >+ * @pps_short_126_reserved: >+ * PPS 126, 127 - reserved >+ */ >+ __be16 pps_short_126_reserved; >+}; >+ >+/** >+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture >+Parameter >+ * Set Metadata >+ * >+ * This structure represents the DSC PPS infoframe required to send the >+Picture >+ * Parameter Set metadata required before enabling VESA Display Stream >+ * Compression. This is based on the DP Secondary Data Packet structure >+and >+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload. >+ * >+ * @pps_header: >+ * >+ * Header for PPS as per DP SDP header format >+ * >+ * @pps_payload: >+ * >+ * PPS payload fields as per DSC specification Table 4-1 */ struct >+drm_dsc_pps_infoframe { >+ struct dp_sdp_header pps_header; >+ struct picture_parameter_set pps_payload; } __packed; >+ >+#endif /* _DRM_DSC_H_ */ >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe 2018-08-17 19:31 ` Srivatsa, Anusha @ 2018-08-23 20:08 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-23 20:08 UTC (permalink / raw) To: Srivatsa, Anusha; +Cc: intel-gfx, dri-devel, Singh, Gaurav K On Fri, Aug 17, 2018 at 12:31:51PM -0700, Srivatsa, Anusha wrote: > This patch needs to now incorporate the newly added slice_row_per_frame parameter in PPS_16. Nope, the slice_row_per_frame and slice_per_line are only required to configure PPS on the source side. They are not DSC spec related PPS parameters. Manasi > > Anusha > > >-----Original Message----- > >From: Navare, Manasi D > >Sent: Tuesday, July 31, 2018 2:07 PM > >To: intel-gfx@lists.freedesktop.org > >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K > ><gaurav.k.singh@intel.com>; dri-devel@lists.freedesktop.org; Jani Nikula > ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; > >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Harry Wentland > ><harry.wentland@amd.com> > >Subject: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS > >infoframe > > > >This patch defines a new header file for all the DSC 1.2 structures and creates a > >structure for PPS infoframe which will be used to send picture parameter set > >secondary data packet for display stream compression. > >All the PPS infoframe syntax elements are taken from DSC 1.2 specification from > >VESA. > > > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > >Cc: dri-devel@lists.freedesktop.org > >Cc: Jani Nikula <jani.nikula@linux.intel.com> > >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > >Cc: Harry Wentland <harry.wentland@amd.com> > >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > >--- > > include/drm/drm_dsc.h | 365 > >++++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 365 insertions(+) > > create mode 100644 include/drm/drm_dsc.h > > > >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h new file mode > >100644 index 0000000..678e8e6 > >--- /dev/null > >+++ b/include/drm/drm_dsc.h > >@@ -0,0 +1,365 @@ > >+/* > >+ * Copyright (C) 2018 Intel Corp. > >+ * > >+ * Permission is hereby granted, free of charge, to any person > >+obtaining a > >+ * copy of this software and associated documentation files (the > >+"Software"), > >+ * to deal in the Software without restriction, including without > >+limitation > >+ * the rights to use, copy, modify, merge, publish, distribute, > >+sublicense, > >+ * and/or sell copies of the Software, and to permit persons to whom > >+the > >+ * Software is furnished to do so, subject to the following conditions: > >+ * > >+ * The above copyright notice and this permission notice shall be > >+included in > >+ * all copies or substantial portions of the Software. > >+ * > >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > >+EXPRESS OR > >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > >+MERCHANTABILITY, > >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO > >EVENT > >+SHALL > >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, > >+DAMAGES OR > >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR > >+OTHERWISE, > >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE > >USE > >+OR > >+ * OTHER DEALINGS IN THE SOFTWARE. > >+ * > >+ * Authors: > >+ * Manasi Navare <manasi.d.navare@intel.com> */ > >+ > >+#ifndef DRM_DSC_H_ > >+#define DRM_DSC_H_ > >+ > >+#include <drm/drm_dp_helper.h> > >+ > >+/* VESA Display Stream Compression DSC 1.2 constants */ > >+#define DSC_NUM_BUF_RANGES 15 > >+ > >+/** > >+ * struct picture_parameter_set - Represents 128 bytes of Picture > >+Parameter Set > >+ * > >+ * The VESA DSC standard defines picture parameter set (PPS) which > >+display > >+ * stream compression encoders must communicate to decoders. > >+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The > >+fields in > >+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. > >+ * The PPS fields that span over more than a byte should be stored in > >+Big Endian > >+ * format. > >+ */ > >+struct picture_parameter_set { > >+ /** > >+ * @dsc_version: > >+ * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC > >+ * PPS0[7:4] - dsc_version_major: Contains major version of DSC > >+ */ > >+ u8 dsc_version; > >+ /** > >+ * @pps_identifier: > >+ * PPS1[7:0] - Application specific identifier that can be > >+ * used to differentiate between different PPS tables. > >+ */ > >+ u8 pps_identifier; > >+ /** > >+ * @pps_reserved: > >+ * PPS2[7:0]- RESERVED Byte > >+ */ > >+ u8 pps_reserved; > >+ /** > >+ * @pps_3: > >+ * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to > >+ * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, > >+ * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, > >+ * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. > >+ * PPS3[7:4] - bits_per_component: Bits per component for the original > >+ * pixels of the encoded picture. > >+ * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) > >+ * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also > >+ * allowed only when dsc_minor_version = 0x2) > >+ */ > >+ u8 pps_3; > >+ /** > >+ * @pps_4: > >+ * PPS4[1:0] -These are the most significant 2 bits of > >+ * compressed BPP bits_per_pixel[9:0] syntax element. > >+ * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled > >+ * PPS4[3] - simple_422: Indicates if decoder drops samples to > >+ * reconstruct the 4:2:2 picture. > >+ * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is > >+ * active. > >+ * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any > >+ * groups in picture > >+ * PPS4[7:6] - Reseved bits > >+ */ > >+ u8 pps_4; > >+ /** > >+ * @bits_per_pixel_low: > >+ * PPS5[7:0] - This indicates the lower significant 8 bits of > >+ * the compressed BPP bits_per_pixel[9:0] element. > >+ */ > >+ u8 bits_per_pixel_low; > >+ /** > >+ * @pic_height: > >+ * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows > >+ * within the raster. > >+ */ > >+ __be16 pic_height; > >+ /** > >+ * @pic_width: > >+ * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within > >+ * the raster. > >+ */ > >+ __be16 pic_width; > >+ /** > >+ * @slice_height: > >+ * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. > >+ */ > >+ __be16 slice_height; > >+ /** > >+ * @slice_width: > >+ * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. > >+ */ > >+ __be16 slice_width; > >+ /** > >+ * @chunk_size: > >+ * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks > >+ * that are used for slice multiplexing. > >+ */ > >+ __be16 chunk_size; > >+ /** > >+ * @initial_xmit_delay_high: > >+ * PPS16[1:0] - Most Significant two bits of initial transmission delay. > >+ * It specifies the number of pixel times that the encoder waits before > >+ * transmitting data from its rate buffer. > >+ * PPS16[7:2] - Reserved > >+ */ > >+ u8 initial_xmit_delay_high; > >+ /** > >+ * @initial_xmit_delay_low: > >+ * PPS17[7:0] - Least significant 8 bits of initial transmission delay. > >+ */ > >+ u8 initial_xmit_delay_low; > >+ /** > >+ * @initial_dec_delay: > >+ * > >+ * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number > >+ * of pixel times that the decoder accumulates data in its rate buffer > >+ * before starting to decode and output pixels. > >+ */ > >+ __be16 initial_dec_delay; > >+ /** > >+ * @pps20_reserved: > >+ * > >+ * PPS20[7:0] - Reserved > >+ */ > >+ u8 pps20_reserved; > >+ /** > >+ * @initial_scale_value: > >+ * PPS21[5:0] - Initial rcXformScale factor used at beginning > >+ * of a slice. > >+ * PPS21[7:6] - Reserved > >+ */ > >+ u8 initial_scale_value; > >+ /** > >+ * @scale_increment_interval: > >+ * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing > >+ * the rcXformScale factor at end of a slice. > >+ */ > >+ __be16 scale_increment_interval; > >+ /** > >+ * @scale_decrement_interval_high: > >+ * PPS24[3:0] - Higher 4 bits indicating number of group times between > >+ * decrementing the rcXformScale factor at beginning of a slice. > >+ * PPS24[7:4] - Reserved > >+ */ > >+ u8 scale_decrement_interval_high; > >+ /** > >+ * @scale_decrement_interval_low: > >+ * PPS25[7:0] - Lower 8 bits of scale decrement interval > >+ */ > >+ u8 scale_decrement_interval_low; > >+ /** > >+ * @pps26_reserved: > >+ * PPS26[7:0] > >+ */ > >+ u8 pps26_reserved; > >+ /** > >+ * @first_line_bpg_offset: > >+ * PPS27[4:0] - Number of additional bits that are allocated > >+ * for each group on first line of a slice. > >+ * PPS27[7:5] - Reserved > >+ */ > >+ u8 first_line_bpg_offset; > >+ /** > >+ * @nfl_bpg_offset: > >+ * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits > >+ * deallocated for each group for groups after the first line of slice. > >+ */ > >+ __be16 nfl_bpg_offset; > >+ /** > >+ * @slice_bpg_offset: > >+ * PPS30, PPS31[7:0] - Number of bits that are deallocated for each > >+ * group to enforce the slice constraint. > >+ */ > >+ __be16 slice_bpg_offset; > >+ /** > >+ * @initial_offset: > >+ * PPS32,33[7:0] - Initial value for rcXformOffset > >+ */ > >+ __be16 initial_offset; > >+ /** > >+ * @final_offset: > >+ * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset > >+ */ > >+ __be16 final_offset; > >+ /** > >+ * @flatness_min_qp: > >+ * PPS36[4:0] - Minimum QP at which flatness is signaled and > >+ * flatness QP adjustment is made. > >+ * PPS36[7:5] - Reserved > >+ */ > >+ u8 flatness_min_qp; > >+ /** > >+ * @flatness_max_qp: > >+ * PPS37[4:0] - Max QP at which flatness is signalled and > >+ * the flatness adjustment is made. > >+ * PPS37[7:5] - Reserved > >+ */ > >+ u8 flatness_max_qp; > >+ /** > >+ * @rc_model_size: > >+ * PPS38,39[7:0] - Number of bits within RC Model. > >+ */ > >+ __be16 rc_model_size; > >+ /** > >+ * @rc_edge_factor: > >+ * PPS40[3:0] - Ratio of current activity vs, previous > >+ * activity to determine presence of edge. > >+ * PPS40[7:4] - Reserved > >+ */ > >+ u8 rc_edge_factor; > >+ /** > >+ * @rc_quant_incr_limit0: > >+ * PPS41[4:0] - QP threshold used in short term RC > >+ * PPS41[7:5] - Reserved > >+ */ > >+ u8 rc_quant_incr_limit0; > >+ /** > >+ * @rc_quant_incr_limit1: > >+ * PPS42[4:0] - QP threshold used in short term RC > >+ * PPS42[7:5] - Reserved > >+ */ > >+ u8 rc_quant_incr_limit1; > >+ /** > >+ * @rc_tgt_offset: > >+ * PPS43[3:0] - Lower end of the variability range around the target > >+ * bits per group that is allowed by short term RC. > >+ * PPS43[7:4]- Upper end of the variability range around the target > >+ * bits per group that i allowed by short term rc. > >+ */ > >+ u8 rc_tgt_offset; > >+ /** > >+ * @rc_buf_thresh: > >+ * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for > >+ * the 15 ranges defined by 14 thresholds. > >+ */ > >+ u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; > >+ /** > >+ * @rc_range_parameters: > >+ * PPS58[7:0] - PPS87[7:0] > >+ * Parameters that correspond to each of the 15 ranges. > >+ */ > >+ __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; > >+ /** > >+ * @native_422_420: > >+ * PPS88[0] - 0 = Native 4:2:2 not used > >+ * 1 = Native 4:2:2 used > >+ * PPS88[1] - 0 = Native 4:2:0 not use > >+ * 1 = Native 4:2:0 used > >+ * PPS88[7:2] - Reserved 6 bits > >+ */ > >+ u8 native_422_420; > >+ /** > >+ * @second_line_bpg_offset: > >+ * PPS89[4:0] - Additional bits/group budget for the > >+ * second line of a slice in Native 4:2:0 mode. > >+ * Set to 0 if DSC minor version is 1 or native420 is 0. > >+ * PPS89[7:5] - Reserved > >+ */ > >+ u8 second_line_bpg_offset; > >+ /** > >+ * @nsl_bpg_offset: > >+ * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated > >+ * for each group that is not in the second line of a slice. > >+ */ > >+ __be16 nsl_bpg_offset; > >+ /** > >+ * @second_line_offset_adj: > >+ * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second > >+ * line in Native 4:2:0 mode. > >+ */ > >+ __be16 second_line_offset_adj; > >+ /** > >+ * @pps_long_94_reserved: > >+ * PPS 94, 95, 96, 97 - Reserved > >+ */ > >+ u32 pps_long_94_reserved; > >+ /** > >+ * @pps_long_98_reserved: > >+ * PPS 98, 99, 100, 101 - Reserved > >+ */ > >+ u32 pps_long_98_reserved; > >+ /** > >+ * @pps_long_102_reserved: > >+ * PPS 102, 103, 104, 105 - Reserved > >+ */ > >+ u32 pps_long_102_reserved; > >+ /** > >+ * @pps_long_106_reserved: > >+ * PPS 106, 107, 108, 109 - reserved > >+ */ > >+ u32 pps_long_106_reserved; > >+ /** > >+ * @pps_long_110_reserved: > >+ * PPS 110, 111, 112, 113 - reserved > >+ */ > >+ u32 pps_long_110_reserved; > >+ /** > >+ * @pps_long_114_reserved: > >+ * PPS 114 - 117 - reserved > >+ */ > >+ u32 pps_long_114_reserved; > >+ /** > >+ * @pps_long_118_reserved: > >+ * PPS 118 - 121 - reserved > >+ */ > >+ u32 pps_long_118_reserved; > >+ /** > >+ * @pps_long_122_reserved: > >+ * PPS 122- 125 - reserved > >+ */ > >+ u32 pps_long_122_reserved; > >+ /** > >+ * @pps_short_126_reserved: > >+ * PPS 126, 127 - reserved > >+ */ > >+ __be16 pps_short_126_reserved; > >+}; > >+ > >+/** > >+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture > >+Parameter > >+ * Set Metadata > >+ * > >+ * This structure represents the DSC PPS infoframe required to send the > >+Picture > >+ * Parameter Set metadata required before enabling VESA Display Stream > >+ * Compression. This is based on the DP Secondary Data Packet structure > >+and > >+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload. > >+ * > >+ * @pps_header: > >+ * > >+ * Header for PPS as per DP SDP header format > >+ * > >+ * @pps_payload: > >+ * > >+ * PPS payload fields as per DSC specification Table 4-1 */ struct > >+drm_dsc_pps_infoframe { > >+ struct dp_sdp_header pps_header; > >+ struct picture_parameter_set pps_payload; } __packed; > >+ > >+#endif /* _DRM_DSC_H_ */ > >-- > >2.7.4 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe 2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare 2018-08-17 19:31 ` Srivatsa, Anusha @ 2018-08-23 19:40 ` Harry Wentland 2018-08-23 20:12 ` Manasi Navare 1 sibling, 1 reply; 73+ messages in thread From: Harry Wentland @ 2018-08-23 19:40 UTC (permalink / raw) To: Manasi Navare, intel-gfx; +Cc: dri-devel On 2018-07-31 05:07 PM, Manasi Navare wrote: > This patch defines a new header file for all the DSC 1.2 structures > and creates a structure for PPS infoframe which will be used to send > picture parameter set secondary data packet for display stream compression. > All the PPS infoframe syntax elements are taken from DSC 1.2 specification > from VESA. > > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > Cc: dri-devel@lists.freedesktop.org > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Harry Wentland <harry.wentland@amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Looks like this version basically removes the bitfield definitions and adds those in the comments, compared to the review in May. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Harry > --- > include/drm/drm_dsc.h | 365 ++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 365 insertions(+) > create mode 100644 include/drm/drm_dsc.h > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > new file mode 100644 > index 0000000..678e8e6 > --- /dev/null > +++ b/include/drm/drm_dsc.h > @@ -0,0 +1,365 @@ > +/* > + * Copyright (C) 2018 Intel Corp. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + * Authors: > + * Manasi Navare <manasi.d.navare@intel.com> > + */ > + > +#ifndef DRM_DSC_H_ > +#define DRM_DSC_H_ > + > +#include <drm/drm_dp_helper.h> > + > +/* VESA Display Stream Compression DSC 1.2 constants */ > +#define DSC_NUM_BUF_RANGES 15 > + > +/** > + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set > + * > + * The VESA DSC standard defines picture parameter set (PPS) which display > + * stream compression encoders must communicate to decoders. > + * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in > + * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. > + * The PPS fields that span over more than a byte should be stored in Big Endian > + * format. > + */ > +struct picture_parameter_set { > + /** > + * @dsc_version: > + * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC > + * PPS0[7:4] - dsc_version_major: Contains major version of DSC > + */ > + u8 dsc_version; > + /** > + * @pps_identifier: > + * PPS1[7:0] - Application specific identifier that can be > + * used to differentiate between different PPS tables. > + */ > + u8 pps_identifier; > + /** > + * @pps_reserved: > + * PPS2[7:0]- RESERVED Byte > + */ > + u8 pps_reserved; > + /** > + * @pps_3: > + * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to > + * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, > + * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, > + * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. > + * PPS3[7:4] - bits_per_component: Bits per component for the original > + * pixels of the encoded picture. > + * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) > + * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also > + * allowed only when dsc_minor_version = 0x2) > + */ > + u8 pps_3; > + /** > + * @pps_4: > + * PPS4[1:0] -These are the most significant 2 bits of > + * compressed BPP bits_per_pixel[9:0] syntax element. > + * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled > + * PPS4[3] - simple_422: Indicates if decoder drops samples to > + * reconstruct the 4:2:2 picture. > + * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is > + * active. > + * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any > + * groups in picture > + * PPS4[7:6] - Reseved bits > + */ > + u8 pps_4; > + /** > + * @bits_per_pixel_low: > + * PPS5[7:0] - This indicates the lower significant 8 bits of > + * the compressed BPP bits_per_pixel[9:0] element. > + */ > + u8 bits_per_pixel_low; > + /** > + * @pic_height: > + * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows > + * within the raster. > + */ > + __be16 pic_height; > + /** > + * @pic_width: > + * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within > + * the raster. > + */ > + __be16 pic_width; > + /** > + * @slice_height: > + * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. > + */ > + __be16 slice_height; > + /** > + * @slice_width: > + * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. > + */ > + __be16 slice_width; > + /** > + * @chunk_size: > + * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks > + * that are used for slice multiplexing. > + */ > + __be16 chunk_size; > + /** > + * @initial_xmit_delay_high: > + * PPS16[1:0] - Most Significant two bits of initial transmission delay. > + * It specifies the number of pixel times that the encoder waits before > + * transmitting data from its rate buffer. > + * PPS16[7:2] - Reserved > + */ > + u8 initial_xmit_delay_high; > + /** > + * @initial_xmit_delay_low: > + * PPS17[7:0] - Least significant 8 bits of initial transmission delay. > + */ > + u8 initial_xmit_delay_low; > + /** > + * @initial_dec_delay: > + * > + * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number > + * of pixel times that the decoder accumulates data in its rate buffer > + * before starting to decode and output pixels. > + */ > + __be16 initial_dec_delay; > + /** > + * @pps20_reserved: > + * > + * PPS20[7:0] - Reserved > + */ > + u8 pps20_reserved; > + /** > + * @initial_scale_value: > + * PPS21[5:0] - Initial rcXformScale factor used at beginning > + * of a slice. > + * PPS21[7:6] - Reserved > + */ > + u8 initial_scale_value; > + /** > + * @scale_increment_interval: > + * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing > + * the rcXformScale factor at end of a slice. > + */ > + __be16 scale_increment_interval; > + /** > + * @scale_decrement_interval_high: > + * PPS24[3:0] - Higher 4 bits indicating number of group times between > + * decrementing the rcXformScale factor at beginning of a slice. > + * PPS24[7:4] - Reserved > + */ > + u8 scale_decrement_interval_high; > + /** > + * @scale_decrement_interval_low: > + * PPS25[7:0] - Lower 8 bits of scale decrement interval > + */ > + u8 scale_decrement_interval_low; > + /** > + * @pps26_reserved: > + * PPS26[7:0] > + */ > + u8 pps26_reserved; > + /** > + * @first_line_bpg_offset: > + * PPS27[4:0] - Number of additional bits that are allocated > + * for each group on first line of a slice. > + * PPS27[7:5] - Reserved > + */ > + u8 first_line_bpg_offset; > + /** > + * @nfl_bpg_offset: > + * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits > + * deallocated for each group for groups after the first line of slice. > + */ > + __be16 nfl_bpg_offset; > + /** > + * @slice_bpg_offset: > + * PPS30, PPS31[7:0] - Number of bits that are deallocated for each > + * group to enforce the slice constraint. > + */ > + __be16 slice_bpg_offset; > + /** > + * @initial_offset: > + * PPS32,33[7:0] - Initial value for rcXformOffset > + */ > + __be16 initial_offset; > + /** > + * @final_offset: > + * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset > + */ > + __be16 final_offset; > + /** > + * @flatness_min_qp: > + * PPS36[4:0] - Minimum QP at which flatness is signaled and > + * flatness QP adjustment is made. > + * PPS36[7:5] - Reserved > + */ > + u8 flatness_min_qp; > + /** > + * @flatness_max_qp: > + * PPS37[4:0] - Max QP at which flatness is signalled and > + * the flatness adjustment is made. > + * PPS37[7:5] - Reserved > + */ > + u8 flatness_max_qp; > + /** > + * @rc_model_size: > + * PPS38,39[7:0] - Number of bits within RC Model. > + */ > + __be16 rc_model_size; > + /** > + * @rc_edge_factor: > + * PPS40[3:0] - Ratio of current activity vs, previous > + * activity to determine presence of edge. > + * PPS40[7:4] - Reserved > + */ > + u8 rc_edge_factor; > + /** > + * @rc_quant_incr_limit0: > + * PPS41[4:0] - QP threshold used in short term RC > + * PPS41[7:5] - Reserved > + */ > + u8 rc_quant_incr_limit0; > + /** > + * @rc_quant_incr_limit1: > + * PPS42[4:0] - QP threshold used in short term RC > + * PPS42[7:5] - Reserved > + */ > + u8 rc_quant_incr_limit1; > + /** > + * @rc_tgt_offset: > + * PPS43[3:0] - Lower end of the variability range around the target > + * bits per group that is allowed by short term RC. > + * PPS43[7:4]- Upper end of the variability range around the target > + * bits per group that i allowed by short term rc. > + */ > + u8 rc_tgt_offset; > + /** > + * @rc_buf_thresh: > + * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for > + * the 15 ranges defined by 14 thresholds. > + */ > + u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; > + /** > + * @rc_range_parameters: > + * PPS58[7:0] - PPS87[7:0] > + * Parameters that correspond to each of the 15 ranges. > + */ > + __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; > + /** > + * @native_422_420: > + * PPS88[0] - 0 = Native 4:2:2 not used > + * 1 = Native 4:2:2 used > + * PPS88[1] - 0 = Native 4:2:0 not use > + * 1 = Native 4:2:0 used > + * PPS88[7:2] - Reserved 6 bits > + */ > + u8 native_422_420; > + /** > + * @second_line_bpg_offset: > + * PPS89[4:0] - Additional bits/group budget for the > + * second line of a slice in Native 4:2:0 mode. > + * Set to 0 if DSC minor version is 1 or native420 is 0. > + * PPS89[7:5] - Reserved > + */ > + u8 second_line_bpg_offset; > + /** > + * @nsl_bpg_offset: > + * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated > + * for each group that is not in the second line of a slice. > + */ > + __be16 nsl_bpg_offset; > + /** > + * @second_line_offset_adj: > + * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second > + * line in Native 4:2:0 mode. > + */ > + __be16 second_line_offset_adj; > + /** > + * @pps_long_94_reserved: > + * PPS 94, 95, 96, 97 - Reserved > + */ > + u32 pps_long_94_reserved; > + /** > + * @pps_long_98_reserved: > + * PPS 98, 99, 100, 101 - Reserved > + */ > + u32 pps_long_98_reserved; > + /** > + * @pps_long_102_reserved: > + * PPS 102, 103, 104, 105 - Reserved > + */ > + u32 pps_long_102_reserved; > + /** > + * @pps_long_106_reserved: > + * PPS 106, 107, 108, 109 - reserved > + */ > + u32 pps_long_106_reserved; > + /** > + * @pps_long_110_reserved: > + * PPS 110, 111, 112, 113 - reserved > + */ > + u32 pps_long_110_reserved; > + /** > + * @pps_long_114_reserved: > + * PPS 114 - 117 - reserved > + */ > + u32 pps_long_114_reserved; > + /** > + * @pps_long_118_reserved: > + * PPS 118 - 121 - reserved > + */ > + u32 pps_long_118_reserved; > + /** > + * @pps_long_122_reserved: > + * PPS 122- 125 - reserved > + */ > + u32 pps_long_122_reserved; > + /** > + * @pps_short_126_reserved: > + * PPS 126, 127 - reserved > + */ > + __be16 pps_short_126_reserved; > +}; > + > +/** > + * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter > + * Set Metadata > + * > + * This structure represents the DSC PPS infoframe required to send the Picture > + * Parameter Set metadata required before enabling VESA Display Stream > + * Compression. This is based on the DP Secondary Data Packet structure and > + * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload. > + * > + * @pps_header: > + * > + * Header for PPS as per DP SDP header format > + * > + * @pps_payload: > + * > + * PPS payload fields as per DSC specification Table 4-1 > + */ > +struct drm_dsc_pps_infoframe { > + struct dp_sdp_header pps_header; > + struct picture_parameter_set pps_payload; > +} __packed; > + > +#endif /* _DRM_DSC_H_ */ > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe 2018-08-23 19:40 ` Harry Wentland @ 2018-08-23 20:12 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-23 20:12 UTC (permalink / raw) To: Harry Wentland; +Cc: Anusha Srivatsa, intel-gfx, dri-devel, Gaurav K Singh Thanks for the review. And yes it just removes the bitfields in PPS since the packing of the bitfields and memory allocations are heavily dependent on HW. So we cant have them in DRM level. I will make sure to add this in version history and also add Suggested-by: jani.nikula@linux.intel.com Manasi On Thu, Aug 23, 2018 at 03:40:12PM -0400, Harry Wentland wrote: > On 2018-07-31 05:07 PM, Manasi Navare wrote: > > This patch defines a new header file for all the DSC 1.2 structures > > and creates a structure for PPS infoframe which will be used to send > > picture parameter set secondary data packet for display stream compression. > > All the PPS infoframe syntax elements are taken from DSC 1.2 specification > > from VESA. > > > > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > > Cc: dri-devel@lists.freedesktop.org > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > > Cc: Harry Wentland <harry.wentland@amd.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > Looks like this version basically removes the bitfield definitions and adds those > in the comments, compared to the review in May. > > Reviewed-by: Harry Wentland <harry.wentland@amd.com> > > Harry > > > --- > > include/drm/drm_dsc.h | 365 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 365 insertions(+) > > create mode 100644 include/drm/drm_dsc.h > > > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > > new file mode 100644 > > index 0000000..678e8e6 > > --- /dev/null > > +++ b/include/drm/drm_dsc.h > > @@ -0,0 +1,365 @@ > > +/* > > + * Copyright (C) 2018 Intel Corp. > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a > > + * copy of this software and associated documentation files (the "Software"), > > + * to deal in the Software without restriction, including without limitation > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > > + * and/or sell copies of the Software, and to permit persons to whom the > > + * Software is furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > > + * OTHER DEALINGS IN THE SOFTWARE. > > + * > > + * Authors: > > + * Manasi Navare <manasi.d.navare@intel.com> > > + */ > > + > > +#ifndef DRM_DSC_H_ > > +#define DRM_DSC_H_ > > + > > +#include <drm/drm_dp_helper.h> > > + > > +/* VESA Display Stream Compression DSC 1.2 constants */ > > +#define DSC_NUM_BUF_RANGES 15 > > + > > +/** > > + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set > > + * > > + * The VESA DSC standard defines picture parameter set (PPS) which display > > + * stream compression encoders must communicate to decoders. > > + * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in > > + * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. > > + * The PPS fields that span over more than a byte should be stored in Big Endian > > + * format. > > + */ > > +struct picture_parameter_set { > > + /** > > + * @dsc_version: > > + * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC > > + * PPS0[7:4] - dsc_version_major: Contains major version of DSC > > + */ > > + u8 dsc_version; > > + /** > > + * @pps_identifier: > > + * PPS1[7:0] - Application specific identifier that can be > > + * used to differentiate between different PPS tables. > > + */ > > + u8 pps_identifier; > > + /** > > + * @pps_reserved: > > + * PPS2[7:0]- RESERVED Byte > > + */ > > + u8 pps_reserved; > > + /** > > + * @pps_3: > > + * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to > > + * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, > > + * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, > > + * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. > > + * PPS3[7:4] - bits_per_component: Bits per component for the original > > + * pixels of the encoded picture. > > + * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) > > + * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also > > + * allowed only when dsc_minor_version = 0x2) > > + */ > > + u8 pps_3; > > + /** > > + * @pps_4: > > + * PPS4[1:0] -These are the most significant 2 bits of > > + * compressed BPP bits_per_pixel[9:0] syntax element. > > + * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled > > + * PPS4[3] - simple_422: Indicates if decoder drops samples to > > + * reconstruct the 4:2:2 picture. > > + * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is > > + * active. > > + * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any > > + * groups in picture > > + * PPS4[7:6] - Reseved bits > > + */ > > + u8 pps_4; > > + /** > > + * @bits_per_pixel_low: > > + * PPS5[7:0] - This indicates the lower significant 8 bits of > > + * the compressed BPP bits_per_pixel[9:0] element. > > + */ > > + u8 bits_per_pixel_low; > > + /** > > + * @pic_height: > > + * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows > > + * within the raster. > > + */ > > + __be16 pic_height; > > + /** > > + * @pic_width: > > + * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within > > + * the raster. > > + */ > > + __be16 pic_width; > > + /** > > + * @slice_height: > > + * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. > > + */ > > + __be16 slice_height; > > + /** > > + * @slice_width: > > + * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. > > + */ > > + __be16 slice_width; > > + /** > > + * @chunk_size: > > + * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks > > + * that are used for slice multiplexing. > > + */ > > + __be16 chunk_size; > > + /** > > + * @initial_xmit_delay_high: > > + * PPS16[1:0] - Most Significant two bits of initial transmission delay. > > + * It specifies the number of pixel times that the encoder waits before > > + * transmitting data from its rate buffer. > > + * PPS16[7:2] - Reserved > > + */ > > + u8 initial_xmit_delay_high; > > + /** > > + * @initial_xmit_delay_low: > > + * PPS17[7:0] - Least significant 8 bits of initial transmission delay. > > + */ > > + u8 initial_xmit_delay_low; > > + /** > > + * @initial_dec_delay: > > + * > > + * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number > > + * of pixel times that the decoder accumulates data in its rate buffer > > + * before starting to decode and output pixels. > > + */ > > + __be16 initial_dec_delay; > > + /** > > + * @pps20_reserved: > > + * > > + * PPS20[7:0] - Reserved > > + */ > > + u8 pps20_reserved; > > + /** > > + * @initial_scale_value: > > + * PPS21[5:0] - Initial rcXformScale factor used at beginning > > + * of a slice. > > + * PPS21[7:6] - Reserved > > + */ > > + u8 initial_scale_value; > > + /** > > + * @scale_increment_interval: > > + * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing > > + * the rcXformScale factor at end of a slice. > > + */ > > + __be16 scale_increment_interval; > > + /** > > + * @scale_decrement_interval_high: > > + * PPS24[3:0] - Higher 4 bits indicating number of group times between > > + * decrementing the rcXformScale factor at beginning of a slice. > > + * PPS24[7:4] - Reserved > > + */ > > + u8 scale_decrement_interval_high; > > + /** > > + * @scale_decrement_interval_low: > > + * PPS25[7:0] - Lower 8 bits of scale decrement interval > > + */ > > + u8 scale_decrement_interval_low; > > + /** > > + * @pps26_reserved: > > + * PPS26[7:0] > > + */ > > + u8 pps26_reserved; > > + /** > > + * @first_line_bpg_offset: > > + * PPS27[4:0] - Number of additional bits that are allocated > > + * for each group on first line of a slice. > > + * PPS27[7:5] - Reserved > > + */ > > + u8 first_line_bpg_offset; > > + /** > > + * @nfl_bpg_offset: > > + * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits > > + * deallocated for each group for groups after the first line of slice. > > + */ > > + __be16 nfl_bpg_offset; > > + /** > > + * @slice_bpg_offset: > > + * PPS30, PPS31[7:0] - Number of bits that are deallocated for each > > + * group to enforce the slice constraint. > > + */ > > + __be16 slice_bpg_offset; > > + /** > > + * @initial_offset: > > + * PPS32,33[7:0] - Initial value for rcXformOffset > > + */ > > + __be16 initial_offset; > > + /** > > + * @final_offset: > > + * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset > > + */ > > + __be16 final_offset; > > + /** > > + * @flatness_min_qp: > > + * PPS36[4:0] - Minimum QP at which flatness is signaled and > > + * flatness QP adjustment is made. > > + * PPS36[7:5] - Reserved > > + */ > > + u8 flatness_min_qp; > > + /** > > + * @flatness_max_qp: > > + * PPS37[4:0] - Max QP at which flatness is signalled and > > + * the flatness adjustment is made. > > + * PPS37[7:5] - Reserved > > + */ > > + u8 flatness_max_qp; > > + /** > > + * @rc_model_size: > > + * PPS38,39[7:0] - Number of bits within RC Model. > > + */ > > + __be16 rc_model_size; > > + /** > > + * @rc_edge_factor: > > + * PPS40[3:0] - Ratio of current activity vs, previous > > + * activity to determine presence of edge. > > + * PPS40[7:4] - Reserved > > + */ > > + u8 rc_edge_factor; > > + /** > > + * @rc_quant_incr_limit0: > > + * PPS41[4:0] - QP threshold used in short term RC > > + * PPS41[7:5] - Reserved > > + */ > > + u8 rc_quant_incr_limit0; > > + /** > > + * @rc_quant_incr_limit1: > > + * PPS42[4:0] - QP threshold used in short term RC > > + * PPS42[7:5] - Reserved > > + */ > > + u8 rc_quant_incr_limit1; > > + /** > > + * @rc_tgt_offset: > > + * PPS43[3:0] - Lower end of the variability range around the target > > + * bits per group that is allowed by short term RC. > > + * PPS43[7:4]- Upper end of the variability range around the target > > + * bits per group that i allowed by short term rc. > > + */ > > + u8 rc_tgt_offset; > > + /** > > + * @rc_buf_thresh: > > + * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for > > + * the 15 ranges defined by 14 thresholds. > > + */ > > + u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; > > + /** > > + * @rc_range_parameters: > > + * PPS58[7:0] - PPS87[7:0] > > + * Parameters that correspond to each of the 15 ranges. > > + */ > > + __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; > > + /** > > + * @native_422_420: > > + * PPS88[0] - 0 = Native 4:2:2 not used > > + * 1 = Native 4:2:2 used > > + * PPS88[1] - 0 = Native 4:2:0 not use > > + * 1 = Native 4:2:0 used > > + * PPS88[7:2] - Reserved 6 bits > > + */ > > + u8 native_422_420; > > + /** > > + * @second_line_bpg_offset: > > + * PPS89[4:0] - Additional bits/group budget for the > > + * second line of a slice in Native 4:2:0 mode. > > + * Set to 0 if DSC minor version is 1 or native420 is 0. > > + * PPS89[7:5] - Reserved > > + */ > > + u8 second_line_bpg_offset; > > + /** > > + * @nsl_bpg_offset: > > + * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated > > + * for each group that is not in the second line of a slice. > > + */ > > + __be16 nsl_bpg_offset; > > + /** > > + * @second_line_offset_adj: > > + * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second > > + * line in Native 4:2:0 mode. > > + */ > > + __be16 second_line_offset_adj; > > + /** > > + * @pps_long_94_reserved: > > + * PPS 94, 95, 96, 97 - Reserved > > + */ > > + u32 pps_long_94_reserved; > > + /** > > + * @pps_long_98_reserved: > > + * PPS 98, 99, 100, 101 - Reserved > > + */ > > + u32 pps_long_98_reserved; > > + /** > > + * @pps_long_102_reserved: > > + * PPS 102, 103, 104, 105 - Reserved > > + */ > > + u32 pps_long_102_reserved; > > + /** > > + * @pps_long_106_reserved: > > + * PPS 106, 107, 108, 109 - reserved > > + */ > > + u32 pps_long_106_reserved; > > + /** > > + * @pps_long_110_reserved: > > + * PPS 110, 111, 112, 113 - reserved > > + */ > > + u32 pps_long_110_reserved; > > + /** > > + * @pps_long_114_reserved: > > + * PPS 114 - 117 - reserved > > + */ > > + u32 pps_long_114_reserved; > > + /** > > + * @pps_long_118_reserved: > > + * PPS 118 - 121 - reserved > > + */ > > + u32 pps_long_118_reserved; > > + /** > > + * @pps_long_122_reserved: > > + * PPS 122- 125 - reserved > > + */ > > + u32 pps_long_122_reserved; > > + /** > > + * @pps_short_126_reserved: > > + * PPS 126, 127 - reserved > > + */ > > + __be16 pps_short_126_reserved; > > +}; > > + > > +/** > > + * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter > > + * Set Metadata > > + * > > + * This structure represents the DSC PPS infoframe required to send the Picture > > + * Parameter Set metadata required before enabling VESA Display Stream > > + * Compression. This is based on the DP Secondary Data Packet structure and > > + * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload. > > + * > > + * @pps_header: > > + * > > + * Header for PPS as per DP SDP header format > > + * > > + * @pps_payload: > > + * > > + * PPS payload fields as per DSC specification Table 4-1 > > + */ > > +struct drm_dsc_pps_infoframe { > > + struct dp_sdp_header pps_header; > > + struct picture_parameter_set pps_payload; > > +} __packed; > > + > > +#endif /* _DRM_DSC_H_ */ > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (6 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-23 20:01 ` Harry Wentland 2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare ` (22 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Harry Wentland From: Gaurav K Singh <gaurav.k.singh@intel.com> This defines all the DSC parameters as per the VESA DSC spec that will be required for DSC encoder/decoder v4 (From Manasi) * Add the DSC_MUX_WORD_SIZE constants (Manasi) v3 (From Manasi) * Remove the duplicate define (Suggested By:Harry Wentland) v2: Define this struct in DRM (From Manasi) * Changed the data types to u8/u16 instead of unsigned longs (Manasi) * Remove driver specific fields (Manasi) * Move this struct definition to DRM (Manasi) * Define DSC 1.2 parameters (Manasi) * Use DSC_NUM_BUF_RANGES (Manasi) * Call it drm_dsc_config (Manasi) Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> --- include/drm/drm_dsc.h | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index 678e8e6..eda323d 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -30,6 +30,116 @@ /* VESA Display Stream Compression DSC 1.2 constants */ #define DSC_NUM_BUF_RANGES 15 +#define DSC_MUX_WORD_SIZE_8_10_BPC 48 +#define DSC_MUX_WORD_SIZE_12_BPC 64 + +/* Configuration for a single Rate Control model range */ +struct dsc_rc_range_parameters { + /* Min Quantization Parameters allowed for this range */ + u8 range_min_qp; + /* Max Quantization Parameters allowed for this range */ + u8 range_max_qp; + /* Bits/group offset to apply to target for this group */ + u8 range_bpg_offset; +}; + +struct drm_dsc_config { + /* Bits / component for previous reconstructed line buffer */ + u8 line_buf_depth; + /* Bits per component to code (must be 8, 10, or 12) */ + u8 bits_per_component; + /* + * Flag indicating to do RGB - YCoCg conversion + * and back (should be 1 for RGB input) + */ + bool convert_rgb; + u8 slice_count; + /* Slice Width */ + u16 slice_width; + /* Slice Height */ + u16 slice_height; + /* + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens + * outside of DSC encode/decode algorithm) + */ + bool enable422; + /* Picture Width */ + u16 pic_width; + /* Picture Height */ + u16 pic_height; + /* Offset to bits/group used by RC to determine QP adjustment */ + u8 rc_tgt_offset_high; + /* Offset to bits/group used by RC to determine QP adjustment */ + u8 rc_tgt_offset_low; + /* Bits/pixel target << 4 (ie., 4 fractional bits) */ + u16 bits_per_pixel; + /* + * Factor to determine if an edge is present based + * on the bits produced + */ + u8 rc_edge_factor; + /* Slow down incrementing once the range reaches this value */ + u8 rc_quant_incr_limit1; + /* Slow down incrementing once the range reaches this value */ + u8 rc_quant_incr_limit0; + /* Number of pixels to delay the initial transmission */ + u16 initial_xmit_delay; + /* Number of pixels to delay the VLD on the decoder,not including SSM */ + u16 initial_dec_delay; + /* Block prediction enable */ + bool block_pred_enable; + /* Bits/group offset to use for first line of the slice */ + u8 first_line_bpg_offset; + /* Value to use for RC model offset at slice start */ + u16 initial_offset; + /* Thresholds defining each of the buffer ranges */ + u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; + /* Parameters for each of the RC ranges */ + struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; + /* Total size of RC model */ + u16 rc_model_size; + /* Minimum QP where flatness information is sent */ + u8 flatness_min_qp; + /* Maximum QP where flatness information is sent */ + u8 flatness_max_qp; + /* Initial value for scale factor */ + u8 initial_scale_value; + /* Decrement scale factor every scale_decrement_interval groups */ + u16 scale_decrement_interval; + /* Increment scale factor every scale_increment_interval groups */ + u16 scale_increment_interval; + /* Non-first line BPG offset to use */ + u16 nfl_bpg_offset; + /* BPG offset used to enforce slice bit */ + u16 slice_bpg_offset; + /* Final RC linear transformation offset value */ + u16 final_offset; + /* Enable on-off VBR (ie., disable stuffing bits) */ + bool vbr_enable; + /* Mux word size (in bits) for SSM mode */ + u8 mux_word_size; + /* + * The (max) size in bytes of the "chunks" that are + * used in slice multiplexing + */ + u16 slice_chunk_size; + /* Rate Control buffer siz in bits */ + u16 rc_bits; + /* DSC Minor Version */ + u8 dsc_version_minor; + /* DSC Major version */ + u8 dsc_version_major; + /* Native 4:2:2 support */ + bool native_422; + /* Native 4:2:0 support */ + bool native_420; + /* Additional bits/grp for seconnd line of slice for native 4:2:0 */ + u8 second_line_bpg_offset; + /* Num of bits deallocated for each grp that is not in second line of slice */ + u16 nsl_bpg_offset; + /* Offset adj fr second line in Native 4:2:0 mode */ + u16 second_line_offset_adj; +}; /** * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities 2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare @ 2018-08-23 20:01 ` Harry Wentland 2018-08-28 21:12 ` Srivatsa, Anusha 0 siblings, 1 reply; 73+ messages in thread From: Harry Wentland @ 2018-08-23 20:01 UTC (permalink / raw) To: Manasi Navare, intel-gfx; +Cc: Anusha Srivatsa, Gaurav K Singh, dri-devel On 2018-07-31 05:07 PM, Manasi Navare wrote: > From: Gaurav K Singh <gaurav.k.singh@intel.com> > > This defines all the DSC parameters as per the VESA DSC spec > that will be required for DSC encoder/decoder > > v4 (From Manasi) > * Add the DSC_MUX_WORD_SIZE constants (Manasi) > > v3 (From Manasi) > * Remove the duplicate define (Suggested By:Harry Wentland) > > v2: Define this struct in DRM (From Manasi) > * Changed the data types to u8/u16 instead of unsigned longs (Manasi) > * Remove driver specific fields (Manasi) > * Move this struct definition to DRM (Manasi) > * Define DSC 1.2 parameters (Manasi) > * Use DSC_NUM_BUF_RANGES (Manasi) > * Call it drm_dsc_config (Manasi) > > Cc: dri-devel@lists.freedesktop.org > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Harry Wentland <harry.wentland@amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Harry > --- > include/drm/drm_dsc.h | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 110 insertions(+) > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > index 678e8e6..eda323d 100644 > --- a/include/drm/drm_dsc.h > +++ b/include/drm/drm_dsc.h > @@ -30,6 +30,116 @@ > > /* VESA Display Stream Compression DSC 1.2 constants */ > #define DSC_NUM_BUF_RANGES 15 > +#define DSC_MUX_WORD_SIZE_8_10_BPC 48 > +#define DSC_MUX_WORD_SIZE_12_BPC 64 > + > +/* Configuration for a single Rate Control model range */ > +struct dsc_rc_range_parameters { > + /* Min Quantization Parameters allowed for this range */ > + u8 range_min_qp; > + /* Max Quantization Parameters allowed for this range */ > + u8 range_max_qp; > + /* Bits/group offset to apply to target for this group */ > + u8 range_bpg_offset; > +}; > + > +struct drm_dsc_config { > + /* Bits / component for previous reconstructed line buffer */ > + u8 line_buf_depth; > + /* Bits per component to code (must be 8, 10, or 12) */ > + u8 bits_per_component; > + /* > + * Flag indicating to do RGB - YCoCg conversion > + * and back (should be 1 for RGB input) > + */ > + bool convert_rgb; > + u8 slice_count; > + /* Slice Width */ > + u16 slice_width; > + /* Slice Height */ > + u16 slice_height; > + /* > + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens > + * outside of DSC encode/decode algorithm) > + */ > + bool enable422; > + /* Picture Width */ > + u16 pic_width; > + /* Picture Height */ > + u16 pic_height; > + /* Offset to bits/group used by RC to determine QP adjustment */ > + u8 rc_tgt_offset_high; > + /* Offset to bits/group used by RC to determine QP adjustment */ > + u8 rc_tgt_offset_low; > + /* Bits/pixel target << 4 (ie., 4 fractional bits) */ > + u16 bits_per_pixel; > + /* > + * Factor to determine if an edge is present based > + * on the bits produced > + */ > + u8 rc_edge_factor; > + /* Slow down incrementing once the range reaches this value */ > + u8 rc_quant_incr_limit1; > + /* Slow down incrementing once the range reaches this value */ > + u8 rc_quant_incr_limit0; > + /* Number of pixels to delay the initial transmission */ > + u16 initial_xmit_delay; > + /* Number of pixels to delay the VLD on the decoder,not including SSM */ > + u16 initial_dec_delay; > + /* Block prediction enable */ > + bool block_pred_enable; > + /* Bits/group offset to use for first line of the slice */ > + u8 first_line_bpg_offset; > + /* Value to use for RC model offset at slice start */ > + u16 initial_offset; > + /* Thresholds defining each of the buffer ranges */ > + u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; > + /* Parameters for each of the RC ranges */ > + struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; > + /* Total size of RC model */ > + u16 rc_model_size; > + /* Minimum QP where flatness information is sent */ > + u8 flatness_min_qp; > + /* Maximum QP where flatness information is sent */ > + u8 flatness_max_qp; > + /* Initial value for scale factor */ > + u8 initial_scale_value; > + /* Decrement scale factor every scale_decrement_interval groups */ > + u16 scale_decrement_interval; > + /* Increment scale factor every scale_increment_interval groups */ > + u16 scale_increment_interval; > + /* Non-first line BPG offset to use */ > + u16 nfl_bpg_offset; > + /* BPG offset used to enforce slice bit */ > + u16 slice_bpg_offset; > + /* Final RC linear transformation offset value */ > + u16 final_offset; > + /* Enable on-off VBR (ie., disable stuffing bits) */ > + bool vbr_enable; > + /* Mux word size (in bits) for SSM mode */ > + u8 mux_word_size; > + /* > + * The (max) size in bytes of the "chunks" that are > + * used in slice multiplexing > + */ > + u16 slice_chunk_size; > + /* Rate Control buffer siz in bits */ > + u16 rc_bits; > + /* DSC Minor Version */ > + u8 dsc_version_minor; > + /* DSC Major version */ > + u8 dsc_version_major; > + /* Native 4:2:2 support */ > + bool native_422; > + /* Native 4:2:0 support */ > + bool native_420; > + /* Additional bits/grp for seconnd line of slice for native 4:2:0 */ > + u8 second_line_bpg_offset; > + /* Num of bits deallocated for each grp that is not in second line of slice */ > + u16 nsl_bpg_offset; > + /* Offset adj fr second line in Native 4:2:0 mode */ > + u16 second_line_offset_adj; > +}; > > /** > * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities 2018-08-23 20:01 ` Harry Wentland @ 2018-08-28 21:12 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-28 21:12 UTC (permalink / raw) To: Harry Wentland, Navare, Manasi D, intel-gfx; +Cc: dri-devel >-----Original Message----- >From: Harry Wentland [mailto:harry.wentland@amd.com] >Sent: Thursday, August 23, 2018 1:01 PM >To: Navare, Manasi D <manasi.d.navare@intel.com>; intel- >gfx@lists.freedesktop.org >Cc: Singh, Gaurav K <gaurav.k.singh@intel.com>; dri- >devel@lists.freedesktop.org; Jani Nikula <jani.nikula@linux.intel.com>; Ville >Syrjala <ville.syrjala@linux.intel.com>; Srivatsa, Anusha ><anusha.srivatsa@intel.com> >Subject: Re: [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression >Capabilities > >On 2018-07-31 05:07 PM, Manasi Navare wrote: >> From: Gaurav K Singh <gaurav.k.singh@intel.com> >> >> This defines all the DSC parameters as per the VESA DSC spec that will >> be required for DSC encoder/decoder >> >> v4 (From Manasi) >> * Add the DSC_MUX_WORD_SIZE constants (Manasi) >> >> v3 (From Manasi) >> * Remove the duplicate define (Suggested By:Harry Wentland) >> >> v2: Define this struct in DRM (From Manasi) >> * Changed the data types to u8/u16 instead of unsigned longs (Manasi) >> * Remove driver specific fields (Manasi) >> * Move this struct definition to DRM (Manasi) >> * Define DSC 1.2 parameters (Manasi) >> * Use DSC_NUM_BUF_RANGES (Manasi) >> * Call it drm_dsc_config (Manasi) >> >> Cc: dri-devel@lists.freedesktop.org >> Cc: Jani Nikula <jani.nikula@linux.intel.com> >> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >> Cc: Harry Wentland <harry.wentland@amd.com> >> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> >> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > >Acked-by: Harry Wentland <harry.wentland@amd.com> > >Harry Double checked with the Spec, looks good. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> --- >> include/drm/drm_dsc.h | 110 >> ++++++++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 110 insertions(+) >> >> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index >> 678e8e6..eda323d 100644 >> --- a/include/drm/drm_dsc.h >> +++ b/include/drm/drm_dsc.h >> @@ -30,6 +30,116 @@ >> >> /* VESA Display Stream Compression DSC 1.2 constants */ >> #define DSC_NUM_BUF_RANGES 15 >> +#define DSC_MUX_WORD_SIZE_8_10_BPC 48 >> +#define DSC_MUX_WORD_SIZE_12_BPC 64 >> + >> +/* Configuration for a single Rate Control model range */ struct >> +dsc_rc_range_parameters { >> + /* Min Quantization Parameters allowed for this range */ >> + u8 range_min_qp; >> + /* Max Quantization Parameters allowed for this range */ >> + u8 range_max_qp; >> + /* Bits/group offset to apply to target for this group */ >> + u8 range_bpg_offset; >> +}; >> + >> +struct drm_dsc_config { >> + /* Bits / component for previous reconstructed line buffer */ >> + u8 line_buf_depth; >> + /* Bits per component to code (must be 8, 10, or 12) */ >> + u8 bits_per_component; >> + /* >> + * Flag indicating to do RGB - YCoCg conversion >> + * and back (should be 1 for RGB input) >> + */ >> + bool convert_rgb; >> + u8 slice_count; >> + /* Slice Width */ >> + u16 slice_width; >> + /* Slice Height */ >> + u16 slice_height; >> + /* >> + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens >> + * outside of DSC encode/decode algorithm) >> + */ >> + bool enable422; >> + /* Picture Width */ >> + u16 pic_width; >> + /* Picture Height */ >> + u16 pic_height; >> + /* Offset to bits/group used by RC to determine QP adjustment */ >> + u8 rc_tgt_offset_high; >> + /* Offset to bits/group used by RC to determine QP adjustment */ >> + u8 rc_tgt_offset_low; >> + /* Bits/pixel target << 4 (ie., 4 fractional bits) */ >> + u16 bits_per_pixel; >> + /* >> + * Factor to determine if an edge is present based >> + * on the bits produced >> + */ >> + u8 rc_edge_factor; >> + /* Slow down incrementing once the range reaches this value */ >> + u8 rc_quant_incr_limit1; >> + /* Slow down incrementing once the range reaches this value */ >> + u8 rc_quant_incr_limit0; >> + /* Number of pixels to delay the initial transmission */ >> + u16 initial_xmit_delay; >> + /* Number of pixels to delay the VLD on the decoder,not including SSM >*/ >> + u16 initial_dec_delay; >> + /* Block prediction enable */ >> + bool block_pred_enable; >> + /* Bits/group offset to use for first line of the slice */ >> + u8 first_line_bpg_offset; >> + /* Value to use for RC model offset at slice start */ >> + u16 initial_offset; >> + /* Thresholds defining each of the buffer ranges */ >> + u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; >> + /* Parameters for each of the RC ranges */ >> + struct dsc_rc_range_parameters >rc_range_params[DSC_NUM_BUF_RANGES]; >> + /* Total size of RC model */ >> + u16 rc_model_size; >> + /* Minimum QP where flatness information is sent */ >> + u8 flatness_min_qp; >> + /* Maximum QP where flatness information is sent */ >> + u8 flatness_max_qp; >> + /* Initial value for scale factor */ >> + u8 initial_scale_value; >> + /* Decrement scale factor every scale_decrement_interval groups */ >> + u16 scale_decrement_interval; >> + /* Increment scale factor every scale_increment_interval groups */ >> + u16 scale_increment_interval; >> + /* Non-first line BPG offset to use */ >> + u16 nfl_bpg_offset; >> + /* BPG offset used to enforce slice bit */ >> + u16 slice_bpg_offset; >> + /* Final RC linear transformation offset value */ >> + u16 final_offset; >> + /* Enable on-off VBR (ie., disable stuffing bits) */ >> + bool vbr_enable; >> + /* Mux word size (in bits) for SSM mode */ >> + u8 mux_word_size; >> + /* >> + * The (max) size in bytes of the "chunks" that are >> + * used in slice multiplexing >> + */ >> + u16 slice_chunk_size; >> + /* Rate Control buffer siz in bits */ >> + u16 rc_bits; >> + /* DSC Minor Version */ >> + u8 dsc_version_minor; >> + /* DSC Major version */ >> + u8 dsc_version_major; >> + /* Native 4:2:2 support */ >> + bool native_422; >> + /* Native 4:2:0 support */ >> + bool native_420; >> + /* Additional bits/grp for seconnd line of slice for native 4:2:0 */ >> + u8 second_line_bpg_offset; >> + /* Num of bits deallocated for each grp that is not in second line of slice >*/ >> + u16 nsl_bpg_offset; >> + /* Offset adj fr second line in Native 4:2:0 mode */ >> + u16 second_line_offset_adj; >> +}; >> >> /** >> * struct picture_parameter_set - Represents 128 bytes of Picture >> Parameter Set >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (7 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-09-10 19:41 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare ` (21 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Srivatsa, Anusha, Manasi Navare, dri-devel, Gaurav K Singh From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com> DSC has some Rate Control values that remain constant across all configurations. These are as per the DSC standard. v3: * Define them in drm_dsc.h as they are DSC constants (Manasi) v2: * Add DP_DSC_ prefix (Jani Nikula) Cc: dri-devel@lists.freedesktop.org Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- include/drm/drm_dsc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index eda323d..ebd99d7 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -33,6 +33,12 @@ #define DSC_MUX_WORD_SIZE_8_10_BPC 48 #define DSC_MUX_WORD_SIZE_12_BPC 64 +/* DSC Rate Control Constants */ +#define DSC_RC_MODEL_SIZE_CONST 8192 +#define DSC_RC_EDGE_FACTOR_CONST 6 +#define DSC_RC_TGT_OFFSET_HI_CONST 3 +#define DSC_RC_TGT_OFFSET_LO_CONST 3 + /* Configuration for a single Rate Control model range */ struct dsc_rc_range_parameters { /* Min Quantization Parameters allowed for this range */ -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations 2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare @ 2018-09-10 19:41 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-09-10 19:41 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Harry Wentland On Tue, Jul 31, 2018 at 02:07:05PM -0700, Manasi Navare wrote: > From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com> > > DSC has some Rate Control values that remain constant > across all configurations. These are as per the DSC > standard. > > v3: > * Define them in drm_dsc.h as they are > DSC constants (Manasi) > v2: > * Add DP_DSC_ prefix (Jani Nikula) > > Cc: dri-devel@lists.freedesktop.org > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > Cc: Harry Wentland <harry.wentland@amd.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Tested and double checked the values with DSC spec so Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > --- > include/drm/drm_dsc.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > index eda323d..ebd99d7 100644 > --- a/include/drm/drm_dsc.h > +++ b/include/drm/drm_dsc.h > @@ -33,6 +33,12 @@ > #define DSC_MUX_WORD_SIZE_8_10_BPC 48 > #define DSC_MUX_WORD_SIZE_12_BPC 64 > > +/* DSC Rate Control Constants */ > +#define DSC_RC_MODEL_SIZE_CONST 8192 > +#define DSC_RC_EDGE_FACTOR_CONST 6 > +#define DSC_RC_TGT_OFFSET_HI_CONST 3 > +#define DSC_RC_TGT_OFFSET_LO_CONST 3 > + > /* Configuration for a single Rate Control model range */ > struct dsc_rc_range_parameters { > /* Min Quantization Parameters allowed for this range */ > -- > 2.7.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (8 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-07-31 21:16 ` Chris Wilson 2018-08-23 19:58 ` Harry Wentland 2018-07-31 21:07 ` [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare ` (20 subsequent siblings) 30 siblings, 2 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Anusha Srivatsa, Manasi Navare, dri-devel According to Display Stream compression spec 1.2, the picture parameter set metadata is sent from source to sink device using the DP Secondary data packet. An infoframe is formed for the PPS SDP header and PPS SDP payload bytes. This patch adds helpers to fill the PPS SDP header and PPS SDP payload according to the DSC 1.2 specification. v5: Do not use bitfields for DRM structs (Jani N) v4: * Use DSC constants for params that dont change across configurations v3: * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter) v2: * Add EXPORT_SYMBOL for the drm functions (Manasi) Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- Documentation/gpu/drm-kms-helpers.rst | 12 ++ drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_dsc.c | 221 ++++++++++++++++++++++++++++++++++ include/drm/drm_dsc.h | 22 ++++ 4 files changed, 256 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/drm_dsc.c diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst index f9cfcdc..50bb717 100644 --- a/Documentation/gpu/drm-kms-helpers.rst +++ b/Documentation/gpu/drm-kms-helpers.rst @@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c :export: +Display Stream Compression Helper Functions Reference +===================================================== + +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c + :doc: dsc helpers + +.. kernel-doc:: include/drm/drm_dsc.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c + :export: + Output Probing Helper Functions Reference ========================================= diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index a6771ce..961e511 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o -drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \ +drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \ drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \ drm_kms_helper_common.o drm_dp_dual_mode_helper.o \ drm_simple_kms_helper.o drm_modeset_helper.o \ diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c new file mode 100644 index 0000000..99a8794 --- /dev/null +++ b/drivers/gpu/drm/drm_dsc.c @@ -0,0 +1,221 @@ +/* + *Copyright © 2018 Intel Corp + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Author: + * Manasi Navare <manasi.d.navare@intel.com> + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/errno.h> +#include <drm/drm_dp_helper.h> +#include <drm/drm_dsc.h> + +/** + * DOC: dsc helpers + * + * These functions contain some common logic and helpers to deal with VESA + * Display Stream Compression standard required for DSC on Display Port/eDP or + * MIPI display interfaces. + */ + +/** + * drm_dsc_dp_pps_header_init() - Initializes the PPS Header + * for DisplayPort as per the DP 1.4 spec. + * @pps_sdp: Secondary data packet for DSC Picture Parameter Set + */ +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp) +{ + memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header)); + + pps_sdp->pps_header.HB1 = DP_SDP_PPS; + pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; +} +EXPORT_SYMBOL(drm_dsc_dp_pps_header_init); + +/** + * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe + * using the DSC configuration parameters in the order expected + * by the DSC Display Sink device. For the DSC, the sink device + * expects the PPS payload in the big endian format for the fields + * that span more than 1 byte. + * + * @pps_sdp: + * Secondary data packet for DSC Picture Parameter Set + * @dsc_cfg: + * DSC Configuration data filled by driver + */ +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, + struct drm_dsc_config *dsc_cfg) +{ + u8 i = 0; + + memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload)); + + /* PPS 0 */ + pps_sdp->pps_payload.dsc_version = dsc_cfg->dsc_version_minor | + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; + + /* PPS 1, 2 is 0 */ + + /* PPS 3 */ + pps_sdp->pps_payload.pps_3 = dsc_cfg->line_buf_depth | + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; + + /* PPS 4 */ + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel & + DSC_PPS_BPP_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT) | + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; + + /* PPS 5 */ + pps_sdp->pps_payload.bits_per_pixel_low = (u8)(dsc_cfg->bits_per_pixel & + DSC_PPS_LSB_MASK); + + /* + * The DSC panel expects the PPS packet to have big endian format + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert + * to big endian format. If format is little endian, it will swap + * bytes to convert to Big endian else keep it unchanged. + */ + + /* PPS 6, 7 */ + pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height); + + /* PPS 8, 9 */ + pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width); + + /* PPS 10, 11 */ + pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height); + + /* PPS 12, 13 */ + pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width); + + /* PPS 14, 15 */ + pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); + + /* PPS 16 */ + pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay & + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 17 */ + pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay & + DSC_PPS_LSB_MASK); + + /* PPS 18, 19 */ + pps_sdp->pps_payload.initial_dec_delay = cpu_to_be16(dsc_cfg->initial_dec_delay); + + /* PPS 20 is 0 */ + + /* PPS 21 */ + pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value; + + /* PPS 22, 23 */ + pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval); + + /* PPS 24 */ + pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval & + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 25 */ + pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval & + DSC_PPS_LSB_MASK); + + /* PPS 26[7:0], PPS 27[7:5] RESERVED */ + + /* PPS 27 */ + pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset; + + /* PPS 28, 29 */ + pps_sdp->pps_payload.nfl_bpg_offset = cpu_to_be16(dsc_cfg->nfl_bpg_offset); + + /* PPS 30, 31 */ + pps_sdp->pps_payload.slice_bpg_offset = cpu_to_be16(dsc_cfg->slice_bpg_offset); + + /* PPS 32, 33 */ + pps_sdp->pps_payload.initial_offset = cpu_to_be16(dsc_cfg->initial_offset); + + /* PPS 34, 35 */ + pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset); + + /* PPS 36 */ + pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp; + + /* PPS 37 */ + pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp; + + /* PPS 38, 39 */ + pps_sdp->pps_payload.rc_model_size = cpu_to_be16((u16)DSC_RC_MODEL_SIZE_CONST); + + /* PPS 40 */ + pps_sdp->pps_payload.rc_edge_factor = (u8)DSC_RC_EDGE_FACTOR_CONST; + + /* PPS 41 */ + pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0; + + /* PPS 42 */ + pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1; + + /* PPS 43 */ + pps_sdp->pps_payload.rc_tgt_offset = (u8)DSC_RC_TGT_OFFSET_LO_CONST | + (u8)DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; + + /* PPS 44 - 57 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) + pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i]; + + /* PPS 58 - 87 */ + /* + * For DSC sink programming the RC Range parameter fields + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] + */ + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + pps_sdp->pps_payload.rc_range_parameters[i] = + (u16)((dsc_cfg->rc_range_params[i].range_min_qp << + DSC_PPS_RC_RANGE_MINQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_max_qp << + DSC_PPS_RC_RANGE_MAXQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_bpg_offset)); + pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]); + } + + /* PPS 88 */ + pps_sdp->pps_payload.native_422_420 = (u8)dsc_cfg->native_422 | + (u8)dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; + + /* PPS 89 */ + pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset; + + /* PPS 90, 91 */ + pps_sdp->pps_payload.nsl_bpg_offset = cpu_to_be16(dsc_cfg->nsl_bpg_offset); + + /* PPS 92, 93 */ + pps_sdp->pps_payload.second_line_offset_adj = cpu_to_be16(dsc_cfg->second_line_offset_adj); + + /* PPS 94 - 127 are O */ +} +EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack); diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index ebd99d7..30adc15 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -26,6 +26,7 @@ #ifndef DRM_DSC_H_ #define DRM_DSC_H_ +#include <linux/byteorder/generic.h> #include <drm/drm_dp_helper.h> /* VESA Display Stream Compression DSC 1.2 constants */ @@ -39,6 +40,23 @@ #define DSC_RC_TGT_OFFSET_HI_CONST 3 #define DSC_RC_TGT_OFFSET_LO_CONST 3 +/* DSC PPS constants and macros */ +#define DSC_PPS_VERSION_MAJOR_SHIFT 4 +#define DSC_PPS_BPC_SHIFT 4 +#define DSC_PPS_MSB_SHIFT 8 +#define DSC_PPS_LSB_MASK (0xFF << 0) +#define DSC_PPS_BPP_HIGH_MASK (0x3 << 8) +#define DSC_PPS_VBR_EN_SHIFT 2 +#define DSC_PPS_SIMPLE422_SHIFT 3 +#define DSC_PPS_CONVERT_RGB_SHIFT 4 +#define DSC_PPS_BLOCK_PRED_EN_SHIFT 5 +#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8) +#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8) +#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4 +#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 +#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 +#define DSC_PPS_NATIVE_420_SHIFT 1 + /* Configuration for a single Rate Control model range */ struct dsc_rc_range_parameters { /* Min Quantization Parameters allowed for this range */ @@ -478,4 +496,8 @@ struct drm_dsc_pps_infoframe { struct picture_parameter_set pps_payload; } __packed; +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp); +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, + struct drm_dsc_config *dsc_cfg); + #endif /* _DRM_DSC_H_ */ -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes 2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare @ 2018-07-31 21:16 ` Chris Wilson 2018-08-03 19:18 ` Manasi Navare 2018-08-23 19:58 ` Harry Wentland 1 sibling, 1 reply; 73+ messages in thread From: Chris Wilson @ 2018-07-31 21:16 UTC (permalink / raw) To: Manasi Navare, intel-gfx; +Cc: dri-devel Quoting Manasi Navare (2018-07-31 22:07:06) > + /* PPS 4 */ > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel & > + DSC_PPS_BPP_HIGH_MASK) >> > + DSC_PPS_MSB_SHIFT) | To avoid overhanging cliffs, insert the newline after the sequence point. Quite a few examples throughout the series that would benefit from more judicial placement of line breaks. > + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | > + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | > + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | > + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; Furthermore, you only need the SPDX shorthand rather than full licence text. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes 2018-07-31 21:16 ` Chris Wilson @ 2018-08-03 19:18 ` Manasi Navare 2018-08-03 19:43 ` Chris Wilson 0 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-08-03 19:18 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, dri-devel On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote: > Quoting Manasi Navare (2018-07-31 22:07:06) > > + /* PPS 4 */ > > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel & > > + DSC_PPS_BPP_HIGH_MASK) >> > > + DSC_PPS_MSB_SHIFT) | > > To avoid overhanging cliffs, insert the newline after the sequence > point. Quite a few examples throughout the series that would benefit > from more judicial placement of line breaks. What exactly are you refering to by sequence point here? I am adding newline here after the operator if the next operand exceeds the 80 column limit. > > > + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | > > + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | > > + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | > > + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; > > Furthermore, you only need the SPDX shorthand rather than full licence > text. Here the header is what all the other .c files in drm have. They all tend to use complete text. Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file? Should I remove the entire paragraph about the Copyright? Manasi > -Chris > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes 2018-08-03 19:18 ` Manasi Navare @ 2018-08-03 19:43 ` Chris Wilson 2018-08-03 19:55 ` Manasi Navare 0 siblings, 1 reply; 73+ messages in thread From: Chris Wilson @ 2018-08-03 19:43 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx, dri-devel Quoting Manasi Navare (2018-08-03 20:18:42) > On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote: > > Quoting Manasi Navare (2018-07-31 22:07:06) > > > + /* PPS 4 */ > > > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel & > > > + DSC_PPS_BPP_HIGH_MASK) >> > > > + DSC_PPS_MSB_SHIFT) | > > > > To avoid overhanging cliffs, insert the newline after the sequence > > point. Quite a few examples throughout the series that would benefit > > from more judicial placement of line breaks. > > What exactly are you refering to by sequence point here? Which ever makes sense visually, here '='. pps_sdp->pps_payload.pps_4 = dsc_cfg->bits_per_pixel >> X << DSC_PPS_MSB_SHIFT | dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; If you want to mask with 0xff do it without having to refer to C type promotion rules. > > Furthermore, you only need the SPDX shorthand rather than full licence > > text. > > Here the header is what all the other .c files in drm have. They all tend to use > complete text. And they all need updating, eventually. There's no reason for new file to use the old style. > Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file? > Should I remove the entire paragraph about the Copyright? No, the code is MIT. You replace the licence with just a SPDX link. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes 2018-08-03 19:43 ` Chris Wilson @ 2018-08-03 19:55 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-03 19:55 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, dri-devel On Fri, Aug 03, 2018 at 08:43:51PM +0100, Chris Wilson wrote: > Quoting Manasi Navare (2018-08-03 20:18:42) > > On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote: > > > Quoting Manasi Navare (2018-07-31 22:07:06) > > > > + /* PPS 4 */ > > > > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel & > > > > + DSC_PPS_BPP_HIGH_MASK) >> > > > > + DSC_PPS_MSB_SHIFT) | > > > > > > To avoid overhanging cliffs, insert the newline after the sequence > > > point. Quite a few examples throughout the series that would benefit > > > from more judicial placement of line breaks. > > > > What exactly are you refering to by sequence point here? > > Which ever makes sense visually, here '='. > > pps_sdp->pps_payload.pps_4 = > dsc_cfg->bits_per_pixel >> X << DSC_PPS_MSB_SHIFT | > dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | > dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | > dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | > dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; Ok understood about the sequence point > > If you want to mask with 0xff do it without having to refer to C type promotion > rules. This point is still not clear. is this not correct: (dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> DSC_PPS_MSB_SHIFT > > > > Furthermore, you only need the SPDX shorthand rather than full licence > > > text. > > > > Here the header is what all the other .c files in drm have. They all tend to use > > complete text. > > And they all need updating, eventually. There's no reason for new file > to use the old style. > > > Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file? > > Should I remove the entire paragraph about the Copyright? > > No, the code is MIT. You replace the licence with just a SPDX link. Could you give an example here for the correct way of adding SPDX info in the header and what part of the existing header needs to stay? That would be helpful. Manasi > -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes 2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare 2018-07-31 21:16 ` Chris Wilson @ 2018-08-23 19:58 ` Harry Wentland 1 sibling, 0 replies; 73+ messages in thread From: Harry Wentland @ 2018-08-23 19:58 UTC (permalink / raw) To: Manasi Navare, intel-gfx; +Cc: Anusha Srivatsa, dri-devel On 2018-07-31 05:07 PM, Manasi Navare wrote: > According to Display Stream compression spec 1.2, the picture > parameter set metadata is sent from source to sink device > using the DP Secondary data packet. An infoframe is formed > for the PPS SDP header and PPS SDP payload bytes. > This patch adds helpers to fill the PPS SDP header > and PPS SDP payload according to the DSC 1.2 specification. > > v5: > Do not use bitfields for DRM structs (Jani N) > v4: > * Use DSC constants for params that dont change across > configurations > v3: > * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst > (Daniel Vetter) > > v2: > * Add EXPORT_SYMBOL for the drm functions (Manasi) > > Cc: dri-devel@lists.freedesktop.org > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Harry Wentland <harry.wentland@amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Harry > --- > Documentation/gpu/drm-kms-helpers.rst | 12 ++ > drivers/gpu/drm/Makefile | 2 +- > drivers/gpu/drm/drm_dsc.c | 221 ++++++++++++++++++++++++++++++++++ > include/drm/drm_dsc.h | 22 ++++ > 4 files changed, 256 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/drm_dsc.c > > diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst > index f9cfcdc..50bb717 100644 > --- a/Documentation/gpu/drm-kms-helpers.rst > +++ b/Documentation/gpu/drm-kms-helpers.rst > @@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference > .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c > :export: > > +Display Stream Compression Helper Functions Reference > +===================================================== > + > +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c > + :doc: dsc helpers > + > +.. kernel-doc:: include/drm/drm_dsc.h > + :internal: > + > +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c > + :export: > + > Output Probing Helper Functions Reference > ========================================= > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index a6771ce..961e511 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o > drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o > drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o > > -drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \ > +drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \ > drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \ > drm_kms_helper_common.o drm_dp_dual_mode_helper.o \ > drm_simple_kms_helper.o drm_modeset_helper.o \ > diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c > new file mode 100644 > index 0000000..99a8794 > --- /dev/null > +++ b/drivers/gpu/drm/drm_dsc.c > @@ -0,0 +1,221 @@ > +/* > + *Copyright © 2018 Intel Corp > + * > + * Permission to use, copy, modify, distribute, and sell this software and its > + * documentation for any purpose is hereby granted without fee, provided that > + * the above copyright notice appear in all copies and that both that copyright > + * notice and this permission notice appear in supporting documentation, and > + * that the name of the copyright holders not be used in advertising or > + * publicity pertaining to distribution of the software without specific, > + * written prior permission. The copyright holders make no representations > + * about the suitability of this software for any purpose. It is provided "as > + * is" without express or implied warranty. > + * > + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, > + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO > + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR > + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, > + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER > + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE > + * OF THIS SOFTWARE. > + * > + * Author: > + * Manasi Navare <manasi.d.navare@intel.com> > + */ > + > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/init.h> > +#include <linux/errno.h> > +#include <drm/drm_dp_helper.h> > +#include <drm/drm_dsc.h> > + > +/** > + * DOC: dsc helpers > + * > + * These functions contain some common logic and helpers to deal with VESA > + * Display Stream Compression standard required for DSC on Display Port/eDP or > + * MIPI display interfaces. > + */ > + > +/** > + * drm_dsc_dp_pps_header_init() - Initializes the PPS Header > + * for DisplayPort as per the DP 1.4 spec. > + * @pps_sdp: Secondary data packet for DSC Picture Parameter Set > + */ > +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp) > +{ > + memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header)); > + > + pps_sdp->pps_header.HB1 = DP_SDP_PPS; > + pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; > +} > +EXPORT_SYMBOL(drm_dsc_dp_pps_header_init); > + > +/** > + * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe > + * using the DSC configuration parameters in the order expected > + * by the DSC Display Sink device. For the DSC, the sink device > + * expects the PPS payload in the big endian format for the fields > + * that span more than 1 byte. > + * > + * @pps_sdp: > + * Secondary data packet for DSC Picture Parameter Set > + * @dsc_cfg: > + * DSC Configuration data filled by driver > + */ > +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, > + struct drm_dsc_config *dsc_cfg) > +{ > + u8 i = 0; > + > + memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload)); > + > + /* PPS 0 */ > + pps_sdp->pps_payload.dsc_version = dsc_cfg->dsc_version_minor | > + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; > + > + /* PPS 1, 2 is 0 */ > + > + /* PPS 3 */ > + pps_sdp->pps_payload.pps_3 = dsc_cfg->line_buf_depth | > + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; > + > + /* PPS 4 */ > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel & > + DSC_PPS_BPP_HIGH_MASK) >> > + DSC_PPS_MSB_SHIFT) | > + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | > + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | > + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | > + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; > + > + /* PPS 5 */ > + pps_sdp->pps_payload.bits_per_pixel_low = (u8)(dsc_cfg->bits_per_pixel & > + DSC_PPS_LSB_MASK); > + > + /* > + * The DSC panel expects the PPS packet to have big endian format > + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert > + * to big endian format. If format is little endian, it will swap > + * bytes to convert to Big endian else keep it unchanged. > + */ > + > + /* PPS 6, 7 */ > + pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height); > + > + /* PPS 8, 9 */ > + pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width); > + > + /* PPS 10, 11 */ > + pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height); > + > + /* PPS 12, 13 */ > + pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width); > + > + /* PPS 14, 15 */ > + pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); > + > + /* PPS 16 */ > + pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay & > + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> > + DSC_PPS_MSB_SHIFT); > + > + /* PPS 17 */ > + pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay & > + DSC_PPS_LSB_MASK); > + > + /* PPS 18, 19 */ > + pps_sdp->pps_payload.initial_dec_delay = cpu_to_be16(dsc_cfg->initial_dec_delay); > + > + /* PPS 20 is 0 */ > + > + /* PPS 21 */ > + pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value; > + > + /* PPS 22, 23 */ > + pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval); > + > + /* PPS 24 */ > + pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval & > + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> > + DSC_PPS_MSB_SHIFT); > + > + /* PPS 25 */ > + pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval & > + DSC_PPS_LSB_MASK); > + > + /* PPS 26[7:0], PPS 27[7:5] RESERVED */ > + > + /* PPS 27 */ > + pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset; > + > + /* PPS 28, 29 */ > + pps_sdp->pps_payload.nfl_bpg_offset = cpu_to_be16(dsc_cfg->nfl_bpg_offset); > + > + /* PPS 30, 31 */ > + pps_sdp->pps_payload.slice_bpg_offset = cpu_to_be16(dsc_cfg->slice_bpg_offset); > + > + /* PPS 32, 33 */ > + pps_sdp->pps_payload.initial_offset = cpu_to_be16(dsc_cfg->initial_offset); > + > + /* PPS 34, 35 */ > + pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset); > + > + /* PPS 36 */ > + pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp; > + > + /* PPS 37 */ > + pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp; > + > + /* PPS 38, 39 */ > + pps_sdp->pps_payload.rc_model_size = cpu_to_be16((u16)DSC_RC_MODEL_SIZE_CONST); > + > + /* PPS 40 */ > + pps_sdp->pps_payload.rc_edge_factor = (u8)DSC_RC_EDGE_FACTOR_CONST; > + > + /* PPS 41 */ > + pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0; > + > + /* PPS 42 */ > + pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1; > + > + /* PPS 43 */ > + pps_sdp->pps_payload.rc_tgt_offset = (u8)DSC_RC_TGT_OFFSET_LO_CONST | > + (u8)DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; > + > + /* PPS 44 - 57 */ > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) > + pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i]; > + > + /* PPS 58 - 87 */ > + /* > + * For DSC sink programming the RC Range parameter fields > + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] > + */ > + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { > + pps_sdp->pps_payload.rc_range_parameters[i] = > + (u16)((dsc_cfg->rc_range_params[i].range_min_qp << > + DSC_PPS_RC_RANGE_MINQP_SHIFT) | > + (dsc_cfg->rc_range_params[i].range_max_qp << > + DSC_PPS_RC_RANGE_MAXQP_SHIFT) | > + (dsc_cfg->rc_range_params[i].range_bpg_offset)); > + pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]); > + } > + > + /* PPS 88 */ > + pps_sdp->pps_payload.native_422_420 = (u8)dsc_cfg->native_422 | > + (u8)dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; > + > + /* PPS 89 */ > + pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset; > + > + /* PPS 90, 91 */ > + pps_sdp->pps_payload.nsl_bpg_offset = cpu_to_be16(dsc_cfg->nsl_bpg_offset); > + > + /* PPS 92, 93 */ > + pps_sdp->pps_payload.second_line_offset_adj = cpu_to_be16(dsc_cfg->second_line_offset_adj); > + > + /* PPS 94 - 127 are O */ > +} > +EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack); > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > index ebd99d7..30adc15 100644 > --- a/include/drm/drm_dsc.h > +++ b/include/drm/drm_dsc.h > @@ -26,6 +26,7 @@ > #ifndef DRM_DSC_H_ > #define DRM_DSC_H_ > > +#include <linux/byteorder/generic.h> > #include <drm/drm_dp_helper.h> > > /* VESA Display Stream Compression DSC 1.2 constants */ > @@ -39,6 +40,23 @@ > #define DSC_RC_TGT_OFFSET_HI_CONST 3 > #define DSC_RC_TGT_OFFSET_LO_CONST 3 > > +/* DSC PPS constants and macros */ > +#define DSC_PPS_VERSION_MAJOR_SHIFT 4 > +#define DSC_PPS_BPC_SHIFT 4 > +#define DSC_PPS_MSB_SHIFT 8 > +#define DSC_PPS_LSB_MASK (0xFF << 0) > +#define DSC_PPS_BPP_HIGH_MASK (0x3 << 8) > +#define DSC_PPS_VBR_EN_SHIFT 2 > +#define DSC_PPS_SIMPLE422_SHIFT 3 > +#define DSC_PPS_CONVERT_RGB_SHIFT 4 > +#define DSC_PPS_BLOCK_PRED_EN_SHIFT 5 > +#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8) > +#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8) > +#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4 > +#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 > +#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 > +#define DSC_PPS_NATIVE_420_SHIFT 1 > + > /* Configuration for a single Rate Control model range */ > struct dsc_rc_range_parameters { > /* Min Quantization Parameters allowed for this range */ > @@ -478,4 +496,8 @@ struct drm_dsc_pps_infoframe { > struct picture_parameter_set pps_payload; > } __packed; > > +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp); > +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, > + struct drm_dsc_config *dsc_cfg); > + > #endif /* _DRM_DSC_H_ */ > -- 2.7.4 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (9 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-17 19:51 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare ` (19 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx Basic DSC parameters and DSC configuration data needs to be computed for each of the requested mode during atomic check. This is required since for certain modes, valid DSC parameters and config data might not be computed in which case compression cannot be enabled for that mode. For that reason we need to add these params and config structure to the intel_crtc_state so that if valid this state information can directly be used while enabling DSC in atomic commit. Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f49f99..334a5db 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -52,6 +52,7 @@ #include <drm/drm_gem.h> #include <drm/drm_auth.h> #include <drm/drm_cache.h> +#include <drm/drm_dsc.h> #include "i915_params.h" #include "i915_reg.h" diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 68b2401..b7c2652 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -895,6 +895,15 @@ struct intel_crtc_state { /* output format is YCBCR 4:2:0 */ bool ycbcr420; + + /* Display Stream compression state */ + struct { + bool compression_enable; + bool dsc_split; + u16 compressed_bpp; + u8 slice_count; + } dsc_params; + struct drm_dsc_config dp_dsc_cfg; }; struct intel_crtc { -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state 2018-07-31 21:07 ` [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare @ 2018-08-17 19:51 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-17 19:51 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K ><gaurav.k.singh@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>; Ville >Syrjala <ville.syrjala@linux.intel.com>; Srivatsa, Anusha ><anusha.srivatsa@intel.com> >Subject: [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to >intel_crtc_state > >Basic DSC parameters and DSC configuration data needs to be computed for each >of the requested mode during atomic check. This is required since for certain >modes, valid DSC parameters and config data might not be computed in which >case compression cannot be enabled for that mode. >For that reason we need to add these params and config structure to the >intel_crtc_state so that if valid this state information can directly be used while >enabling DSC in atomic commit. > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++ > 2 files changed, 10 insertions(+) > >diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >index 0f49f99..334a5db 100644 >--- a/drivers/gpu/drm/i915/i915_drv.h >+++ b/drivers/gpu/drm/i915/i915_drv.h >@@ -52,6 +52,7 @@ > #include <drm/drm_gem.h> > #include <drm/drm_auth.h> > #include <drm/drm_cache.h> >+#include <drm/drm_dsc.h> > > #include "i915_params.h" > #include "i915_reg.h" >diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >index 68b2401..b7c2652 100644 >--- a/drivers/gpu/drm/i915/intel_drv.h >+++ b/drivers/gpu/drm/i915/intel_drv.h >@@ -895,6 +895,15 @@ struct intel_crtc_state { > > /* output format is YCBCR 4:2:0 */ > bool ycbcr420; >+ >+ /* Display Stream compression state */ >+ struct { >+ bool compression_enable; >+ bool dsc_split; >+ u16 compressed_bpp; >+ u8 slice_count; >+ } dsc_params; >+ struct drm_dsc_config dp_dsc_cfg; > }; > > struct intel_crtc { >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (10 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-28 23:40 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare ` (18 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx DSC params like the enable, compressed bpp, slice ocunt and dsc_split are added to the intel_crtc_state. These parameters are set based on the requested mode and available link parameters during the pipe configuration in atomic check phase. These values are then later used to populate the remaining DSC and RC parameters before enbaling DSC in atomic commit. v7: * Fix indentation in compute_m_n (Manasi) v6 (From Gaurav): * Remove function call of intel_dp_compute_dsc_params() and invoke intel_dp_compute_dsc_params() in the patch where it is defined to fix compilation warning (Gaurav) v5: Add drm_dsc_cfg in intel_crtc_state (Manasi) v4: * Rebase on refactoring of intel_dp_compute_config on tip (Manasi) * Add a comment why we need to check PSR while enabling DSC (Gaurav) v3: * Check PPR > max_cdclock to use 2 VDSC instances (Ville) v2: * Add if-else for eDP/DP (Gaurav) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 20 +++-- drivers/gpu/drm/i915/intel_display.h | 3 +- drivers/gpu/drm/i915/intel_dp.c | 141 +++++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- 4 files changed, 142 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 577b30d..de895ab 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6460,7 +6460,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, pipe_config->fdi_lanes = lane; - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock, link_bw, &pipe_config->fdi_m_n, false); ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); @@ -6697,17 +6697,25 @@ static void compute_m_n(unsigned int m, unsigned int n, } void -intel_link_compute_m_n(int bits_per_pixel, int nlanes, +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp, + int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, bool reduce_m_n) { m_n->tu = 64; - compute_m_n(bits_per_pixel * pixel_clock, - link_clock * nlanes * 8, - &m_n->gmch_m, &m_n->gmch_n, - reduce_m_n); + /* For DSC, Data M/N calculation uses compressed BPP */ + if (compressed_bpp) + compute_m_n(compressed_bpp * pixel_clock, + link_clock * nlanes * 8, + &m_n->gmch_m, &m_n->gmch_n, + reduce_m_n); + else + compute_m_n(bits_per_pixel * pixel_clock, + link_clock * nlanes * 8, + &m_n->gmch_m, &m_n->gmch_n, + reduce_m_n); compute_m_n(pixel_clock, link_clock, &m_n->link_m, &m_n->link_n, diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h index 0a79a46..ba013e4 100644 --- a/drivers/gpu/drm/i915/intel_display.h +++ b/drivers/gpu/drm/i915/intel_display.h @@ -360,7 +360,8 @@ struct intel_link_m_n { (__i)++) \ for_each_if(plane) -void intel_link_compute_m_n(int bpp, int nlanes, +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp, + int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, bool reduce_m_n); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8459d74..7132f52 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -47,6 +47,8 @@ /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */ #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440 +#define DP_DSC_MIN_SUPPORTED_BPC 8 +#define DP_DSC_MAX_SUPPORTED_BPC 10 /* DP DSC throughput values used for slice count calculations KPixels/s */ #define DP_DSC_PEAK_PIXEL_RATE 2720000 @@ -1897,6 +1899,16 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, } } + /* If DSC is supported, use the max value reported by panel */ + if (INTEL_GEN(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + bpc = min_t(u8, + drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd), + DP_DSC_MAX_SUPPORTED_BPC); + if (!bpc) + bpp = 3 * bpc; + } + return bpp; } @@ -1957,14 +1969,11 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, link_clock = intel_dp->common_rates[clock]; link_avail = intel_dp_max_data_rate(link_clock, lane_count); - - if (mode_rate <= link_avail) { - pipe_config->lane_count = lane_count; - pipe_config->pipe_bpp = bpp; - pipe_config->port_clock = link_clock; - + pipe_config->lane_count = lane_count; + pipe_config->pipe_bpp = bpp; + pipe_config->port_clock = link_clock; + if (mode_rate <= link_avail) return true; - } } } } @@ -1972,10 +1981,82 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return false; } +static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct link_config_limits *limits) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; + enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; + u16 dsc_max_output_bpp = 0; + u8 dsc_dp_slice_count = 0; + + if (INTEL_GEN(dev_priv) < 10 || + !drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) + return false; + + /* DP DSC only supported on Pipe B and C */ + if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp)) + return false; + + /* DSC not supported for DSC sink BPC < 8 */ + if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) { + DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); + return false; + } + + if (intel_dp_is_edp(intel_dp)) { + pipe_config->dsc_params.compressed_bpp = + drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; + pipe_config->dsc_params.slice_count = + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, + true); + } else { + + dsc_max_output_bpp = intel_dp_dsc_get_output_bpp(pipe_config->port_clock, + pipe_config->lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay); + dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay); + if (!(dsc_max_output_bpp && dsc_dp_slice_count)) { + DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); + return false; + } + pipe_config->dsc_params.compressed_bpp = dsc_max_output_bpp >> 4; + pipe_config->dsc_params.slice_count = dsc_dp_slice_count; + } + /* + * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate + * is greater than the maximum Cdclock and if slice count is even + * then we need to use 2 VDSC instances. + */ + pipe_config->dsc_params.dsc_split = false; + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { + if (pipe_config->dsc_params.slice_count > 1) { + pipe_config->dsc_params.dsc_split = true; + } else { + DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); + return false; + } + } + pipe_config->dsc_params.compression_enable = true; + DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " + "Compressed Bpp = %d Slice Count = %d\n", + pipe_config->pipe_bpp, + pipe_config->dsc_params.compressed_bpp, + pipe_config->dsc_params.slice_count); + + return true; +} + static bool intel_dp_compute_link_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct link_config_limits limits; @@ -1993,7 +2074,9 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.min_lane_count = 1; limits.max_lane_count = intel_dp_max_lane_count(intel_dp); - limits.min_bpp = 6 * 3; + limits.min_bpp = (INTEL_GEN(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) ? + DP_DSC_MIN_SUPPORTED_BPC * 3 : 6 * 3; limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); if (intel_dp_is_edp(intel_dp)) { @@ -2020,19 +2103,43 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, * Optimize for slow and wide. This is the place to add alternative * optimization policy. */ - if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits)) - return false; + if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, + &limits)) { - DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", - pipe_config->lane_count, pipe_config->port_clock, - pipe_config->pipe_bpp); + DRM_DEBUG_KMS("DP required Link rate %i does not fit available %i\n", + intel_dp_link_required(adjusted_mode->crtc_clock, + pipe_config->pipe_bpp), + intel_dp_max_data_rate(pipe_config->port_clock, + pipe_config->lane_count)); + + /* enable compression if the mode doesn't fit available BW */ + if (!intel_dp_dsc_compute_config(intel_dp, pipe_config, + &limits)) + return false; + } + + if (pipe_config->dsc_params.compression_enable) { + DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", + pipe_config->lane_count, pipe_config->port_clock, + pipe_config->pipe_bpp, + pipe_config->dsc_params.compressed_bpp); DRM_DEBUG_KMS("DP link rate required %i available %i\n", intel_dp_link_required(adjusted_mode->crtc_clock, - pipe_config->pipe_bpp), + pipe_config->dsc_params.compressed_bpp), intel_dp_max_data_rate(pipe_config->port_clock, pipe_config->lane_count)); + } else { + DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", + pipe_config->lane_count, pipe_config->port_clock, + pipe_config->pipe_bpp); + DRM_DEBUG_KMS("DP link rate required %i available %i\n", + intel_dp_link_required(adjusted_mode->crtc_clock, + pipe_config->pipe_bpp), + intel_dp_max_data_rate(pipe_config->port_clock, + pipe_config->lane_count)); + } return true; } @@ -2111,7 +2218,9 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; } - intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count, + intel_link_compute_m_n(pipe_config->pipe_bpp, + pipe_config->dsc_params.compressed_bpp, + pipe_config->lane_count, adjusted_mode->crtc_clock, pipe_config->port_clock, &pipe_config->dp_m_n, @@ -2120,7 +2229,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (intel_connector->panel.downclock_mode != NULL && dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { pipe_config->has_drrs = true; - intel_link_compute_m_n(pipe_config->pipe_bpp, + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, pipe_config->lane_count, intel_connector->panel.downclock_mode->clock, pipe_config->port_clock, diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 352e521..4f941b8 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -83,7 +83,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, return false; } - intel_link_compute_m_n(bpp, lane_count, + intel_link_compute_m_n(bpp, 0, lane_count, adjusted_mode->crtc_clock, pipe_config->port_clock, &pipe_config->dp_m_n, -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check 2018-07-31 21:07 ` [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare @ 2018-08-28 23:40 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-28 23:40 UTC (permalink / raw) To: intel-gfx Jani, Ville, Could you take a look at this patch since it touches the DP compute config quite a bit and I want to make sure that it enables DSC as per our design agreement that we enable it only for resolutions that do not fit available link BW. I have one comment below that I need to fix. But apart from that it will be good to get some feedback on this logic. On Tue, Jul 31, 2018 at 02:07:08PM -0700, Manasi Navare wrote: > DSC params like the enable, compressed bpp, slice ocunt and > dsc_split are added to the intel_crtc_state. These parameters > are set based on the requested mode and available link parameters > during the pipe configuration in atomic check phase. > These values are then later used to populate the remaining DSC > and RC parameters before enbaling DSC in atomic commit. > > v7: > * Fix indentation in compute_m_n (Manasi) > > v6 (From Gaurav): > * Remove function call of intel_dp_compute_dsc_params() and > invoke intel_dp_compute_dsc_params() in the patch where > it is defined to fix compilation warning (Gaurav) > > v5: > Add drm_dsc_cfg in intel_crtc_state (Manasi) > > v4: > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi) > * Add a comment why we need to check PSR while enabling DSC (Gaurav) > > v3: > * Check PPR > max_cdclock to use 2 VDSC instances (Ville) > > v2: > * Add if-else for eDP/DP (Gaurav) > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 20 +++-- > drivers/gpu/drm/i915/intel_display.h | 3 +- > drivers/gpu/drm/i915/intel_dp.c | 141 +++++++++++++++++++++++++++++++---- > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > 4 files changed, 142 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 577b30d..de895ab 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6460,7 +6460,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, > > pipe_config->fdi_lanes = lane; > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock, > link_bw, &pipe_config->fdi_m_n, false); > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); > @@ -6697,17 +6697,25 @@ static void compute_m_n(unsigned int m, unsigned int n, > } > > void > -intel_link_compute_m_n(int bits_per_pixel, int nlanes, > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp, > + int nlanes, > int pixel_clock, int link_clock, > struct intel_link_m_n *m_n, > bool reduce_m_n) > { > m_n->tu = 64; > > - compute_m_n(bits_per_pixel * pixel_clock, > - link_clock * nlanes * 8, > - &m_n->gmch_m, &m_n->gmch_n, > - reduce_m_n); > + /* For DSC, Data M/N calculation uses compressed BPP */ > + if (compressed_bpp) > + compute_m_n(compressed_bpp * pixel_clock, > + link_clock * nlanes * 8, > + &m_n->gmch_m, &m_n->gmch_n, > + reduce_m_n); > + else > + compute_m_n(bits_per_pixel * pixel_clock, > + link_clock * nlanes * 8, > + &m_n->gmch_m, &m_n->gmch_n, > + reduce_m_n); > > compute_m_n(pixel_clock, link_clock, > &m_n->link_m, &m_n->link_n, > diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h > index 0a79a46..ba013e4 100644 > --- a/drivers/gpu/drm/i915/intel_display.h > +++ b/drivers/gpu/drm/i915/intel_display.h > @@ -360,7 +360,8 @@ struct intel_link_m_n { > (__i)++) \ > for_each_if(plane) > > -void intel_link_compute_m_n(int bpp, int nlanes, > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp, > + int nlanes, > int pixel_clock, int link_clock, > struct intel_link_m_n *m_n, > bool reduce_m_n); > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 8459d74..7132f52 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -47,6 +47,8 @@ > > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */ > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440 > +#define DP_DSC_MIN_SUPPORTED_BPC 8 > +#define DP_DSC_MAX_SUPPORTED_BPC 10 > > /* DP DSC throughput values used for slice count calculations KPixels/s */ > #define DP_DSC_PEAK_PIXEL_RATE 2720000 > @@ -1897,6 +1899,16 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, > } > } > > + /* If DSC is supported, use the max value reported by panel */ > + if (INTEL_GEN(dev_priv) >= 10 && > + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { > + bpc = min_t(u8, > + drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd), > + DP_DSC_MAX_SUPPORTED_BPC); > + if (!bpc) This actually should be checking for if (bpc) since for an invalid value, the drm_dp_dsc_sink_max_color_depth will return 0. I will make this change in the final rev. Manasi > + bpp = 3 * bpc; > + } > + > return bpp; > } > > @@ -1957,14 +1969,11 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, > link_clock = intel_dp->common_rates[clock]; > link_avail = intel_dp_max_data_rate(link_clock, > lane_count); > - > - if (mode_rate <= link_avail) { > - pipe_config->lane_count = lane_count; > - pipe_config->pipe_bpp = bpp; > - pipe_config->port_clock = link_clock; > - > + pipe_config->lane_count = lane_count; > + pipe_config->pipe_bpp = bpp; > + pipe_config->port_clock = link_clock; > + if (mode_rate <= link_avail) > return true; > - } > } > } > } > @@ -1972,10 +1981,82 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, > return false; > } > > +static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > + struct intel_crtc_state *pipe_config, > + struct link_config_limits *limits) > +{ > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > + struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; > + enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; > + u16 dsc_max_output_bpp = 0; > + u8 dsc_dp_slice_count = 0; > + > + if (INTEL_GEN(dev_priv) < 10 || > + !drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) > + return false; > + > + /* DP DSC only supported on Pipe B and C */ > + if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp)) > + return false; > + > + /* DSC not supported for DSC sink BPC < 8 */ > + if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) { > + DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); > + return false; > + } > + > + if (intel_dp_is_edp(intel_dp)) { > + pipe_config->dsc_params.compressed_bpp = > + drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; > + pipe_config->dsc_params.slice_count = > + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, > + true); > + } else { > + > + dsc_max_output_bpp = intel_dp_dsc_get_output_bpp(pipe_config->port_clock, > + pipe_config->lane_count, > + adjusted_mode->crtc_clock, > + adjusted_mode->crtc_hdisplay); > + dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, > + adjusted_mode->crtc_clock, > + adjusted_mode->crtc_hdisplay); > + if (!(dsc_max_output_bpp && dsc_dp_slice_count)) { > + DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); > + return false; > + } > + pipe_config->dsc_params.compressed_bpp = dsc_max_output_bpp >> 4; > + pipe_config->dsc_params.slice_count = dsc_dp_slice_count; > + } > + /* > + * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate > + * is greater than the maximum Cdclock and if slice count is even > + * then we need to use 2 VDSC instances. > + */ > + pipe_config->dsc_params.dsc_split = false; > + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { > + if (pipe_config->dsc_params.slice_count > 1) { > + pipe_config->dsc_params.dsc_split = true; > + } else { > + DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); > + return false; > + } > + } > + pipe_config->dsc_params.compression_enable = true; > + DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > + "Compressed Bpp = %d Slice Count = %d\n", > + pipe_config->pipe_bpp, > + pipe_config->dsc_params.compressed_bpp, > + pipe_config->dsc_params.slice_count); > + > + return true; > +} > + > static bool > intel_dp_compute_link_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > struct link_config_limits limits; > @@ -1993,7 +2074,9 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, > limits.min_lane_count = 1; > limits.max_lane_count = intel_dp_max_lane_count(intel_dp); > > - limits.min_bpp = 6 * 3; > + limits.min_bpp = (INTEL_GEN(dev_priv) >= 10 && > + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) ? > + DP_DSC_MIN_SUPPORTED_BPC * 3 : 6 * 3; > limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); > > if (intel_dp_is_edp(intel_dp)) { > @@ -2020,19 +2103,43 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, > * Optimize for slow and wide. This is the place to add alternative > * optimization policy. > */ > - if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits)) > - return false; > + if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, > + &limits)) { > > - DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", > - pipe_config->lane_count, pipe_config->port_clock, > - pipe_config->pipe_bpp); > + DRM_DEBUG_KMS("DP required Link rate %i does not fit available %i\n", > + intel_dp_link_required(adjusted_mode->crtc_clock, > + pipe_config->pipe_bpp), > + intel_dp_max_data_rate(pipe_config->port_clock, > + pipe_config->lane_count)); > + > + /* enable compression if the mode doesn't fit available BW */ > + if (!intel_dp_dsc_compute_config(intel_dp, pipe_config, > + &limits)) > + return false; > + } > + > + if (pipe_config->dsc_params.compression_enable) { > + DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", > + pipe_config->lane_count, pipe_config->port_clock, > + pipe_config->pipe_bpp, > + pipe_config->dsc_params.compressed_bpp); > > DRM_DEBUG_KMS("DP link rate required %i available %i\n", > intel_dp_link_required(adjusted_mode->crtc_clock, > - pipe_config->pipe_bpp), > + pipe_config->dsc_params.compressed_bpp), > intel_dp_max_data_rate(pipe_config->port_clock, > pipe_config->lane_count)); > + } else { > + DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", > + pipe_config->lane_count, pipe_config->port_clock, > + pipe_config->pipe_bpp); > > + DRM_DEBUG_KMS("DP link rate required %i available %i\n", > + intel_dp_link_required(adjusted_mode->crtc_clock, > + pipe_config->pipe_bpp), > + intel_dp_max_data_rate(pipe_config->port_clock, > + pipe_config->lane_count)); > + } > return true; > } > > @@ -2111,7 +2218,9 @@ intel_dp_compute_config(struct intel_encoder *encoder, > intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; > } > > - intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count, > + intel_link_compute_m_n(pipe_config->pipe_bpp, > + pipe_config->dsc_params.compressed_bpp, > + pipe_config->lane_count, > adjusted_mode->crtc_clock, > pipe_config->port_clock, > &pipe_config->dp_m_n, > @@ -2120,7 +2229,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, > if (intel_connector->panel.downclock_mode != NULL && > dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { > pipe_config->has_drrs = true; > - intel_link_compute_m_n(pipe_config->pipe_bpp, > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, > pipe_config->lane_count, > intel_connector->panel.downclock_mode->clock, > pipe_config->port_clock, > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c > index 352e521..4f941b8 100644 > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > @@ -83,7 +83,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, > return false; > } > > - intel_link_compute_m_n(bpp, lane_count, > + intel_link_compute_m_n(bpp, 0, lane_count, > adjusted_mode->crtc_clock, > pipe_config->port_clock, > &pipe_config->dp_m_n, > -- > 2.7.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (11 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-09 5:55 ` Rodrigo Vivi 2018-07-31 21:07 ` [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare ` (17 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi If a eDP panel supports both PSR2 and VDSC, our HW cannot support both at a time. Give priority to PSR2 if a requested resolution can be supported without compression else enable VDSC and keep PSR2 disabled. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 4bd5768..fdb028f 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (!dev_priv->psr.sink_psr2_support) return false; + /* + * DSC and PSR2 cannot be enabled simultaneously. If a requested + * resolution requires DSC to be enabled, priority is given to DSC + * over PSR2. + */ + if (crtc_state->dsc_params.compression_enable) { + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); + return false; + } + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304; -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled 2018-07-31 21:07 ` [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare @ 2018-08-09 5:55 ` Rodrigo Vivi 2018-08-23 19:22 ` Manasi Navare 2018-08-23 20:34 ` Dhinakaran Pandiyan 0 siblings, 2 replies; 73+ messages in thread From: Rodrigo Vivi @ 2018-08-09 5:55 UTC (permalink / raw) To: Manasi Navare; +Cc: Jani Nikula, intel-gfx On Tue, Jul 31, 2018 at 02:07:09PM -0700, Manasi Navare wrote: > If a eDP panel supports both PSR2 and VDSC, our HW cannot > support both at a time. Give priority to PSR2 if a requested > resolution can be supported without compression else enable > VDSC and keep PSR2 disabled. what about PSR1 on PSR2 panels? could it be enabled with VSC? or is there any restriction? > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 4bd5768..fdb028f 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > if (!dev_priv->psr.sink_psr2_support) > return false; > > + /* > + * DSC and PSR2 cannot be enabled simultaneously. If a requested > + * resolution requires DSC to be enabled, priority is given to DSC > + * over PSR2. > + */ > + if (crtc_state->dsc_params.compression_enable) { > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); > + return false; > + } one concern I had when I first saw this patch is the order, but I saw that psr compute config is the last one inside dp compute config, so we are good... only "concern" now is about PSR1 restrictions. But if not restriction with PSR1 and VSC: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > + > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > psr_max_h = 4096; > psr_max_v = 2304; > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled 2018-08-09 5:55 ` Rodrigo Vivi @ 2018-08-23 19:22 ` Manasi Navare 2018-08-23 20:26 ` Rodrigo Vivi 2018-08-23 20:34 ` Dhinakaran Pandiyan 1 sibling, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-08-23 19:22 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Jani Nikula, intel-gfx Thanks Rodrigo for your review. Please find the answers below: On Wed, Aug 08, 2018 at 10:55:13PM -0700, Rodrigo Vivi wrote: > On Tue, Jul 31, 2018 at 02:07:09PM -0700, Manasi Navare wrote: > > If a eDP panel supports both PSR2 and VDSC, our HW cannot > > support both at a time. Give priority to PSR2 if a requested > > resolution can be supported without compression else enable > > VDSC and keep PSR2 disabled. > > what about PSR1 on PSR2 panels? could it be enabled with VSC? > or is there any restriction? > PSR1 can be enabled simultaneously with VDSC. Its only the PSR2 with selective updates that cannot work along with DSC. Manasi > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > > index 4bd5768..fdb028f 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > if (!dev_priv->psr.sink_psr2_support) > > return false; > > > > + /* > > + * DSC and PSR2 cannot be enabled simultaneously. If a requested > > + * resolution requires DSC to be enabled, priority is given to DSC > > + * over PSR2. > > + */ > > + if (crtc_state->dsc_params.compression_enable) { > > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); > > + return false; > > + } > > one concern I had when I first saw this patch is the order, but > I saw that psr compute config is the last one inside dp compute config, > so we are good... > > only "concern" now is about PSR1 restrictions. > > But if not restriction with PSR1 and VSC: > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > + > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > > psr_max_h = 4096; > > psr_max_v = 2304; > > -- > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled 2018-08-23 19:22 ` Manasi Navare @ 2018-08-23 20:26 ` Rodrigo Vivi 0 siblings, 0 replies; 73+ messages in thread From: Rodrigo Vivi @ 2018-08-23 20:26 UTC (permalink / raw) To: Manasi Navare; +Cc: Jani Nikula, intel-gfx On Thu, Aug 23, 2018 at 12:22:29PM -0700, Manasi Navare wrote: > Thanks Rodrigo for your review. Please find the answers below: > > On Wed, Aug 08, 2018 at 10:55:13PM -0700, Rodrigo Vivi wrote: > > On Tue, Jul 31, 2018 at 02:07:09PM -0700, Manasi Navare wrote: > > > If a eDP panel supports both PSR2 and VDSC, our HW cannot > > > support both at a time. Give priority to PSR2 if a requested > > > resolution can be supported without compression else enable > > > VDSC and keep PSR2 disabled. > > > > what about PSR1 on PSR2 panels? could it be enabled with VSC? > > or is there any restriction? > > > > PSR1 can be enabled simultaneously with VDSC. Its only the PSR2 with selective updates > that cannot work along with DSC. cool, thanks for the confirmation.... feel free to use Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Manasi > > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Jani Nikula <jani.nikula@intel.com> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > > > index 4bd5768..fdb028f 100644 > > > --- a/drivers/gpu/drm/i915/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > > @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > > if (!dev_priv->psr.sink_psr2_support) > > > return false; > > > > > > + /* > > > + * DSC and PSR2 cannot be enabled simultaneously. If a requested > > > + * resolution requires DSC to be enabled, priority is given to DSC > > > + * over PSR2. > > > + */ > > > + if (crtc_state->dsc_params.compression_enable) { > > > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); > > > + return false; > > > + } > > > > one concern I had when I first saw this patch is the order, but > > I saw that psr compute config is the last one inside dp compute config, > > so we are good... > > > > only "concern" now is about PSR1 restrictions. > > > > But if not restriction with PSR1 and VSC: > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > > > > + > > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > > > psr_max_h = 4096; > > > psr_max_v = 2304; > > > -- > > > 2.7.4 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled 2018-08-09 5:55 ` Rodrigo Vivi 2018-08-23 19:22 ` Manasi Navare @ 2018-08-23 20:34 ` Dhinakaran Pandiyan 2018-08-23 20:57 ` Rodrigo Vivi 1 sibling, 1 reply; 73+ messages in thread From: Dhinakaran Pandiyan @ 2018-08-23 20:34 UTC (permalink / raw) To: Rodrigo Vivi, Manasi Navare; +Cc: Jani Nikula, intel-gfx On Wed, 2018-08-08 at 22:55 -0700, Rodrigo Vivi wrote: > On Tue, Jul 31, 2018 at 02:07:09PM -0700, Manasi Navare wrote: > > If a eDP panel supports both PSR2 and VDSC, our HW cannot > > support both at a time. Give priority to PSR2 if a requested > > resolution can be supported without compression else enable > > VDSC and keep PSR2 disabled. > > what about PSR1 on PSR2 panels? could it be enabled with VSC? > or is there any restriction? > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 4bd5768..fdb028f 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > if (!dev_priv->psr.sink_psr2_support) > > return false; > > > > + /* > > + * DSC and PSR2 cannot be enabled simultaneously. If a > > requested > > + * resolution requires DSC to be enabled, priority is > > given to DSC > > + * over PSR2. > > + */ > > + if (crtc_state->dsc_params.compression_enable) { > > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is > > enabled\n"); > > + return false; > > + } > > one concern I had when I first saw this patch is the order, but > I saw that psr compute config is the last one inside dp compute > config, Do something more to ensure that order stays as it is? A warn if both get enabled, or a comment in intel_dp.c perhaps. That is what we do for drrs and psr. > so we are good... > > only "concern" now is about PSR1 restrictions. > > But if not restriction with PSR1 and VSC: > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > + > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > { > > psr_max_h = 4096; > > psr_max_v = 2304; > > -- > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled 2018-08-23 20:34 ` Dhinakaran Pandiyan @ 2018-08-23 20:57 ` Rodrigo Vivi 2018-08-29 6:52 ` Manasi Navare 0 siblings, 1 reply; 73+ messages in thread From: Rodrigo Vivi @ 2018-08-23 20:57 UTC (permalink / raw) To: Dhinakaran Pandiyan; +Cc: Jani Nikula, intel-gfx On Thu, Aug 23, 2018 at 01:34:54PM -0700, Dhinakaran Pandiyan wrote: > > > On Wed, 2018-08-08 at 22:55 -0700, Rodrigo Vivi wrote: > > On Tue, Jul 31, 2018 at 02:07:09PM -0700, Manasi Navare wrote: > > > If a eDP panel supports both PSR2 and VDSC, our HW cannot > > > support both at a time. Give priority to PSR2 if a requested > > > resolution can be supported without compression else enable > > > VDSC and keep PSR2 disabled. > > > > what about PSR1 on PSR2 panels? could it be enabled with VSC? > > or is there any restriction? > > > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Jani Nikula <jani.nikula@intel.com> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > > b/drivers/gpu/drm/i915/intel_psr.c > > > index 4bd5768..fdb028f 100644 > > > --- a/drivers/gpu/drm/i915/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > > @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct > > > intel_dp *intel_dp, > > > if (!dev_priv->psr.sink_psr2_support) > > > return false; > > > > > > + /* > > > + * DSC and PSR2 cannot be enabled simultaneously. If a > > > requested > > > + * resolution requires DSC to be enabled, priority is > > > given to DSC > > > + * over PSR2. > > > + */ > > > + if (crtc_state->dsc_params.compression_enable) { > > > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is > > > enabled\n"); > > > + return false; > > > + } > > > > one concern I had when I first saw this patch is the order, but > > I saw that psr compute config is the last one inside dp compute > > config, > Do something more to ensure that order stays as it is? A warn if both > get enabled, or a comment in intel_dp.c perhaps. That is what we do for > drrs and psr. hmm... that's a good idea. > > > so we are good... > > > > only "concern" now is about PSR1 restrictions. > > > > But if not restriction with PSR1 and VSC: > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > > > > + > > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > > { > > > psr_max_h = 4096; > > > psr_max_v = 2304; > > > -- > > > 2.7.4 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled 2018-08-23 20:57 ` Rodrigo Vivi @ 2018-08-29 6:52 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-29 6:52 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Jani Nikula, intel-gfx, Dhinakaran Pandiyan On Thu, Aug 23, 2018 at 01:57:46PM -0700, Rodrigo Vivi wrote: > On Thu, Aug 23, 2018 at 01:34:54PM -0700, Dhinakaran Pandiyan wrote: > > > > > > On Wed, 2018-08-08 at 22:55 -0700, Rodrigo Vivi wrote: > > > On Tue, Jul 31, 2018 at 02:07:09PM -0700, Manasi Navare wrote: > > > > If a eDP panel supports both PSR2 and VDSC, our HW cannot > > > > support both at a time. Give priority to PSR2 if a requested > > > > resolution can be supported without compression else enable > > > > VDSC and keep PSR2 disabled. > > > > > > what about PSR1 on PSR2 panels? could it be enabled with VSC? > > > or is there any restriction? > > > > > > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > Cc: Jani Nikula <jani.nikula@intel.com> > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++ > > > > 1 file changed, 10 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > > > b/drivers/gpu/drm/i915/intel_psr.c > > > > index 4bd5768..fdb028f 100644 > > > > --- a/drivers/gpu/drm/i915/intel_psr.c > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > > > @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct > > > > intel_dp *intel_dp, > > > > if (!dev_priv->psr.sink_psr2_support) > > > > return false; > > > > > > > > + /* > > > > + * DSC and PSR2 cannot be enabled simultaneously. If a > > > > requested > > > > + * resolution requires DSC to be enabled, priority is > > > > given to DSC > > > > + * over PSR2. > > > > + */ > > > > + if (crtc_state->dsc_params.compression_enable) { > > > > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is > > > > enabled\n"); > > > > + return false; > > > > + } > > > > > > one concern I had when I first saw this patch is the order, but > > > I saw that psr compute config is the last one inside dp compute > > > config, > > Do something more to ensure that order stays as it is? A warn if both > > get enabled, or a comment in intel_dp.c perhaps. That is what we do for > > drrs and psr. > > hmm... that's a good idea. Are you suggesting a Warning after psr_compute_config if psr and dsc both are enabled? Manasi > > > > > > so we are good... > > > > > > only "concern" now is about PSR1 restrictions. > > > > > > But if not restriction with PSR1 and VSC: > > > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > > > > > > > + > > > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > > > { > > > > psr_max_h = 4096; > > > > psr_max_v = 2304; > > > > -- > > > > 2.7.4 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (12 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare ` (16 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Manasi Navare, Gaurav K Singh, dri-devel From: Gaurav K Singh <gaurav.k.singh@intel.com> DSC specification defines linebuf_depth which contains the line buffer bit depth used to generate the bitstream. These values are defined as per Table 4.1 in DSC 1.2 spec v2 (From Manasi): * Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2 Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- include/drm/drm_dsc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index 30adc15..4cfcd03 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -56,6 +56,9 @@ #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 #define DSC_PPS_NATIVE_420_SHIFT 1 +#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 +#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 +#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 /* Configuration for a single Rate Control model range */ struct dsc_rc_range_parameters { -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (13 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-28 22:18 ` Srivatsa, Anusha 2018-09-05 20:04 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare ` (15 subsequent siblings) 30 siblings, 2 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx From: Gaurav K Singh <gaurav.k.singh@intel.com> This patches does the following: 1. This patch defines all the DSC parameters as per the VESA DSC specification. These are stored in the encoder and used to compute the PPS parameters to be sent to the Sink. 2. Compute all the DSC parameters which are derived from DSC state of intel_crtc_state. 3. Compute all parameters that are VESA DSC specific This computation happens in the atomic check phase during compute_config() to validate if display stream compression can be enabled for the requested mode. v5 (From Manasi): * Add logic to limit the max line buf depth for DSC 1.1 to 13 as per DSC 1.1 spec * Fix dim checkpatch warnings/checks v4 (From Gaurav): * Rebase on latest drm tip * rename variable name(Manasi) * Populate linebuf_depth variable(Manasi) v3 (From Gaurav): * Rebase my previous patches on top of Manasi's latest patch series * Using >>n rather than /2^n (Manasi) * Change the commit message to explain what the patch is doing(Gaurav) Fixed review comments from Ville: * Don't use macro TWOS_COMPLEMENT * Mention in comment about the source of RC params * Return directly from case statements * Using single asssignment for assigning rc_range_params * Using <<n rather than *2^n and removing the comments about the fixed point numbers v2 (From Manasi): * Update logic for minor version to consider the dpcd value and what supported by the HW platform * Use DRM DSC config struct instead of intel_dp struct * Move the DSC constants to DRM DSC header file * Use u16, u8 where bigger data types not needed * * Compute the DSC parameters as part of DSC compute config since the computation can fail (Manasi) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/intel_dp.c | 7 + drivers/gpu/drm/i915/intel_drv.h | 4 + drivers/gpu/drm/i915/intel_vdsc.c | 455 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_dp_helper.h | 3 + include/drm/drm_dsc.h | 2 +- 6 files changed, 472 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5794f10..deaf2d4 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \ intel_sdvo.o \ intel_tv.o \ vlv_dsi.o \ - vlv_dsi_pll.o + vlv_dsi_pll.o \ + intel_vdsc.o # Post-mortem debug and GPU hang state capture i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7132f52..dc0a3c2 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return false; } } + if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d" + "Compressed BPP = %d\n", + pipe_config->pipe_bpp, + pipe_config->dsc_params.compressed_bpp); + return false; + } pipe_config->dsc_params.compression_enable = true; DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " "Compressed Bpp = %d Slice Count = %d\n", diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index b7c2652..33cc777 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, int mode_hdisplay); +/* intel_vdsc.c */ +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config); + static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { return ~((1 << lane_count) - 1) & 0xf; diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c new file mode 100644 index 0000000..ecd270c --- /dev/null +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -0,0 +1,455 @@ +/* + * Copyright © 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Gaurav K Singh <gaurav.k.singh@intel.com> + * Manasi Navare <manasi.d.navare@intel.com> + */ + +#include <drm/drmP.h> +#include <drm/i915_drm.h> +#include "i915_drv.h" +#include "intel_drv.h" + +enum ROW_INDEX_BPP { + ROW_INDEX_6BPP = 0, + ROW_INDEX_8BPP, + ROW_INDEX_10BPP, + ROW_INDEX_12BPP, + ROW_INDEX_15BPP, + MAX_ROW_INDEX +}; + +enum COLUMN_INDEX_BPC { + COLUMN_INDEX_8BPC = 0, + COLUMN_INDEX_10BPC, + COLUMN_INDEX_12BPC, + COLUMN_INDEX_14BPC, + COLUMN_INDEX_16BPC, + MAX_COLUMN_INDEX +}; + +#define DSC_SUPPORTED_VERSION_MIN 1 + +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ +static u16 rc_buf_thresh[] = { + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, + 7744, 7872, 8000, 8064 +}; + +struct rc_parameters { + u16 initial_xmit_delay; + u8 first_line_bpg_offset; + u16 initial_offset; + u8 flatness_min_qp; + u8 flatness_max_qp; + u8 rc_quant_incr_limit0; + u8 rc_quant_incr_limit1; + struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; +}; + +/* + * Selected Rate Control Related Parameter Recommended Values + * from DSC_v1.11 spec & C Model release: DSC_model_20161212 + */ +static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { +{ + /* 6BPP/8BPC */ + { 768, 15, 6144, 3, 13, 11, 11, { + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } + } + }, + /* 6BPP/10BPC */ + { 768, 15, 6144, 7, 17, 15, 15, { + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, + { 17, 18, -12 } + } + }, + /* 6BPP/12BPC */ + { 768, 15, 6144, 11, 21, 19, 19, { + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, + { 21, 22, -12 } + } + }, + /* 6BPP/14BPC */ + { 768, 15, 6144, 15, 25, 23, 27, { + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, + { 25, 26, -12 } + } + }, + /* 6BPP/16BPC */ + { 768, 15, 6144, 19, 29, 27, 27, { + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, + { 29, 30, -12 } + } + }, +}, +{ + /* 8BPP/8BPC */ + { 512, 12, 6144, 3, 12, 11, 11, { + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + }, + /* 8BPP/10BPC */ + { 512, 12, 6144, 7, 16, 15, 15, { + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + }, + /* 8BPP/12BPC */ + { 512, 12, 6144, 11, 20, 19, 19, { + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + }, + /* 8BPP/14BPC */ + { 512, 12, 6144, 15, 24, 23, 23, { + { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, + { 24, 25, -12 } + } + }, + /* 8BPP/16BPC */ + { 512, 12, 6144, 19, 28, 27, 27, { + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, + { 28, 29, -12 } + } + }, +}, +{ + /* 10BPP/8BPC */ + { 410, 15, 5632, 3, 12, 11, 11, { + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } + } + }, + /* 10BPP/10BPC */ + { 410, 15, 5632, 7, 16, 15, 15, { + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } + } + }, + /* 10BPP/12BPC */ + { 410, 15, 5632, 11, 20, 19, 19, { + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, + { 19, 20, -12 } + } + }, + /* 10BPP/14BPC */ + { 410, 15, 5632, 15, 24, 23, 23, { + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, + { 23, 24, -12 } + } + }, + /* 10BPP/16BPC */ + { 410, 15, 5632, 19, 28, 27, 27, { + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, + { 27, 28, -12 } + } + }, +}, +{ + /* 12BPP/8BPC */ + { 341, 15, 2048, 3, 12, 11, 11, { + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + }, + /* 12BPP/10BPC */ + { 341, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + }, + /* 12BPP/12BPC */ + { 341, 15, 2048, 11, 20, 19, 19, { + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + }, + /* 12BPP/14BPC */ + { 341, 15, 2048, 15, 24, 23, 23, { + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, + { 22, 23, -12 } + } + }, + /* 12BPP/16BPC */ + { 341, 15, 2048, 19, 28, 27, 27, { + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, + { 26, 27, -12 } + } + }, +}, +{ + /* 15BPP/8BPC */ + { 273, 15, 2048, 3, 12, 11, 11, { + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } + } + }, + /* 15BPP/10BPC */ + { 273, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } + } + }, + /* 15BPP/12BPC */ + { 273, 15, 2048, 11, 20, 19, 19, { + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, + { 16, 17, -12 } + } + }, + /* 15BPP/14BPC */ + { 273, 15, 2048, 15, 24, 23, 23, { + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, + { 20, 21, -12 } + } + }, + /* 15BPP/16BPC */ + { 273, 15, 2048, 19, 28, 27, 27, { + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, + { 24, 25, -12 } + } + } +} +}; + +static int get_row_index_for_rc_params(u16 compressed_bpp) +{ + switch (compressed_bpp) { + case 6: + return ROW_INDEX_6BPP; + case 8: + return ROW_INDEX_8BPP; + case 10: + return ROW_INDEX_10BPP; + case 12: + return ROW_INDEX_12BPP; + case 15: + return ROW_INDEX_15BPP; + default: + return -EINVAL; + } +} + +static int get_column_index_for_rc_params(u8 bits_per_component) +{ + switch (bits_per_component) { + case 8: + return COLUMN_INDEX_8BPC; + case 10: + return COLUMN_INDEX_10BPC; + case 12: + return COLUMN_INDEX_12BPC; + case 14: + return COLUMN_INDEX_14BPC; + case 16: + return COLUMN_INDEX_16BPC; + default: + return -EINVAL; + } +} + +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config) +{ + struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; + u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; + u8 i = 0; + u8 row_index = 0; + u8 column_index = 0; + u8 line_buf_depth = 0; + + vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; + vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; + vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, + pipe_config->dsc_params.slice_count); + /* + * Slice Height of 8 works for all currently available panels. So start + * with that if pic_height is an integral multiple of 8. + * Eventually add logic to try multiple slice heights. + */ + if (vdsc_cfg->pic_height % 8 == 0) + vdsc_cfg->slice_height = 8; + else if (vdsc_cfg->pic_height % 4 == 0) + vdsc_cfg->slice_height = 4; + else + vdsc_cfg->slice_height = 2; + + /* Values filled from DSC Sink DPCD */ + vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & + DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; + vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN, + (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & + DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); + + vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & + DP_DSC_RGB; + + line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); + if (vdsc_cfg->dsc_version_minor == 2) + vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? + DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; + else + vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? + DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; + + /* Gen 11 does not support YCbCr */ + vdsc_cfg->enable422 = false; + /* Gen 11 does not support VBR */ + vdsc_cfg->vbr_enable = false; + vdsc_cfg->block_pred_enable = + intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & + DP_DSC_BLK_PREDICTION_IS_SUPPORTED; + + /* Gen 11 only supports integral values of bpp */ + vdsc_cfg->bits_per_pixel = compressed_bpp << 4; + vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; + + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { + /* + * six 0s are appended to the lsb of each threshold value + * internally in h/w. + * Only 8 bits are allowed for programming RcBufThreshold + */ + vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; + } + + /* + * For 6bpp, RC Buffer threshold 12 and 13 need a different value + * as per C Model + */ + if (compressed_bpp == 6) { + vdsc_cfg->rc_buf_thresh[12] = 0x7C; + vdsc_cfg->rc_buf_thresh[13] = 0x7D; + } + + row_index = get_row_index_for_rc_params(compressed_bpp); + column_index = + get_column_index_for_rc_params(vdsc_cfg->bits_per_component); + + if (row_index < 0 || column_index < 0) + return -EINVAL; + + vdsc_cfg->first_line_bpg_offset = + rc_params[row_index][column_index].first_line_bpg_offset; + vdsc_cfg->initial_xmit_delay = + rc_params[row_index][column_index].initial_xmit_delay; + vdsc_cfg->initial_offset = + rc_params[row_index][column_index].initial_offset; + vdsc_cfg->flatness_min_qp = + rc_params[row_index][column_index].flatness_min_qp; + vdsc_cfg->flatness_max_qp = + rc_params[row_index][column_index].flatness_max_qp; + vdsc_cfg->rc_quant_incr_limit0 = + rc_params[row_index][column_index].rc_quant_incr_limit0; + vdsc_cfg->rc_quant_incr_limit1 = + rc_params[row_index][column_index].rc_quant_incr_limit1; + + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) + vdsc_cfg->rc_range_params[i] = + rc_params[row_index][column_index].rc_range_params[i]; + + /* + * BitsPerComponent value determines mux_word_size: + * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits + * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to + * 48 bits + */ + if (vdsc_cfg->bits_per_component == 8 || + vdsc_cfg->bits_per_component == 10) + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; + else if (vdsc_cfg->bits_per_component == 12) + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; + + /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ + vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / + (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); + + return 0; +} diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 0cf2407..f178933 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -186,6 +186,9 @@ #define DP_GUID 0x030 /* 1.2 */ +#define DP_DSC_RC_PIXELS_PER_GROUP 3 +#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 + #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index 4cfcd03..796c798 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -67,7 +67,7 @@ struct dsc_rc_range_parameters { /* Max Quantization Parameters allowed for this range */ u8 range_max_qp; /* Bits/group offset to apply to target for this group */ - u8 range_bpg_offset; + s8 range_bpg_offset; }; struct drm_dsc_config { -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params 2018-07-31 21:07 ` [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare @ 2018-08-28 22:18 ` Srivatsa, Anusha 2018-08-28 22:47 ` Manasi Navare 2018-09-05 20:04 ` Manasi Navare 1 sibling, 1 reply; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-28 22:18 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Singh, Gaurav K <gaurav.k.singh@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Navare, Manasi D ><manasi.d.navare@intel.com> >Subject: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params > >From: Gaurav K Singh <gaurav.k.singh@intel.com> > >This patches does the following: > >1. This patch defines all the DSC parameters as per the VESA DSC specification. >These are stored in the encoder and used to compute the PPS parameters to be >sent to the Sink. >2. Compute all the DSC parameters which are derived from DSC state of >intel_crtc_state. >3. Compute all parameters that are VESA DSC specific > >This computation happens in the atomic check phase during >compute_config() to validate if display stream compression can be enabled for >the requested mode. > >v5 (From Manasi): >* Add logic to limit the max line buf depth for DSC 1.1 to 13 as per DSC 1.1 spec >* Fix dim checkpatch warnings/checks > >v4 (From Gaurav): >* Rebase on latest drm tip >* rename variable name(Manasi) >* Populate linebuf_depth variable(Manasi) > >v3 (From Gaurav): >* Rebase my previous patches on top of Manasi's latest patch series >* Using >>n rather than /2^n (Manasi) >* Change the commit message to explain what the patch is doing(Gaurav) > >Fixed review comments from Ville: >* Don't use macro TWOS_COMPLEMENT >* Mention in comment about the source of RC params >* Return directly from case statements >* Using single asssignment for assigning rc_range_params >* Using <<n rather than *2^n and removing the comments about the fixed point >numbers > >v2 (From Manasi): >* Update logic for minor version to consider the dpcd value and what supported >by the HW platform >* Use DRM DSC config struct instead of intel_dp struct >* Move the DSC constants to DRM DSC header file >* Use u16, u8 where bigger data types not needed >* * Compute the DSC parameters as part of DSC compute config since the >computation can fail (Manasi) > >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> >--- > drivers/gpu/drm/i915/Makefile | 3 +- > drivers/gpu/drm/i915/intel_dp.c | 7 + > drivers/gpu/drm/i915/intel_drv.h | 4 + > drivers/gpu/drm/i915/intel_vdsc.c | 455 >++++++++++++++++++++++++++++++++++++++ > include/drm/drm_dp_helper.h | 3 + > include/drm/drm_dsc.h | 2 +- > 6 files changed, 472 insertions(+), 2 deletions(-) create mode 100644 >drivers/gpu/drm/i915/intel_vdsc.c > >diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile >index 5794f10..deaf2d4 100644 >--- a/drivers/gpu/drm/i915/Makefile >+++ b/drivers/gpu/drm/i915/Makefile >@@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \ > intel_sdvo.o \ > intel_tv.o \ > vlv_dsi.o \ >- vlv_dsi_pll.o >+ vlv_dsi_pll.o \ >+ intel_vdsc.o > > # Post-mortem debug and GPU hang state capture > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git >a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index >7132f52..dc0a3c2 100644 >--- a/drivers/gpu/drm/i915/intel_dp.c >+++ b/drivers/gpu/drm/i915/intel_dp.c >@@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct >intel_dp *intel_dp, > return false; > } > } >+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { >+ DRM_ERROR("Cannot compute valid DSC parameters for Input >Bpp = %d" >+ "Compressed BPP = %d\n", >+ pipe_config->pipe_bpp, >+ pipe_config->dsc_params.compressed_bpp); >+ return false; >+ } > pipe_config->dsc_params.compression_enable = true; > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > "Compressed Bpp = %d Slice Count = %d\n", diff --git >a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >index b7c2652..33cc777 100644 >--- a/drivers/gpu/drm/i915/intel_drv.h >+++ b/drivers/gpu/drm/i915/intel_drv.h >@@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, >uint8_t lane_count, uint8_t intel_dp_dsc_get_slice_count(struct intel_dp >*intel_dp, int mode_clock, > int mode_hdisplay); > >+/* intel_vdsc.c */ >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, >+ struct intel_crtc_state *pipe_config); >+ > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { > return ~((1 << lane_count) - 1) & 0xf; diff --git >a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c >new file mode 100644 >index 0000000..ecd270c >--- /dev/null >+++ b/drivers/gpu/drm/i915/intel_vdsc.c >@@ -0,0 +1,455 @@ >+/* >+ * Copyright © 2018 Intel Corporation >+ * >+ * Permission is hereby granted, free of charge, to any person >+obtaining a >+ * copy of this software and associated documentation files (the >+"Software"), >+ * to deal in the Software without restriction, including without >+limitation >+ * the rights to use, copy, modify, merge, publish, distribute, >+sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom >+the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice (including the >+next >+ * paragraph) shall be included in all copies or substantial portions >+of the >+ * Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >+EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >+MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO >EVENT >+SHALL >+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, >DAMAGES OR >+OTHER >+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ARISING >+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >OTHER >+ * DEALINGS IN THE SOFTWARE. >+ * >+ * Author: Gaurav K Singh <gaurav.k.singh@intel.com> >+ * Manasi Navare <manasi.d.navare@intel.com> >+ */ >+ >+#include <drm/drmP.h> >+#include <drm/i915_drm.h> >+#include "i915_drv.h" >+#include "intel_drv.h" >+ >+enum ROW_INDEX_BPP { >+ ROW_INDEX_6BPP = 0, >+ ROW_INDEX_8BPP, >+ ROW_INDEX_10BPP, >+ ROW_INDEX_12BPP, >+ ROW_INDEX_15BPP, >+ MAX_ROW_INDEX >+}; >+ >+enum COLUMN_INDEX_BPC { >+ COLUMN_INDEX_8BPC = 0, >+ COLUMN_INDEX_10BPC, >+ COLUMN_INDEX_12BPC, >+ COLUMN_INDEX_14BPC, >+ COLUMN_INDEX_16BPC, >+ MAX_COLUMN_INDEX >+}; >+ >+#define DSC_SUPPORTED_VERSION_MIN 1 >+ >+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically >+constant */ static u16 rc_buf_thresh[] = { >+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, >+ 7744, 7872, 8000, 8064 >+}; >+ >+struct rc_parameters { >+ u16 initial_xmit_delay; >+ u8 first_line_bpg_offset; >+ u16 initial_offset; >+ u8 flatness_min_qp; >+ u8 flatness_max_qp; >+ u8 rc_quant_incr_limit0; >+ u8 rc_quant_incr_limit1; >+ struct dsc_rc_range_parameters >rc_range_params[DSC_NUM_BUF_RANGES]; >+}; >+ >+/* >+ * Selected Rate Control Related Parameter Recommended Values >+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212 */ static >+struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { { >+ /* 6BPP/8BPC */ >+ { 768, 15, 6144, 3, 13, 11, 11, { >+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, >+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, >+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, >+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } >+ } >+ }, >+ /* 6BPP/10BPC */ >+ { 768, 15, 6144, 7, 17, 15, 15, { >+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, >+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, >+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, >+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, >+ { 17, 18, -12 } >+ } >+ }, >+ /* 6BPP/12BPC */ >+ { 768, 15, 6144, 11, 21, 19, 19, { >+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, >+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, >+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, >+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, >+ { 21, 22, -12 } >+ } >+ }, >+ /* 6BPP/14BPC */ >+ { 768, 15, 6144, 15, 25, 23, 27, { >+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, >+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, >+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, >+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, >+ { 25, 26, -12 } >+ } >+ }, >+ /* 6BPP/16BPC */ >+ { 768, 15, 6144, 19, 29, 27, 27, { >+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, >+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, >+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, >+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, >+ { 29, 30, -12 } >+ } >+ }, >+}, >+{ >+ /* 8BPP/8BPC */ >+ { 512, 12, 6144, 3, 12, 11, 11, { >+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, >+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } >+ } >+ }, >+ /* 8BPP/10BPC */ >+ { 512, 12, 6144, 7, 16, 15, 15, { >+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } >+ } >+ }, >+ /* 8BPP/12BPC */ >+ { 512, 12, 6144, 11, 20, 19, 19, { >+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, >+ { 21, 23, -12 } >+ } >+ }, >+ /* 8BPP/14BPC */ >+ { 512, 12, 6144, 15, 24, 23, 23, { >+ { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, >+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, >+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, >+ { 24, 25, -12 } >+ } >+ }, >+ /* 8BPP/16BPC */ >+ { 512, 12, 6144, 19, 28, 27, 27, { >+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, >+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, >+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, >+ { 28, 29, -12 } >+ } >+ }, >+}, >+{ >+ /* 10BPP/8BPC */ >+ { 410, 15, 5632, 3, 12, 11, 11, { >+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, >+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, >+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } >+ } >+ }, >+ /* 10BPP/10BPC */ >+ { 410, 15, 5632, 7, 16, 15, 15, { >+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, >+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, >+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } >+ } >+ }, >+ /* 10BPP/12BPC */ >+ { 410, 15, 5632, 11, 20, 19, 19, { >+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, >+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, >+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, >+ { 19, 20, -12 } >+ } >+ }, >+ /* 10BPP/14BPC */ >+ { 410, 15, 5632, 15, 24, 23, 23, { >+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, >+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, >+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, >+ { 23, 24, -12 } >+ } >+ }, >+ /* 10BPP/16BPC */ >+ { 410, 15, 5632, 19, 28, 27, 27, { >+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, >+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, >+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, >+ { 27, 28, -12 } >+ } >+ }, >+}, >+{ >+ /* 12BPP/8BPC */ >+ { 341, 15, 2048, 3, 12, 11, 11, { >+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, >+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } >+ } >+ }, >+ /* 12BPP/10BPC */ >+ { 341, 15, 2048, 7, 16, 15, 15, { >+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, >+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } >+ } >+ }, >+ /* 12BPP/12BPC */ >+ { 341, 15, 2048, 11, 20, 19, 19, { >+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, >+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, >+ { 21, 23, -12 } >+ } >+ }, >+ /* 12BPP/14BPC */ >+ { 341, 15, 2048, 15, 24, 23, 23, { >+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, >+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, >+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, >+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, >+ { 22, 23, -12 } >+ } >+ }, >+ /* 12BPP/16BPC */ >+ { 341, 15, 2048, 19, 28, 27, 27, { >+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, >+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, >+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, >+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, >+ { 26, 27, -12 } >+ } >+ }, >+}, >+{ >+ /* 15BPP/8BPC */ >+ { 273, 15, 2048, 3, 12, 11, 11, { >+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, >+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, >+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, >+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } >+ } >+ }, >+ /* 15BPP/10BPC */ >+ { 273, 15, 2048, 7, 16, 15, 15, { >+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, >+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, >+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, >+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } >+ } >+ }, >+ /* 15BPP/12BPC */ >+ { 273, 15, 2048, 11, 20, 19, 19, { >+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, >+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, >+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, >+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, >+ { 16, 17, -12 } >+ } >+ }, >+ /* 15BPP/14BPC */ >+ { 273, 15, 2048, 15, 24, 23, 23, { >+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, >+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, >+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, >+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, >+ { 20, 21, -12 } >+ } >+ }, >+ /* 15BPP/16BPC */ >+ { 273, 15, 2048, 19, 28, 27, 27, { >+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, >+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, >+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, >+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, >+ { 24, 25, -12 } >+ } >+ } >+} >+}; >+ >+static int get_row_index_for_rc_params(u16 compressed_bpp) { >+ switch (compressed_bpp) { >+ case 6: >+ return ROW_INDEX_6BPP; >+ case 8: >+ return ROW_INDEX_8BPP; >+ case 10: >+ return ROW_INDEX_10BPP; >+ case 12: >+ return ROW_INDEX_12BPP; >+ case 15: >+ return ROW_INDEX_15BPP; >+ default: >+ return -EINVAL; >+ } >+} >+ >+static int get_column_index_for_rc_params(u8 bits_per_component) { >+ switch (bits_per_component) { >+ case 8: >+ return COLUMN_INDEX_8BPC; >+ case 10: >+ return COLUMN_INDEX_10BPC; >+ case 12: >+ return COLUMN_INDEX_12BPC; >+ case 14: >+ return COLUMN_INDEX_14BPC; >+ case 16: >+ return COLUMN_INDEX_16BPC; >+ default: >+ return -EINVAL; >+ } >+} >+ >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, >+ struct intel_crtc_state *pipe_config) { >+ struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; >+ u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; >+ u8 i = 0; >+ u8 row_index = 0; >+ u8 column_index = 0; >+ u8 line_buf_depth = 0; >+ >+ vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; >+ vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; >+ vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, >+ pipe_config- >>dsc_params.slice_count); >+ /* >+ * Slice Height of 8 works for all currently available panels. So start >+ * with that if pic_height is an integral multiple of 8. >+ * Eventually add logic to try multiple slice heights. >+ */ >+ if (vdsc_cfg->pic_height % 8 == 0) >+ vdsc_cfg->slice_height = 8; >+ else if (vdsc_cfg->pic_height % 4 == 0) >+ vdsc_cfg->slice_height = 4; >+ else >+ vdsc_cfg->slice_height = 2; >+ >+ /* Values filled from DSC Sink DPCD */ >+ vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - >DP_DSC_SUPPORT] & >+ DP_DSC_MAJOR_MASK) >> >DP_DSC_MAJOR_SHIFT; >+ vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN, >+ (intel_dp->dsc_dpcd[DP_DSC_REV - >DP_DSC_SUPPORT] & >+ DP_DSC_MINOR_MASK) >> >DP_DSC_MINOR_SHIFT); >+ >+ vdsc_cfg->convert_rgb = intel_dp- >>dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & >+ DP_DSC_RGB; >+ >+ line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); >+ if (vdsc_cfg->dsc_version_minor == 2) >+ vdsc_cfg->line_buf_depth = (line_buf_depth == >DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? >+ DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; Shouldn't this be line_buf_depth >= DSC_1_2_MAX_LINEBUF_DEPTH_BITS? >+ else >+ vdsc_cfg->line_buf_depth = (line_buf_depth > Line_buf_depth >= DSC_1_1_MAX_LINEBUF_DEPTH_BITS?? Anusha >DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? >+ DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; >+ >+ /* Gen 11 does not support YCbCr */ >+ vdsc_cfg->enable422 = false; >+ /* Gen 11 does not support VBR */ >+ vdsc_cfg->vbr_enable = false; >+ vdsc_cfg->block_pred_enable = >+ intel_dp- >>dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & >+ DP_DSC_BLK_PREDICTION_IS_SUPPORTED; >+ >+ /* Gen 11 only supports integral values of bpp */ >+ vdsc_cfg->bits_per_pixel = compressed_bpp << 4; >+ vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; >+ >+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { >+ /* >+ * six 0s are appended to the lsb of each threshold value >+ * internally in h/w. >+ * Only 8 bits are allowed for programming RcBufThreshold >+ */ >+ vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; >+ } >+ >+ /* >+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value >+ * as per C Model >+ */ >+ if (compressed_bpp == 6) { >+ vdsc_cfg->rc_buf_thresh[12] = 0x7C; >+ vdsc_cfg->rc_buf_thresh[13] = 0x7D; >+ } >+ >+ row_index = get_row_index_for_rc_params(compressed_bpp); >+ column_index = >+ get_column_index_for_rc_params(vdsc_cfg- >>bits_per_component); >+ >+ if (row_index < 0 || column_index < 0) >+ return -EINVAL; >+ >+ vdsc_cfg->first_line_bpg_offset = >+ rc_params[row_index][column_index].first_line_bpg_offset; >+ vdsc_cfg->initial_xmit_delay = >+ rc_params[row_index][column_index].initial_xmit_delay; >+ vdsc_cfg->initial_offset = >+ rc_params[row_index][column_index].initial_offset; >+ vdsc_cfg->flatness_min_qp = >+ rc_params[row_index][column_index].flatness_min_qp; >+ vdsc_cfg->flatness_max_qp = >+ rc_params[row_index][column_index].flatness_max_qp; >+ vdsc_cfg->rc_quant_incr_limit0 = >+ rc_params[row_index][column_index].rc_quant_incr_limit0; >+ vdsc_cfg->rc_quant_incr_limit1 = >+ rc_params[row_index][column_index].rc_quant_incr_limit1; >+ >+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) >+ vdsc_cfg->rc_range_params[i] = >+ > rc_params[row_index][column_index].rc_range_params[i]; >+ >+ /* >+ * BitsPerComponent value determines mux_word_size: >+ * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 >bits >+ * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to >+ * 48 bits >+ */ >+ if (vdsc_cfg->bits_per_component == 8 || >+ vdsc_cfg->bits_per_component == 10) >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; >+ else if (vdsc_cfg->bits_per_component == 12) >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; >+ >+ /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ >+ vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / >+ (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); >+ >+ return 0; >+} >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index >0cf2407..f178933 100644 >--- a/include/drm/drm_dp_helper.h >+++ b/include/drm/drm_dp_helper.h >@@ -186,6 +186,9 @@ > > #define DP_GUID 0x030 /* 1.2 */ > >+#define DP_DSC_RC_PIXELS_PER_GROUP 3 >+#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 >+ > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index >4cfcd03..796c798 100644 >--- a/include/drm/drm_dsc.h >+++ b/include/drm/drm_dsc.h >@@ -67,7 +67,7 @@ struct dsc_rc_range_parameters { > /* Max Quantization Parameters allowed for this range */ > u8 range_max_qp; > /* Bits/group offset to apply to target for this group */ >- u8 range_bpg_offset; >+ s8 range_bpg_offset; > }; > > struct drm_dsc_config { >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params 2018-08-28 22:18 ` Srivatsa, Anusha @ 2018-08-28 22:47 ` Manasi Navare 2018-08-28 23:31 ` Manasi Navare 0 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-08-28 22:47 UTC (permalink / raw) To: Srivatsa, Anusha; +Cc: intel-gfx On Tue, Aug 28, 2018 at 03:18:56PM -0700, Srivatsa, Anusha wrote: > > > >-----Original Message----- > >From: Navare, Manasi D > >Sent: Tuesday, July 31, 2018 2:07 PM > >To: intel-gfx@lists.freedesktop.org > >Cc: Singh, Gaurav K <gaurav.k.singh@intel.com>; Jani Nikula > ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; > >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Navare, Manasi D > ><manasi.d.navare@intel.com> > >Subject: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params > > > >From: Gaurav K Singh <gaurav.k.singh@intel.com> > > > >This patches does the following: > > > >1. This patch defines all the DSC parameters as per the VESA DSC specification. > >These are stored in the encoder and used to compute the PPS parameters to be > >sent to the Sink. > >2. Compute all the DSC parameters which are derived from DSC state of > >intel_crtc_state. > >3. Compute all parameters that are VESA DSC specific > > > >This computation happens in the atomic check phase during > >compute_config() to validate if display stream compression can be enabled for > >the requested mode. > > > >v5 (From Manasi): > >* Add logic to limit the max line buf depth for DSC 1.1 to 13 as per DSC 1.1 spec > >* Fix dim checkpatch warnings/checks > > > >v4 (From Gaurav): > >* Rebase on latest drm tip > >* rename variable name(Manasi) > >* Populate linebuf_depth variable(Manasi) > > > >v3 (From Gaurav): > >* Rebase my previous patches on top of Manasi's latest patch series > >* Using >>n rather than /2^n (Manasi) > >* Change the commit message to explain what the patch is doing(Gaurav) > > > >Fixed review comments from Ville: > >* Don't use macro TWOS_COMPLEMENT > >* Mention in comment about the source of RC params > >* Return directly from case statements > >* Using single asssignment for assigning rc_range_params > >* Using <<n rather than *2^n and removing the comments about the fixed point > >numbers > > > >v2 (From Manasi): > >* Update logic for minor version to consider the dpcd value and what supported > >by the HW platform > >* Use DRM DSC config struct instead of intel_dp struct > >* Move the DSC constants to DRM DSC header file > >* Use u16, u8 where bigger data types not needed > >* * Compute the DSC parameters as part of DSC compute config since the > >computation can fail (Manasi) > > > >Cc: Jani Nikula <jani.nikula@linux.intel.com> > >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > >Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > >--- > > drivers/gpu/drm/i915/Makefile | 3 +- > > drivers/gpu/drm/i915/intel_dp.c | 7 + > > drivers/gpu/drm/i915/intel_drv.h | 4 + > > drivers/gpu/drm/i915/intel_vdsc.c | 455 > >++++++++++++++++++++++++++++++++++++++ > > include/drm/drm_dp_helper.h | 3 + > > include/drm/drm_dsc.h | 2 +- > > 6 files changed, 472 insertions(+), 2 deletions(-) create mode 100644 > >drivers/gpu/drm/i915/intel_vdsc.c > > > >diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > >index 5794f10..deaf2d4 100644 > >--- a/drivers/gpu/drm/i915/Makefile > >+++ b/drivers/gpu/drm/i915/Makefile > >@@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \ > > intel_sdvo.o \ > > intel_tv.o \ > > vlv_dsi.o \ > >- vlv_dsi_pll.o > >+ vlv_dsi_pll.o \ > >+ intel_vdsc.o > > > > # Post-mortem debug and GPU hang state capture > > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git > >a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index > >7132f52..dc0a3c2 100644 > >--- a/drivers/gpu/drm/i915/intel_dp.c > >+++ b/drivers/gpu/drm/i915/intel_dp.c > >@@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct > >intel_dp *intel_dp, > > return false; > > } > > } > >+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { > >+ DRM_ERROR("Cannot compute valid DSC parameters for Input > >Bpp = %d" > >+ "Compressed BPP = %d\n", > >+ pipe_config->pipe_bpp, > >+ pipe_config->dsc_params.compressed_bpp); > >+ return false; > >+ } > > pipe_config->dsc_params.compression_enable = true; > > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > > "Compressed Bpp = %d Slice Count = %d\n", diff --git > >a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > >index b7c2652..33cc777 100644 > >--- a/drivers/gpu/drm/i915/intel_drv.h > >+++ b/drivers/gpu/drm/i915/intel_drv.h > >@@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, > >uint8_t lane_count, uint8_t intel_dp_dsc_get_slice_count(struct intel_dp > >*intel_dp, int mode_clock, > > int mode_hdisplay); > > > >+/* intel_vdsc.c */ > >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > >+ struct intel_crtc_state *pipe_config); > >+ > > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { > > return ~((1 << lane_count) - 1) & 0xf; diff --git > >a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > >new file mode 100644 > >index 0000000..ecd270c > >--- /dev/null > >+++ b/drivers/gpu/drm/i915/intel_vdsc.c > >@@ -0,0 +1,455 @@ > >+/* > >+ * Copyright © 2018 Intel Corporation > >+ * > >+ * Permission is hereby granted, free of charge, to any person > >+obtaining a > >+ * copy of this software and associated documentation files (the > >+"Software"), > >+ * to deal in the Software without restriction, including without > >+limitation > >+ * the rights to use, copy, modify, merge, publish, distribute, > >+sublicense, > >+ * and/or sell copies of the Software, and to permit persons to whom > >+the > >+ * Software is furnished to do so, subject to the following conditions: > >+ * > >+ * The above copyright notice and this permission notice (including the > >+next > >+ * paragraph) shall be included in all copies or substantial portions > >+of the > >+ * Software. > >+ * > >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > >+EXPRESS OR > >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > >+MERCHANTABILITY, > >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO > >EVENT > >+SHALL > >+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, > >DAMAGES OR > >+OTHER > >+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > >+ARISING > >+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > >OTHER > >+ * DEALINGS IN THE SOFTWARE. > >+ * > >+ * Author: Gaurav K Singh <gaurav.k.singh@intel.com> > >+ * Manasi Navare <manasi.d.navare@intel.com> > >+ */ > >+ > >+#include <drm/drmP.h> > >+#include <drm/i915_drm.h> > >+#include "i915_drv.h" > >+#include "intel_drv.h" > >+ > >+enum ROW_INDEX_BPP { > >+ ROW_INDEX_6BPP = 0, > >+ ROW_INDEX_8BPP, > >+ ROW_INDEX_10BPP, > >+ ROW_INDEX_12BPP, > >+ ROW_INDEX_15BPP, > >+ MAX_ROW_INDEX > >+}; > >+ > >+enum COLUMN_INDEX_BPC { > >+ COLUMN_INDEX_8BPC = 0, > >+ COLUMN_INDEX_10BPC, > >+ COLUMN_INDEX_12BPC, > >+ COLUMN_INDEX_14BPC, > >+ COLUMN_INDEX_16BPC, > >+ MAX_COLUMN_INDEX > >+}; > >+ > >+#define DSC_SUPPORTED_VERSION_MIN 1 > >+ > >+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically > >+constant */ static u16 rc_buf_thresh[] = { > >+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, > >+ 7744, 7872, 8000, 8064 > >+}; > >+ > >+struct rc_parameters { > >+ u16 initial_xmit_delay; > >+ u8 first_line_bpg_offset; > >+ u16 initial_offset; > >+ u8 flatness_min_qp; > >+ u8 flatness_max_qp; > >+ u8 rc_quant_incr_limit0; > >+ u8 rc_quant_incr_limit1; > >+ struct dsc_rc_range_parameters > >rc_range_params[DSC_NUM_BUF_RANGES]; > >+}; > >+ > >+/* > >+ * Selected Rate Control Related Parameter Recommended Values > >+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212 */ static > >+struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { { > >+ /* 6BPP/8BPC */ > >+ { 768, 15, 6144, 3, 13, 11, 11, { > >+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, > >+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, > >+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, > >+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } > >+ } > >+ }, > >+ /* 6BPP/10BPC */ > >+ { 768, 15, 6144, 7, 17, 15, 15, { > >+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, > >+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, > >+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, > >+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, > >+ { 17, 18, -12 } > >+ } > >+ }, > >+ /* 6BPP/12BPC */ > >+ { 768, 15, 6144, 11, 21, 19, 19, { > >+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, > >+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, > >+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, > >+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, > >+ { 21, 22, -12 } > >+ } > >+ }, > >+ /* 6BPP/14BPC */ > >+ { 768, 15, 6144, 15, 25, 23, 27, { > >+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, > >+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, > >+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, > >+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, > >+ { 25, 26, -12 } > >+ } > >+ }, > >+ /* 6BPP/16BPC */ > >+ { 768, 15, 6144, 19, 29, 27, 27, { > >+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, > >+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, > >+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, > >+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, > >+ { 29, 30, -12 } > >+ } > >+ }, > >+}, > >+{ > >+ /* 8BPP/8BPC */ > >+ { 512, 12, 6144, 3, 12, 11, 11, { > >+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, > >+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > >+ } > >+ }, > >+ /* 8BPP/10BPC */ > >+ { 512, 12, 6144, 7, 16, 15, 15, { > >+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > >+ } > >+ }, > >+ /* 8BPP/12BPC */ > >+ { 512, 12, 6144, 11, 20, 19, 19, { > >+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, > >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > >+ { 21, 23, -12 } > >+ } > >+ }, > >+ /* 8BPP/14BPC */ > >+ { 512, 12, 6144, 15, 24, 23, 23, { > >+ { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, > >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > >+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, > >+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, > >+ { 24, 25, -12 } > >+ } > >+ }, > >+ /* 8BPP/16BPC */ > >+ { 512, 12, 6144, 19, 28, 27, 27, { > >+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, > >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > >+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, > >+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, > >+ { 28, 29, -12 } > >+ } > >+ }, > >+}, > >+{ > >+ /* 10BPP/8BPC */ > >+ { 410, 15, 5632, 3, 12, 11, 11, { > >+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, > >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > >+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, > >+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } > >+ } > >+ }, > >+ /* 10BPP/10BPC */ > >+ { 410, 15, 5632, 7, 16, 15, 15, { > >+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, > >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > >+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, > >+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } > >+ } > >+ }, > >+ /* 10BPP/12BPC */ > >+ { 410, 15, 5632, 11, 20, 19, 19, { > >+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, > >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > >+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, > >+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, > >+ { 19, 20, -12 } > >+ } > >+ }, > >+ /* 10BPP/14BPC */ > >+ { 410, 15, 5632, 15, 24, 23, 23, { > >+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, > >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > >+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, > >+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, > >+ { 23, 24, -12 } > >+ } > >+ }, > >+ /* 10BPP/16BPC */ > >+ { 410, 15, 5632, 19, 28, 27, 27, { > >+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, > >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > >+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, > >+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, > >+ { 27, 28, -12 } > >+ } > >+ }, > >+}, > >+{ > >+ /* 12BPP/8BPC */ > >+ { 341, 15, 2048, 3, 12, 11, 11, { > >+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, > >+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > >+ } > >+ }, > >+ /* 12BPP/10BPC */ > >+ { 341, 15, 2048, 7, 16, 15, 15, { > >+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, > >+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > >+ } > >+ }, > >+ /* 12BPP/12BPC */ > >+ { 341, 15, 2048, 11, 20, 19, 19, { > >+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, > >+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > >+ { 21, 23, -12 } > >+ } > >+ }, > >+ /* 12BPP/14BPC */ > >+ { 341, 15, 2048, 15, 24, 23, 23, { > >+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, > >+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > >+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, > >+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, > >+ { 22, 23, -12 } > >+ } > >+ }, > >+ /* 12BPP/16BPC */ > >+ { 341, 15, 2048, 19, 28, 27, 27, { > >+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, > >+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > >+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, > >+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, > >+ { 26, 27, -12 } > >+ } > >+ }, > >+}, > >+{ > >+ /* 15BPP/8BPC */ > >+ { 273, 15, 2048, 3, 12, 11, 11, { > >+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, > >+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, > >+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, > >+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } > >+ } > >+ }, > >+ /* 15BPP/10BPC */ > >+ { 273, 15, 2048, 7, 16, 15, 15, { > >+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, > >+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, > >+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, > >+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } > >+ } > >+ }, > >+ /* 15BPP/12BPC */ > >+ { 273, 15, 2048, 11, 20, 19, 19, { > >+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, > >+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, > >+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, > >+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, > >+ { 16, 17, -12 } > >+ } > >+ }, > >+ /* 15BPP/14BPC */ > >+ { 273, 15, 2048, 15, 24, 23, 23, { > >+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, > >+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, > >+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, > >+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, > >+ { 20, 21, -12 } > >+ } > >+ }, > >+ /* 15BPP/16BPC */ > >+ { 273, 15, 2048, 19, 28, 27, 27, { > >+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, > >+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, > >+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, > >+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, > >+ { 24, 25, -12 } > >+ } > >+ } > >+} > >+}; > >+ > >+static int get_row_index_for_rc_params(u16 compressed_bpp) { > >+ switch (compressed_bpp) { > >+ case 6: > >+ return ROW_INDEX_6BPP; > >+ case 8: > >+ return ROW_INDEX_8BPP; > >+ case 10: > >+ return ROW_INDEX_10BPP; > >+ case 12: > >+ return ROW_INDEX_12BPP; > >+ case 15: > >+ return ROW_INDEX_15BPP; > >+ default: > >+ return -EINVAL; > >+ } > >+} > >+ > >+static int get_column_index_for_rc_params(u8 bits_per_component) { > >+ switch (bits_per_component) { > >+ case 8: > >+ return COLUMN_INDEX_8BPC; > >+ case 10: > >+ return COLUMN_INDEX_10BPC; > >+ case 12: > >+ return COLUMN_INDEX_12BPC; > >+ case 14: > >+ return COLUMN_INDEX_14BPC; > >+ case 16: > >+ return COLUMN_INDEX_16BPC; > >+ default: > >+ return -EINVAL; > >+ } > >+} > >+ > >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > >+ struct intel_crtc_state *pipe_config) { > >+ struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > >+ u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; > >+ u8 i = 0; > >+ u8 row_index = 0; > >+ u8 column_index = 0; > >+ u8 line_buf_depth = 0; > >+ > >+ vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; > >+ vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; > >+ vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > >+ pipe_config- > >>dsc_params.slice_count); > >+ /* > >+ * Slice Height of 8 works for all currently available panels. So start > >+ * with that if pic_height is an integral multiple of 8. > >+ * Eventually add logic to try multiple slice heights. > >+ */ > >+ if (vdsc_cfg->pic_height % 8 == 0) > >+ vdsc_cfg->slice_height = 8; > >+ else if (vdsc_cfg->pic_height % 4 == 0) > >+ vdsc_cfg->slice_height = 4; > >+ else > >+ vdsc_cfg->slice_height = 2; > >+ > >+ /* Values filled from DSC Sink DPCD */ > >+ vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - > >DP_DSC_SUPPORT] & > >+ DP_DSC_MAJOR_MASK) >> > >DP_DSC_MAJOR_SHIFT; > >+ vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN, > >+ (intel_dp->dsc_dpcd[DP_DSC_REV - > >DP_DSC_SUPPORT] & > >+ DP_DSC_MINOR_MASK) >> > >DP_DSC_MINOR_SHIFT); > >+ > >+ vdsc_cfg->convert_rgb = intel_dp- > >>dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & > >+ DP_DSC_RGB; > >+ > >+ line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); > >+ if (vdsc_cfg->dsc_version_minor == 2) > >+ vdsc_cfg->line_buf_depth = (line_buf_depth == > >DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? > >+ DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; > Shouldn't this be line_buf_depth >= DSC_1_2_MAX_LINEBUF_DEPTH_BITS? If you look at drm_dp_dsc_sink_line_buf_depth() function, it will only return maximum of 16. Greater than DSC_1_2_MAX_LINEBUF_DEPTH_BITS is not a valid value and the function will return 0 for that. > > >+ else > >+ vdsc_cfg->line_buf_depth = (line_buf_depth > > Line_buf_depth >= DSC_1_1_MAX_LINEBUF_DEPTH_BITS?? This should be only greater than since if its equal to the max then it can just use the maximum value. Manasi > > Anusha > >DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? > >+ DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; > >+ > >+ /* Gen 11 does not support YCbCr */ > >+ vdsc_cfg->enable422 = false; > >+ /* Gen 11 does not support VBR */ > >+ vdsc_cfg->vbr_enable = false; > >+ vdsc_cfg->block_pred_enable = > >+ intel_dp- > >>dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & > >+ DP_DSC_BLK_PREDICTION_IS_SUPPORTED; > >+ > >+ /* Gen 11 only supports integral values of bpp */ > >+ vdsc_cfg->bits_per_pixel = compressed_bpp << 4; > >+ vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; > >+ > >+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { > >+ /* > >+ * six 0s are appended to the lsb of each threshold value > >+ * internally in h/w. > >+ * Only 8 bits are allowed for programming RcBufThreshold > >+ */ > >+ vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; > >+ } > >+ > >+ /* > >+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value > >+ * as per C Model > >+ */ > >+ if (compressed_bpp == 6) { > >+ vdsc_cfg->rc_buf_thresh[12] = 0x7C; > >+ vdsc_cfg->rc_buf_thresh[13] = 0x7D; > >+ } > >+ > >+ row_index = get_row_index_for_rc_params(compressed_bpp); > >+ column_index = > >+ get_column_index_for_rc_params(vdsc_cfg- > >>bits_per_component); > >+ > >+ if (row_index < 0 || column_index < 0) > >+ return -EINVAL; > >+ > >+ vdsc_cfg->first_line_bpg_offset = > >+ rc_params[row_index][column_index].first_line_bpg_offset; > >+ vdsc_cfg->initial_xmit_delay = > >+ rc_params[row_index][column_index].initial_xmit_delay; > >+ vdsc_cfg->initial_offset = > >+ rc_params[row_index][column_index].initial_offset; > >+ vdsc_cfg->flatness_min_qp = > >+ rc_params[row_index][column_index].flatness_min_qp; > >+ vdsc_cfg->flatness_max_qp = > >+ rc_params[row_index][column_index].flatness_max_qp; > >+ vdsc_cfg->rc_quant_incr_limit0 = > >+ rc_params[row_index][column_index].rc_quant_incr_limit0; > >+ vdsc_cfg->rc_quant_incr_limit1 = > >+ rc_params[row_index][column_index].rc_quant_incr_limit1; > >+ > >+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) > >+ vdsc_cfg->rc_range_params[i] = > >+ > > rc_params[row_index][column_index].rc_range_params[i]; > >+ > >+ /* > >+ * BitsPerComponent value determines mux_word_size: > >+ * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 > >bits > >+ * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to > >+ * 48 bits > >+ */ > >+ if (vdsc_cfg->bits_per_component == 8 || > >+ vdsc_cfg->bits_per_component == 10) > >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; > >+ else if (vdsc_cfg->bits_per_component == 12) > >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; > >+ > >+ /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ > >+ vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > >+ (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > >+ > >+ return 0; > >+} > >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index > >0cf2407..f178933 100644 > >--- a/include/drm/drm_dp_helper.h > >+++ b/include/drm/drm_dp_helper.h > >@@ -186,6 +186,9 @@ > > > > #define DP_GUID 0x030 /* 1.2 */ > > > >+#define DP_DSC_RC_PIXELS_PER_GROUP 3 > >+#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 > >+ > > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > > > >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index > >4cfcd03..796c798 100644 > >--- a/include/drm/drm_dsc.h > >+++ b/include/drm/drm_dsc.h > >@@ -67,7 +67,7 @@ struct dsc_rc_range_parameters { > > /* Max Quantization Parameters allowed for this range */ > > u8 range_max_qp; > > /* Bits/group offset to apply to target for this group */ > >- u8 range_bpg_offset; > >+ s8 range_bpg_offset; > > }; > > > > struct drm_dsc_config { > >-- > >2.7.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params 2018-08-28 22:47 ` Manasi Navare @ 2018-08-28 23:31 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-28 23:31 UTC (permalink / raw) To: Srivatsa, Anusha; +Cc: intel-gfx On Tue, Aug 28, 2018 at 03:47:21PM -0700, Manasi Navare wrote: > On Tue, Aug 28, 2018 at 03:18:56PM -0700, Srivatsa, Anusha wrote: > > > > > > >-----Original Message----- > > >From: Navare, Manasi D > > >Sent: Tuesday, July 31, 2018 2:07 PM > > >To: intel-gfx@lists.freedesktop.org > > >Cc: Singh, Gaurav K <gaurav.k.singh@intel.com>; Jani Nikula > > ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; > > >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Navare, Manasi D > > ><manasi.d.navare@intel.com> > > >Subject: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params > > > > > >From: Gaurav K Singh <gaurav.k.singh@intel.com> > > > > > >This patches does the following: > > > > > >1. This patch defines all the DSC parameters as per the VESA DSC specification. > > >These are stored in the encoder and used to compute the PPS parameters to be > > >sent to the Sink. > > >2. Compute all the DSC parameters which are derived from DSC state of > > >intel_crtc_state. > > >3. Compute all parameters that are VESA DSC specific > > > > > >This computation happens in the atomic check phase during > > >compute_config() to validate if display stream compression can be enabled for > > >the requested mode. > > > > > >v5 (From Manasi): > > >* Add logic to limit the max line buf depth for DSC 1.1 to 13 as per DSC 1.1 spec > > >* Fix dim checkpatch warnings/checks > > > > > >v4 (From Gaurav): > > >* Rebase on latest drm tip > > >* rename variable name(Manasi) > > >* Populate linebuf_depth variable(Manasi) > > > > > >v3 (From Gaurav): > > >* Rebase my previous patches on top of Manasi's latest patch series > > >* Using >>n rather than /2^n (Manasi) > > >* Change the commit message to explain what the patch is doing(Gaurav) > > > > > >Fixed review comments from Ville: > > >* Don't use macro TWOS_COMPLEMENT > > >* Mention in comment about the source of RC params > > >* Return directly from case statements > > >* Using single asssignment for assigning rc_range_params > > >* Using <<n rather than *2^n and removing the comments about the fixed point > > >numbers > > > > > >v2 (From Manasi): > > >* Update logic for minor version to consider the dpcd value and what supported > > >by the HW platform > > >* Use DRM DSC config struct instead of intel_dp struct > > >* Move the DSC constants to DRM DSC header file > > >* Use u16, u8 where bigger data types not needed > > >* * Compute the DSC parameters as part of DSC compute config since the > > >computation can fail (Manasi) > > > > > >Cc: Jani Nikula <jani.nikula@linux.intel.com> > > >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > > >Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > > >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > >--- > > > drivers/gpu/drm/i915/Makefile | 3 +- > > > drivers/gpu/drm/i915/intel_dp.c | 7 + > > > drivers/gpu/drm/i915/intel_drv.h | 4 + > > > drivers/gpu/drm/i915/intel_vdsc.c | 455 > > >++++++++++++++++++++++++++++++++++++++ > > > include/drm/drm_dp_helper.h | 3 + > > > include/drm/drm_dsc.h | 2 +- > > > 6 files changed, 472 insertions(+), 2 deletions(-) create mode 100644 > > >drivers/gpu/drm/i915/intel_vdsc.c > > > > > >diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > >index 5794f10..deaf2d4 100644 > > >--- a/drivers/gpu/drm/i915/Makefile > > >+++ b/drivers/gpu/drm/i915/Makefile > > >@@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \ > > > intel_sdvo.o \ > > > intel_tv.o \ > > > vlv_dsi.o \ > > >- vlv_dsi_pll.o > > >+ vlv_dsi_pll.o \ > > >+ intel_vdsc.o > > > > > > # Post-mortem debug and GPU hang state capture > > > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git > > >a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index > > >7132f52..dc0a3c2 100644 > > >--- a/drivers/gpu/drm/i915/intel_dp.c > > >+++ b/drivers/gpu/drm/i915/intel_dp.c > > >@@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct > > >intel_dp *intel_dp, > > > return false; > > > } > > > } > > >+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { > > >+ DRM_ERROR("Cannot compute valid DSC parameters for Input > > >Bpp = %d" > > >+ "Compressed BPP = %d\n", > > >+ pipe_config->pipe_bpp, > > >+ pipe_config->dsc_params.compressed_bpp); > > >+ return false; > > >+ } > > > pipe_config->dsc_params.compression_enable = true; > > > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > > > "Compressed Bpp = %d Slice Count = %d\n", diff --git > > >a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > >index b7c2652..33cc777 100644 > > >--- a/drivers/gpu/drm/i915/intel_drv.h > > >+++ b/drivers/gpu/drm/i915/intel_drv.h > > >@@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, > > >uint8_t lane_count, uint8_t intel_dp_dsc_get_slice_count(struct intel_dp > > >*intel_dp, int mode_clock, > > > int mode_hdisplay); > > > > > >+/* intel_vdsc.c */ > > >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > > >+ struct intel_crtc_state *pipe_config); > > >+ > > > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { > > > return ~((1 << lane_count) - 1) & 0xf; diff --git > > >a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > > >new file mode 100644 > > >index 0000000..ecd270c > > >--- /dev/null > > >+++ b/drivers/gpu/drm/i915/intel_vdsc.c > > >@@ -0,0 +1,455 @@ > > >+/* > > >+ * Copyright © 2018 Intel Corporation > > >+ * > > >+ * Permission is hereby granted, free of charge, to any person > > >+obtaining a > > >+ * copy of this software and associated documentation files (the > > >+"Software"), > > >+ * to deal in the Software without restriction, including without > > >+limitation > > >+ * the rights to use, copy, modify, merge, publish, distribute, > > >+sublicense, > > >+ * and/or sell copies of the Software, and to permit persons to whom > > >+the > > >+ * Software is furnished to do so, subject to the following conditions: > > >+ * > > >+ * The above copyright notice and this permission notice (including the > > >+next > > >+ * paragraph) shall be included in all copies or substantial portions > > >+of the > > >+ * Software. > > >+ * > > >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > > >+EXPRESS OR > > >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > > >+MERCHANTABILITY, > > >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO > > >EVENT > > >+SHALL > > >+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, > > >DAMAGES OR > > >+OTHER > > >+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > > >+ARISING > > >+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > > >OTHER > > >+ * DEALINGS IN THE SOFTWARE. > > >+ * > > >+ * Author: Gaurav K Singh <gaurav.k.singh@intel.com> > > >+ * Manasi Navare <manasi.d.navare@intel.com> > > >+ */ > > >+ > > >+#include <drm/drmP.h> > > >+#include <drm/i915_drm.h> > > >+#include "i915_drv.h" > > >+#include "intel_drv.h" > > >+ > > >+enum ROW_INDEX_BPP { > > >+ ROW_INDEX_6BPP = 0, > > >+ ROW_INDEX_8BPP, > > >+ ROW_INDEX_10BPP, > > >+ ROW_INDEX_12BPP, > > >+ ROW_INDEX_15BPP, > > >+ MAX_ROW_INDEX > > >+}; > > >+ > > >+enum COLUMN_INDEX_BPC { > > >+ COLUMN_INDEX_8BPC = 0, > > >+ COLUMN_INDEX_10BPC, > > >+ COLUMN_INDEX_12BPC, > > >+ COLUMN_INDEX_14BPC, > > >+ COLUMN_INDEX_16BPC, > > >+ MAX_COLUMN_INDEX > > >+}; > > >+ > > >+#define DSC_SUPPORTED_VERSION_MIN 1 > > >+ > > >+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically > > >+constant */ static u16 rc_buf_thresh[] = { > > >+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, > > >+ 7744, 7872, 8000, 8064 > > >+}; > > >+ > > >+struct rc_parameters { > > >+ u16 initial_xmit_delay; > > >+ u8 first_line_bpg_offset; > > >+ u16 initial_offset; > > >+ u8 flatness_min_qp; > > >+ u8 flatness_max_qp; > > >+ u8 rc_quant_incr_limit0; > > >+ u8 rc_quant_incr_limit1; > > >+ struct dsc_rc_range_parameters > > >rc_range_params[DSC_NUM_BUF_RANGES]; > > >+}; > > >+ > > >+/* > > >+ * Selected Rate Control Related Parameter Recommended Values > > >+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212 */ static > > >+struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { { > > >+ /* 6BPP/8BPC */ > > >+ { 768, 15, 6144, 3, 13, 11, 11, { > > >+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, > > >+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, > > >+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, > > >+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } > > >+ } > > >+ }, > > >+ /* 6BPP/10BPC */ > > >+ { 768, 15, 6144, 7, 17, 15, 15, { > > >+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, > > >+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, > > >+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, > > >+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, > > >+ { 17, 18, -12 } > > >+ } > > >+ }, > > >+ /* 6BPP/12BPC */ > > >+ { 768, 15, 6144, 11, 21, 19, 19, { > > >+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, > > >+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, > > >+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, > > >+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, > > >+ { 21, 22, -12 } > > >+ } > > >+ }, > > >+ /* 6BPP/14BPC */ > > >+ { 768, 15, 6144, 15, 25, 23, 27, { > > >+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, > > >+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, > > >+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, > > >+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, > > >+ { 25, 26, -12 } > > >+ } > > >+ }, > > >+ /* 6BPP/16BPC */ > > >+ { 768, 15, 6144, 19, 29, 27, 27, { > > >+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, > > >+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, > > >+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, > > >+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, > > >+ { 29, 30, -12 } > > >+ } > > >+ }, > > >+}, > > >+{ > > >+ /* 8BPP/8BPC */ > > >+ { 512, 12, 6144, 3, 12, 11, 11, { > > >+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > > >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, > > >+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > > >+ } > > >+ }, > > >+ /* 8BPP/10BPC */ > > >+ { 512, 12, 6144, 7, 16, 15, 15, { > > >+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > > >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > > >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > > >+ } > > >+ }, > > >+ /* 8BPP/12BPC */ > > >+ { 512, 12, 6144, 11, 20, 19, 19, { > > >+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, > > >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > > >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > > >+ { 21, 23, -12 } > > >+ } > > >+ }, > > >+ /* 8BPP/14BPC */ > > >+ { 512, 12, 6144, 15, 24, 23, 23, { > > >+ { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, > > >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > >+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, > > >+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, > > >+ { 24, 25, -12 } > > >+ } > > >+ }, > > >+ /* 8BPP/16BPC */ > > >+ { 512, 12, 6144, 19, 28, 27, 27, { > > >+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, > > >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > >+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, > > >+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, > > >+ { 28, 29, -12 } > > >+ } > > >+ }, > > >+}, > > >+{ > > >+ /* 10BPP/8BPC */ > > >+ { 410, 15, 5632, 3, 12, 11, 11, { > > >+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, > > >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > >+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, > > >+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } > > >+ } > > >+ }, > > >+ /* 10BPP/10BPC */ > > >+ { 410, 15, 5632, 7, 16, 15, 15, { > > >+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, > > >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > >+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, > > >+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } > > >+ } > > >+ }, > > >+ /* 10BPP/12BPC */ > > >+ { 410, 15, 5632, 11, 20, 19, 19, { > > >+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, > > >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > >+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, > > >+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, > > >+ { 19, 20, -12 } > > >+ } > > >+ }, > > >+ /* 10BPP/14BPC */ > > >+ { 410, 15, 5632, 15, 24, 23, 23, { > > >+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, > > >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > >+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, > > >+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, > > >+ { 23, 24, -12 } > > >+ } > > >+ }, > > >+ /* 10BPP/16BPC */ > > >+ { 410, 15, 5632, 19, 28, 27, 27, { > > >+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, > > >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > >+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, > > >+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, > > >+ { 27, 28, -12 } > > >+ } > > >+ }, > > >+}, > > >+{ > > >+ /* 12BPP/8BPC */ > > >+ { 341, 15, 2048, 3, 12, 11, 11, { > > >+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > > >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, > > >+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > > >+ } > > >+ }, > > >+ /* 12BPP/10BPC */ > > >+ { 341, 15, 2048, 7, 16, 15, 15, { > > >+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, > > >+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > > >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > > >+ } > > >+ }, > > >+ /* 12BPP/12BPC */ > > >+ { 341, 15, 2048, 11, 20, 19, 19, { > > >+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, > > >+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > > >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > > >+ { 21, 23, -12 } > > >+ } > > >+ }, > > >+ /* 12BPP/14BPC */ > > >+ { 341, 15, 2048, 15, 24, 23, 23, { > > >+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, > > >+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > >+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, > > >+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, > > >+ { 22, 23, -12 } > > >+ } > > >+ }, > > >+ /* 12BPP/16BPC */ > > >+ { 341, 15, 2048, 19, 28, 27, 27, { > > >+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, > > >+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > >+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, > > >+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, > > >+ { 26, 27, -12 } > > >+ } > > >+ }, > > >+}, > > >+{ > > >+ /* 15BPP/8BPC */ > > >+ { 273, 15, 2048, 3, 12, 11, 11, { > > >+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, > > >+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, > > >+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, > > >+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } > > >+ } > > >+ }, > > >+ /* 15BPP/10BPC */ > > >+ { 273, 15, 2048, 7, 16, 15, 15, { > > >+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, > > >+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, > > >+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, > > >+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } > > >+ } > > >+ }, > > >+ /* 15BPP/12BPC */ > > >+ { 273, 15, 2048, 11, 20, 19, 19, { > > >+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, > > >+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, > > >+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, > > >+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, > > >+ { 16, 17, -12 } > > >+ } > > >+ }, > > >+ /* 15BPP/14BPC */ > > >+ { 273, 15, 2048, 15, 24, 23, 23, { > > >+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, > > >+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, > > >+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, > > >+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, > > >+ { 20, 21, -12 } > > >+ } > > >+ }, > > >+ /* 15BPP/16BPC */ > > >+ { 273, 15, 2048, 19, 28, 27, 27, { > > >+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, > > >+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, > > >+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, > > >+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, > > >+ { 24, 25, -12 } > > >+ } > > >+ } > > >+} > > >+}; > > >+ > > >+static int get_row_index_for_rc_params(u16 compressed_bpp) { > > >+ switch (compressed_bpp) { > > >+ case 6: > > >+ return ROW_INDEX_6BPP; > > >+ case 8: > > >+ return ROW_INDEX_8BPP; > > >+ case 10: > > >+ return ROW_INDEX_10BPP; > > >+ case 12: > > >+ return ROW_INDEX_12BPP; > > >+ case 15: > > >+ return ROW_INDEX_15BPP; > > >+ default: > > >+ return -EINVAL; > > >+ } > > >+} > > >+ > > >+static int get_column_index_for_rc_params(u8 bits_per_component) { > > >+ switch (bits_per_component) { > > >+ case 8: > > >+ return COLUMN_INDEX_8BPC; > > >+ case 10: > > >+ return COLUMN_INDEX_10BPC; > > >+ case 12: > > >+ return COLUMN_INDEX_12BPC; > > >+ case 14: > > >+ return COLUMN_INDEX_14BPC; > > >+ case 16: > > >+ return COLUMN_INDEX_16BPC; > > >+ default: > > >+ return -EINVAL; > > >+ } > > >+} > > >+ > > >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > > >+ struct intel_crtc_state *pipe_config) { > > >+ struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > > >+ u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; > > >+ u8 i = 0; > > >+ u8 row_index = 0; > > >+ u8 column_index = 0; > > >+ u8 line_buf_depth = 0; > > >+ > > >+ vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; > > >+ vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; > > >+ vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > > >+ pipe_config- > > >>dsc_params.slice_count); > > >+ /* > > >+ * Slice Height of 8 works for all currently available panels. So start > > >+ * with that if pic_height is an integral multiple of 8. > > >+ * Eventually add logic to try multiple slice heights. > > >+ */ > > >+ if (vdsc_cfg->pic_height % 8 == 0) > > >+ vdsc_cfg->slice_height = 8; > > >+ else if (vdsc_cfg->pic_height % 4 == 0) > > >+ vdsc_cfg->slice_height = 4; > > >+ else > > >+ vdsc_cfg->slice_height = 2; > > >+ > > >+ /* Values filled from DSC Sink DPCD */ > > >+ vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - > > >DP_DSC_SUPPORT] & > > >+ DP_DSC_MAJOR_MASK) >> > > >DP_DSC_MAJOR_SHIFT; > > >+ vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN, > > >+ (intel_dp->dsc_dpcd[DP_DSC_REV - > > >DP_DSC_SUPPORT] & > > >+ DP_DSC_MINOR_MASK) >> > > >DP_DSC_MINOR_SHIFT); > > >+ > > >+ vdsc_cfg->convert_rgb = intel_dp- > > >>dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & > > >+ DP_DSC_RGB; > > >+ > > >+ line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); > > >+ if (vdsc_cfg->dsc_version_minor == 2) > > >+ vdsc_cfg->line_buf_depth = (line_buf_depth == > > >DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? > > >+ DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; > > Shouldn't this be line_buf_depth >= DSC_1_2_MAX_LINEBUF_DEPTH_BITS? > > If you look at drm_dp_dsc_sink_line_buf_depth() function, it will only return maximum of 16. > Greater than DSC_1_2_MAX_LINEBUF_DEPTH_BITS is not a valid value and the function will return 0 for that. > But if at all its an invalid value greater than 16, then the function returns 0, so I will need to add a check for it to be greater than 0. Thanks for catching this! Manasi > > > > >+ else > > >+ vdsc_cfg->line_buf_depth = (line_buf_depth > > > Line_buf_depth >= DSC_1_1_MAX_LINEBUF_DEPTH_BITS?? > > This should be only greater than since if its equal to the max then it can just use the maximum value. > > Manasi > > > > > Anusha > > >DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? > > >+ DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; > > >+ > > >+ /* Gen 11 does not support YCbCr */ > > >+ vdsc_cfg->enable422 = false; > > >+ /* Gen 11 does not support VBR */ > > >+ vdsc_cfg->vbr_enable = false; > > >+ vdsc_cfg->block_pred_enable = > > >+ intel_dp- > > >>dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & > > >+ DP_DSC_BLK_PREDICTION_IS_SUPPORTED; > > >+ > > >+ /* Gen 11 only supports integral values of bpp */ > > >+ vdsc_cfg->bits_per_pixel = compressed_bpp << 4; > > >+ vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; > > >+ > > >+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { > > >+ /* > > >+ * six 0s are appended to the lsb of each threshold value > > >+ * internally in h/w. > > >+ * Only 8 bits are allowed for programming RcBufThreshold > > >+ */ > > >+ vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; > > >+ } > > >+ > > >+ /* > > >+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value > > >+ * as per C Model > > >+ */ > > >+ if (compressed_bpp == 6) { > > >+ vdsc_cfg->rc_buf_thresh[12] = 0x7C; > > >+ vdsc_cfg->rc_buf_thresh[13] = 0x7D; > > >+ } > > >+ > > >+ row_index = get_row_index_for_rc_params(compressed_bpp); > > >+ column_index = > > >+ get_column_index_for_rc_params(vdsc_cfg- > > >>bits_per_component); > > >+ > > >+ if (row_index < 0 || column_index < 0) > > >+ return -EINVAL; > > >+ > > >+ vdsc_cfg->first_line_bpg_offset = > > >+ rc_params[row_index][column_index].first_line_bpg_offset; > > >+ vdsc_cfg->initial_xmit_delay = > > >+ rc_params[row_index][column_index].initial_xmit_delay; > > >+ vdsc_cfg->initial_offset = > > >+ rc_params[row_index][column_index].initial_offset; > > >+ vdsc_cfg->flatness_min_qp = > > >+ rc_params[row_index][column_index].flatness_min_qp; > > >+ vdsc_cfg->flatness_max_qp = > > >+ rc_params[row_index][column_index].flatness_max_qp; > > >+ vdsc_cfg->rc_quant_incr_limit0 = > > >+ rc_params[row_index][column_index].rc_quant_incr_limit0; > > >+ vdsc_cfg->rc_quant_incr_limit1 = > > >+ rc_params[row_index][column_index].rc_quant_incr_limit1; > > >+ > > >+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) > > >+ vdsc_cfg->rc_range_params[i] = > > >+ > > > rc_params[row_index][column_index].rc_range_params[i]; > > >+ > > >+ /* > > >+ * BitsPerComponent value determines mux_word_size: > > >+ * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 > > >bits > > >+ * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to > > >+ * 48 bits > > >+ */ > > >+ if (vdsc_cfg->bits_per_component == 8 || > > >+ vdsc_cfg->bits_per_component == 10) > > >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; > > >+ else if (vdsc_cfg->bits_per_component == 12) > > >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; > > >+ > > >+ /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ > > >+ vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > > >+ (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > > >+ > > >+ return 0; > > >+} > > >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index > > >0cf2407..f178933 100644 > > >--- a/include/drm/drm_dp_helper.h > > >+++ b/include/drm/drm_dp_helper.h > > >@@ -186,6 +186,9 @@ > > > > > > #define DP_GUID 0x030 /* 1.2 */ > > > > > >+#define DP_DSC_RC_PIXELS_PER_GROUP 3 > > >+#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 > > >+ > > > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > > > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > > > > > >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index > > >4cfcd03..796c798 100644 > > >--- a/include/drm/drm_dsc.h > > >+++ b/include/drm/drm_dsc.h > > >@@ -67,7 +67,7 @@ struct dsc_rc_range_parameters { > > > /* Max Quantization Parameters allowed for this range */ > > > u8 range_max_qp; > > > /* Bits/group offset to apply to target for this group */ > > >- u8 range_bpg_offset; > > >+ s8 range_bpg_offset; > > > }; > > > > > > struct drm_dsc_config { > > >-- > > >2.7.4 > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params 2018-07-31 21:07 ` [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare 2018-08-28 22:18 ` Srivatsa, Anusha @ 2018-09-05 20:04 ` Manasi Navare 2018-09-05 20:33 ` Manasi Navare 1 sibling, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-09-05 20:04 UTC (permalink / raw) To: intel-gfx Gaurav, Please find my review comments below. Caught them when I tested your patch on DSC sink. On Tue, Jul 31, 2018 at 02:07:11PM -0700, Manasi Navare wrote: > From: Gaurav K Singh <gaurav.k.singh@intel.com> > > This patches does the following: > > 1. This patch defines all the DSC parameters as per the VESA > DSC specification. These are stored in the encoder and used > to compute the PPS parameters to be sent to the Sink. > 2. Compute all the DSC parameters which are derived from DSC > state of intel_crtc_state. > 3. Compute all parameters that are VESA DSC specific > > This computation happens in the atomic check phase during > compute_config() to validate if display stream compression > can be enabled for the requested mode. > > v5 (From Manasi): > * Add logic to limit the max line buf depth for DSC 1.1 to 13 > as per DSC 1.1 spec > * Fix dim checkpatch warnings/checks > > v4 (From Gaurav): > * Rebase on latest drm tip > * rename variable name(Manasi) > * Populate linebuf_depth variable(Manasi) > > v3 (From Gaurav): > * Rebase my previous patches on top of Manasi's latest patch > series > * Using >>n rather than /2^n (Manasi) > * Change the commit message to explain what the patch is doing(Gaurav) > > Fixed review comments from Ville: > * Don't use macro TWOS_COMPLEMENT > * Mention in comment about the source of RC params > * Return directly from case statements > * Using single asssignment for assigning rc_range_params > * Using <<n rather than *2^n and removing the comments > about the fixed point numbers > > v2 (From Manasi): > * Update logic for minor version to consider the dpcd value > and what supported by the HW platform > * Use DRM DSC config struct instead of intel_dp struct > * Move the DSC constants to DRM DSC header file > * Use u16, u8 where bigger data types not needed > * * Compute the DSC parameters as part of DSC compute config > since the computation can fail (Manasi) > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/Makefile | 3 +- > drivers/gpu/drm/i915/intel_dp.c | 7 + > drivers/gpu/drm/i915/intel_drv.h | 4 + > drivers/gpu/drm/i915/intel_vdsc.c | 455 ++++++++++++++++++++++++++++++++++++++ > include/drm/drm_dp_helper.h | 3 + > include/drm/drm_dsc.h | 2 +- > 6 files changed, 472 insertions(+), 2 deletions(-) > create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 5794f10..deaf2d4 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \ > intel_sdvo.o \ > intel_tv.o \ > vlv_dsi.o \ > - vlv_dsi_pll.o > + vlv_dsi_pll.o \ > + intel_vdsc.o > > # Post-mortem debug and GPU hang state capture > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 7132f52..dc0a3c2 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > return false; > } > } > + if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { > + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d" > + "Compressed BPP = %d\n", > + pipe_config->pipe_bpp, > + pipe_config->dsc_params.compressed_bpp); > + return false; > + } > pipe_config->dsc_params.compression_enable = true; > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > "Compressed Bpp = %d Slice Count = %d\n", > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index b7c2652..33cc777 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, > uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, > int mode_hdisplay); > > +/* intel_vdsc.c */ > +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > + struct intel_crtc_state *pipe_config); > + > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) > { > return ~((1 << lane_count) - 1) & 0xf; > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > new file mode 100644 > index 0000000..ecd270c > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > @@ -0,0 +1,455 @@ > +/* > + * Copyright © 2018 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice (including the next > + * paragraph) shall be included in all copies or substantial portions of the > + * Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > + * DEALINGS IN THE SOFTWARE. > + * > + * Author: Gaurav K Singh <gaurav.k.singh@intel.com> > + * Manasi Navare <manasi.d.navare@intel.com> > + */ > + > +#include <drm/drmP.h> > +#include <drm/i915_drm.h> > +#include "i915_drv.h" > +#include "intel_drv.h" > + > +enum ROW_INDEX_BPP { > + ROW_INDEX_6BPP = 0, > + ROW_INDEX_8BPP, > + ROW_INDEX_10BPP, > + ROW_INDEX_12BPP, > + ROW_INDEX_15BPP, > + MAX_ROW_INDEX > +}; > + > +enum COLUMN_INDEX_BPC { > + COLUMN_INDEX_8BPC = 0, > + COLUMN_INDEX_10BPC, > + COLUMN_INDEX_12BPC, > + COLUMN_INDEX_14BPC, > + COLUMN_INDEX_16BPC, > + MAX_COLUMN_INDEX > +}; > + > +#define DSC_SUPPORTED_VERSION_MIN 1 > + > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ > +static u16 rc_buf_thresh[] = { > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, > + 7744, 7872, 8000, 8064 > +}; > + > +struct rc_parameters { > + u16 initial_xmit_delay; > + u8 first_line_bpg_offset; > + u16 initial_offset; > + u8 flatness_min_qp; > + u8 flatness_max_qp; > + u8 rc_quant_incr_limit0; > + u8 rc_quant_incr_limit1; > + struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; > +}; > + > +/* > + * Selected Rate Control Related Parameter Recommended Values > + * from DSC_v1.11 spec & C Model release: DSC_model_20161212 > + */ > +static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { > +{ > + /* 6BPP/8BPC */ > + { 768, 15, 6144, 3, 13, 11, 11, { > + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, > + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, > + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, > + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } > + } > + }, > + /* 6BPP/10BPC */ > + { 768, 15, 6144, 7, 17, 15, 15, { > + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, > + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, > + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, > + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, > + { 17, 18, -12 } > + } > + }, > + /* 6BPP/12BPC */ > + { 768, 15, 6144, 11, 21, 19, 19, { > + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, > + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, > + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, > + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, > + { 21, 22, -12 } > + } > + }, > + /* 6BPP/14BPC */ > + { 768, 15, 6144, 15, 25, 23, 27, { > + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, > + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, > + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, > + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, > + { 25, 26, -12 } > + } > + }, > + /* 6BPP/16BPC */ > + { 768, 15, 6144, 19, 29, 27, 27, { > + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, > + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, > + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, > + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, > + { 29, 30, -12 } > + } > + }, > +}, > +{ > + /* 8BPP/8BPC */ > + { 512, 12, 6144, 3, 12, 11, 11, { > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > + } > + }, > + /* 8BPP/10BPC */ > + { 512, 12, 6144, 7, 16, 15, 15, { > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > + } > + }, > + /* 8BPP/12BPC */ > + { 512, 12, 6144, 11, 20, 19, 19, { > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > + { 21, 23, -12 } > + } > + }, > + /* 8BPP/14BPC */ > + { 512, 12, 6144, 15, 24, 23, 23, { > + { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, > + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, > + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, > + { 24, 25, -12 } > + } > + }, > + /* 8BPP/16BPC */ > + { 512, 12, 6144, 19, 28, 27, 27, { > + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, > + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, > + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, > + { 28, 29, -12 } > + } > + }, > +}, > +{ > + /* 10BPP/8BPC */ > + { 410, 15, 5632, 3, 12, 11, 11, { > + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, > + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } > + } > + }, > + /* 10BPP/10BPC */ > + { 410, 15, 5632, 7, 16, 15, 15, { > + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, > + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } > + } > + }, > + /* 10BPP/12BPC */ > + { 410, 15, 5632, 11, 20, 19, 19, { > + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, > + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, > + { 19, 20, -12 } > + } > + }, > + /* 10BPP/14BPC */ > + { 410, 15, 5632, 15, 24, 23, 23, { > + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, > + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, > + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, > + { 23, 24, -12 } > + } > + }, > + /* 10BPP/16BPC */ > + { 410, 15, 5632, 19, 28, 27, 27, { > + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, > + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, > + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, > + { 27, 28, -12 } > + } > + }, > +}, > +{ > + /* 12BPP/8BPC */ > + { 341, 15, 2048, 3, 12, 11, 11, { > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > + } > + }, > + /* 12BPP/10BPC */ > + { 341, 15, 2048, 7, 16, 15, 15, { > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > + } > + }, > + /* 12BPP/12BPC */ > + { 341, 15, 2048, 11, 20, 19, 19, { > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > + { 21, 23, -12 } > + } > + }, > + /* 12BPP/14BPC */ > + { 341, 15, 2048, 15, 24, 23, 23, { > + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, > + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, > + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, > + { 22, 23, -12 } > + } > + }, > + /* 12BPP/16BPC */ > + { 341, 15, 2048, 19, 28, 27, 27, { > + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, > + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, > + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, > + { 26, 27, -12 } > + } > + }, > +}, > +{ > + /* 15BPP/8BPC */ > + { 273, 15, 2048, 3, 12, 11, 11, { > + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, > + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, > + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, > + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } > + } > + }, > + /* 15BPP/10BPC */ > + { 273, 15, 2048, 7, 16, 15, 15, { > + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, > + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, > + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, > + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } > + } > + }, > + /* 15BPP/12BPC */ > + { 273, 15, 2048, 11, 20, 19, 19, { > + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, > + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, > + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, > + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, > + { 16, 17, -12 } > + } > + }, > + /* 15BPP/14BPC */ > + { 273, 15, 2048, 15, 24, 23, 23, { > + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, > + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, > + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, > + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, > + { 20, 21, -12 } > + } > + }, > + /* 15BPP/16BPC */ > + { 273, 15, 2048, 19, 28, 27, 27, { > + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, > + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, > + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, > + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, > + { 24, 25, -12 } > + } > + } > +} > +}; > + > +static int get_row_index_for_rc_params(u16 compressed_bpp) > +{ > + switch (compressed_bpp) { > + case 6: > + return ROW_INDEX_6BPP; > + case 8: > + return ROW_INDEX_8BPP; > + case 10: > + return ROW_INDEX_10BPP; > + case 12: > + return ROW_INDEX_12BPP; > + case 15: > + return ROW_INDEX_15BPP; > + default: > + return -EINVAL; > + } > +} > + > +static int get_column_index_for_rc_params(u8 bits_per_component) > +{ > + switch (bits_per_component) { > + case 8: > + return COLUMN_INDEX_8BPC; > + case 10: > + return COLUMN_INDEX_10BPC; > + case 12: > + return COLUMN_INDEX_12BPC; > + case 14: > + return COLUMN_INDEX_14BPC; > + case 16: > + return COLUMN_INDEX_16BPC; > + default: > + return -EINVAL; > + } > +} > + > +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > + struct intel_crtc_state *pipe_config) > +{ > + struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > + u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; > + u8 i = 0; > + u8 row_index = 0; > + u8 column_index = 0; > + u8 line_buf_depth = 0; > + > + vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; > + vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; > + vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > + pipe_config->dsc_params.slice_count); > + /* > + * Slice Height of 8 works for all currently available panels. So start > + * with that if pic_height is an integral multiple of 8. > + * Eventually add logic to try multiple slice heights. > + */ > + if (vdsc_cfg->pic_height % 8 == 0) > + vdsc_cfg->slice_height = 8; > + else if (vdsc_cfg->pic_height % 4 == 0) > + vdsc_cfg->slice_height = 4; > + else > + vdsc_cfg->slice_height = 2; > + > + /* Values filled from DSC Sink DPCD */ > + vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & > + DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; > + vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN, > + (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & > + DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); > + > + vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & > + DP_DSC_RGB; > + > + line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); Add a check for return value of 0 > + if (vdsc_cfg->dsc_version_minor == 2) > + vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? > + DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; > + else > + vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? > + DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; > + > + /* Gen 11 does not support YCbCr */ > + vdsc_cfg->enable422 = false; > + /* Gen 11 does not support VBR */ > + vdsc_cfg->vbr_enable = false; > + vdsc_cfg->block_pred_enable = > + intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & > + DP_DSC_BLK_PREDICTION_IS_SUPPORTED; > + > + /* Gen 11 only supports integral values of bpp */ > + vdsc_cfg->bits_per_pixel = compressed_bpp << 4; > + vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; > + > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { > + /* > + * six 0s are appended to the lsb of each threshold value > + * internally in h/w. > + * Only 8 bits are allowed for programming RcBufThreshold > + */ > + vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; > + } > + > + /* > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value > + * as per C Model > + */ > + if (compressed_bpp == 6) { > + vdsc_cfg->rc_buf_thresh[12] = 0x7C; > + vdsc_cfg->rc_buf_thresh[13] = 0x7D; > + } > + > + row_index = get_row_index_for_rc_params(compressed_bpp); > + column_index = > + get_column_index_for_rc_params(vdsc_cfg->bits_per_component); > + > + if (row_index < 0 || column_index < 0) > + return -EINVAL; > + > + vdsc_cfg->first_line_bpg_offset = > + rc_params[row_index][column_index].first_line_bpg_offset; > + vdsc_cfg->initial_xmit_delay = > + rc_params[row_index][column_index].initial_xmit_delay; > + vdsc_cfg->initial_offset = > + rc_params[row_index][column_index].initial_offset; > + vdsc_cfg->flatness_min_qp = > + rc_params[row_index][column_index].flatness_min_qp; > + vdsc_cfg->flatness_max_qp = > + rc_params[row_index][column_index].flatness_max_qp; > + vdsc_cfg->rc_quant_incr_limit0 = > + rc_params[row_index][column_index].rc_quant_incr_limit0; > + vdsc_cfg->rc_quant_incr_limit1 = > + rc_params[row_index][column_index].rc_quant_incr_limit1; > + > + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) > + vdsc_cfg->rc_range_params[i] = > + rc_params[row_index][column_index].rc_range_params[i]; > + > + /* > + * BitsPerComponent value determines mux_word_size: > + * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits > + * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to > + * 48 bits > + */ > + if (vdsc_cfg->bits_per_component == 8 || > + vdsc_cfg->bits_per_component == 10) > + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; > + else if (vdsc_cfg->bits_per_component == 12) > + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; > + > + /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ > + vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > + (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); ^^^^^vdsc_cfg->rc_model_size is only defined but not getting set anywhere. It should be set to DSC_RC_MODEL_SIZE_CONST defined in drm_dsc.h else it results into an incorrect default value. > + > + return 0; > +} > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 0cf2407..f178933 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -186,6 +186,9 @@ > > #define DP_GUID 0x030 /* 1.2 */ > > +#define DP_DSC_RC_PIXELS_PER_GROUP 3 > +#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 This patch in drm should be sent as a separate patch or combined with the patch where you are defining DRM DSC parameters and constants. Manasi > + > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > index 4cfcd03..796c798 100644 > --- a/include/drm/drm_dsc.h > +++ b/include/drm/drm_dsc.h > @@ -67,7 +67,7 @@ struct dsc_rc_range_parameters { > /* Max Quantization Parameters allowed for this range */ > u8 range_max_qp; > /* Bits/group offset to apply to target for this group */ > - u8 range_bpg_offset; > + s8 range_bpg_offset; > }; > > struct drm_dsc_config { > -- > 2.7.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params 2018-09-05 20:04 ` Manasi Navare @ 2018-09-05 20:33 ` Manasi Navare 2018-09-07 2:14 ` Manasi Navare 0 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-09-05 20:33 UTC (permalink / raw) To: intel-gfx One more fix below which was the cause of all the artifacts On Wed, Sep 05, 2018 at 01:04:48PM -0700, Manasi Navare wrote: > Gaurav, > > Please find my review comments below. Caught them when I tested > your patch on DSC sink. > > On Tue, Jul 31, 2018 at 02:07:11PM -0700, Manasi Navare wrote: > > From: Gaurav K Singh <gaurav.k.singh@intel.com> > > > > This patches does the following: > > > > 1. This patch defines all the DSC parameters as per the VESA > > DSC specification. These are stored in the encoder and used > > to compute the PPS parameters to be sent to the Sink. > > 2. Compute all the DSC parameters which are derived from DSC > > state of intel_crtc_state. > > 3. Compute all parameters that are VESA DSC specific > > > > This computation happens in the atomic check phase during > > compute_config() to validate if display stream compression > > can be enabled for the requested mode. > > > > v5 (From Manasi): > > * Add logic to limit the max line buf depth for DSC 1.1 to 13 > > as per DSC 1.1 spec > > * Fix dim checkpatch warnings/checks > > > > v4 (From Gaurav): > > * Rebase on latest drm tip > > * rename variable name(Manasi) > > * Populate linebuf_depth variable(Manasi) > > > > v3 (From Gaurav): > > * Rebase my previous patches on top of Manasi's latest patch > > series > > * Using >>n rather than /2^n (Manasi) > > * Change the commit message to explain what the patch is doing(Gaurav) > > > > Fixed review comments from Ville: > > * Don't use macro TWOS_COMPLEMENT > > * Mention in comment about the source of RC params > > * Return directly from case statements > > * Using single asssignment for assigning rc_range_params > > * Using <<n rather than *2^n and removing the comments > > about the fixed point numbers > > > > v2 (From Manasi): > > * Update logic for minor version to consider the dpcd value > > and what supported by the HW platform > > * Use DRM DSC config struct instead of intel_dp struct > > * Move the DSC constants to DRM DSC header file > > * Use u16, u8 where bigger data types not needed > > * * Compute the DSC parameters as part of DSC compute config > > since the computation can fail (Manasi) > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/i915/Makefile | 3 +- > > drivers/gpu/drm/i915/intel_dp.c | 7 + > > drivers/gpu/drm/i915/intel_drv.h | 4 + > > drivers/gpu/drm/i915/intel_vdsc.c | 455 ++++++++++++++++++++++++++++++++++++++ > > include/drm/drm_dp_helper.h | 3 + > > include/drm/drm_dsc.h | 2 +- > > 6 files changed, 472 insertions(+), 2 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c > > > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > index 5794f10..deaf2d4 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \ > > intel_sdvo.o \ > > intel_tv.o \ > > vlv_dsi.o \ > > - vlv_dsi_pll.o > > + vlv_dsi_pll.o \ > > + intel_vdsc.o > > > > # Post-mortem debug and GPU hang state capture > > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 7132f52..dc0a3c2 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > > return false; > > } > > } > > + if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { > > + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d" > > + "Compressed BPP = %d\n", > > + pipe_config->pipe_bpp, > > + pipe_config->dsc_params.compressed_bpp); > > + return false; > > + } > > pipe_config->dsc_params.compression_enable = true; > > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > > "Compressed Bpp = %d Slice Count = %d\n", > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index b7c2652..33cc777 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, > > uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, > > int mode_hdisplay); > > > > +/* intel_vdsc.c */ > > +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > > + struct intel_crtc_state *pipe_config); > > + > > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) > > { > > return ~((1 << lane_count) - 1) & 0xf; > > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > > new file mode 100644 > > index 0000000..ecd270c > > --- /dev/null > > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > > @@ -0,0 +1,455 @@ > > +/* > > + * Copyright © 2018 Intel Corporation > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a > > + * copy of this software and associated documentation files (the "Software"), > > + * to deal in the Software without restriction, including without limitation > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > > + * and/or sell copies of the Software, and to permit persons to whom the > > + * Software is furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice (including the next > > + * paragraph) shall be included in all copies or substantial portions of the > > + * Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > > + * DEALINGS IN THE SOFTWARE. > > + * > > + * Author: Gaurav K Singh <gaurav.k.singh@intel.com> > > + * Manasi Navare <manasi.d.navare@intel.com> > > + */ > > + > > +#include <drm/drmP.h> > > +#include <drm/i915_drm.h> > > +#include "i915_drv.h" > > +#include "intel_drv.h" > > + > > +enum ROW_INDEX_BPP { > > + ROW_INDEX_6BPP = 0, > > + ROW_INDEX_8BPP, > > + ROW_INDEX_10BPP, > > + ROW_INDEX_12BPP, > > + ROW_INDEX_15BPP, > > + MAX_ROW_INDEX > > +}; > > + > > +enum COLUMN_INDEX_BPC { > > + COLUMN_INDEX_8BPC = 0, > > + COLUMN_INDEX_10BPC, > > + COLUMN_INDEX_12BPC, > > + COLUMN_INDEX_14BPC, > > + COLUMN_INDEX_16BPC, > > + MAX_COLUMN_INDEX > > +}; > > + > > +#define DSC_SUPPORTED_VERSION_MIN 1 > > + > > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ > > +static u16 rc_buf_thresh[] = { > > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, > > + 7744, 7872, 8000, 8064 > > +}; > > + > > +struct rc_parameters { > > + u16 initial_xmit_delay; > > + u8 first_line_bpg_offset; > > + u16 initial_offset; > > + u8 flatness_min_qp; > > + u8 flatness_max_qp; > > + u8 rc_quant_incr_limit0; > > + u8 rc_quant_incr_limit1; > > + struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; > > +}; > > + > > +/* > > + * Selected Rate Control Related Parameter Recommended Values > > + * from DSC_v1.11 spec & C Model release: DSC_model_20161212 > > + */ > > +static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { > > +{ > > + /* 6BPP/8BPC */ > > + { 768, 15, 6144, 3, 13, 11, 11, { > > + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, > > + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, > > + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, > > + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } > > + } > > + }, > > + /* 6BPP/10BPC */ > > + { 768, 15, 6144, 7, 17, 15, 15, { > > + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, > > + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, > > + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, > > + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, > > + { 17, 18, -12 } > > + } > > + }, > > + /* 6BPP/12BPC */ > > + { 768, 15, 6144, 11, 21, 19, 19, { > > + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, > > + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, > > + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, > > + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, > > + { 21, 22, -12 } > > + } > > + }, > > + /* 6BPP/14BPC */ > > + { 768, 15, 6144, 15, 25, 23, 27, { > > + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, > > + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, > > + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, > > + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, > > + { 25, 26, -12 } > > + } > > + }, > > + /* 6BPP/16BPC */ > > + { 768, 15, 6144, 19, 29, 27, 27, { > > + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, > > + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, > > + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, > > + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, > > + { 29, 30, -12 } > > + } > > + }, > > +}, > > +{ > > + /* 8BPP/8BPC */ > > + { 512, 12, 6144, 3, 12, 11, 11, { > > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, > > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > > + } > > + }, > > + /* 8BPP/10BPC */ > > + { 512, 12, 6144, 7, 16, 15, 15, { > > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > > + } > > + }, > > + /* 8BPP/12BPC */ > > + { 512, 12, 6144, 11, 20, 19, 19, { > > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, > > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > > + { 21, 23, -12 } > > + } > > + }, > > + /* 8BPP/14BPC */ > > + { 512, 12, 6144, 15, 24, 23, 23, { > > + { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, > > + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, > > + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, > > + { 24, 25, -12 } > > + } > > + }, > > + /* 8BPP/16BPC */ > > + { 512, 12, 6144, 19, 28, 27, 27, { > > + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, > > + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, > > + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, > > + { 28, 29, -12 } > > + } > > + }, > > +}, > > +{ > > + /* 10BPP/8BPC */ > > + { 410, 15, 5632, 3, 12, 11, 11, { > > + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, > > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, > > + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } > > + } > > + }, > > + /* 10BPP/10BPC */ > > + { 410, 15, 5632, 7, 16, 15, 15, { > > + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, > > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, > > + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } > > + } > > + }, > > + /* 10BPP/12BPC */ > > + { 410, 15, 5632, 11, 20, 19, 19, { > > + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, > > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, > > + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, > > + { 19, 20, -12 } > > + } > > + }, > > + /* 10BPP/14BPC */ > > + { 410, 15, 5632, 15, 24, 23, 23, { > > + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, > > + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, > > + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, > > + { 23, 24, -12 } > > + } > > + }, > > + /* 10BPP/16BPC */ > > + { 410, 15, 5632, 19, 28, 27, 27, { > > + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, > > + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, > > + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, > > + { 27, 28, -12 } > > + } > > + }, > > +}, > > +{ > > + /* 12BPP/8BPC */ > > + { 341, 15, 2048, 3, 12, 11, 11, { > > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, > > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > > + } > > + }, > > + /* 12BPP/10BPC */ > > + { 341, 15, 2048, 7, 16, 15, 15, { > > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, > > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > > + } > > + }, > > + /* 12BPP/12BPC */ > > + { 341, 15, 2048, 11, 20, 19, 19, { > > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, > > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > > + { 21, 23, -12 } > > + } > > + }, > > + /* 12BPP/14BPC */ > > + { 341, 15, 2048, 15, 24, 23, 23, { > > + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, > > + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, > > + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, > > + { 22, 23, -12 } > > + } > > + }, > > + /* 12BPP/16BPC */ > > + { 341, 15, 2048, 19, 28, 27, 27, { > > + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, > > + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, > > + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, > > + { 26, 27, -12 } > > + } > > + }, > > +}, > > +{ > > + /* 15BPP/8BPC */ > > + { 273, 15, 2048, 3, 12, 11, 11, { > > + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, > > + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, > > + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, > > + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } > > + } > > + }, > > + /* 15BPP/10BPC */ > > + { 273, 15, 2048, 7, 16, 15, 15, { > > + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, > > + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, > > + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, > > + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } > > + } > > + }, > > + /* 15BPP/12BPC */ > > + { 273, 15, 2048, 11, 20, 19, 19, { > > + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, > > + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, > > + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, > > + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, > > + { 16, 17, -12 } > > + } > > + }, > > + /* 15BPP/14BPC */ > > + { 273, 15, 2048, 15, 24, 23, 23, { > > + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, > > + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, > > + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, > > + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, > > + { 20, 21, -12 } > > + } > > + }, > > + /* 15BPP/16BPC */ > > + { 273, 15, 2048, 19, 28, 27, 27, { > > + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, > > + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, > > + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, > > + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, > > + { 24, 25, -12 } > > + } > > + } > > +} > > +}; > > + > > +static int get_row_index_for_rc_params(u16 compressed_bpp) > > +{ > > + switch (compressed_bpp) { > > + case 6: > > + return ROW_INDEX_6BPP; > > + case 8: > > + return ROW_INDEX_8BPP; > > + case 10: > > + return ROW_INDEX_10BPP; > > + case 12: > > + return ROW_INDEX_12BPP; > > + case 15: > > + return ROW_INDEX_15BPP; > > + default: > > + return -EINVAL; > > + } > > +} > > + > > +static int get_column_index_for_rc_params(u8 bits_per_component) > > +{ > > + switch (bits_per_component) { > > + case 8: > > + return COLUMN_INDEX_8BPC; > > + case 10: > > + return COLUMN_INDEX_10BPC; > > + case 12: > > + return COLUMN_INDEX_12BPC; > > + case 14: > > + return COLUMN_INDEX_14BPC; > > + case 16: > > + return COLUMN_INDEX_16BPC; > > + default: > > + return -EINVAL; > > + } > > +} > > + > > +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > > + struct intel_crtc_state *pipe_config) > > +{ > > + struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > > + u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; > > + u8 i = 0; > > + u8 row_index = 0; > > + u8 column_index = 0; > > + u8 line_buf_depth = 0; > > + > > + vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; > > + vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; > > + vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > > + pipe_config->dsc_params.slice_count); > > + /* > > + * Slice Height of 8 works for all currently available panels. So start > > + * with that if pic_height is an integral multiple of 8. > > + * Eventually add logic to try multiple slice heights. > > + */ > > + if (vdsc_cfg->pic_height % 8 == 0) > > + vdsc_cfg->slice_height = 8; > > + else if (vdsc_cfg->pic_height % 4 == 0) > > + vdsc_cfg->slice_height = 4; > > + else > > + vdsc_cfg->slice_height = 2; > > + > > + /* Values filled from DSC Sink DPCD */ > > + vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & > > + DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; > > + vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN, > > + (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & > > + DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); > > + > > + vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & > > + DP_DSC_RGB; > > + > > + line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); > > Add a check for return value of 0 > > > + if (vdsc_cfg->dsc_version_minor == 2) > > + vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? > > + DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; > > + else > > + vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? > > + DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; > > + > > + /* Gen 11 does not support YCbCr */ > > + vdsc_cfg->enable422 = false; > > + /* Gen 11 does not support VBR */ > > + vdsc_cfg->vbr_enable = false; > > + vdsc_cfg->block_pred_enable = > > + intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & > > + DP_DSC_BLK_PREDICTION_IS_SUPPORTED; > > + > > + /* Gen 11 only supports integral values of bpp */ > > + vdsc_cfg->bits_per_pixel = compressed_bpp << 4; > > + vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; > > + > > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { > > + /* > > + * six 0s are appended to the lsb of each threshold value > > + * internally in h/w. > > + * Only 8 bits are allowed for programming RcBufThreshold > > + */ > > + vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; > > + } > > + > > + /* > > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value > > + * as per C Model > > + */ > > + if (compressed_bpp == 6) { > > + vdsc_cfg->rc_buf_thresh[12] = 0x7C; > > + vdsc_cfg->rc_buf_thresh[13] = 0x7D; > > + } > > + > > + row_index = get_row_index_for_rc_params(compressed_bpp); > > + column_index = > > + get_column_index_for_rc_params(vdsc_cfg->bits_per_component); > > + > > + if (row_index < 0 || column_index < 0) > > + return -EINVAL; > > + > > + vdsc_cfg->first_line_bpg_offset = > > + rc_params[row_index][column_index].first_line_bpg_offset; > > + vdsc_cfg->initial_xmit_delay = > > + rc_params[row_index][column_index].initial_xmit_delay; > > + vdsc_cfg->initial_offset = > > + rc_params[row_index][column_index].initial_offset; > > + vdsc_cfg->flatness_min_qp = > > + rc_params[row_index][column_index].flatness_min_qp; > > + vdsc_cfg->flatness_max_qp = > > + rc_params[row_index][column_index].flatness_max_qp; > > + vdsc_cfg->rc_quant_incr_limit0 = > > + rc_params[row_index][column_index].rc_quant_incr_limit0; > > + vdsc_cfg->rc_quant_incr_limit1 = > > + rc_params[row_index][column_index].rc_quant_incr_limit1; > > + > > + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) > > + vdsc_cfg->rc_range_params[i] = > > + rc_params[row_index][column_index].rc_range_params[i]; > > + > > + /* > > + * BitsPerComponent value determines mux_word_size: > > + * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits > > + * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to > > + * 48 bits > > + */ > > + if (vdsc_cfg->bits_per_component == 8 || > > + vdsc_cfg->bits_per_component == 10) > > + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; > > + else if (vdsc_cfg->bits_per_component == 12) > > + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; > > + > > + /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ > > + vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > > + (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > > ^^^^^vdsc_cfg->rc_model_size is only defined but not getting set anywhere. > It should be set to DSC_RC_MODEL_SIZE_CONST defined in drm_dsc.h else it results into an incorrect default value. > > > + > > + return 0; > > +} > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index 0cf2407..f178933 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -186,6 +186,9 @@ > > > > #define DP_GUID 0x030 /* 1.2 */ > > > > +#define DP_DSC_RC_PIXELS_PER_GROUP 3 > > +#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 > > This patch in drm should be sent as a separate patch or combined with the patch > where you are defining DRM DSC parameters and constants. > > Manasi > > > + > > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > > > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > > index 4cfcd03..796c798 100644 > > --- a/include/drm/drm_dsc.h > > +++ b/include/drm/drm_dsc.h > > @@ -67,7 +67,7 @@ struct dsc_rc_range_parameters { > > /* Max Quantization Parameters allowed for this range */ > > u8 range_max_qp; > > /* Bits/group offset to apply to target for this group */ > > - u8 range_bpg_offset; > > + s8 range_bpg_offset; This cannot be signed int since the PPS value expects it to be 2s complement and stored as an unsigned value. It needs to stay as u8 Manasi > > }; > > > > struct drm_dsc_config { > > -- > > 2.7.4 > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params 2018-09-05 20:33 ` Manasi Navare @ 2018-09-07 2:14 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-09-07 2:14 UTC (permalink / raw) To: intel-gfx Few more comments here regarding the fixes required for fixing all the seen corruption. I have made these fixes and will add themin the next revision submission. On Wed, Sep 05, 2018 at 01:33:35PM -0700, Manasi Navare wrote: > One more fix below which was the cause of all the artifacts > > On Wed, Sep 05, 2018 at 01:04:48PM -0700, Manasi Navare wrote: > > Gaurav, > > > > Please find my review comments below. Caught them when I tested > > your patch on DSC sink. > > > > On Tue, Jul 31, 2018 at 02:07:11PM -0700, Manasi Navare wrote: > > > From: Gaurav K Singh <gaurav.k.singh@intel.com> > > > > > > This patches does the following: > > > > > > 1. This patch defines all the DSC parameters as per the VESA > > > DSC specification. These are stored in the encoder and used > > > to compute the PPS parameters to be sent to the Sink. > > > 2. Compute all the DSC parameters which are derived from DSC > > > state of intel_crtc_state. > > > 3. Compute all parameters that are VESA DSC specific > > > > > > This computation happens in the atomic check phase during > > > compute_config() to validate if display stream compression > > > can be enabled for the requested mode. > > > > > > v5 (From Manasi): > > > * Add logic to limit the max line buf depth for DSC 1.1 to 13 > > > as per DSC 1.1 spec > > > * Fix dim checkpatch warnings/checks > > > > > > v4 (From Gaurav): > > > * Rebase on latest drm tip > > > * rename variable name(Manasi) > > > * Populate linebuf_depth variable(Manasi) > > > > > > v3 (From Gaurav): > > > * Rebase my previous patches on top of Manasi's latest patch > > > series > > > * Using >>n rather than /2^n (Manasi) > > > * Change the commit message to explain what the patch is doing(Gaurav) > > > > > > Fixed review comments from Ville: > > > * Don't use macro TWOS_COMPLEMENT > > > * Mention in comment about the source of RC params > > > * Return directly from case statements > > > * Using single asssignment for assigning rc_range_params > > > * Using <<n rather than *2^n and removing the comments > > > about the fixed point numbers > > > > > > v2 (From Manasi): > > > * Update logic for minor version to consider the dpcd value > > > and what supported by the HW platform > > > * Use DRM DSC config struct instead of intel_dp struct > > > * Move the DSC constants to DRM DSC header file > > > * Use u16, u8 where bigger data types not needed > > > * * Compute the DSC parameters as part of DSC compute config > > > since the computation can fail (Manasi) > > > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > > > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > > > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > --- > > > drivers/gpu/drm/i915/Makefile | 3 +- > > > drivers/gpu/drm/i915/intel_dp.c | 7 + > > > drivers/gpu/drm/i915/intel_drv.h | 4 + > > > drivers/gpu/drm/i915/intel_vdsc.c | 455 ++++++++++++++++++++++++++++++++++++++ > > > include/drm/drm_dp_helper.h | 3 + > > > include/drm/drm_dsc.h | 2 +- > > > 6 files changed, 472 insertions(+), 2 deletions(-) > > > create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c > > > > > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > > index 5794f10..deaf2d4 100644 > > > --- a/drivers/gpu/drm/i915/Makefile > > > +++ b/drivers/gpu/drm/i915/Makefile > > > @@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \ > > > intel_sdvo.o \ > > > intel_tv.o \ > > > vlv_dsi.o \ > > > - vlv_dsi_pll.o > > > + vlv_dsi_pll.o \ > > > + intel_vdsc.o > > > > > > # Post-mortem debug and GPU hang state capture > > > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > > index 7132f52..dc0a3c2 100644 > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > @@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > > > return false; > > > } > > > } > > > + if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { > > > + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d" > > > + "Compressed BPP = %d\n", > > > + pipe_config->pipe_bpp, > > > + pipe_config->dsc_params.compressed_bpp); > > > + return false; > > > + } > > > pipe_config->dsc_params.compression_enable = true; > > > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > > > "Compressed Bpp = %d Slice Count = %d\n", > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > > index b7c2652..33cc777 100644 > > > --- a/drivers/gpu/drm/i915/intel_drv.h > > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > > @@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, > > > uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, > > > int mode_hdisplay); > > > > > > +/* intel_vdsc.c */ > > > +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > > > + struct intel_crtc_state *pipe_config); > > > + > > > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) > > > { > > > return ~((1 << lane_count) - 1) & 0xf; > > > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > > > new file mode 100644 > > > index 0000000..ecd270c > > > --- /dev/null > > > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > > > @@ -0,0 +1,455 @@ > > > +/* > > > + * Copyright © 2018 Intel Corporation > > > + * > > > + * Permission is hereby granted, free of charge, to any person obtaining a > > > + * copy of this software and associated documentation files (the "Software"), > > > + * to deal in the Software without restriction, including without limitation > > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > > > + * and/or sell copies of the Software, and to permit persons to whom the > > > + * Software is furnished to do so, subject to the following conditions: > > > + * > > > + * The above copyright notice and this permission notice (including the next > > > + * paragraph) shall be included in all copies or substantial portions of the > > > + * Software. > > > + * > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > > > + * DEALINGS IN THE SOFTWARE. > > > + * > > > + * Author: Gaurav K Singh <gaurav.k.singh@intel.com> > > > + * Manasi Navare <manasi.d.navare@intel.com> > > > + */ > > > + > > > +#include <drm/drmP.h> > > > +#include <drm/i915_drm.h> > > > +#include "i915_drv.h" > > > +#include "intel_drv.h" > > > + > > > +enum ROW_INDEX_BPP { > > > + ROW_INDEX_6BPP = 0, > > > + ROW_INDEX_8BPP, > > > + ROW_INDEX_10BPP, > > > + ROW_INDEX_12BPP, > > > + ROW_INDEX_15BPP, > > > + MAX_ROW_INDEX > > > +}; > > > + > > > +enum COLUMN_INDEX_BPC { > > > + COLUMN_INDEX_8BPC = 0, > > > + COLUMN_INDEX_10BPC, > > > + COLUMN_INDEX_12BPC, > > > + COLUMN_INDEX_14BPC, > > > + COLUMN_INDEX_16BPC, > > > + MAX_COLUMN_INDEX > > > +}; > > > + > > > +#define DSC_SUPPORTED_VERSION_MIN 1 > > > + > > > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ > > > +static u16 rc_buf_thresh[] = { > > > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, > > > + 7744, 7872, 8000, 8064 > > > +}; > > > + > > > +struct rc_parameters { > > > + u16 initial_xmit_delay; > > > + u8 first_line_bpg_offset; > > > + u16 initial_offset; > > > + u8 flatness_min_qp; > > > + u8 flatness_max_qp; > > > + u8 rc_quant_incr_limit0; > > > + u8 rc_quant_incr_limit1; > > > + struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; > > > +}; > > > + > > > +/* > > > + * Selected Rate Control Related Parameter Recommended Values > > > + * from DSC_v1.11 spec & C Model release: DSC_model_20161212 > > > + */ > > > +static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { > > > +{ > > > + /* 6BPP/8BPC */ > > > + { 768, 15, 6144, 3, 13, 11, 11, { > > > + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, > > > + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, > > > + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, > > > + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } > > > + } > > > + }, > > > + /* 6BPP/10BPC */ > > > + { 768, 15, 6144, 7, 17, 15, 15, { > > > + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, > > > + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, > > > + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, > > > + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, > > > + { 17, 18, -12 } > > > + } > > > + }, > > > + /* 6BPP/12BPC */ > > > + { 768, 15, 6144, 11, 21, 19, 19, { > > > + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, > > > + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, > > > + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, > > > + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, > > > + { 21, 22, -12 } > > > + } > > > + }, > > > + /* 6BPP/14BPC */ > > > + { 768, 15, 6144, 15, 25, 23, 27, { > > > + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, > > > + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, > > > + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, > > > + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, > > > + { 25, 26, -12 } > > > + } > > > + }, > > > + /* 6BPP/16BPC */ > > > + { 768, 15, 6144, 19, 29, 27, 27, { > > > + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, > > > + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, > > > + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, > > > + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, > > > + { 29, 30, -12 } > > > + } > > > + }, > > > +}, > > > +{ > > > + /* 8BPP/8BPC */ > > > + { 512, 12, 6144, 3, 12, 11, 11, { > > > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > > > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, > > > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > > > + } > > > + }, > > > + /* 8BPP/10BPC */ > > > + { 512, 12, 6144, 7, 16, 15, 15, { > > > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > > > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > > > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > > > + } > > > + }, > > > + /* 8BPP/12BPC */ > > > + { 512, 12, 6144, 11, 20, 19, 19, { > > > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, > > > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > > > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > > > + { 21, 23, -12 } > > > + } > > > + }, > > > + /* 8BPP/14BPC */ > > > + { 512, 12, 6144, 15, 24, 23, 23, { > > > + { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, > > > + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > > + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, > > > + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, > > > + { 24, 25, -12 } > > > + } > > > + }, > > > + /* 8BPP/16BPC */ > > > + { 512, 12, 6144, 19, 28, 27, 27, { > > > + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, > > > + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > > + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, > > > + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, > > > + { 28, 29, -12 } > > > + } > > > + }, > > > +}, > > > +{ > > > + /* 10BPP/8BPC */ > > > + { 410, 15, 5632, 3, 12, 11, 11, { > > > + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, > > > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > > + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, > > > + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } > > > + } > > > + }, > > > + /* 10BPP/10BPC */ > > > + { 410, 15, 5632, 7, 16, 15, 15, { > > > + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, > > > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > > + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, > > > + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } > > > + } > > > + }, > > > + /* 10BPP/12BPC */ > > > + { 410, 15, 5632, 11, 20, 19, 19, { > > > + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, > > > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > > + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, > > > + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, > > > + { 19, 20, -12 } > > > + } > > > + }, > > > + /* 10BPP/14BPC */ > > > + { 410, 15, 5632, 15, 24, 23, 23, { > > > + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, > > > + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > > + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, > > > + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, > > > + { 23, 24, -12 } > > > + } > > > + }, > > > + /* 10BPP/16BPC */ > > > + { 410, 15, 5632, 19, 28, 27, 27, { > > > + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, > > > + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > > + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, > > > + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, > > > + { 27, 28, -12 } > > > + } > > > + }, > > > +}, > > > +{ > > > + /* 12BPP/8BPC */ > > > + { 341, 15, 2048, 3, 12, 11, 11, { > > > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > > > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > > > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, > > > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > > > + } > > > + }, > > > + /* 12BPP/10BPC */ > > > + { 341, 15, 2048, 7, 16, 15, 15, { > > > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, > > > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > > > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > > > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > > > + } > > > + }, > > > + /* 12BPP/12BPC */ > > > + { 341, 15, 2048, 11, 20, 19, 19, { > > > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, > > > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > > > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > > > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > > > + { 21, 23, -12 } > > > + } > > > + }, > > > + /* 12BPP/14BPC */ > > > + { 341, 15, 2048, 15, 24, 23, 23, { > > > + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, > > > + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, > > > + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, > > > + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, > > > + { 22, 23, -12 } > > > + } > > > + }, > > > + /* 12BPP/16BPC */ > > > + { 341, 15, 2048, 19, 28, 27, 27, { > > > + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, > > > + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, > > > + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, > > > + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, > > > + { 26, 27, -12 } > > > + } > > > + }, > > > +}, > > > +{ > > > + /* 15BPP/8BPC */ > > > + { 273, 15, 2048, 3, 12, 11, 11, { > > > + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, > > > + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, > > > + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, > > > + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } > > > + } > > > + }, > > > + /* 15BPP/10BPC */ > > > + { 273, 15, 2048, 7, 16, 15, 15, { > > > + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, > > > + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, > > > + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, > > > + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } > > > + } > > > + }, > > > + /* 15BPP/12BPC */ > > > + { 273, 15, 2048, 11, 20, 19, 19, { > > > + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, > > > + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, > > > + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, > > > + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, > > > + { 16, 17, -12 } > > > + } > > > + }, > > > + /* 15BPP/14BPC */ > > > + { 273, 15, 2048, 15, 24, 23, 23, { > > > + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, > > > + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, > > > + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, > > > + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, > > > + { 20, 21, -12 } > > > + } > > > + }, > > > + /* 15BPP/16BPC */ > > > + { 273, 15, 2048, 19, 28, 27, 27, { > > > + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, > > > + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, > > > + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, > > > + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, > > > + { 24, 25, -12 } > > > + } > > > + } > > > +} > > > +}; > > > + > > > +static int get_row_index_for_rc_params(u16 compressed_bpp) > > > +{ > > > + switch (compressed_bpp) { > > > + case 6: > > > + return ROW_INDEX_6BPP; > > > + case 8: > > > + return ROW_INDEX_8BPP; > > > + case 10: > > > + return ROW_INDEX_10BPP; > > > + case 12: > > > + return ROW_INDEX_12BPP; > > > + case 15: > > > + return ROW_INDEX_15BPP; > > > + default: > > > + return -EINVAL; > > > + } > > > +} > > > + > > > +static int get_column_index_for_rc_params(u8 bits_per_component) > > > +{ > > > + switch (bits_per_component) { > > > + case 8: > > > + return COLUMN_INDEX_8BPC; > > > + case 10: > > > + return COLUMN_INDEX_10BPC; > > > + case 12: > > > + return COLUMN_INDEX_12BPC; > > > + case 14: > > > + return COLUMN_INDEX_14BPC; > > > + case 16: > > > + return COLUMN_INDEX_16BPC; > > > + default: > > > + return -EINVAL; > > > + } > > > +} > > > + > > > +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > > > + struct intel_crtc_state *pipe_config) > > > +{ > > > + struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > > > + u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; > > > + u8 i = 0; > > > + u8 row_index = 0; > > > + u8 column_index = 0; > > > + u8 line_buf_depth = 0; > > > + > > > + vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; > > > + vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; > > > + vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > > > + pipe_config->dsc_params.slice_count); > > > + /* > > > + * Slice Height of 8 works for all currently available panels. So start > > > + * with that if pic_height is an integral multiple of 8. > > > + * Eventually add logic to try multiple slice heights. > > > + */ > > > + if (vdsc_cfg->pic_height % 8 == 0) > > > + vdsc_cfg->slice_height = 8; > > > + else if (vdsc_cfg->pic_height % 4 == 0) > > > + vdsc_cfg->slice_height = 4; > > > + else > > > + vdsc_cfg->slice_height = 2; > > > + > > > + /* Values filled from DSC Sink DPCD */ > > > + vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & > > > + DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; > > > + vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN, > > > + (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & > > > + DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); > > > + > > > + vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & > > > + DP_DSC_RGB; > > > + > > > + line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); > > > > Add a check for return value of 0 > > > > > + if (vdsc_cfg->dsc_version_minor == 2) > > > + vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? > > > + DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; > > > + else > > > + vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? > > > + DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; > > > + > > > + /* Gen 11 does not support YCbCr */ > > > + vdsc_cfg->enable422 = false; > > > + /* Gen 11 does not support VBR */ > > > + vdsc_cfg->vbr_enable = false; > > > + vdsc_cfg->block_pred_enable = > > > + intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & > > > + DP_DSC_BLK_PREDICTION_IS_SUPPORTED; > > > + > > > + /* Gen 11 only supports integral values of bpp */ > > > + vdsc_cfg->bits_per_pixel = compressed_bpp << 4; > > > + vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; > > > + > > > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { > > > + /* > > > + * six 0s are appended to the lsb of each threshold value > > > + * internally in h/w. > > > + * Only 8 bits are allowed for programming RcBufThreshold > > > + */ > > > + vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; > > > + } > > > + > > > + /* > > > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value > > > + * as per C Model > > > + */ > > > + if (compressed_bpp == 6) { > > > + vdsc_cfg->rc_buf_thresh[12] = 0x7C; > > > + vdsc_cfg->rc_buf_thresh[13] = 0x7D; > > > + } > > > + > > > + row_index = get_row_index_for_rc_params(compressed_bpp); > > > + column_index = > > > + get_column_index_for_rc_params(vdsc_cfg->bits_per_component); > > > + > > > + if (row_index < 0 || column_index < 0) > > > + return -EINVAL; > > > + > > > + vdsc_cfg->first_line_bpg_offset = > > > + rc_params[row_index][column_index].first_line_bpg_offset; > > > + vdsc_cfg->initial_xmit_delay = > > > + rc_params[row_index][column_index].initial_xmit_delay; > > > + vdsc_cfg->initial_offset = > > > + rc_params[row_index][column_index].initial_offset; > > > + vdsc_cfg->flatness_min_qp = > > > + rc_params[row_index][column_index].flatness_min_qp; > > > + vdsc_cfg->flatness_max_qp = > > > + rc_params[row_index][column_index].flatness_max_qp; > > > + vdsc_cfg->rc_quant_incr_limit0 = > > > + rc_params[row_index][column_index].rc_quant_incr_limit0; > > > + vdsc_cfg->rc_quant_incr_limit1 = > > > + rc_params[row_index][column_index].rc_quant_incr_limit1; > > > + > > > + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) > > > + vdsc_cfg->rc_range_params[i] = > > > + rc_params[row_index][column_index].rc_range_params[i]; Here the range_bpg_offset is a 2's compliment 6 bit value so in order to get the correct value , we need to mask it with 0x3f to get only 6 bits. You forgot this mask from your initial patch here after the values were defined as negative values directly. For Eg: -2 will result into 11111101 binary but we should use only 6 lsb bits otherwise the remainder 2 bits interfere with the other fields in rc_range_params. I am changing it as below: vdsc_cfg->rc_range_params[i].range_bpg_offset = rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; where the mask is defined to 0x3f in the DRM patch that adds DSC capabilities. Manasi > > > + > > > + /* > > > + * BitsPerComponent value determines mux_word_size: > > > + * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits > > > + * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to > > > + * 48 bits > > > + */ > > > + if (vdsc_cfg->bits_per_component == 8 || > > > + vdsc_cfg->bits_per_component == 10) > > > + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; > > > + else if (vdsc_cfg->bits_per_component == 12) > > > + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; > > > + > > > + /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ > > > + vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > > > + (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > > > > ^^^^^vdsc_cfg->rc_model_size is only defined but not getting set anywhere. > > It should be set to DSC_RC_MODEL_SIZE_CONST defined in drm_dsc.h else it results into an incorrect default value. > > > > > + > > > + return 0; > > > +} > > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > > index 0cf2407..f178933 100644 > > > --- a/include/drm/drm_dp_helper.h > > > +++ b/include/drm/drm_dp_helper.h > > > @@ -186,6 +186,9 @@ > > > > > > #define DP_GUID 0x030 /* 1.2 */ > > > > > > +#define DP_DSC_RC_PIXELS_PER_GROUP 3 > > > +#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 > > > > This patch in drm should be sent as a separate patch or combined with the patch > > where you are defining DRM DSC parameters and constants. > > > > Manasi > > > > > + > > > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > > > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > > > > > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > > > index 4cfcd03..796c798 100644 > > > --- a/include/drm/drm_dsc.h > > > +++ b/include/drm/drm_dsc.h > > > @@ -67,7 +67,7 @@ struct dsc_rc_range_parameters { > > > /* Max Quantization Parameters allowed for this range */ > > > u8 range_max_qp; > > > /* Bits/group offset to apply to target for this group */ > > > - u8 range_bpg_offset; > > > + s8 range_bpg_offset; > > This cannot be signed int since the PPS value expects it to be 2s complement > and stored as an unsigned value. It needs to stay as u8 > > Manasi > > > > }; > > > > > > struct drm_dsc_config { > > > -- > > > 2.7.4 > > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (14 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-09-05 21:10 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare ` (14 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx From: Gaurav K Singh <gaurav.k.singh@intel.com> This computation of RC params happens in the atomic commit phase during compute_config() to validate if display stream compression can be enabled for the requested mode. v5 (From Manasi): * Fix dim checkpatch warnings/checks v4(From Gaurav): * No change.Rebase on drm-tip v3 (From Gaurav): * Rebase on top of Manasi's latest series * Return -ve value in case of failure scenarios (Manasi) Fix review comments from Ville: * Remove unnecessary comments * Remove unnecessary paranthesis * Add comments for few RC params calculations v2 (From Manasi): * Rebase Gaurav's patch from intel-gfx to gfx-internal * Use struct drm_dsc_cfg instead of struct intel_dp as a parameter Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_vdsc.c | 129 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index ecd270c..23ba083 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -335,6 +335,132 @@ static int get_column_index_for_rc_params(u8 bits_per_component) } } +static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) +{ + unsigned long groups_per_line = 0; + unsigned long groups_total = 0; + unsigned long num_extra_mux_bits = 0; + unsigned long slice_bits = 0; + unsigned long hrd_delay = 0; + unsigned long final_scale = 0; + unsigned long rbs_min = 0; + + /* RC_MODEL_SIZE is a constant across all configurations */ + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DP_DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, 8); + + if (vdsc_cfg->convert_rgb) + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + - 2); + else + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 2 * (4 * vdsc_cfg->bits_per_component) - 2; + /* Number of bits in one Slice */ + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; + + while ((num_extra_mux_bits > 0) && + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) + num_extra_mux_bits--; + + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) + vdsc_cfg->initial_scale_value = groups_per_line + 8; + + /* scale_decrement_interval calculation according to DSC spec 1.11 */ + if (vdsc_cfg->initial_scale_value > 8) + vdsc_cfg->scale_decrement_interval = groups_per_line / + (8 * vdsc_cfg->initial_scale_value - 8); + else + vdsc_cfg->scale_decrement_interval = + DP_DSC_SCALE_DECREMENT_INTERVAL_MAX; + + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - + (vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel) + num_extra_mux_bits; + + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { + DRM_ERROR("FinalOfs < RcModelSze for this InitialXmitDelay\n"); + return -1; + } + + final_scale = (vdsc_cfg->rc_model_size << 3) / + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); + if (vdsc_cfg->slice_height > 1) + /* + * NflBpgOffset is 16 bit value with 11 fractional bits + * hence we multiply by 2^11 for preserving the + * fractional part + */ + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), + (vdsc_cfg->slice_height - 1)); + else + vdsc_cfg->nfl_bpg_offset = 0; + + /* 2^16 - 1 */ + if (vdsc_cfg->nfl_bpg_offset > 65535) { + DRM_ERROR("NflBpgOffset is too large for this slice height\n"); + return -1; + } + + /* Number of groups used to code the entire slice */ + groups_total = groups_per_line * vdsc_cfg->slice_height; + + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - + vdsc_cfg->initial_offset + + num_extra_mux_bits) << 11), + groups_total); + + if (final_scale > 0x9) { + /* + * ScaleIncrementInterval = + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, + * we need divide by 2^11 from pstDscCfg values + */ + vdsc_cfg->scale_increment_interval = + (vdsc_cfg->final_offset * (1 << 11)) / + ((vdsc_cfg->nfl_bpg_offset + + vdsc_cfg->slice_bpg_offset)* + (final_scale - 9)); + } else { + /* + * If finalScaleValue is less than or equal to 9, a value of 0 should + * be used to disable the scale increment at the end of the slice + */ + vdsc_cfg->scale_increment_interval = 0; + } + + if (vdsc_cfg->scale_increment_interval > 65535) { + DRM_ERROR("ScaleIncrementInterval is large for slice height\n"); + return -1; + } + + /* + * DSC spec mentions that bits_per_pixel specifies the target + * bits/pixel (bpp) rate that is used by the encoder, + * in steps of 1/16 of a bit per pixel + */ + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel, 16) + + groups_per_line * vdsc_cfg->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; + + return 0; +} + + int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config) { @@ -451,5 +577,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); + if (intel_compute_rc_parameters(vdsc_cfg) < 0) + return -1; + return 0; } -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC 2018-07-31 21:07 ` [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare @ 2018-09-05 21:10 ` Manasi Navare 0 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-09-05 21:10 UTC (permalink / raw) To: intel-gfx Gaurav, I needed to make following changes to teh RC parameter values during testing to get this to work: On Tue, Jul 31, 2018 at 02:07:12PM -0700, Manasi Navare wrote: > From: Gaurav K Singh <gaurav.k.singh@intel.com> > > This computation of RC params happens in the atomic commit phase > during compute_config() to validate if display stream compression > can be enabled for the requested mode. > > v5 (From Manasi): > * Fix dim checkpatch warnings/checks > v4(From Gaurav): > * No change.Rebase on drm-tip > > v3 (From Gaurav): > * Rebase on top of Manasi's latest series > * Return -ve value in case of failure scenarios (Manasi) > > Fix review comments from Ville: > * Remove unnecessary comments > * Remove unnecessary paranthesis > * Add comments for few RC params calculations > > v2 (From Manasi): > * Rebase Gaurav's patch from intel-gfx to gfx-internal > * Use struct drm_dsc_cfg instead of struct intel_dp > as a parameter > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/intel_vdsc.c | 129 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 129 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > index ecd270c..23ba083 100644 > --- a/drivers/gpu/drm/i915/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > @@ -335,6 +335,132 @@ static int get_column_index_for_rc_params(u8 bits_per_component) > } > } > > +static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) > +{ > + unsigned long groups_per_line = 0; > + unsigned long groups_total = 0; > + unsigned long num_extra_mux_bits = 0; > + unsigned long slice_bits = 0; > + unsigned long hrd_delay = 0; > + unsigned long final_scale = 0; > + unsigned long rbs_min = 0; > + > + /* RC_MODEL_SIZE is a constant across all configurations */ > + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > + /* Number of groups used to code each line of a slice */ > + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, > + DP_DSC_RC_PIXELS_PER_GROUP); > + > + /* chunksize in Bytes */ > + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * > + vdsc_cfg->bits_per_pixel, 8); ^^8 * 16 This is what you had in the initial patches and thats the value that works. The DSC spec actually has it as just 8, could you tell how you got the 8*16 in your original patches? > + > + if (vdsc_cfg->convert_rgb) > + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + > + (4 * vdsc_cfg->bits_per_component + 4) > + - 2); > + else > + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + > + (4 * vdsc_cfg->bits_per_component + 4) + > + 2 * (4 * vdsc_cfg->bits_per_component) - 2; > + /* Number of bits in one Slice */ > + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; > + > + while ((num_extra_mux_bits > 0) && > + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) > + num_extra_mux_bits--; > + > + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) > + vdsc_cfg->initial_scale_value = groups_per_line + 8; > + > + /* scale_decrement_interval calculation according to DSC spec 1.11 */ > + if (vdsc_cfg->initial_scale_value > 8) > + vdsc_cfg->scale_decrement_interval = groups_per_line / > + (8 * vdsc_cfg->initial_scale_value - 8); ^^vdsc_cfg->initial_scale_value - 8 This is how it was set in your original patches. > + else > + vdsc_cfg->scale_decrement_interval = > + DP_DSC_SCALE_DECREMENT_INTERVAL_MAX; > + > + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - > + (vdsc_cfg->initial_xmit_delay * > + vdsc_cfg->bits_per_pixel) + num_extra_mux_bits; ^^^^^vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; Which was in your original patch. Could you change these back to the original patch values and have a comment about how they are obtained. Manasi > + > + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { > + DRM_ERROR("FinalOfs < RcModelSze for this InitialXmitDelay\n"); > + return -1; > + } > + > + final_scale = (vdsc_cfg->rc_model_size << 3) / > + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); > + if (vdsc_cfg->slice_height > 1) > + /* > + * NflBpgOffset is 16 bit value with 11 fractional bits > + * hence we multiply by 2^11 for preserving the > + * fractional part > + */ > + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), > + (vdsc_cfg->slice_height - 1)); > + else > + vdsc_cfg->nfl_bpg_offset = 0; > + > + /* 2^16 - 1 */ > + if (vdsc_cfg->nfl_bpg_offset > 65535) { > + DRM_ERROR("NflBpgOffset is too large for this slice height\n"); > + return -1; > + } > + > + /* Number of groups used to code the entire slice */ > + groups_total = groups_per_line * vdsc_cfg->slice_height; > + > + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ > + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - > + vdsc_cfg->initial_offset + > + num_extra_mux_bits) << 11), > + groups_total); > + > + if (final_scale > 0x9) { > + /* > + * ScaleIncrementInterval = > + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) > + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, > + * we need divide by 2^11 from pstDscCfg values > + */ > + vdsc_cfg->scale_increment_interval = > + (vdsc_cfg->final_offset * (1 << 11)) / > + ((vdsc_cfg->nfl_bpg_offset + > + vdsc_cfg->slice_bpg_offset)* > + (final_scale - 9)); > + } else { > + /* > + * If finalScaleValue is less than or equal to 9, a value of 0 should > + * be used to disable the scale increment at the end of the slice > + */ > + vdsc_cfg->scale_increment_interval = 0; > + } > + > + if (vdsc_cfg->scale_increment_interval > 65535) { > + DRM_ERROR("ScaleIncrementInterval is large for slice height\n"); > + return -1; > + } > + > + /* > + * DSC spec mentions that bits_per_pixel specifies the target > + * bits/pixel (bpp) rate that is used by the encoder, > + * in steps of 1/16 of a bit per pixel > + */ > + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + > + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * > + vdsc_cfg->bits_per_pixel, 16) + > + groups_per_line * vdsc_cfg->first_line_bpg_offset; > + > + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); > + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; > + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; > + > + return 0; > +} > + > + > int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > struct intel_crtc_state *pipe_config) > { > @@ -451,5 +577,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > > + if (intel_compute_rc_parameters(vdsc_cfg) < 0) > + return -1; > + > return 0; > } > -- > 2.7.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (15 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-31 18:21 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare ` (13 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx From: Gaurav K Singh <gaurav.k.singh@intel.com> This patch enables decompression support in sink device before link training and disables the same during the DDI disabling. v2:(From Manasi) * Change the enable/disable function to take crtc_state instead of intel_dp as an argument (Manasi) * Use the compression_enable flag as part of crtc_state (Manasi) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 5 +++++ drivers/gpu/drm/i915/intel_dp.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 0adc043..5e8c891 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2825,6 +2825,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_ddi_init_dp_buf_reg(encoder); if (!is_mst) intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); + intel_dp_sink_set_decompression_state(intel_dp, crtc_state, + DP_DECOMPRESSION_EN); intel_dp_start_link_train(intel_dp); if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); @@ -3154,6 +3156,9 @@ static void intel_disable_ddi_dp(struct intel_encoder *encoder, intel_edp_drrs_disable(intel_dp, old_crtc_state); intel_psr_disable(intel_dp, old_crtc_state); intel_edp_backlight_off(old_conn_state); + /* Disable the decompression in DP Sink */ + intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, + ~DP_DECOMPRESSION_EN); } static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index dc0a3c2..1a8329c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2925,6 +2925,21 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; } +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int state) +{ + int ret; + + if (!crtc_state->dsc_params.compression_enable) + return; + + ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, state); + if (ret < 0) + DRM_DEBUG_KMS("Failed to %s sink decompression state\n", + state == DP_DECOMPRESSION_EN ? "enable" : "disable"); +} + /* If the sink supports it, try to set the power state appropriately */ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 33cc777..ced62e0 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1691,6 +1691,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp); int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx); void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int state); void intel_dp_encoder_reset(struct drm_encoder *encoder); void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void intel_dp_encoder_destroy(struct drm_encoder *encoder); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink 2018-07-31 21:07 ` [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare @ 2018-08-31 18:21 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-31 18:21 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Singh, Gaurav K <gaurav.k.singh@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Navare, Manasi D ><manasi.d.navare@intel.com> >Subject: [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink > >From: Gaurav K Singh <gaurav.k.singh@intel.com> > >This patch enables decompression support in sink device before link training and >disables the same during the DDI disabling. > >v2:(From Manasi) >* Change the enable/disable function to take crtc_state instead of intel_dp as an >argument (Manasi) >* Use the compression_enable flag as part of crtc_state (Manasi) > >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Looks good. Setting the state at the right time. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/intel_ddi.c | 5 +++++ drivers/gpu/drm/i915/intel_dp.c | >15 +++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ > 3 files changed, 23 insertions(+) > >diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >index 0adc043..5e8c891 100644 >--- a/drivers/gpu/drm/i915/intel_ddi.c >+++ b/drivers/gpu/drm/i915/intel_ddi.c >@@ -2825,6 +2825,8 @@ static void intel_ddi_pre_enable_dp(struct >intel_encoder *encoder, > intel_ddi_init_dp_buf_reg(encoder); > if (!is_mst) > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); >+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state, >+ DP_DECOMPRESSION_EN); > intel_dp_start_link_train(intel_dp); > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) > intel_dp_stop_link_train(intel_dp); >@@ -3154,6 +3156,9 @@ static void intel_disable_ddi_dp(struct intel_encoder >*encoder, > intel_edp_drrs_disable(intel_dp, old_crtc_state); > intel_psr_disable(intel_dp, old_crtc_state); > intel_edp_backlight_off(old_conn_state); >+ /* Disable the decompression in DP Sink */ >+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, >+ ~DP_DECOMPRESSION_EN); > } > > static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, diff --git >a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index >dc0a3c2..1a8329c 100644 >--- a/drivers/gpu/drm/i915/intel_dp.c >+++ b/drivers/gpu/drm/i915/intel_dp.c >@@ -2925,6 +2925,21 @@ static bool downstream_hpd_needs_d0(struct >intel_dp *intel_dp) > intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; } > >+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, >+ const struct intel_crtc_state >*crtc_state, >+ int state) >+{ >+ int ret; >+ >+ if (!crtc_state->dsc_params.compression_enable) >+ return; >+ >+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, state); >+ if (ret < 0) >+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n", >+ state == DP_DECOMPRESSION_EN ? "enable" : >"disable"); } >+ > /* If the sink supports it, try to set the power state appropriately */ void >intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) { diff --git >a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >index 33cc777..ced62e0 100644 >--- a/drivers/gpu/drm/i915/intel_drv.h >+++ b/drivers/gpu/drm/i915/intel_drv.h >@@ -1691,6 +1691,9 @@ void intel_dp_stop_link_train(struct intel_dp >*intel_dp); int intel_dp_retrain_link(struct intel_encoder *encoder, > struct drm_modeset_acquire_ctx *ctx); void >intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); >+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, >+ const struct intel_crtc_state >*crtc_state, >+ int state); > void intel_dp_encoder_reset(struct drm_encoder *encoder); void >intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void >intel_dp_encoder_destroy(struct drm_encoder *encoder); >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (16 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-06 19:41 ` [PATCH v3] " Manasi Navare 2018-08-06 19:50 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare ` (12 subsequent siblings) 30 siblings, 2 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the pipe and after compression is enabled on the sink. v2: * Enable PG2 power well for VDSC on eDP Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_display.c | 6 + drivers/gpu/drm/i915/intel_vdsc.c | 423 +++++++++++++++++++++++++++++++++++ 3 files changed, 431 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 334a5db..0ffc9a7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3425,6 +3425,8 @@ extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); +extern void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index de895ab..6b1d151 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5410,6 +5410,12 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc, if (encoder->pre_enable) encoder->pre_enable(encoder, crtc_state, conn_state); + + /* + * Enable and Configure Display Stream Compression in the source + * if enabled in intel_crtc_state. + */ + intel_dsc_enable(encoder, crtc_state); } } diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 23ba083..e3db9dc 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -582,3 +582,426 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, return 0; } + +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + enum pipe pipe = crtc->pipe; + u32 pps_val = 0; + u32 rc_buf_thresh_dword[4]; + u32 rc_range_params_dword[8]; + u8 num_vdsc_instances = 0; + int i = 0; + + /* Populate PICTURE_PARAMETER_SET_0 registers */ + pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << + DSC_VER_MIN_SHIFT | + vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | + vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; + if (vdsc_cfg->block_pred_enable) + pps_val |= DSC_BLOCK_PREDICTION; + else + pps_val &= ~DSC_BLOCK_PREDICTION; + if (vdsc_cfg->convert_rgb) + pps_val |= DSC_COLOR_SPACE_CONVERSION; + else + pps_val &= ~DSC_COLOR_SPACE_CONVERSION; + if (vdsc_cfg->enable422) + pps_val |= DSC_422_ENABLE; + else + pps_val &= ~DSC_422_ENABLE; + if (vdsc_cfg->vbr_enable) + pps_val |= DSC_VBR_ENABLE; + else + pps_val &= ~DSC_VBR_ENABLE; + + DRM_INFO("PPS0 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_1 registers */ + pps_val = 0; + pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); + DRM_INFO("PPS1 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_2 registers */ + pps_val = 0; + pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | + DSC_PIC_WIDTH(vdsc_cfg->pic_width); + DRM_INFO("PPS2 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_3 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | + DSC_SLICE_WIDTH(vdsc_cfg->slice_width); + DRM_INFO("PPS3 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_4 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | + DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); + DRM_INFO("PPS4 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), + pps_val); + } + + /* Populate PICTIRE_PARAMETER_SET_5 registers */ + pps_val = 0; + pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | + DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); + DRM_INFO("PPS5 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_6 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | + DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | + DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | + DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); + DRM_INFO("PPS6 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_7 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | + DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); + DRM_INFO("PPS7 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_8 registers */ + pps_val = 0; + pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | + DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); + DRM_INFO("PPS8 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_9 registers */ + pps_val = 0; + pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | + DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); + DRM_INFO("PPS9 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_10 registers */ + pps_val = 0; + pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | + DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | + DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | + DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); + DRM_INFO("PPS10 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), + pps_val); + } + + /* Populate the RC_BUF_THRESH registers */ + memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { + rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << + BITS_PER_BYTE * (i%4)); + DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, + rc_buf_thresh_dword[i/4]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); + I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); + I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); + I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_BUF_THRESH_0, + rc_buf_thresh_dword[0]); + I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, + rc_buf_thresh_dword[1]); + I915_WRITE(DSCC_RC_BUF_THRESH_1, + rc_buf_thresh_dword[2]); + I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, + rc_buf_thresh_dword[3]); + } + } else { + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + } + } + + /* Populate the RC_RANGE_PARAMETERS registers */ + memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << + RC_BPG_OFFSET_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_max_qp << + RC_MAX_QP_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_min_qp << + RC_MIN_QP_SHIFT)) << 16 * (i%2)); + DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, + rc_range_params_dword[i/2]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + } + } else { + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + } + } + + /* Populate Picture parameter set 16 */ + pps_val = 0; + num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; + pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | + DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / + vdsc_cfg->slice_width); + DRM_INFO("PPS16 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), + pps_val); + } +} + +void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + + if (!crtc_state->dsc_params.compression_enable) + return; + + /* Enable PG2 for VDSC on eDP*/ + /* FIXME: Use VDSC Power domain when its added */ + if (intel_dp_is_edp(intel_dp)) + intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); + + intel_configure_pps_for_dsc_encoder(encoder, crtc_state); + + return; +} -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v3] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 2018-07-31 21:07 ` [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare @ 2018-08-06 19:41 ` Manasi Navare 2018-08-06 19:50 ` Manasi Navare 1 sibling, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-06 19:41 UTC (permalink / raw) To: intel-gfx After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the pipe and after compression is enabled on the sink. v3: * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe are used (Manasi) v2: * Enable PG2 power well for VDSC on eDP Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_display.c | 6 + drivers/gpu/drm/i915/intel_vdsc.c | 423 +++++++++++++++++++++++++++++++++++ 3 files changed, 431 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 22c5ad6..dda690f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3433,6 +3433,8 @@ extern void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive); extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); +extern void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4931d59..94de4ef 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5410,6 +5410,12 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc, if (encoder->pre_enable) encoder->pre_enable(encoder, crtc_state, conn_state); + + /* + * Enable and Configure Display Stream Compression in the source + * if enabled in intel_crtc_state. + */ + intel_dsc_enable(encoder, crtc_state); } } diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 23ba083..e2f3f35 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -582,3 +582,426 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, return 0; } + +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + enum pipe pipe = crtc->pipe; + u32 pps_val = 0; + u32 rc_buf_thresh_dword[4]; + u32 rc_range_params_dword[8]; + u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; + int i = 0; + + /* Populate PICTURE_PARAMETER_SET_0 registers */ + pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << + DSC_VER_MIN_SHIFT | + vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | + vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; + if (vdsc_cfg->block_pred_enable) + pps_val |= DSC_BLOCK_PREDICTION; + else + pps_val &= ~DSC_BLOCK_PREDICTION; + if (vdsc_cfg->convert_rgb) + pps_val |= DSC_COLOR_SPACE_CONVERSION; + else + pps_val &= ~DSC_COLOR_SPACE_CONVERSION; + if (vdsc_cfg->enable422) + pps_val |= DSC_422_ENABLE; + else + pps_val &= ~DSC_422_ENABLE; + if (vdsc_cfg->vbr_enable) + pps_val |= DSC_VBR_ENABLE; + else + pps_val &= ~DSC_VBR_ENABLE; + + DRM_INFO("PPS0 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_1 registers */ + pps_val = 0; + pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); + DRM_INFO("PPS1 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_2 registers */ + pps_val = 0; + pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | + DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); + DRM_INFO("PPS2 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_3 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | + DSC_SLICE_WIDTH(vdsc_cfg->slice_width); + DRM_INFO("PPS3 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_4 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | + DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); + DRM_INFO("PPS4 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), + pps_val); + } + + /* Populate PICTIRE_PARAMETER_SET_5 registers */ + pps_val = 0; + pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | + DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); + DRM_INFO("PPS5 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_6 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | + DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | + DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | + DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); + DRM_INFO("PPS6 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_7 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | + DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); + DRM_INFO("PPS7 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_8 registers */ + pps_val = 0; + pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | + DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); + DRM_INFO("PPS8 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_9 registers */ + pps_val = 0; + pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | + DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); + DRM_INFO("PPS9 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_10 registers */ + pps_val = 0; + pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | + DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | + DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | + DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); + DRM_INFO("PPS10 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), + pps_val); + } + + /* Populate the RC_BUF_THRESH registers */ + memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { + rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << + BITS_PER_BYTE * (i%4)); + DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, + rc_buf_thresh_dword[i/4]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); + I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); + I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); + I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_BUF_THRESH_0, + rc_buf_thresh_dword[0]); + I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, + rc_buf_thresh_dword[1]); + I915_WRITE(DSCC_RC_BUF_THRESH_1, + rc_buf_thresh_dword[2]); + I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, + rc_buf_thresh_dword[3]); + } + } else { + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + } + } + + /* Populate the RC_RANGE_PARAMETERS registers */ + memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << + RC_BPG_OFFSET_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_max_qp << + RC_MAX_QP_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_min_qp << + RC_MIN_QP_SHIFT)) << 16 * (i%2)); + DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, + rc_range_params_dword[i/2]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + } + } else { + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + } + } + + /* Populate Picture parameter set 16 */ + pps_val = 0; + pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | + DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / + vdsc_cfg->slice_width); + DRM_INFO("PPS16 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), + pps_val); + } +} + +void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + if (!crtc_state->dsc_params.compression_enable) + return; + + /* Enable PG2 for VDSC on eDP*/ + /* FIXME: Use VDSC Power domain when its added */ + if (intel_dp_is_edp(intel_dp)) + intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); + + intel_configure_pps_for_dsc_encoder(encoder, crtc_state); + + return; +} -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v3] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 2018-07-31 21:07 ` [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare 2018-08-06 19:41 ` [PATCH v3] " Manasi Navare @ 2018-08-06 19:50 ` Manasi Navare 1 sibling, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-08-06 19:50 UTC (permalink / raw) To: intel-gfx After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the pipe and after compression is enabled on the sink. v3: * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe are used (Manasi) v2: * Enable PG2 power well for VDSC on eDP Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_display.c | 6 + drivers/gpu/drm/i915/intel_vdsc.c | 423 +++++++++++++++++++++++++++++++++++ 3 files changed, 431 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 22c5ad6..dda690f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3433,6 +3433,8 @@ extern void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive); extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); +extern void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4931d59..94de4ef 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5410,6 +5410,12 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc, if (encoder->pre_enable) encoder->pre_enable(encoder, crtc_state, conn_state); + + /* + * Enable and Configure Display Stream Compression in the source + * if enabled in intel_crtc_state. + */ + intel_dsc_enable(encoder, crtc_state); } } diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 23ba083..e2f3f35 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -582,3 +582,426 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, return 0; } + +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + enum pipe pipe = crtc->pipe; + u32 pps_val = 0; + u32 rc_buf_thresh_dword[4]; + u32 rc_range_params_dword[8]; + u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; + int i = 0; + + /* Populate PICTURE_PARAMETER_SET_0 registers */ + pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << + DSC_VER_MIN_SHIFT | + vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | + vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; + if (vdsc_cfg->block_pred_enable) + pps_val |= DSC_BLOCK_PREDICTION; + else + pps_val &= ~DSC_BLOCK_PREDICTION; + if (vdsc_cfg->convert_rgb) + pps_val |= DSC_COLOR_SPACE_CONVERSION; + else + pps_val &= ~DSC_COLOR_SPACE_CONVERSION; + if (vdsc_cfg->enable422) + pps_val |= DSC_422_ENABLE; + else + pps_val &= ~DSC_422_ENABLE; + if (vdsc_cfg->vbr_enable) + pps_val |= DSC_VBR_ENABLE; + else + pps_val &= ~DSC_VBR_ENABLE; + + DRM_INFO("PPS0 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_1 registers */ + pps_val = 0; + pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); + DRM_INFO("PPS1 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_2 registers */ + pps_val = 0; + pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | + DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); + DRM_INFO("PPS2 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_3 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | + DSC_SLICE_WIDTH(vdsc_cfg->slice_width); + DRM_INFO("PPS3 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_4 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | + DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); + DRM_INFO("PPS4 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), + pps_val); + } + + /* Populate PICTIRE_PARAMETER_SET_5 registers */ + pps_val = 0; + pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | + DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); + DRM_INFO("PPS5 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_6 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | + DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | + DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | + DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); + DRM_INFO("PPS6 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_7 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | + DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); + DRM_INFO("PPS7 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_8 registers */ + pps_val = 0; + pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | + DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); + DRM_INFO("PPS8 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_9 registers */ + pps_val = 0; + pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | + DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); + DRM_INFO("PPS9 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_10 registers */ + pps_val = 0; + pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | + DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | + DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | + DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); + DRM_INFO("PPS10 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), + pps_val); + } + + /* Populate the RC_BUF_THRESH registers */ + memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { + rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << + BITS_PER_BYTE * (i%4)); + DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, + rc_buf_thresh_dword[i/4]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); + I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); + I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); + I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_BUF_THRESH_0, + rc_buf_thresh_dword[0]); + I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, + rc_buf_thresh_dword[1]); + I915_WRITE(DSCC_RC_BUF_THRESH_1, + rc_buf_thresh_dword[2]); + I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, + rc_buf_thresh_dword[3]); + } + } else { + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + } + } + + /* Populate the RC_RANGE_PARAMETERS registers */ + memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << + RC_BPG_OFFSET_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_max_qp << + RC_MAX_QP_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_min_qp << + RC_MIN_QP_SHIFT)) << 16 * (i%2)); + DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, + rc_range_params_dword[i/2]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + } + } else { + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + } + } + + /* Populate Picture parameter set 16 */ + pps_val = 0; + pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | + DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / + vdsc_cfg->slice_width); + DRM_INFO("PPS16 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), + pps_val); + } +} + +void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + if (!crtc_state->dsc_params.compression_enable) + return; + + /* Enable PG2 for VDSC on eDP*/ + /* FIXME: Use VDSC Power domain when its added */ + if (intel_dp_is_edp(intel_dp)) + intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); + + intel_configure_pps_for_dsc_encoder(encoder, crtc_state); + + return; +} -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (17 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-28 22:57 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare ` (11 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx Infoframes are used to send secondary data packets. This patch adds support for DSC Picture parameter set secondary data packets in the existing write_infoframe helpers. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 23 +++++++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7bdc214..b8e41db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4658,6 +4658,7 @@ enum { * of the infoframe structure specified by CEA-861. */ #define VIDEO_DIP_DATA_SIZE 32 #define VIDEO_DIP_VSC_DATA_SIZE 36 +#define VIDEO_DIP_PPS_DATA_SIZE 132 #define VIDEO_DIP_CTL _MMIO(0x61170) /* Pre HSW: */ #define VIDEO_DIP_ENABLE (1 << 31) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 8363fbd..a37fbf0 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type) switch (type) { case DP_SDP_VSC: return VIDEO_DIP_ENABLE_VSC_HSW; + case DP_SDP_PPS: + return VDIP_ENABLE_PPS; case HDMI_INFOFRAME_TYPE_AVI: return VIDEO_DIP_ENABLE_AVI_HSW; case HDMI_INFOFRAME_TYPE_SPD: @@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, switch (type) { case DP_SDP_VSC: return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); + case DP_SDP_PPS: + return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_SPD: @@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, } } +static int hsw_dip_data_size(unsigned int type) +{ + switch (type) { + case DP_SDP_VSC: + return VIDEO_DIP_VSC_DATA_SIZE; + case DP_SDP_PPS: + return VIDEO_DIP_PPS_DATA_SIZE; + default: + return VIDEO_DIP_DATA_SIZE; + } +} + static void g4x_write_infoframe(struct drm_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type, @@ -390,11 +406,14 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); - int data_size = type == DP_SDP_VSC ? - VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE; + i915_reg_t data_reg; + int data_size = 0; int i; u32 val = I915_READ(ctl_reg); + data_size = hsw_dip_data_size(type); + data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); + val &= ~hsw_infoframe_enable(type); I915_WRITE(ctl_reg, val); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 2018-07-31 21:07 ` [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare @ 2018-08-28 22:57 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-28 22:57 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com> >Subject: [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for >DSC PPS SDPs > >Infoframes are used to send secondary data packets. This patch adds support for >DSC Picture parameter set secondary data packets in the existing write_infoframe >helpers. > >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_hdmi.c | 23 +++++++++++++++++++++-- > 2 files changed, 22 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >index 7bdc214..b8e41db 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -4658,6 +4658,7 @@ enum { > * of the infoframe structure specified by CEA-861. */ > #define VIDEO_DIP_DATA_SIZE 32 > #define VIDEO_DIP_VSC_DATA_SIZE 36 >+#define VIDEO_DIP_PPS_DATA_SIZE 132 > #define VIDEO_DIP_CTL _MMIO(0x61170) > /* Pre HSW: */ > #define VIDEO_DIP_ENABLE (1 << 31) >diff --git a/drivers/gpu/drm/i915/intel_hdmi.c >b/drivers/gpu/drm/i915/intel_hdmi.c >index 8363fbd..a37fbf0 100644 >--- a/drivers/gpu/drm/i915/intel_hdmi.c >+++ b/drivers/gpu/drm/i915/intel_hdmi.c >@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type) > switch (type) { > case DP_SDP_VSC: > return VIDEO_DIP_ENABLE_VSC_HSW; >+ case DP_SDP_PPS: >+ return VDIP_ENABLE_PPS; > case HDMI_INFOFRAME_TYPE_AVI: > return VIDEO_DIP_ENABLE_AVI_HSW; > case HDMI_INFOFRAME_TYPE_SPD: >@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, > switch (type) { > case DP_SDP_VSC: > return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); >+ case DP_SDP_PPS: >+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); > case HDMI_INFOFRAME_TYPE_AVI: > return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); > case HDMI_INFOFRAME_TYPE_SPD: >@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, > } > } > >+static int hsw_dip_data_size(unsigned int type) { >+ switch (type) { >+ case DP_SDP_VSC: >+ return VIDEO_DIP_VSC_DATA_SIZE; >+ case DP_SDP_PPS: >+ return VIDEO_DIP_PPS_DATA_SIZE; >+ default: >+ return VIDEO_DIP_DATA_SIZE; >+ } >+} >+ > static void g4x_write_infoframe(struct drm_encoder *encoder, > const struct intel_crtc_state *crtc_state, > unsigned int type, >@@ -390,11 +406,14 @@ static void hsw_write_infoframe(struct drm_encoder >*encoder, > struct drm_i915_private *dev_priv = to_i915(dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); >- int data_size = type == DP_SDP_VSC ? >- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE; >+ i915_reg_t data_reg; >+ int data_size = 0; > int i; > u32 val = I915_READ(ctl_reg); > >+ data_size = hsw_dip_data_size(type); >+ data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); >+ > val &= ~hsw_infoframe_enable(type); > I915_WRITE(ctl_reg, val); > >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (18 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-31 18:35 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 21/23] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare ` (10 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx DSC PPS secondary data packet infoframes are filled with DSC picure parameter set metadata according to the DSC standard. These infoframes are sent to the sink device and used during DSC decoding. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index e3db9dc..bd5dc96 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, } } +static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; + + /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ + drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp); + + /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ + drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg); + + intel_dig_port->write_infoframe(&encoder->base, crtc_state, + DP_SDP_PPS, &dp_dsc_pps_sdp, + sizeof(dp_dsc_pps_sdp)); +} + void intel_dsc_enable(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { @@ -1003,5 +1022,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, intel_configure_pps_for_dsc_encoder(encoder, crtc_state); + intel_dp_send_dsc_pps_sdp(encoder, crtc_state); + return; } -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 2018-07-31 21:07 ` [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare @ 2018-08-31 18:35 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-31 18:35 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com> >Subject: [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS >infoframes > >DSC PPS secondary data packet infoframes are filled with DSC picure parameter >set metadata according to the DSC standard. >These infoframes are sent to the sink device and used during DSC decoding. > >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > >diff --git a/drivers/gpu/drm/i915/intel_vdsc.c >b/drivers/gpu/drm/i915/intel_vdsc.c >index e3db9dc..bd5dc96 100644 >--- a/drivers/gpu/drm/i915/intel_vdsc.c >+++ b/drivers/gpu/drm/i915/intel_vdsc.c >@@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct >intel_encoder *encoder, > } > } > >+static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder, >+ struct intel_crtc_state *crtc_state) { >+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); >+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); >+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; >+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; >+ >+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ >+ drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp); >+ >+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ >+ drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg); >+ >+ intel_dig_port->write_infoframe(&encoder->base, crtc_state, >+ DP_SDP_PPS, &dp_dsc_pps_sdp, >+ sizeof(dp_dsc_pps_sdp)); >+} >+ > void intel_dsc_enable(struct intel_encoder *encoder, > struct intel_crtc_state *crtc_state) { @@ -1003,5 +1022,7 >@@ void intel_dsc_enable(struct intel_encoder *encoder, > > intel_configure_pps_for_dsc_encoder(encoder, crtc_state); > >+ intel_dp_send_dsc_pps_sdp(encoder, crtc_state); >+ > return; > } >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 21/23] drm/i915/icl: Add Display Stream Splitter control registers 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (19 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare ` (9 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com> Add defines for DSS_CTL registers. These registers specify the big joiner, splitter, overlap pixels and info regarding display stream compression enabled on left or right branch. v2: - Add define to conditionally check the buffer target depth (James Ausmus) Suggested-by: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b8e41db..0ae38b6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7792,6 +7792,39 @@ enum { #define RC_MAX_QP_SHIFT 5 #define RC_MIN_QP_SHIFT 0 +/* Display Stream Splitter Control */ +#define DSS_CTL1 _MMIO(0x67400) +#define SPLITTER_ENABLE (1 << 31) +#define JOINER_ENABLE (1 << 30) +#define DUAL_LINK_MODE_INTERLEAVE (1 << 24) +#define DUAL_LINK_MODE_FRONTBACK (0 << 24) +#define OVERLAP_PIXELS_MASK (0xf << 16) +#define OVERLAP_PIXELS(pixels) ((pixels) << 16) +#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0 + +#define DSS_CTL2 _MMIO(0x67404) +#define LEFT_BRANCH_VDSC_ENABLE (1 << 31) +#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) + +#define _ICL_PIPE_DSS_CTL1_PB 0x78200 +#define _ICL_PIPE_DSS_CTL1_PC 0x78400 +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_PIPE_DSS_CTL1_PB, \ + _ICL_PIPE_DSS_CTL1_PC) +#define BIG_JOINER_ENABLE (1 << 29) +#define MASTER_BIG_JOINER_ENABLE (1 << 28) +#define VGA_CENTERING_ENABLE (1 << 27) + +#define _ICL_PIPE_DSS_CTL2_PB 0x78204 +#define _ICL_PIPE_DSS_CTL2_PC 0x78404 +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_PIPE_DSS_CTL2_PB, \ + _ICL_PIPE_DSS_CTL2_PC) + #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v2 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (20 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 21/23] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-06 19:41 ` [PATCH v3] " Manasi Navare 2018-07-31 21:07 ` [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare ` (8 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_vdsc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index bd5dc96..32da285 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -1011,6 +1011,12 @@ void intel_dsc_enable(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum pipe pipe = crtc->pipe; + i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1_val = 0; + u32 dss_ctl2_val = 0; if (!crtc_state->dsc_params.compression_enable) return; @@ -1024,5 +1030,21 @@ void intel_dsc_enable(struct intel_encoder *encoder, intel_dp_send_dsc_pps_sdp(encoder, crtc_state); + /* Configure DSS_CTL registers for DSC */ + if (encoder->type == INTEL_OUTPUT_EDP) { + dss_ctl1_reg = DSS_CTL1; + dss_ctl2_reg = DSS_CTL2; + } else { + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); + } + dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; + if (crtc_state->dsc_params.dsc_split) { + dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; + dss_ctl1_val |= JOINER_ENABLE; + } + I915_WRITE(dss_ctl1_reg, dss_ctl1_val); + I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + return; } -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v3] drm/i915/dp: Configure Display stream splitter registers during DSC enable 2018-07-31 21:07 ` [PATCH v2 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare @ 2018-08-06 19:41 ` Manasi Navare 2018-08-31 18:52 ` Srivatsa, Anusha 0 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-08-06 19:41 UTC (permalink / raw) To: intel-gfx Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. v2: * Rebase (Manasi) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 098f9b6..10e38396 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -1011,6 +1011,11 @@ void intel_dsc_enable(struct intel_encoder *encoder, { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + enum pipe pipe = crtc->pipe; + i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1_val = 0; + u32 dss_ctl2_val = 0; if (!crtc_state->dsc_params.compression_enable) return; @@ -1024,5 +1029,21 @@ void intel_dsc_enable(struct intel_encoder *encoder, intel_dp_send_dsc_pps_sdp(encoder, crtc_state); + /* Configure DSS_CTL registers for DSC */ + if (encoder->type == INTEL_OUTPUT_EDP) { + dss_ctl1_reg = DSS_CTL1; + dss_ctl2_reg = DSS_CTL2; + } else { + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); + } + dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; + if (crtc_state->dsc_params.dsc_split) { + dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; + dss_ctl1_val |= JOINER_ENABLE; + } + I915_WRITE(dss_ctl1_reg, dss_ctl1_val); + I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + return; } -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v3] drm/i915/dp: Configure Display stream splitter registers during DSC enable 2018-08-06 19:41 ` [PATCH v3] " Manasi Navare @ 2018-08-31 18:52 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-31 18:52 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Monday, August 6, 2018 12:41 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com> >Subject: [PATCH v3] drm/i915/dp: Configure Display stream splitter registers >during DSC enable > >Display Stream Splitter registers need to be programmed to enable the joiner if >two DSC engines are used and also to enable the left and the right DSC engines. >This happens as part of the DSC enabling routine in the source in atomic commit. > >v2: >* Rebase (Manasi) This is v2 of the patch correct? No functional changes since the v1...only rebase. I got confused with the patch prefix. But the patch itself looks good, assuming this is the latest version: Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom> >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> >--- > drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > >diff --git a/drivers/gpu/drm/i915/intel_vdsc.c >b/drivers/gpu/drm/i915/intel_vdsc.c >index 098f9b6..10e38396 100644 >--- a/drivers/gpu/drm/i915/intel_vdsc.c >+++ b/drivers/gpu/drm/i915/intel_vdsc.c >@@ -1011,6 +1011,11 @@ void intel_dsc_enable(struct intel_encoder *encoder, >{ > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >+ enum pipe pipe = crtc->pipe; >+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg; >+ u32 dss_ctl1_val = 0; >+ u32 dss_ctl2_val = 0; > > if (!crtc_state->dsc_params.compression_enable) > return; >@@ -1024,5 +1029,21 @@ void intel_dsc_enable(struct intel_encoder *encoder, > > intel_dp_send_dsc_pps_sdp(encoder, crtc_state); > >+ /* Configure DSS_CTL registers for DSC */ >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ dss_ctl1_reg = DSS_CTL1; >+ dss_ctl2_reg = DSS_CTL2; >+ } else { >+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); >+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); >+ } >+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; >+ if (crtc_state->dsc_params.dsc_split) { >+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; >+ dss_ctl1_val |= JOINER_ENABLE; >+ } >+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val); >+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val); >+ > return; > } >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (21 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare @ 2018-07-31 21:07 ` Manasi Navare 2018-08-31 21:42 ` Srivatsa, Anusha 2018-07-31 22:07 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP Patchwork ` (7 subsequent siblings) 30 siblings, 1 reply; 73+ messages in thread From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw) To: intel-gfx From: Gaurav K Singh <gaurav.k.singh@intel.com> 1. Disable Left/right VDSC branch in DSS Ctrl reg depending on the number of VDSC engines being used 2. Disable joiner in DSS Ctrl reg v5 (From Manasi): * Add Disable PG2 for VDSC on eDP v4: (From Manasi) * Rebase on top of revised patches v3 (From Manasi): * Use old_crtc_state to find dsc params * Add a condition to disable only if dsc state compression is enabled * Use correct DSS CTL regs v2 (From Manasi): * Fix tons of compilation errors like undefined variables, incorrect use of macros and all dirty laundry Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++ drivers/gpu/drm/i915/intel_vdsc.c | 38 ++++++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0ffc9a7..cb6a80a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3427,6 +3427,8 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); extern void intel_dsc_enable(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state); +extern void intel_dsc_disable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6b1d151..2b0be6f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5829,6 +5829,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; + struct drm_connector_state *conn_state; + struct drm_connector *conn; + int i; intel_encoders_disable(crtc, old_crtc_state, old_state); @@ -5845,6 +5848,16 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_disable_transcoder_func(old_crtc_state); + for_each_new_connector_in_state(old_state, conn, conn_state, i) { + struct intel_encoder *encoder = + to_intel_encoder(conn_state->best_encoder); + + if (conn_state->crtc != crtc) + continue; + + intel_dsc_disable(encoder, old_crtc_state); + } + if (INTEL_GEN(dev_priv) >= 9) skylake_scaler_disable(intel_crtc); else diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 32da285..96f6f94 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -1048,3 +1048,41 @@ void intel_dsc_enable(struct intel_encoder *encoder, return; } + +void intel_dsc_disable(struct intel_encoder *encoder, + struct intel_crtc_state *old_crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum pipe pipe = crtc->pipe; + i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1_val = 0, dss_ctl2_val = 0; + + if (!old_crtc_state->dsc_params.compression_enable) + return; + + if (encoder->type == INTEL_OUTPUT_EDP) { + dss_ctl1_reg = DSS_CTL1; + dss_ctl2_reg = DSS_CTL2; + } else { + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); + } + dss_ctl1_val = I915_READ(dss_ctl1_reg); + if (dss_ctl1_val & JOINER_ENABLE) + dss_ctl1_val &= ~JOINER_ENABLE; + I915_WRITE(dss_ctl1_reg, dss_ctl1_val); + + dss_ctl2_val = I915_READ(dss_ctl2_reg); + if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || + dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) + dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | + RIGHT_BRANCH_VDSC_ENABLE); + I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + + /* Put the PG2 power well for VDSC on eDP */ + /* FIXME: Use VDSC power domain when its added */ + if (intel_dp_is_edp(intel_dp)) + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); +} -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits 2018-07-31 21:07 ` [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare @ 2018-08-31 21:42 ` Srivatsa, Anusha 0 siblings, 0 replies; 73+ messages in thread From: Srivatsa, Anusha @ 2018-08-31 21:42 UTC (permalink / raw) To: Navare, Manasi D, intel-gfx >-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Singh, Gaurav K <gaurav.k.singh@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Navare, Manasi D ><manasi.d.navare@intel.com> >Subject: [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS >CTL bits > >From: Gaurav K Singh <gaurav.k.singh@intel.com> > >1. Disable Left/right VDSC branch in DSS Ctrl reg > depending on the number of VDSC engines being used 2. Disable joiner in DSS >Ctrl reg > >v5 (From Manasi): >* Add Disable PG2 for VDSC on eDP >v4: (From Manasi) >* Rebase on top of revised patches >v3 (From Manasi): >* Use old_crtc_state to find dsc params >* Add a condition to disable only if >dsc state compression is enabled >* Use correct DSS CTL regs >v2 (From Manasi): >* Fix tons of compilation errors like undefined variables, incorrect use of macros >and all dirty laundry > >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> >Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++ > drivers/gpu/drm/i915/intel_vdsc.c | 38 >++++++++++++++++++++++++++++++++++++ > 3 files changed, 53 insertions(+) > >diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >index 0ffc9a7..cb6a80a 100644 >--- a/drivers/gpu/drm/i915/i915_drv.h >+++ b/drivers/gpu/drm/i915/i915_drv.h >@@ -3427,6 +3427,8 @@ extern bool intel_set_memory_cxsr(struct >drm_i915_private *dev_priv, > bool enable); > extern void intel_dsc_enable(struct intel_encoder *encoder, > struct intel_crtc_state *crtc_state); >+extern void intel_dsc_disable(struct intel_encoder *encoder, >+ struct intel_crtc_state *crtc_state); > > int i915_reg_read_ioctl(struct drm_device *dev, void *data, > struct drm_file *file); >diff --git a/drivers/gpu/drm/i915/intel_display.c >b/drivers/gpu/drm/i915/intel_display.c >index 6b1d151..2b0be6f 100644 >--- a/drivers/gpu/drm/i915/intel_display.c >+++ b/drivers/gpu/drm/i915/intel_display.c >@@ -5829,6 +5829,9 @@ static void haswell_crtc_disable(struct intel_crtc_state >*old_crtc_state, > struct drm_i915_private *dev_priv = to_i915(crtc->dev); > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; >+ struct drm_connector_state *conn_state; >+ struct drm_connector *conn; >+ int i; > > intel_encoders_disable(crtc, old_crtc_state, old_state); > >@@ -5845,6 +5848,16 @@ static void haswell_crtc_disable(struct >intel_crtc_state *old_crtc_state, > if (!transcoder_is_dsi(cpu_transcoder)) > intel_ddi_disable_transcoder_func(old_crtc_state); > >+ for_each_new_connector_in_state(old_state, conn, conn_state, i) { >+ struct intel_encoder *encoder = >+ to_intel_encoder(conn_state->best_encoder); >+ >+ if (conn_state->crtc != crtc) >+ continue; >+ >+ intel_dsc_disable(encoder, old_crtc_state); >+ } >+ > if (INTEL_GEN(dev_priv) >= 9) > skylake_scaler_disable(intel_crtc); > else >diff --git a/drivers/gpu/drm/i915/intel_vdsc.c >b/drivers/gpu/drm/i915/intel_vdsc.c >index 32da285..96f6f94 100644 >--- a/drivers/gpu/drm/i915/intel_vdsc.c >+++ b/drivers/gpu/drm/i915/intel_vdsc.c >@@ -1048,3 +1048,41 @@ void intel_dsc_enable(struct intel_encoder *encoder, > > return; > } >+ >+void intel_dsc_disable(struct intel_encoder *encoder, >+ struct intel_crtc_state *old_crtc_state) { >+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); >+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); >+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >+ enum pipe pipe = crtc->pipe; >+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg; >+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0; >+ >+ if (!old_crtc_state->dsc_params.compression_enable) >+ return; >+ >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ dss_ctl1_reg = DSS_CTL1; >+ dss_ctl2_reg = DSS_CTL2; >+ } else { >+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); >+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); >+ } >+ dss_ctl1_val = I915_READ(dss_ctl1_reg); >+ if (dss_ctl1_val & JOINER_ENABLE) >+ dss_ctl1_val &= ~JOINER_ENABLE; >+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val); >+ >+ dss_ctl2_val = I915_READ(dss_ctl2_reg); >+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || >+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) >+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | >+ RIGHT_BRANCH_VDSC_ENABLE); >+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val); >+ >+ /* Put the PG2 power well for VDSC on eDP */ >+ /* FIXME: Use VDSC power domain when its added */ >+ if (intel_dp_is_edp(intel_dp)) >+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); } >-- >2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (22 preceding siblings ...) 2018-07-31 21:07 ` [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare @ 2018-07-31 22:07 ` Patchwork 2018-07-31 22:08 ` Patchwork ` (6 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-07-31 22:07 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Applying: drm/dp: Define payload size for DP SDP PPS packet Applying: drm/dsc: Define Display Stream Compression PPS infoframe Applying: drm/dsc: Define VESA Display Stream Compression Capabilities Applying: drm/dsc: Define Rate Control values that do not change over configurations Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Applying: drm/i915/dp: Compute DSC pipe config in atomic check Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Applying: drm/i915/dsc: Define & Compute VESA DSC params Applying: drm/i915/dsc: Compute Rate Control parameters for DSC Applying: drm/i915/dp: Enable/Disable DSC in DP Sink Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c). error: could not build fake ancestor Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (23 preceding siblings ...) 2018-07-31 22:07 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP Patchwork @ 2018-07-31 22:08 ` Patchwork 2018-07-31 22:40 ` Patchwork ` (5 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-07-31 22:08 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Applying: drm/dp: Define payload size for DP SDP PPS packet Applying: drm/dsc: Define Display Stream Compression PPS infoframe Applying: drm/dsc: Define VESA Display Stream Compression Capabilities Applying: drm/dsc: Define Rate Control values that do not change over configurations Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Applying: drm/i915/dp: Compute DSC pipe config in atomic check Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Applying: drm/i915/dsc: Define & Compute VESA DSC params Applying: drm/i915/dsc: Compute Rate Control parameters for DSC Applying: drm/i915/dp: Enable/Disable DSC in DP Sink Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c). error: could not build fake ancestor Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (24 preceding siblings ...) 2018-07-31 22:08 ` Patchwork @ 2018-07-31 22:40 ` Patchwork 2018-08-06 19:40 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP (rev2) Patchwork ` (4 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-07-31 22:40 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Applying: drm/dp: Define payload size for DP SDP PPS packet Applying: drm/dsc: Define Display Stream Compression PPS infoframe Applying: drm/dsc: Define VESA Display Stream Compression Capabilities Applying: drm/dsc: Define Rate Control values that do not change over configurations Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Applying: drm/i915/dp: Compute DSC pipe config in atomic check Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Applying: drm/i915/dsc: Define & Compute VESA DSC params Applying: drm/i915/dsc: Compute Rate Control parameters for DSC Applying: drm/i915/dp: Enable/Disable DSC in DP Sink Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c). error: could not build fake ancestor Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP (rev2) 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (25 preceding siblings ...) 2018-07-31 22:40 ` Patchwork @ 2018-08-06 19:40 ` Patchwork 2018-08-06 20:15 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev3) Patchwork ` (3 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-08-06 19:40 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP (rev2) URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Applying: drm/dp: Define payload size for DP SDP PPS packet Applying: drm/dsc: Define Display Stream Compression PPS infoframe Applying: drm/dsc: Define VESA Display Stream Compression Capabilities Applying: drm/dsc: Define Rate Control values that do not change over configurations Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Applying: drm/i915/dp: Compute DSC pipe config in atomic check Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Applying: drm/i915/dsc: Define & Compute VESA DSC params Applying: drm/i915/dsc: Compute Rate Control parameters for DSC Applying: drm/i915/dp: Enable/Disable DSC in DP Sink Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c). error: could not build fake ancestor Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev3) 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (26 preceding siblings ...) 2018-08-06 19:40 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP (rev2) Patchwork @ 2018-08-06 20:15 ` Patchwork 2018-08-06 20:25 ` ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-08-06 20:15 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP (rev3) URL : https://patchwork.freedesktop.org/series/47514/ State : warning == Summary == $ dim checkpatch origin/drm-tip 260bd82c6e63 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT ad45004f3beb drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 3f4cbb06f531 drm/dp: DRM DP helper/macros to get DP sink DSC parameters 84cd213b3601 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC -:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #24: * rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha) total: 0 errors, 1 warnings, 0 checks, 132 lines checked 094f8213eaf6 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 5024c746bceb drm/dp: Define payload size for DP SDP PPS packet 8cd06876e63d drm/dsc: Define Display Stream Compression PPS infoframe -:21: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #21: new file mode 100644 -:26: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #26: FILE: include/drm/drm_dsc.h:1: +/* total: 0 errors, 2 warnings, 0 checks, 365 lines checked 08a99be4a6e7 drm/dsc: Define VESA Display Stream Compression Capabilities 3382d55c3c90 drm/dsc: Define Rate Control values that do not change over configurations bdb5662452d7 drm/dsc: Add helpers for DSC picture parameter set infoframes -:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #19: * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst -:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #69: new file mode 100644 -:74: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #74: FILE: drivers/gpu/drm/drm_dsc.c:1: +/* -:210: WARNING:LONG_LINE: line over 100 characters #210: FILE: drivers/gpu/drm/drm_dsc.c:137: + pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval); -:213: WARNING:LONG_LINE: line over 100 characters #213: FILE: drivers/gpu/drm/drm_dsc.c:140: + pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval & -:214: WARNING:LONG_LINE: line over 100 characters #214: FILE: drivers/gpu/drm/drm_dsc.c:141: + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> -:276: WARNING:LONG_LINE: line over 100 characters #276: FILE: drivers/gpu/drm/drm_dsc.c:203: + pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]); total: 0 errors, 7 warnings, 0 checks, 285 lines checked 91f41efbc087 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state b86b83d10bfc drm/i915/dp: Compute DSC pipe config in atomic check -:183: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #183: FILE: drivers/gpu/drm/i915/intel_dp.c:2016: + } else { + total: 0 errors, 0 warnings, 1 checks, 256 lines checked e899b233c01b drm/i915/dp: Do not enable PSR2 if DSC is enabled 882650dcfe2e drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants f53b12e6c243 drm/i915/dsc: Define & Compute VESA DSC params -:83: WARNING:MISSING_SPACE: break quoted strings at a space character #83: FILE: drivers/gpu/drm/i915/intel_dp.c:2047: + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d" + "Compressed BPP = %d\n", -:107: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #107: new file mode 100644 -:112: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #112: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1: +/* -:411: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #411: FILE: drivers/gpu/drm/i915/intel_vdsc.c:300: +} +}; -:450: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #450: FILE: drivers/gpu/drm/i915/intel_vdsc.c:339: +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config) total: 0 errors, 3 warnings, 2 checks, 504 lines checked 1dcccc9d47d4 drm/i915/dsc: Compute Rate Control parameters for DSC -:136: CHECK:SPACING: space preferred before that '*' (ctx:VxE) #136: FILE: drivers/gpu/drm/i915/intel_vdsc.c:431: + vdsc_cfg->slice_bpg_offset)* ^ -:168: CHECK:LINE_SPACING: Please don't use multiple blank lines #168: FILE: drivers/gpu/drm/i915/intel_vdsc.c:463: + + total: 0 errors, 0 warnings, 2 checks, 140 lines checked 8a45c3bd9e1f drm/i915/dp: Enable/Disable DSC in DP Sink e6b09134e9a9 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -:34: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #34: FILE: drivers/gpu/drm/i915/i915_drv.h:3434: +extern void intel_dsc_enable(struct intel_encoder *encoder, -:322: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #322: FILE: drivers/gpu/drm/i915/intel_vdsc.c:843: + rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << ^ -:323: CHECK:SPACING: spaces preferred around that '%' (ctx:VxV) #323: FILE: drivers/gpu/drm/i915/intel_vdsc.c:844: + BITS_PER_BYTE * (i%4)); ^ -:325: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #325: FILE: drivers/gpu/drm/i915/intel_vdsc.c:846: + rc_buf_thresh_dword[i/4]); ^ -:366: WARNING:LONG_LINE: line over 100 characters #366: FILE: drivers/gpu/drm/i915/intel_vdsc.c:887: + rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << -:366: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #366: FILE: drivers/gpu/drm/i915/intel_vdsc.c:887: + rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << ^ -:371: CHECK:SPACING: spaces preferred around that '%' (ctx:VxV) #371: FILE: drivers/gpu/drm/i915/intel_vdsc.c:892: + RC_MIN_QP_SHIFT)) << 16 * (i%2)); ^ -:373: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #373: FILE: drivers/gpu/drm/i915/intel_vdsc.c:894: + rc_range_params_dword[i/2]); ^ -:486: WARNING:RETURN_VOID: void function return statements are not generally useful #486: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1007: + return; +} total: 0 errors, 2 warnings, 7 checks, 446 lines checked fc37151a8ea1 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 51deacd428b9 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 80b74dc61b97 drm/i915/icl: Add Display Stream Splitter control registers d8c7d9d3b120 drm/i915/dp: Configure Display stream splitter registers during DSC enable d910d245a98c drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -:37: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #37: FILE: drivers/gpu/drm/i915/i915_drv.h:3436: +extern void intel_dsc_disable(struct intel_encoder *encoder, total: 0 errors, 0 warnings, 1 checks, 74 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Display Stream Compression enabling on eDP/DP (rev3) 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (27 preceding siblings ...) 2018-08-06 20:15 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev3) Patchwork @ 2018-08-06 20:25 ` Patchwork 2018-08-06 20:31 ` ✓ Fi.CI.BAT: success " Patchwork 2018-08-07 0:21 ` ✓ Fi.CI.IGT: " Patchwork 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-08-06 20:25 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP (rev3) URL : https://patchwork.freedesktop.org/series/47514/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Okay! Commit: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Okay! Commit: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Okay! Commit: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC +drivers/gpu/drm/i915/intel_dp.c:4133:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4133:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4176:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4176:27: warning: expression using sizeof(void) Commit: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Okay! Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:197:61: expected restricted __be16 <noident> +drivers/gpu/drm/drm_dsc.c:197:61: got unsigned short [unsigned] [usertype] <noident> +drivers/gpu/drm/drm_dsc.c:197:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:203:63: expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:203:63: got restricted __be16 <noident> +drivers/gpu/drm/drm_dsc.c:203:63: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:203:63: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:203:63: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:203:63: warning: incorrect type in argument 1 (different base types) Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3651:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3652:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1905:23: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:367:39: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3652:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3654:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/icl: Add Display Stream Splitter control registers Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3654:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3656:16: warning: expression using sizeof(void) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✓ Fi.CI.BAT: success for Display Stream Compression enabling on eDP/DP (rev3) 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (28 preceding siblings ...) 2018-08-06 20:25 ` ✗ Fi.CI.SPARSE: " Patchwork @ 2018-08-06 20:31 ` Patchwork 2018-08-07 0:21 ` ✓ Fi.CI.IGT: " Patchwork 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-08-06 20:31 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP (rev3) URL : https://patchwork.freedesktop.org/series/47514/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4624 -> Patchwork_9864 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/47514/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_9864 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_selftest@live_coherency: fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164) igt@drv_selftest@live_workarounds: {fi-bsw-kefka}: PASS -> DMESG-FAIL (fdo#107292) fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292) igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: PASS -> FAIL (fdo#103841) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#106103, fdo#102614) {igt@kms_psr@primary_mmap_gtt}: fi-cnl-psr: PASS -> DMESG-WARN (fdo#107372) ==== Possible fixes ==== igt@drv_selftest@live_hangcheck: fi-kbl-7560u: DMESG-FAIL (fdo#106947, fdo#106560) -> PASS fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS igt@gem_exec_suspend@basic-s3: {fi-cfl-8109u}: DMESG-WARN (fdo#107345) -> PASS +1 igt@kms_flip@basic-flip-vs-modeset: {fi-cfl-8109u}: INCOMPLETE (fdo#107468) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174 fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372 fdo#107468 https://bugs.freedesktop.org/show_bug.cgi?id=107468 == Participating hosts (52 -> 47) == Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4624 -> Patchwork_9864 CI_DRM_4624: e885609282870bc92658a5f63d592f806e8206e8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4587: 5d78c73d871525ec9caecd88ad7d9abe36637314 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9864: d910d245a98c098a5caba9af73c1bcf6ad456c98 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d910d245a98c drm/i915/dp: Disable DSC in source by disabling DSS CTL bits d8c7d9d3b120 drm/i915/dp: Configure Display stream splitter registers during DSC enable 80b74dc61b97 drm/i915/icl: Add Display Stream Splitter control registers 51deacd428b9 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes fc37151a8ea1 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs e6b09134e9a9 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 8a45c3bd9e1f drm/i915/dp: Enable/Disable DSC in DP Sink 1dcccc9d47d4 drm/i915/dsc: Compute Rate Control parameters for DSC f53b12e6c243 drm/i915/dsc: Define & Compute VESA DSC params 882650dcfe2e drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants e899b233c01b drm/i915/dp: Do not enable PSR2 if DSC is enabled b86b83d10bfc drm/i915/dp: Compute DSC pipe config in atomic check 91f41efbc087 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state bdb5662452d7 drm/dsc: Add helpers for DSC picture parameter set infoframes 3382d55c3c90 drm/dsc: Define Rate Control values that do not change over configurations 08a99be4a6e7 drm/dsc: Define VESA Display Stream Compression Capabilities 8cd06876e63d drm/dsc: Define Display Stream Compression PPS infoframe 5024c746bceb drm/dp: Define payload size for DP SDP PPS packet 094f8213eaf6 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 84cd213b3601 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC 3f4cbb06f531 drm/dp: DRM DP helper/macros to get DP sink DSC parameters ad45004f3beb drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 260bd82c6e63 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9864/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
* ✓ Fi.CI.IGT: success for Display Stream Compression enabling on eDP/DP (rev3) 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare ` (29 preceding siblings ...) 2018-08-06 20:31 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-08-07 0:21 ` Patchwork 30 siblings, 0 replies; 73+ messages in thread From: Patchwork @ 2018-08-07 0:21 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: Display Stream Compression enabling on eDP/DP (rev3) URL : https://patchwork.freedesktop.org/series/47514/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4624_full -> Patchwork_9864_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9864_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9864_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9864_full: === IGT changes === ==== Warnings ==== igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt: shard-snb: SKIP -> PASS igt@pm_rc6_residency@rc6-accuracy: shard-snb: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9864_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-snb: NOTRUN -> INCOMPLETE (fdo#105411) ==== Possible fixes ==== igt@drv_suspend@shrink: shard-snb: INCOMPLETE (fdo#106886, fdo#105411) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS igt@perf_pmu@busy-accuracy-50-bcs0: shard-snb: INCOMPLETE (fdo#105411) -> SKIP fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4624 -> Patchwork_9864 CI_DRM_4624: e885609282870bc92658a5f63d592f806e8206e8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4587: 5d78c73d871525ec9caecd88ad7d9abe36637314 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9864: d910d245a98c098a5caba9af73c1bcf6ad456c98 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9864/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 73+ messages in thread
end of thread, other threads:[~2018-09-11 11:22 UTC | newest] Thread overview: 73+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare 2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare 2018-07-31 22:17 ` Srivatsa, Anusha 2018-07-31 21:06 ` [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare 2018-07-31 22:32 ` Srivatsa, Anusha 2018-09-11 11:22 ` Singh, Gaurav K 2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare 2018-07-31 23:33 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare 2018-08-17 19:21 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare 2018-08-17 19:20 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare 2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare 2018-08-17 19:31 ` Srivatsa, Anusha 2018-08-23 20:08 ` Manasi Navare 2018-08-23 19:40 ` Harry Wentland 2018-08-23 20:12 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare 2018-08-23 20:01 ` Harry Wentland 2018-08-28 21:12 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare 2018-09-10 19:41 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare 2018-07-31 21:16 ` Chris Wilson 2018-08-03 19:18 ` Manasi Navare 2018-08-03 19:43 ` Chris Wilson 2018-08-03 19:55 ` Manasi Navare 2018-08-23 19:58 ` Harry Wentland 2018-07-31 21:07 ` [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare 2018-08-17 19:51 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare 2018-08-28 23:40 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare 2018-08-09 5:55 ` Rodrigo Vivi 2018-08-23 19:22 ` Manasi Navare 2018-08-23 20:26 ` Rodrigo Vivi 2018-08-23 20:34 ` Dhinakaran Pandiyan 2018-08-23 20:57 ` Rodrigo Vivi 2018-08-29 6:52 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare 2018-07-31 21:07 ` [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare 2018-08-28 22:18 ` Srivatsa, Anusha 2018-08-28 22:47 ` Manasi Navare 2018-08-28 23:31 ` Manasi Navare 2018-09-05 20:04 ` Manasi Navare 2018-09-05 20:33 ` Manasi Navare 2018-09-07 2:14 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare 2018-09-05 21:10 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare 2018-08-31 18:21 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare 2018-08-06 19:41 ` [PATCH v3] " Manasi Navare 2018-08-06 19:50 ` Manasi Navare 2018-07-31 21:07 ` [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare 2018-08-28 22:57 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare 2018-08-31 18:35 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 21/23] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare 2018-07-31 21:07 ` [PATCH v2 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare 2018-08-06 19:41 ` [PATCH v3] " Manasi Navare 2018-08-31 18:52 ` Srivatsa, Anusha 2018-07-31 21:07 ` [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare 2018-08-31 21:42 ` Srivatsa, Anusha 2018-07-31 22:07 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP Patchwork 2018-07-31 22:08 ` Patchwork 2018-07-31 22:40 ` Patchwork 2018-08-06 19:40 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP (rev2) Patchwork 2018-08-06 20:15 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev3) Patchwork 2018-08-06 20:25 ` ✗ Fi.CI.SPARSE: " Patchwork 2018-08-06 20:31 ` ✓ Fi.CI.BAT: success " Patchwork 2018-08-07 0:21 ` ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.