* [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
@ 2023-03-05 14:34 ~abordado
2023-03-14 0:54 ` Bin Meng
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: ~abordado @ 2023-03-05 14:34 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei
From: Afonso Bordado <afonsobordado@gmail.com>
RISC-V does not expose all extensions via hwcaps, thus some userspace
applications may want to query these via /proc/cpuinfo.
Currently when querying this file the host's file is shown instead
which is slightly confusing. Emulate a basic /proc/cpuinfo file
with mmu info and an ISA string.
Changes from V1:
- Call `g_free` on ISA string.
- Use `riscv_cpu_cfg` API.
- Query `cpu_env->xl` to check for RV32.
Signed-off-by: Afonso Bordado <afonsobordado@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
---
linux-user/syscall.c | 34 +++++++++++++++++++++++++++++--
tests/tcg/riscv64/Makefile.target | 1 +
tests/tcg/riscv64/cpuinfo.c | 30 +++++++++++++++++++++++++++
3 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/riscv64/cpuinfo.c
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 24cea6fb6a..0388f8b0b0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const char *fmt, int code)
}
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
- defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
+ defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
+ defined(TARGET_RISCV)
static int is_proc(const char *filename, const char *entry)
{
return strcmp(filename, entry) == 0;
@@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
}
#endif
+#if defined(TARGET_RISCV)
+static int open_cpuinfo(CPUArchState *cpu_env, int fd)
+{
+ int i;
+ int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
+ RISCVCPU *cpu = env_archcpu(cpu_env);
+ const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
+ char *isa_string = riscv_isa_string(cpu);
+ const char *mmu;
+
+ if (cfg->mmu) {
+ mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
+ } else {
+ mmu = "none";
+ }
+
+ for (i = 0; i < num_cpus; i++) {
+ dprintf(fd, "processor\t: %d\n", i);
+ dprintf(fd, "hart\t\t: %d\n", i);
+ dprintf(fd, "isa\t\t: %s\n", isa_string);
+ dprintf(fd, "mmu\t\t: %s\n", mmu);
+ dprintf(fd, "uarch\t\t: qemu\n\n");
+ }
+
+ g_free(isa_string);
+ return 0;
+}
+#endif
+
#if defined(TARGET_M68K)
static int open_hardware(CPUArchState *cpu_env, int fd)
{
@@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd, const char *pathname, int
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
-#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
+#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
index cc3ed65ffd..df93a2ce1f 100644
--- a/tests/tcg/riscv64/Makefile.target
+++ b/tests/tcg/riscv64/Makefile.target
@@ -4,6 +4,7 @@
VPATH += $(SRC_PATH)/tests/tcg/riscv64
TESTS += test-div
TESTS += noexec
+TESTS += cpuinfo
# Disable compressed instructions for test-noc
TESTS += test-noc
diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
new file mode 100644
index 0000000000..296abd0a8c
--- /dev/null
+++ b/tests/tcg/riscv64/cpuinfo.c
@@ -0,0 +1,30 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+
+#define BUFFER_SIZE 1024
+
+int main(void)
+{
+ char buffer[BUFFER_SIZE];
+ FILE *fp = fopen("/proc/cpuinfo", "r");
+ assert(fp != NULL);
+
+ while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
+ if (strstr(buffer, "processor") != NULL) {
+ assert(strstr(buffer, "processor\t: ") == buffer);
+ } else if (strstr(buffer, "hart") != NULL) {
+ assert(strstr(buffer, "hart\t\t: ") == buffer);
+ } else if (strstr(buffer, "isa") != NULL) {
+ assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") == 0);
+ } else if (strstr(buffer, "mmu") != NULL) {
+ assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
+ } else if (strstr(buffer, "uarch") != NULL) {
+ assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
+ }
+ }
+
+ fclose(fp);
+ return 0;
+}
--
2.34.7
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
2023-03-05 14:34 [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv ~abordado
@ 2023-03-14 0:54 ` Bin Meng
2023-03-14 4:06 ` Alistair Francis
2023-03-17 7:33 ` LIU Zhiwei
2 siblings, 0 replies; 4+ messages in thread
From: Bin Meng @ 2023-03-14 0:54 UTC (permalink / raw)
To: ~abordado
Cc: qemu-devel, Laurent Vivier, qemu-riscv, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei
On Tue, Mar 14, 2023 at 4:29 AM ~abordado <abordado@git.sr.ht> wrote:
>
> From: Afonso Bordado <afonsobordado@gmail.com>
>
> RISC-V does not expose all extensions via hwcaps, thus some userspace
> applications may want to query these via /proc/cpuinfo.
>
> Currently when querying this file the host's file is shown instead
> which is slightly confusing. Emulate a basic /proc/cpuinfo file
> with mmu info and an ISA string.
>
> Changes from V1:
The changelog should go below ---
>
> - Call `g_free` on ISA string.
> - Use `riscv_cpu_cfg` API.
> - Query `cpu_env->xl` to check for RV32.
>
> Signed-off-by: Afonso Bordado <afonsobordado@gmail.com>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> ---
> linux-user/syscall.c | 34 +++++++++++++++++++++++++++++--
> tests/tcg/riscv64/Makefile.target | 1 +
> tests/tcg/riscv64/cpuinfo.c | 30 +++++++++++++++++++++++++++
> 3 files changed, 63 insertions(+), 2 deletions(-)
> create mode 100644 tests/tcg/riscv64/cpuinfo.c
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 24cea6fb6a..0388f8b0b0 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const char *fmt, int code)
> }
>
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
> - defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
> + defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
> + defined(TARGET_RISCV)
> static int is_proc(const char *filename, const char *entry)
> {
> return strcmp(filename, entry) == 0;
> @@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> }
> #endif
>
> +#if defined(TARGET_RISCV)
> +static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> +{
> + int i;
> + int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
> + RISCVCPU *cpu = env_archcpu(cpu_env);
> + const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
> + char *isa_string = riscv_isa_string(cpu);
> + const char *mmu;
> +
> + if (cfg->mmu) {
> + mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
> + } else {
> + mmu = "none";
> + }
> +
> + for (i = 0; i < num_cpus; i++) {
> + dprintf(fd, "processor\t: %d\n", i);
> + dprintf(fd, "hart\t\t: %d\n", i);
> + dprintf(fd, "isa\t\t: %s\n", isa_string);
> + dprintf(fd, "mmu\t\t: %s\n", mmu);
> + dprintf(fd, "uarch\t\t: qemu\n\n");
> + }
> +
> + g_free(isa_string);
> + return 0;
> +}
> +#endif
> +
> #if defined(TARGET_M68K)
> static int open_hardware(CPUArchState *cpu_env, int fd)
> {
> @@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd, const char *pathname, int
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
> { "/proc/net/route", open_net_route, is_proc },
> #endif
> -#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
> +#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
> { "/proc/cpuinfo", open_cpuinfo, is_proc },
> #endif
> #if defined(TARGET_M68K)
> diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
> index cc3ed65ffd..df93a2ce1f 100644
> --- a/tests/tcg/riscv64/Makefile.target
> +++ b/tests/tcg/riscv64/Makefile.target
> @@ -4,6 +4,7 @@
> VPATH += $(SRC_PATH)/tests/tcg/riscv64
> TESTS += test-div
> TESTS += noexec
> +TESTS += cpuinfo
>
> # Disable compressed instructions for test-noc
> TESTS += test-noc
> diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
> new file mode 100644
> index 0000000000..296abd0a8c
> --- /dev/null
> +++ b/tests/tcg/riscv64/cpuinfo.c
> @@ -0,0 +1,30 @@
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <assert.h>
> +
> +#define BUFFER_SIZE 1024
> +
> +int main(void)
> +{
> + char buffer[BUFFER_SIZE];
> + FILE *fp = fopen("/proc/cpuinfo", "r");
> + assert(fp != NULL);
> +
> + while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
> + if (strstr(buffer, "processor") != NULL) {
> + assert(strstr(buffer, "processor\t: ") == buffer);
> + } else if (strstr(buffer, "hart") != NULL) {
> + assert(strstr(buffer, "hart\t\t: ") == buffer);
> + } else if (strstr(buffer, "isa") != NULL) {
> + assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") == 0);
> + } else if (strstr(buffer, "mmu") != NULL) {
> + assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
> + } else if (strstr(buffer, "uarch") != NULL) {
> + assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
> + }
> + }
> +
> + fclose(fp);
> + return 0;
> +}
Regards,
Bin
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
2023-03-05 14:34 [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv ~abordado
2023-03-14 0:54 ` Bin Meng
@ 2023-03-14 4:06 ` Alistair Francis
2023-03-17 7:33 ` LIU Zhiwei
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-03-14 4:06 UTC (permalink / raw)
To: ~abordado
Cc: qemu-devel, Laurent Vivier, qemu-riscv, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei
On Tue, Mar 14, 2023 at 6:28 AM ~abordado <abordado@git.sr.ht> wrote:
>
> From: Afonso Bordado <afonsobordado@gmail.com>
>
> RISC-V does not expose all extensions via hwcaps, thus some userspace
> applications may want to query these via /proc/cpuinfo.
>
> Currently when querying this file the host's file is shown instead
> which is slightly confusing. Emulate a basic /proc/cpuinfo file
> with mmu info and an ISA string.
>
> Changes from V1:
>
> - Call `g_free` on ISA string.
> - Use `riscv_cpu_cfg` API.
> - Query `cpu_env->xl` to check for RV32.
>
> Signed-off-by: Afonso Bordado <afonsobordado@gmail.com>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> ---
With the changelog below these dashes:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> linux-user/syscall.c | 34 +++++++++++++++++++++++++++++--
> tests/tcg/riscv64/Makefile.target | 1 +
> tests/tcg/riscv64/cpuinfo.c | 30 +++++++++++++++++++++++++++
> 3 files changed, 63 insertions(+), 2 deletions(-)
> create mode 100644 tests/tcg/riscv64/cpuinfo.c
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 24cea6fb6a..0388f8b0b0 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const char *fmt, int code)
> }
>
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
> - defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
> + defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
> + defined(TARGET_RISCV)
> static int is_proc(const char *filename, const char *entry)
> {
> return strcmp(filename, entry) == 0;
> @@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> }
> #endif
>
> +#if defined(TARGET_RISCV)
> +static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> +{
> + int i;
> + int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
> + RISCVCPU *cpu = env_archcpu(cpu_env);
> + const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
> + char *isa_string = riscv_isa_string(cpu);
> + const char *mmu;
> +
> + if (cfg->mmu) {
> + mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
> + } else {
> + mmu = "none";
> + }
> +
> + for (i = 0; i < num_cpus; i++) {
> + dprintf(fd, "processor\t: %d\n", i);
> + dprintf(fd, "hart\t\t: %d\n", i);
> + dprintf(fd, "isa\t\t: %s\n", isa_string);
> + dprintf(fd, "mmu\t\t: %s\n", mmu);
> + dprintf(fd, "uarch\t\t: qemu\n\n");
> + }
> +
> + g_free(isa_string);
> + return 0;
> +}
> +#endif
> +
> #if defined(TARGET_M68K)
> static int open_hardware(CPUArchState *cpu_env, int fd)
> {
> @@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd, const char *pathname, int
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
> { "/proc/net/route", open_net_route, is_proc },
> #endif
> -#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
> +#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
> { "/proc/cpuinfo", open_cpuinfo, is_proc },
> #endif
> #if defined(TARGET_M68K)
> diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
> index cc3ed65ffd..df93a2ce1f 100644
> --- a/tests/tcg/riscv64/Makefile.target
> +++ b/tests/tcg/riscv64/Makefile.target
> @@ -4,6 +4,7 @@
> VPATH += $(SRC_PATH)/tests/tcg/riscv64
> TESTS += test-div
> TESTS += noexec
> +TESTS += cpuinfo
>
> # Disable compressed instructions for test-noc
> TESTS += test-noc
> diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
> new file mode 100644
> index 0000000000..296abd0a8c
> --- /dev/null
> +++ b/tests/tcg/riscv64/cpuinfo.c
> @@ -0,0 +1,30 @@
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <assert.h>
> +
> +#define BUFFER_SIZE 1024
> +
> +int main(void)
> +{
> + char buffer[BUFFER_SIZE];
> + FILE *fp = fopen("/proc/cpuinfo", "r");
> + assert(fp != NULL);
> +
> + while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
> + if (strstr(buffer, "processor") != NULL) {
> + assert(strstr(buffer, "processor\t: ") == buffer);
> + } else if (strstr(buffer, "hart") != NULL) {
> + assert(strstr(buffer, "hart\t\t: ") == buffer);
> + } else if (strstr(buffer, "isa") != NULL) {
> + assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") == 0);
> + } else if (strstr(buffer, "mmu") != NULL) {
> + assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
> + } else if (strstr(buffer, "uarch") != NULL) {
> + assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
> + }
> + }
> +
> + fclose(fp);
> + return 0;
> +}
> --
> 2.34.7
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
2023-03-05 14:34 [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv ~abordado
2023-03-14 0:54 ` Bin Meng
2023-03-14 4:06 ` Alistair Francis
@ 2023-03-17 7:33 ` LIU Zhiwei
2 siblings, 0 replies; 4+ messages in thread
From: LIU Zhiwei @ 2023-03-17 7:33 UTC (permalink / raw)
To: ~abordado, qemu-devel
Cc: Laurent Vivier, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza
On 2023/3/5 22:34, ~abordado wrote:
> From: Afonso Bordado <afonsobordado@gmail.com>
>
> RISC-V does not expose all extensions via hwcaps, thus some userspace
> applications may want to query these via /proc/cpuinfo.
>
> Currently when querying this file the host's file is shown instead
> which is slightly confusing. Emulate a basic /proc/cpuinfo file
> with mmu info and an ISA string.
>
> Changes from V1:
>
> - Call `g_free` on ISA string.
> - Use `riscv_cpu_cfg` API.
> - Query `cpu_env->xl` to check for RV32.
>
> Signed-off-by: Afonso Bordado <afonsobordado@gmail.com>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> ---
> linux-user/syscall.c | 34 +++++++++++++++++++++++++++++--
> tests/tcg/riscv64/Makefile.target | 1 +
> tests/tcg/riscv64/cpuinfo.c | 30 +++++++++++++++++++++++++++
> 3 files changed, 63 insertions(+), 2 deletions(-)
> create mode 100644 tests/tcg/riscv64/cpuinfo.c
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 24cea6fb6a..0388f8b0b0 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const char *fmt, int code)
> }
>
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
> - defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
> + defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
> + defined(TARGET_RISCV)
> static int is_proc(const char *filename, const char *entry)
> {
> return strcmp(filename, entry) == 0;
> @@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> }
> #endif
>
> +#if defined(TARGET_RISCV)
> +static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> +{
> + int i;
> + int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
> + RISCVCPU *cpu = env_archcpu(cpu_env);
> + const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
> + char *isa_string = riscv_isa_string(cpu);
> + const char *mmu;
> +
> + if (cfg->mmu) {
> + mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
> + } else {
> + mmu = "none";
> + }
> +
> + for (i = 0; i < num_cpus; i++) {
> + dprintf(fd, "processor\t: %d\n", i);
> + dprintf(fd, "hart\t\t: %d\n", i);
> + dprintf(fd, "isa\t\t: %s\n", isa_string);
> + dprintf(fd, "mmu\t\t: %s\n", mmu);
> + dprintf(fd, "uarch\t\t: qemu\n\n");
> + }
> +
> + g_free(isa_string);
> + return 0;
> +}
> +#endif
> +
> #if defined(TARGET_M68K)
> static int open_hardware(CPUArchState *cpu_env, int fd)
> {
> @@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd, const char *pathname, int
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
> { "/proc/net/route", open_net_route, is_proc },
> #endif
> -#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
> +#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
> { "/proc/cpuinfo", open_cpuinfo, is_proc },
> #endif
> #if defined(TARGET_M68K)
> diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
> index cc3ed65ffd..df93a2ce1f 100644
> --- a/tests/tcg/riscv64/Makefile.target
> +++ b/tests/tcg/riscv64/Makefile.target
> @@ -4,6 +4,7 @@
> VPATH += $(SRC_PATH)/tests/tcg/riscv64
> TESTS += test-div
> TESTS += noexec
> +TESTS += cpuinfo
>
> # Disable compressed instructions for test-noc
> TESTS += test-noc
> diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
> new file mode 100644
> index 0000000000..296abd0a8c
> --- /dev/null
> +++ b/tests/tcg/riscv64/cpuinfo.c
> @@ -0,0 +1,30 @@
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <assert.h>
> +
> +#define BUFFER_SIZE 1024
> +
> +int main(void)
> +{
> + char buffer[BUFFER_SIZE];
> + FILE *fp = fopen("/proc/cpuinfo", "r");
> + assert(fp != NULL);
> +
> + while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
> + if (strstr(buffer, "processor") != NULL) {
> + assert(strstr(buffer, "processor\t: ") == buffer);
> + } else if (strstr(buffer, "hart") != NULL) {
> + assert(strstr(buffer, "hart\t\t: ") == buffer);
> + } else if (strstr(buffer, "isa") != NULL) {
> + assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") == 0);
> + } else if (strstr(buffer, "mmu") != NULL) {
> + assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
> + } else if (strstr(buffer, "uarch") != NULL) {
> + assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
> + }
> + }
> +
> + fclose(fp);
> + return 0;
> +}
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-03-17 7:34 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-05 14:34 [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv ~abordado
2023-03-14 0:54 ` Bin Meng
2023-03-14 4:06 ` Alistair Francis
2023-03-17 7:33 ` LIU Zhiwei
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