[PATCH V2 0/3] Add S4 SoC clock controller driver

[PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

1. Add clock controller driver for S4 SOC.

Yu Tu (3):
  dt-bindings: clk: meson: add S4 SoC clock controller bindings
  arm64: dts: meson: add S4 Soc clock controller in DT
  clk: meson: s4: add s4 SoC clock controller driver

V1 -> V2: Change format as discussed in the email.

Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/

 .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
 MAINTAINERS                                   |    1 +
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
 drivers/clk/meson/Kconfig                     |   15 +
 drivers/clk/meson/Makefile                    |    1 +
 drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
 drivers/clk/meson/s4.h                        |  296 ++
 include/dt-bindings/clock/s4-clkc.h           |  146 +
 8 files changed, 5203 insertions(+)
 create mode 100644 drivers/clk/meson/s4.c
 create mode 100644 drivers/clk/meson/s4.h
 create mode 100644 include/dt-bindings/clock/s4-clkc.h


base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
-- 
2.33.1

[PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

1. Add clock controller driver for S4 SOC.

Yu Tu (3):
  dt-bindings: clk: meson: add S4 SoC clock controller bindings
  arm64: dts: meson: add S4 Soc clock controller in DT
  clk: meson: s4: add s4 SoC clock controller driver

V1 -> V2: Change format as discussed in the email.

Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/

 .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
 MAINTAINERS                                   |    1 +
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
 drivers/clk/meson/Kconfig                     |   15 +
 drivers/clk/meson/Makefile                    |    1 +
 drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
 drivers/clk/meson/s4.h                        |  296 ++
 include/dt-bindings/clock/s4-clkc.h           |  146 +
 8 files changed, 5203 insertions(+)
 create mode 100644 drivers/clk/meson/s4.c
 create mode 100644 drivers/clk/meson/s4.h
 create mode 100644 include/dt-bindings/clock/s4-clkc.h


base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
-- 
2.33.1


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

1. Add clock controller driver for S4 SOC.

Yu Tu (3):
  dt-bindings: clk: meson: add S4 SoC clock controller bindings
  arm64: dts: meson: add S4 Soc clock controller in DT
  clk: meson: s4: add s4 SoC clock controller driver

V1 -> V2: Change format as discussed in the email.

Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/

 .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
 MAINTAINERS                                   |    1 +
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
 drivers/clk/meson/Kconfig                     |   15 +
 drivers/clk/meson/Makefile                    |    1 +
 drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
 drivers/clk/meson/s4.h                        |  296 ++
 include/dt-bindings/clock/s4-clkc.h           |  146 +
 8 files changed, 5203 insertions(+)
 create mode 100644 drivers/clk/meson/s4.c
 create mode 100644 drivers/clk/meson/s4.h
 create mode 100644 include/dt-bindings/clock/s4-clkc.h


base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
-- 
2.33.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

Add new clock controller compatible and dt-bindings header for the
Everything-Else domain of the S4 SoC.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 .../bindings/clock/amlogic,gxbb-clkc.txt      |   1 +
 MAINTAINERS                                   |   1 +
 include/dt-bindings/clock/s4-clkc.h           | 146 ++++++++++++++++++
 3 files changed, 148 insertions(+)
 create mode 100644 include/dt-bindings/clock/s4-clkc.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 7ccecd5c02c1..301b43dea912 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -12,6 +12,7 @@ Required Properties:
 		"amlogic,g12a-clkc" for G12A SoC.
 		"amlogic,g12b-clkc" for G12B SoC.
 		"amlogic,sm1-clkc" for SM1 SoC.
+		"amlogic,s4-clkc" for S4 SoC.
 - clocks : list of clock phandle, one for each entry clock-names.
 - clock-names : should contain the following:
   * "xtal": the platform xtal
diff --git a/MAINTAINERS b/MAINTAINERS
index c1abc53f9e91..f872d0c0c253 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
 F:	drivers/clk/meson/
 F:	include/dt-bindings/clock/gxbb*
 F:	include/dt-bindings/clock/meson*
+F:	include/dt-bindings/clock/s4-clkc.h
 
 ARM/Amlogic Meson SoC Crypto Drivers
 M:	Corentin Labbe <clabbe@baylibre.com>
diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
new file mode 100644
index 000000000000..b686c8877419
--- /dev/null
+++ b/include/dt-bindings/clock/s4-clkc.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
+#define _DT_BINDINGS_CLOCK_S4_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_FIXED_PLL			1
+#define CLKID_FCLK_DIV2			3
+#define CLKID_FCLK_DIV3			5
+#define CLKID_FCLK_DIV4			7
+#define CLKID_FCLK_DIV5			9
+#define CLKID_FCLK_DIV7			11
+#define CLKID_FCLK_DIV2P5		13
+#define CLKID_GP0_PLL			15
+#define CLKID_HIFI_PLL			17
+#define CLKID_HDMI_PLL			20
+#define CLKID_MPLL_50M			22
+#define CLKID_MPLL0			25
+#define CLKID_MPLL1			27
+#define CLKID_MPLL2			29
+#define CLKID_MPLL3			31
+#define CLKID_RTC_CLK			36
+#define CLKID_SYS_CLK_B_GATE		39
+#define CLKID_SYS_CLK_A_GATE		42
+#define CLKID_SYS_CLK			43
+#define CLKID_CECA_32K_CLKOUT		48
+#define CLKID_CECB_32K_CLKOUT		53
+#define CLKID_SC_CLK_GATE		56
+#define CLKID_12_24M_CLK_SEL		59
+#define CLKID_VID_PLL			62
+#define CLKID_VCLK			69
+#define CLKID_VCLK2			70
+#define CLKID_VCLK_DIV1			71
+#define CLKID_VCLK2_DIV1		76
+#define CLKID_VCLK_DIV2			81
+#define CLKID_VCLK_DIV4			82
+#define CLKID_VCLK_DIV6			83
+#define CLKID_VCLK_DIV12		84
+#define CLKID_VCLK2_DIV2		85
+#define CLKID_VCLK2_DIV4		86
+#define CLKID_VCLK2_DIV6		87
+#define CLKID_VCLK2_DIV12		88
+#define CLKID_CTS_ENCI			93
+#define CLKID_CTS_ENCP			94
+#define CLKID_CTS_VDAC			95
+#define CLKID_HDMI			99
+#define CLKID_TS_CLK_GATE		101
+#define CLKID_MALI_0			104
+#define CLKID_MALI_1			107
+#define CLKID_MALI			108
+#define CLKID_VDEC_P0			111
+#define CLKID_VDEC_P1			114
+#define CLKID_VDEC_SEL			115
+#define CLKID_HEVCF_P0			118
+#define CLKID_HEVCF_P1			121
+#define CLKID_HEVCF_SEL			122
+#define CLKID_VPU_0			125
+#define CLKID_VPU_1			128
+#define CLKID_VPU			129
+#define CLKID_VPU_CLKB_TMP		132
+#define CLKID_VPU_CLKB			134
+#define CLKID_VPU_CLKC_P0		137
+#define CLKID_VPU_CLKC_P1		140
+#define CLKID_VPU_CLKC_SEL		141
+#define CLKID_VAPB_0			144
+#define CLKID_VAPB_1			147
+#define CLKID_VAPB			148
+#define CLKID_GE2D			149
+#define CLKID_VDIN_MEAS_GATE		152
+#define CLKID_SD_EMMC_C_CLK		155
+#define CLKID_SD_EMMC_A_CLK		158
+#define CLKID_SD_EMMC_B_CLK		161
+#define CLKID_SPICC0_GATE		164
+#define CLKID_PWM_A_GATE		167
+#define CLKID_PWM_B_GATE		170
+#define CLKID_PWM_C_GATE		173
+#define CLKID_PWM_D_GATE		176
+#define CLKID_PWM_E_GATE		179
+#define CLKID_PWM_F_GATE		182
+#define CLKID_PWM_G_GATE		185
+#define CLKID_PWM_H_GATE		188
+#define CLKID_PWM_I_GATE		191
+#define CLKID_PWM_J_GATE		194
+#define CLKID_SARADC_GATE		197
+#define CLKID_GEN_GATE			200
+#define CLKID_DDR			201
+#define CLKID_DOS			202
+#define CLKID_ETHPHY			203
+#define CLKID_MALI_GATE			204
+#define CLKID_AOCPU			205
+#define CLKID_AUCPU			206
+#define CLKID_CEC			207
+#define CLKID_SD_EMMC_A			208
+#define CLKID_SD_EMMC_B			209
+#define CLKID_NAND			210
+#define CLKID_SMARTCARD			211
+#define CLKID_ACODEC			212
+#define CLKID_SPIFC			213
+#define CLKID_MSR_CLK			214
+#define CLKID_IR_CTRL			215
+#define CLKID_AUDIO			216
+#define CLKID_ETH			217
+#define CLKID_UART_A			218
+#define CLKID_UART_B			219
+#define CLKID_UART_C			220
+#define CLKID_UART_D			221
+#define CLKID_UART_E			222
+#define CLKID_AIFIFO			223
+#define CLKID_TS_DDR			224
+#define CLKID_TS_PLL			225
+#define CLKID_G2D			226
+#define CLKID_SPICC0			227
+#define CLKID_SPICC1			228
+#define CLKID_USB			229
+#define CLKID_I2C_M_A			230
+#define CLKID_I2C_M_B			231
+#define CLKID_I2C_M_C			232
+#define CLKID_I2C_M_D			233
+#define CLKID_I2C_M_E			234
+#define CLKID_HDMITX_APB		235
+#define CLKID_I2C_S_A			236
+#define CLKID_USB1_TO_DDR		237
+#define CLKID_HDCP22			238
+#define CLKID_MMC_APB			239
+#define CLKID_RSA			240
+#define CLKID_CPU_DEBUG			241
+#define CLKID_VPU_INTR			242
+#define CLKID_DEMOD			243
+#define CLKID_SAR_ADC			244
+#define CLKID_GIC			245
+#define CLKID_PWM_AB			246
+#define CLKID_PWM_CD			247
+#define CLKID_PWM_EF			248
+#define CLKID_PWM_GH			249
+#define CLKID_PWM_IJ			250
+#define CLKID_HDCP22_ESMCLK_GATE	253
+#define CLKID_HDCP22_SKPCLK_GATE	256
+
+#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
-- 
2.33.1

[PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

Add new clock controller compatible and dt-bindings header for the
Everything-Else domain of the S4 SoC.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 .../bindings/clock/amlogic,gxbb-clkc.txt      |   1 +
 MAINTAINERS                                   |   1 +
 include/dt-bindings/clock/s4-clkc.h           | 146 ++++++++++++++++++
 3 files changed, 148 insertions(+)
 create mode 100644 include/dt-bindings/clock/s4-clkc.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 7ccecd5c02c1..301b43dea912 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -12,6 +12,7 @@ Required Properties:
 		"amlogic,g12a-clkc" for G12A SoC.
 		"amlogic,g12b-clkc" for G12B SoC.
 		"amlogic,sm1-clkc" for SM1 SoC.
+		"amlogic,s4-clkc" for S4 SoC.
 - clocks : list of clock phandle, one for each entry clock-names.
 - clock-names : should contain the following:
   * "xtal": the platform xtal
diff --git a/MAINTAINERS b/MAINTAINERS
index c1abc53f9e91..f872d0c0c253 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
 F:	drivers/clk/meson/
 F:	include/dt-bindings/clock/gxbb*
 F:	include/dt-bindings/clock/meson*
+F:	include/dt-bindings/clock/s4-clkc.h
 
 ARM/Amlogic Meson SoC Crypto Drivers
 M:	Corentin Labbe <clabbe@baylibre.com>
diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
new file mode 100644
index 000000000000..b686c8877419
--- /dev/null
+++ b/include/dt-bindings/clock/s4-clkc.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
+#define _DT_BINDINGS_CLOCK_S4_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_FIXED_PLL			1
+#define CLKID_FCLK_DIV2			3
+#define CLKID_FCLK_DIV3			5
+#define CLKID_FCLK_DIV4			7
+#define CLKID_FCLK_DIV5			9
+#define CLKID_FCLK_DIV7			11
+#define CLKID_FCLK_DIV2P5		13
+#define CLKID_GP0_PLL			15
+#define CLKID_HIFI_PLL			17
+#define CLKID_HDMI_PLL			20
+#define CLKID_MPLL_50M			22
+#define CLKID_MPLL0			25
+#define CLKID_MPLL1			27
+#define CLKID_MPLL2			29
+#define CLKID_MPLL3			31
+#define CLKID_RTC_CLK			36
+#define CLKID_SYS_CLK_B_GATE		39
+#define CLKID_SYS_CLK_A_GATE		42
+#define CLKID_SYS_CLK			43
+#define CLKID_CECA_32K_CLKOUT		48
+#define CLKID_CECB_32K_CLKOUT		53
+#define CLKID_SC_CLK_GATE		56
+#define CLKID_12_24M_CLK_SEL		59
+#define CLKID_VID_PLL			62
+#define CLKID_VCLK			69
+#define CLKID_VCLK2			70
+#define CLKID_VCLK_DIV1			71
+#define CLKID_VCLK2_DIV1		76
+#define CLKID_VCLK_DIV2			81
+#define CLKID_VCLK_DIV4			82
+#define CLKID_VCLK_DIV6			83
+#define CLKID_VCLK_DIV12		84
+#define CLKID_VCLK2_DIV2		85
+#define CLKID_VCLK2_DIV4		86
+#define CLKID_VCLK2_DIV6		87
+#define CLKID_VCLK2_DIV12		88
+#define CLKID_CTS_ENCI			93
+#define CLKID_CTS_ENCP			94
+#define CLKID_CTS_VDAC			95
+#define CLKID_HDMI			99
+#define CLKID_TS_CLK_GATE		101
+#define CLKID_MALI_0			104
+#define CLKID_MALI_1			107
+#define CLKID_MALI			108
+#define CLKID_VDEC_P0			111
+#define CLKID_VDEC_P1			114
+#define CLKID_VDEC_SEL			115
+#define CLKID_HEVCF_P0			118
+#define CLKID_HEVCF_P1			121
+#define CLKID_HEVCF_SEL			122
+#define CLKID_VPU_0			125
+#define CLKID_VPU_1			128
+#define CLKID_VPU			129
+#define CLKID_VPU_CLKB_TMP		132
+#define CLKID_VPU_CLKB			134
+#define CLKID_VPU_CLKC_P0		137
+#define CLKID_VPU_CLKC_P1		140
+#define CLKID_VPU_CLKC_SEL		141
+#define CLKID_VAPB_0			144
+#define CLKID_VAPB_1			147
+#define CLKID_VAPB			148
+#define CLKID_GE2D			149
+#define CLKID_VDIN_MEAS_GATE		152
+#define CLKID_SD_EMMC_C_CLK		155
+#define CLKID_SD_EMMC_A_CLK		158
+#define CLKID_SD_EMMC_B_CLK		161
+#define CLKID_SPICC0_GATE		164
+#define CLKID_PWM_A_GATE		167
+#define CLKID_PWM_B_GATE		170
+#define CLKID_PWM_C_GATE		173
+#define CLKID_PWM_D_GATE		176
+#define CLKID_PWM_E_GATE		179
+#define CLKID_PWM_F_GATE		182
+#define CLKID_PWM_G_GATE		185
+#define CLKID_PWM_H_GATE		188
+#define CLKID_PWM_I_GATE		191
+#define CLKID_PWM_J_GATE		194
+#define CLKID_SARADC_GATE		197
+#define CLKID_GEN_GATE			200
+#define CLKID_DDR			201
+#define CLKID_DOS			202
+#define CLKID_ETHPHY			203
+#define CLKID_MALI_GATE			204
+#define CLKID_AOCPU			205
+#define CLKID_AUCPU			206
+#define CLKID_CEC			207
+#define CLKID_SD_EMMC_A			208
+#define CLKID_SD_EMMC_B			209
+#define CLKID_NAND			210
+#define CLKID_SMARTCARD			211
+#define CLKID_ACODEC			212
+#define CLKID_SPIFC			213
+#define CLKID_MSR_CLK			214
+#define CLKID_IR_CTRL			215
+#define CLKID_AUDIO			216
+#define CLKID_ETH			217
+#define CLKID_UART_A			218
+#define CLKID_UART_B			219
+#define CLKID_UART_C			220
+#define CLKID_UART_D			221
+#define CLKID_UART_E			222
+#define CLKID_AIFIFO			223
+#define CLKID_TS_DDR			224
+#define CLKID_TS_PLL			225
+#define CLKID_G2D			226
+#define CLKID_SPICC0			227
+#define CLKID_SPICC1			228
+#define CLKID_USB			229
+#define CLKID_I2C_M_A			230
+#define CLKID_I2C_M_B			231
+#define CLKID_I2C_M_C			232
+#define CLKID_I2C_M_D			233
+#define CLKID_I2C_M_E			234
+#define CLKID_HDMITX_APB		235
+#define CLKID_I2C_S_A			236
+#define CLKID_USB1_TO_DDR		237
+#define CLKID_HDCP22			238
+#define CLKID_MMC_APB			239
+#define CLKID_RSA			240
+#define CLKID_CPU_DEBUG			241
+#define CLKID_VPU_INTR			242
+#define CLKID_DEMOD			243
+#define CLKID_SAR_ADC			244
+#define CLKID_GIC			245
+#define CLKID_PWM_AB			246
+#define CLKID_PWM_CD			247
+#define CLKID_PWM_EF			248
+#define CLKID_PWM_GH			249
+#define CLKID_PWM_IJ			250
+#define CLKID_HDCP22_ESMCLK_GATE	253
+#define CLKID_HDCP22_SKPCLK_GATE	256
+
+#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
-- 
2.33.1


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

Add new clock controller compatible and dt-bindings header for the
Everything-Else domain of the S4 SoC.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 .../bindings/clock/amlogic,gxbb-clkc.txt      |   1 +
 MAINTAINERS                                   |   1 +
 include/dt-bindings/clock/s4-clkc.h           | 146 ++++++++++++++++++
 3 files changed, 148 insertions(+)
 create mode 100644 include/dt-bindings/clock/s4-clkc.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 7ccecd5c02c1..301b43dea912 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -12,6 +12,7 @@ Required Properties:
 		"amlogic,g12a-clkc" for G12A SoC.
 		"amlogic,g12b-clkc" for G12B SoC.
 		"amlogic,sm1-clkc" for SM1 SoC.
+		"amlogic,s4-clkc" for S4 SoC.
 - clocks : list of clock phandle, one for each entry clock-names.
 - clock-names : should contain the following:
   * "xtal": the platform xtal
diff --git a/MAINTAINERS b/MAINTAINERS
index c1abc53f9e91..f872d0c0c253 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
 F:	drivers/clk/meson/
 F:	include/dt-bindings/clock/gxbb*
 F:	include/dt-bindings/clock/meson*
+F:	include/dt-bindings/clock/s4-clkc.h
 
 ARM/Amlogic Meson SoC Crypto Drivers
 M:	Corentin Labbe <clabbe@baylibre.com>
diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
new file mode 100644
index 000000000000..b686c8877419
--- /dev/null
+++ b/include/dt-bindings/clock/s4-clkc.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
+#define _DT_BINDINGS_CLOCK_S4_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_FIXED_PLL			1
+#define CLKID_FCLK_DIV2			3
+#define CLKID_FCLK_DIV3			5
+#define CLKID_FCLK_DIV4			7
+#define CLKID_FCLK_DIV5			9
+#define CLKID_FCLK_DIV7			11
+#define CLKID_FCLK_DIV2P5		13
+#define CLKID_GP0_PLL			15
+#define CLKID_HIFI_PLL			17
+#define CLKID_HDMI_PLL			20
+#define CLKID_MPLL_50M			22
+#define CLKID_MPLL0			25
+#define CLKID_MPLL1			27
+#define CLKID_MPLL2			29
+#define CLKID_MPLL3			31
+#define CLKID_RTC_CLK			36
+#define CLKID_SYS_CLK_B_GATE		39
+#define CLKID_SYS_CLK_A_GATE		42
+#define CLKID_SYS_CLK			43
+#define CLKID_CECA_32K_CLKOUT		48
+#define CLKID_CECB_32K_CLKOUT		53
+#define CLKID_SC_CLK_GATE		56
+#define CLKID_12_24M_CLK_SEL		59
+#define CLKID_VID_PLL			62
+#define CLKID_VCLK			69
+#define CLKID_VCLK2			70
+#define CLKID_VCLK_DIV1			71
+#define CLKID_VCLK2_DIV1		76
+#define CLKID_VCLK_DIV2			81
+#define CLKID_VCLK_DIV4			82
+#define CLKID_VCLK_DIV6			83
+#define CLKID_VCLK_DIV12		84
+#define CLKID_VCLK2_DIV2		85
+#define CLKID_VCLK2_DIV4		86
+#define CLKID_VCLK2_DIV6		87
+#define CLKID_VCLK2_DIV12		88
+#define CLKID_CTS_ENCI			93
+#define CLKID_CTS_ENCP			94
+#define CLKID_CTS_VDAC			95
+#define CLKID_HDMI			99
+#define CLKID_TS_CLK_GATE		101
+#define CLKID_MALI_0			104
+#define CLKID_MALI_1			107
+#define CLKID_MALI			108
+#define CLKID_VDEC_P0			111
+#define CLKID_VDEC_P1			114
+#define CLKID_VDEC_SEL			115
+#define CLKID_HEVCF_P0			118
+#define CLKID_HEVCF_P1			121
+#define CLKID_HEVCF_SEL			122
+#define CLKID_VPU_0			125
+#define CLKID_VPU_1			128
+#define CLKID_VPU			129
+#define CLKID_VPU_CLKB_TMP		132
+#define CLKID_VPU_CLKB			134
+#define CLKID_VPU_CLKC_P0		137
+#define CLKID_VPU_CLKC_P1		140
+#define CLKID_VPU_CLKC_SEL		141
+#define CLKID_VAPB_0			144
+#define CLKID_VAPB_1			147
+#define CLKID_VAPB			148
+#define CLKID_GE2D			149
+#define CLKID_VDIN_MEAS_GATE		152
+#define CLKID_SD_EMMC_C_CLK		155
+#define CLKID_SD_EMMC_A_CLK		158
+#define CLKID_SD_EMMC_B_CLK		161
+#define CLKID_SPICC0_GATE		164
+#define CLKID_PWM_A_GATE		167
+#define CLKID_PWM_B_GATE		170
+#define CLKID_PWM_C_GATE		173
+#define CLKID_PWM_D_GATE		176
+#define CLKID_PWM_E_GATE		179
+#define CLKID_PWM_F_GATE		182
+#define CLKID_PWM_G_GATE		185
+#define CLKID_PWM_H_GATE		188
+#define CLKID_PWM_I_GATE		191
+#define CLKID_PWM_J_GATE		194
+#define CLKID_SARADC_GATE		197
+#define CLKID_GEN_GATE			200
+#define CLKID_DDR			201
+#define CLKID_DOS			202
+#define CLKID_ETHPHY			203
+#define CLKID_MALI_GATE			204
+#define CLKID_AOCPU			205
+#define CLKID_AUCPU			206
+#define CLKID_CEC			207
+#define CLKID_SD_EMMC_A			208
+#define CLKID_SD_EMMC_B			209
+#define CLKID_NAND			210
+#define CLKID_SMARTCARD			211
+#define CLKID_ACODEC			212
+#define CLKID_SPIFC			213
+#define CLKID_MSR_CLK			214
+#define CLKID_IR_CTRL			215
+#define CLKID_AUDIO			216
+#define CLKID_ETH			217
+#define CLKID_UART_A			218
+#define CLKID_UART_B			219
+#define CLKID_UART_C			220
+#define CLKID_UART_D			221
+#define CLKID_UART_E			222
+#define CLKID_AIFIFO			223
+#define CLKID_TS_DDR			224
+#define CLKID_TS_PLL			225
+#define CLKID_G2D			226
+#define CLKID_SPICC0			227
+#define CLKID_SPICC1			228
+#define CLKID_USB			229
+#define CLKID_I2C_M_A			230
+#define CLKID_I2C_M_B			231
+#define CLKID_I2C_M_C			232
+#define CLKID_I2C_M_D			233
+#define CLKID_I2C_M_E			234
+#define CLKID_HDMITX_APB		235
+#define CLKID_I2C_S_A			236
+#define CLKID_USB1_TO_DDR		237
+#define CLKID_HDCP22			238
+#define CLKID_MMC_APB			239
+#define CLKID_RSA			240
+#define CLKID_CPU_DEBUG			241
+#define CLKID_VPU_INTR			242
+#define CLKID_DEMOD			243
+#define CLKID_SAR_ADC			244
+#define CLKID_GIC			245
+#define CLKID_PWM_AB			246
+#define CLKID_PWM_CD			247
+#define CLKID_PWM_EF			248
+#define CLKID_PWM_GH			249
+#define CLKID_PWM_IJ			250
+#define CLKID_HDCP22_ESMCLK_GATE	253
+#define CLKID_HDCP22_SKPCLK_GATE	256
+
+#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
-- 
2.33.1


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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 07:42, Yu Tu wrote:
> Add new clock controller compatible and dt-bindings header for the
> Everything-Else domain of the S4 SoC.
> 
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>



> diff --git a/MAINTAINERS b/MAINTAINERS
> index c1abc53f9e91..f872d0c0c253 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>  F:	drivers/clk/meson/
>  F:	include/dt-bindings/clock/gxbb*
>  F:	include/dt-bindings/clock/meson*
> +F:	include/dt-bindings/clock/s4-clkc.h
>  
>  ARM/Amlogic Meson SoC Crypto Drivers
>  M:	Corentin Labbe <clabbe@baylibre.com>
> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
> new file mode 100644
> index 000000000000..b686c8877419
> --- /dev/null
> +++ b/include/dt-bindings/clock/s4-clkc.h

Filename with vendor prefix, so:
amlogic,s4-clkc.h

> @@ -0,0 +1,146 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
> +
> +/*
> + * CLKID index values
> + */
> +
> +#define CLKID_FIXED_PLL			1
> +#define CLKID_FCLK_DIV2			3
> +#define CLKID_FCLK_DIV3			5
> +#define CLKID_FCLK_DIV4			7
> +#define CLKID_FCLK_DIV5			9
> +#define CLKID_FCLK_DIV7			11

Why these aren't continuous? IDs are expected to be incremented by 1.

> +
> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */


Best regards,
Krzysztof

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 07:42, Yu Tu wrote:
> Add new clock controller compatible and dt-bindings header for the
> Everything-Else domain of the S4 SoC.
> 
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>



> diff --git a/MAINTAINERS b/MAINTAINERS
> index c1abc53f9e91..f872d0c0c253 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>  F:	drivers/clk/meson/
>  F:	include/dt-bindings/clock/gxbb*
>  F:	include/dt-bindings/clock/meson*
> +F:	include/dt-bindings/clock/s4-clkc.h
>  
>  ARM/Amlogic Meson SoC Crypto Drivers
>  M:	Corentin Labbe <clabbe@baylibre.com>
> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
> new file mode 100644
> index 000000000000..b686c8877419
> --- /dev/null
> +++ b/include/dt-bindings/clock/s4-clkc.h

Filename with vendor prefix, so:
amlogic,s4-clkc.h

> @@ -0,0 +1,146 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
> +
> +/*
> + * CLKID index values
> + */
> +
> +#define CLKID_FIXED_PLL			1
> +#define CLKID_FCLK_DIV2			3
> +#define CLKID_FCLK_DIV3			5
> +#define CLKID_FCLK_DIV4			7
> +#define CLKID_FCLK_DIV5			9
> +#define CLKID_FCLK_DIV7			11

Why these aren't continuous? IDs are expected to be incremented by 1.

> +
> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */


Best regards,
Krzysztof

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 07:42, Yu Tu wrote:
> Add new clock controller compatible and dt-bindings header for the
> Everything-Else domain of the S4 SoC.
> 
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>



> diff --git a/MAINTAINERS b/MAINTAINERS
> index c1abc53f9e91..f872d0c0c253 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>  F:	drivers/clk/meson/
>  F:	include/dt-bindings/clock/gxbb*
>  F:	include/dt-bindings/clock/meson*
> +F:	include/dt-bindings/clock/s4-clkc.h
>  
>  ARM/Amlogic Meson SoC Crypto Drivers
>  M:	Corentin Labbe <clabbe@baylibre.com>
> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
> new file mode 100644
> index 000000000000..b686c8877419
> --- /dev/null
> +++ b/include/dt-bindings/clock/s4-clkc.h

Filename with vendor prefix, so:
amlogic,s4-clkc.h

> @@ -0,0 +1,146 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
> +
> +/*
> + * CLKID index values
> + */
> +
> +#define CLKID_FIXED_PLL			1
> +#define CLKID_FCLK_DIV2			3
> +#define CLKID_FCLK_DIV3			5
> +#define CLKID_FCLK_DIV4			7
> +#define CLKID_FCLK_DIV5			9
> +#define CLKID_FCLK_DIV7			11

Why these aren't continuous? IDs are expected to be incremented by 1.

> +
> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */


Best regards,
Krzysztof

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 07:42, Yu Tu wrote:
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>> 
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>
>
>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..f872d0c0c253 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>  F:	drivers/clk/meson/
>>  F:	include/dt-bindings/clock/gxbb*
>>  F:	include/dt-bindings/clock/meson*
>> +F:	include/dt-bindings/clock/s4-clkc.h
>>  
>>  ARM/Amlogic Meson SoC Crypto Drivers
>>  M:	Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..b686c8877419
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
>
> Filename with vendor prefix, so:
> amlogic,s4-clkc.h
>
>> @@ -0,0 +1,146 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_FIXED_PLL			1
>> +#define CLKID_FCLK_DIV2			3
>> +#define CLKID_FCLK_DIV3			5
>> +#define CLKID_FCLK_DIV4			7
>> +#define CLKID_FCLK_DIV5			9
>> +#define CLKID_FCLK_DIV7			11
>
> Why these aren't continuous? IDs are expected to be incremented by 1.
>

All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
For example, with composite 'mux / div / gate' assembly, we usually need
only the leaf.

Same has been done for the other AML controllers:
For ex:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h

>> +
>> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
>
>
> Best regards,
> Krzysztof

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 07:42, Yu Tu wrote:
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>> 
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>
>
>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..f872d0c0c253 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>  F:	drivers/clk/meson/
>>  F:	include/dt-bindings/clock/gxbb*
>>  F:	include/dt-bindings/clock/meson*
>> +F:	include/dt-bindings/clock/s4-clkc.h
>>  
>>  ARM/Amlogic Meson SoC Crypto Drivers
>>  M:	Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..b686c8877419
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
>
> Filename with vendor prefix, so:
> amlogic,s4-clkc.h
>
>> @@ -0,0 +1,146 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_FIXED_PLL			1
>> +#define CLKID_FCLK_DIV2			3
>> +#define CLKID_FCLK_DIV3			5
>> +#define CLKID_FCLK_DIV4			7
>> +#define CLKID_FCLK_DIV5			9
>> +#define CLKID_FCLK_DIV7			11
>
> Why these aren't continuous? IDs are expected to be incremented by 1.
>

All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
For example, with composite 'mux / div / gate' assembly, we usually need
only the leaf.

Same has been done for the other AML controllers:
For ex:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h

>> +
>> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
>
>
> Best regards,
> Krzysztof


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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 07:42, Yu Tu wrote:
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>> 
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>
>
>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..f872d0c0c253 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>  F:	drivers/clk/meson/
>>  F:	include/dt-bindings/clock/gxbb*
>>  F:	include/dt-bindings/clock/meson*
>> +F:	include/dt-bindings/clock/s4-clkc.h
>>  
>>  ARM/Amlogic Meson SoC Crypto Drivers
>>  M:	Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..b686c8877419
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
>
> Filename with vendor prefix, so:
> amlogic,s4-clkc.h
>
>> @@ -0,0 +1,146 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_FIXED_PLL			1
>> +#define CLKID_FCLK_DIV2			3
>> +#define CLKID_FCLK_DIV3			5
>> +#define CLKID_FCLK_DIV4			7
>> +#define CLKID_FCLK_DIV5			9
>> +#define CLKID_FCLK_DIV7			11
>
> Why these aren't continuous? IDs are expected to be incremented by 1.
>

All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
For example, with composite 'mux / div / gate' assembly, we usually need
only the leaf.

Same has been done for the other AML controllers:
For ex:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h

>> +
>> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
>
>
> Best regards,
> Krzysztof


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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 10:50, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 07:42, Yu Tu wrote:
>>> Add new clock controller compatible and dt-bindings header for the
>>> Everything-Else domain of the S4 SoC.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>
>>
>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index c1abc53f9e91..f872d0c0c253 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>  F:	drivers/clk/meson/
>>>  F:	include/dt-bindings/clock/gxbb*
>>>  F:	include/dt-bindings/clock/meson*
>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>  
>>>  ARM/Amlogic Meson SoC Crypto Drivers
>>>  M:	Corentin Labbe <clabbe@baylibre.com>
>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>> new file mode 100644
>>> index 000000000000..b686c8877419
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>
>> Filename with vendor prefix, so:
>> amlogic,s4-clkc.h
>>
>>> @@ -0,0 +1,146 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>> +/*
>>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>>> + * Author: Yu Tu <yu.tu@amlogic.com>
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>>> +
>>> +/*
>>> + * CLKID index values
>>> + */
>>> +
>>> +#define CLKID_FIXED_PLL			1
>>> +#define CLKID_FCLK_DIV2			3
>>> +#define CLKID_FCLK_DIV3			5
>>> +#define CLKID_FCLK_DIV4			7
>>> +#define CLKID_FCLK_DIV5			9
>>> +#define CLKID_FCLK_DIV7			11
>>
>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>
> 
> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
> For example, with composite 'mux / div / gate' assembly, we usually need
> only the leaf.

I understand you do not expose them all, but that is not the reason to
increment ID by 2 or 3... Otherwise these are not IDs and you are not
expected to put register offsets into the bindings (you do not bindings
in such case).


> Same has been done for the other AML controllers:
> For ex:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h

This cannot be fixed now, but it is very poor argument. Like saying "we
had a bug in other driver, so we implemented the bug here as well".

Best regards,
Krzysztof

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 10:50, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 07:42, Yu Tu wrote:
>>> Add new clock controller compatible and dt-bindings header for the
>>> Everything-Else domain of the S4 SoC.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>
>>
>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index c1abc53f9e91..f872d0c0c253 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>  F:	drivers/clk/meson/
>>>  F:	include/dt-bindings/clock/gxbb*
>>>  F:	include/dt-bindings/clock/meson*
>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>  
>>>  ARM/Amlogic Meson SoC Crypto Drivers
>>>  M:	Corentin Labbe <clabbe@baylibre.com>
>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>> new file mode 100644
>>> index 000000000000..b686c8877419
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>
>> Filename with vendor prefix, so:
>> amlogic,s4-clkc.h
>>
>>> @@ -0,0 +1,146 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>> +/*
>>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>>> + * Author: Yu Tu <yu.tu@amlogic.com>
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>>> +
>>> +/*
>>> + * CLKID index values
>>> + */
>>> +
>>> +#define CLKID_FIXED_PLL			1
>>> +#define CLKID_FCLK_DIV2			3
>>> +#define CLKID_FCLK_DIV3			5
>>> +#define CLKID_FCLK_DIV4			7
>>> +#define CLKID_FCLK_DIV5			9
>>> +#define CLKID_FCLK_DIV7			11
>>
>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>
> 
> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
> For example, with composite 'mux / div / gate' assembly, we usually need
> only the leaf.

I understand you do not expose them all, but that is not the reason to
increment ID by 2 or 3... Otherwise these are not IDs and you are not
expected to put register offsets into the bindings (you do not bindings
in such case).


> Same has been done for the other AML controllers:
> For ex:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h

This cannot be fixed now, but it is very poor argument. Like saying "we
had a bug in other driver, so we implemented the bug here as well".

Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 10:50, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 07:42, Yu Tu wrote:
>>> Add new clock controller compatible and dt-bindings header for the
>>> Everything-Else domain of the S4 SoC.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>
>>
>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index c1abc53f9e91..f872d0c0c253 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>  F:	drivers/clk/meson/
>>>  F:	include/dt-bindings/clock/gxbb*
>>>  F:	include/dt-bindings/clock/meson*
>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>  
>>>  ARM/Amlogic Meson SoC Crypto Drivers
>>>  M:	Corentin Labbe <clabbe@baylibre.com>
>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>> new file mode 100644
>>> index 000000000000..b686c8877419
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>
>> Filename with vendor prefix, so:
>> amlogic,s4-clkc.h
>>
>>> @@ -0,0 +1,146 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>> +/*
>>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>>> + * Author: Yu Tu <yu.tu@amlogic.com>
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>>> +
>>> +/*
>>> + * CLKID index values
>>> + */
>>> +
>>> +#define CLKID_FIXED_PLL			1
>>> +#define CLKID_FCLK_DIV2			3
>>> +#define CLKID_FCLK_DIV3			5
>>> +#define CLKID_FCLK_DIV4			7
>>> +#define CLKID_FCLK_DIV5			9
>>> +#define CLKID_FCLK_DIV7			11
>>
>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>
> 
> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
> For example, with composite 'mux / div / gate' assembly, we usually need
> only the leaf.

I understand you do not expose them all, but that is not the reason to
increment ID by 2 or 3... Otherwise these are not IDs and you are not
expected to put register offsets into the bindings (you do not bindings
in such case).


> Same has been done for the other AML controllers:
> For ex:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h

This cannot be fixed now, but it is very poor argument. Like saying "we
had a bug in other driver, so we implemented the bug here as well".

Best regards,
Krzysztof

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 10:50, Jerome Brunet wrote:
>> 
>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> 
>>> On 28/07/2022 07:42, Yu Tu wrote:
[...]
>>>> +/*
>>>> + * CLKID index values
>>>> + */
>>>> +
>>>> +#define CLKID_FIXED_PLL			1
>>>> +#define CLKID_FCLK_DIV2			3
>>>> +#define CLKID_FCLK_DIV3			5
>>>> +#define CLKID_FCLK_DIV4			7
>>>> +#define CLKID_FCLK_DIV5			9
>>>> +#define CLKID_FCLK_DIV7			11
>>>
>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>
>> 
>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>> For example, with composite 'mux / div / gate' assembly, we usually need
>> only the leaf.
>
> I understand you do not expose them all, but that is not the reason to
> increment ID by 2 or 3... Otherwise these are not IDs and you are not
> expected to put register offsets into the bindings (you do not bindings
> in such case).

Why is it not an IDs if it not continuous in the bindings ?

If there is technical reason, we'll probably end up exposing everything. It
would not be a dramatic change. I asked for this over v1 because we have
done that is the past and I think it makes sense.

I'm happy to be convinced to do things differently. Just looking for the
technical reason that require contiuous exposed IDs.

The other IDs exists, but we do not expose them as bindings.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125

>
>
>> Same has been done for the other AML controllers:
>> For ex:
>> 
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h
>
> This cannot be fixed now, but it is very poor argument. Like saying "we
> had a bug in other driver, so we implemented the bug here as well".

I agree, "done before" is not a good argument. I was trying to provide a
better picutre. I'm just surprised to have this new requirement that IDs
have to be incremented by 1 (in the bindings) and I'd like to understand
why what we had done could be considered a bug now.

For example the simple-reset driver compute the reset offset from the IDs:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/reset/reset-simple.c
There might be holes in the IDs if not all bits have reset maps.
I don't think that would be a bug either.

>
> Best regards,
> Krzysztof

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 10:50, Jerome Brunet wrote:
>> 
>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> 
>>> On 28/07/2022 07:42, Yu Tu wrote:
[...]
>>>> +/*
>>>> + * CLKID index values
>>>> + */
>>>> +
>>>> +#define CLKID_FIXED_PLL			1
>>>> +#define CLKID_FCLK_DIV2			3
>>>> +#define CLKID_FCLK_DIV3			5
>>>> +#define CLKID_FCLK_DIV4			7
>>>> +#define CLKID_FCLK_DIV5			9
>>>> +#define CLKID_FCLK_DIV7			11
>>>
>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>
>> 
>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>> For example, with composite 'mux / div / gate' assembly, we usually need
>> only the leaf.
>
> I understand you do not expose them all, but that is not the reason to
> increment ID by 2 or 3... Otherwise these are not IDs and you are not
> expected to put register offsets into the bindings (you do not bindings
> in such case).

Why is it not an IDs if it not continuous in the bindings ?

If there is technical reason, we'll probably end up exposing everything. It
would not be a dramatic change. I asked for this over v1 because we have
done that is the past and I think it makes sense.

I'm happy to be convinced to do things differently. Just looking for the
technical reason that require contiuous exposed IDs.

The other IDs exists, but we do not expose them as bindings.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125

>
>
>> Same has been done for the other AML controllers:
>> For ex:
>> 
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h
>
> This cannot be fixed now, but it is very poor argument. Like saying "we
> had a bug in other driver, so we implemented the bug here as well".

I agree, "done before" is not a good argument. I was trying to provide a
better picutre. I'm just surprised to have this new requirement that IDs
have to be incremented by 1 (in the bindings) and I'd like to understand
why what we had done could be considered a bug now.

For example the simple-reset driver compute the reset offset from the IDs:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/reset/reset-simple.c
There might be holes in the IDs if not all bits have reset maps.
I don't think that would be a bug either.

>
> Best regards,
> Krzysztof


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 10:50, Jerome Brunet wrote:
>> 
>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> 
>>> On 28/07/2022 07:42, Yu Tu wrote:
[...]
>>>> +/*
>>>> + * CLKID index values
>>>> + */
>>>> +
>>>> +#define CLKID_FIXED_PLL			1
>>>> +#define CLKID_FCLK_DIV2			3
>>>> +#define CLKID_FCLK_DIV3			5
>>>> +#define CLKID_FCLK_DIV4			7
>>>> +#define CLKID_FCLK_DIV5			9
>>>> +#define CLKID_FCLK_DIV7			11
>>>
>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>
>> 
>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>> For example, with composite 'mux / div / gate' assembly, we usually need
>> only the leaf.
>
> I understand you do not expose them all, but that is not the reason to
> increment ID by 2 or 3... Otherwise these are not IDs and you are not
> expected to put register offsets into the bindings (you do not bindings
> in such case).

Why is it not an IDs if it not continuous in the bindings ?

If there is technical reason, we'll probably end up exposing everything. It
would not be a dramatic change. I asked for this over v1 because we have
done that is the past and I think it makes sense.

I'm happy to be convinced to do things differently. Just looking for the
technical reason that require contiuous exposed IDs.

The other IDs exists, but we do not expose them as bindings.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125

>
>
>> Same has been done for the other AML controllers:
>> For ex:
>> 
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h
>
> This cannot be fixed now, but it is very poor argument. Like saying "we
> had a bug in other driver, so we implemented the bug here as well".

I agree, "done before" is not a good argument. I was trying to provide a
better picutre. I'm just surprised to have this new requirement that IDs
have to be incremented by 1 (in the bindings) and I'd like to understand
why what we had done could be considered a bug now.

For example the simple-reset driver compute the reset offset from the IDs:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/reset/reset-simple.c
There might be holes in the IDs if not all bits have reset maps.
I don't think that would be a bug either.

>
> Best regards,
> Krzysztof


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 11:09, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>
>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>
>>>> On 28/07/2022 07:42, Yu Tu wrote:
> [...]
>>>>> +/*
>>>>> + * CLKID index values
>>>>> + */
>>>>> +
>>>>> +#define CLKID_FIXED_PLL			1
>>>>> +#define CLKID_FCLK_DIV2			3
>>>>> +#define CLKID_FCLK_DIV3			5
>>>>> +#define CLKID_FCLK_DIV4			7
>>>>> +#define CLKID_FCLK_DIV5			9
>>>>> +#define CLKID_FCLK_DIV7			11
>>>>
>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>
>>>
>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>> only the leaf.
>>
>> I understand you do not expose them all, but that is not the reason to
>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>> expected to put register offsets into the bindings (you do not bindings
>> in such case).
> 
> Why is it not an IDs if it not continuous in the bindings ?
> 
> If there is technical reason, we'll probably end up exposing everything. It
> would not be a dramatic change. I asked for this over v1 because we have
> done that is the past and I think it makes sense.
> 
> I'm happy to be convinced to do things differently. Just looking for the
> technical reason that require contiuous exposed IDs.
> 
> The other IDs exists, but we do not expose them as bindings.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125

https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/

https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/

https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/

The IDs are abstract numbers, where the number does not matter because
it is not tied to driver implementation or device programming model. The
driver maps ID to respective clock.

Using some meaningful numbers as these IDs, means you tied bindings to
your implementation and any change in implementation requires change in
the bindings. This contradicts the idea of bindings.

> 
>>
>>
>>> Same has been done for the other AML controllers:
>>> For ex:
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h
>>
>> This cannot be fixed now, but it is very poor argument. Like saying "we
>> had a bug in other driver, so we implemented the bug here as well".
> 
> I agree, "done before" is not a good argument. I was trying to provide a
> better picutre. I'm just surprised to have this new requirement that IDs
> have to be incremented by 1 (in the bindings) and I'd like to understand
> why what we had done could be considered a bug now.

It was always, just no one ever enforced it. And almost all clock and
reset providers follow it. There are just literally few exceptions.

> For example the simple-reset driver compute the reset offset from the IDs:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/reset/reset-simple.c

This is one of the exceptions where it actually made sense, but I would
argue it still contradicts the bindings. You have now binding which is
tied to both Linux implementation and to device programming model.

However fixing it would require creating huge mapping tables for each
SoC, so obviously this exception is quite reasonable.

Clock drivers require tables and translation anyway. Almost all clock
drivers did it, so such exception is not justified.

> There might be holes in the IDs if not all bits have reset maps.
> I don't think that would be a bug either.

Bug was of course highly exaggerated example. :)

Best regards,
Krzysztof

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 11:09, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>
>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>
>>>> On 28/07/2022 07:42, Yu Tu wrote:
> [...]
>>>>> +/*
>>>>> + * CLKID index values
>>>>> + */
>>>>> +
>>>>> +#define CLKID_FIXED_PLL			1
>>>>> +#define CLKID_FCLK_DIV2			3
>>>>> +#define CLKID_FCLK_DIV3			5
>>>>> +#define CLKID_FCLK_DIV4			7
>>>>> +#define CLKID_FCLK_DIV5			9
>>>>> +#define CLKID_FCLK_DIV7			11
>>>>
>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>
>>>
>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>> only the leaf.
>>
>> I understand you do not expose them all, but that is not the reason to
>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>> expected to put register offsets into the bindings (you do not bindings
>> in such case).
> 
> Why is it not an IDs if it not continuous in the bindings ?
> 
> If there is technical reason, we'll probably end up exposing everything. It
> would not be a dramatic change. I asked for this over v1 because we have
> done that is the past and I think it makes sense.
> 
> I'm happy to be convinced to do things differently. Just looking for the
> technical reason that require contiuous exposed IDs.
> 
> The other IDs exists, but we do not expose them as bindings.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125

https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/

https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/

https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/

The IDs are abstract numbers, where the number does not matter because
it is not tied to driver implementation or device programming model. The
driver maps ID to respective clock.

Using some meaningful numbers as these IDs, means you tied bindings to
your implementation and any change in implementation requires change in
the bindings. This contradicts the idea of bindings.

> 
>>
>>
>>> Same has been done for the other AML controllers:
>>> For ex:
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h
>>
>> This cannot be fixed now, but it is very poor argument. Like saying "we
>> had a bug in other driver, so we implemented the bug here as well".
> 
> I agree, "done before" is not a good argument. I was trying to provide a
> better picutre. I'm just surprised to have this new requirement that IDs
> have to be incremented by 1 (in the bindings) and I'd like to understand
> why what we had done could be considered a bug now.

It was always, just no one ever enforced it. And almost all clock and
reset providers follow it. There are just literally few exceptions.

> For example the simple-reset driver compute the reset offset from the IDs:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/reset/reset-simple.c

This is one of the exceptions where it actually made sense, but I would
argue it still contradicts the bindings. You have now binding which is
tied to both Linux implementation and to device programming model.

However fixing it would require creating huge mapping tables for each
SoC, so obviously this exception is quite reasonable.

Clock drivers require tables and translation anyway. Almost all clock
drivers did it, so such exception is not justified.

> There might be holes in the IDs if not all bits have reset maps.
> I don't think that would be a bug either.

Bug was of course highly exaggerated example. :)

Best regards,
Krzysztof

_______________________________________________
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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 11:09, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>
>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>
>>>> On 28/07/2022 07:42, Yu Tu wrote:
> [...]
>>>>> +/*
>>>>> + * CLKID index values
>>>>> + */
>>>>> +
>>>>> +#define CLKID_FIXED_PLL			1
>>>>> +#define CLKID_FCLK_DIV2			3
>>>>> +#define CLKID_FCLK_DIV3			5
>>>>> +#define CLKID_FCLK_DIV4			7
>>>>> +#define CLKID_FCLK_DIV5			9
>>>>> +#define CLKID_FCLK_DIV7			11
>>>>
>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>
>>>
>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>> only the leaf.
>>
>> I understand you do not expose them all, but that is not the reason to
>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>> expected to put register offsets into the bindings (you do not bindings
>> in such case).
> 
> Why is it not an IDs if it not continuous in the bindings ?
> 
> If there is technical reason, we'll probably end up exposing everything. It
> would not be a dramatic change. I asked for this over v1 because we have
> done that is the past and I think it makes sense.
> 
> I'm happy to be convinced to do things differently. Just looking for the
> technical reason that require contiuous exposed IDs.
> 
> The other IDs exists, but we do not expose them as bindings.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125

https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/

https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/

https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/

The IDs are abstract numbers, where the number does not matter because
it is not tied to driver implementation or device programming model. The
driver maps ID to respective clock.

Using some meaningful numbers as these IDs, means you tied bindings to
your implementation and any change in implementation requires change in
the bindings. This contradicts the idea of bindings.

> 
>>
>>
>>> Same has been done for the other AML controllers:
>>> For ex:
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h
>>
>> This cannot be fixed now, but it is very poor argument. Like saying "we
>> had a bug in other driver, so we implemented the bug here as well".
> 
> I agree, "done before" is not a good argument. I was trying to provide a
> better picutre. I'm just surprised to have this new requirement that IDs
> have to be incremented by 1 (in the bindings) and I'd like to understand
> why what we had done could be considered a bug now.

It was always, just no one ever enforced it. And almost all clock and
reset providers follow it. There are just literally few exceptions.

> For example the simple-reset driver compute the reset offset from the IDs:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/reset/reset-simple.c

This is one of the exceptions where it actually made sense, but I would
argue it still contradicts the bindings. You have now binding which is
tied to both Linux implementation and to device programming model.

However fixing it would require creating huge mapping tables for each
SoC, so obviously this exception is quite reasonable.

Clock drivers require tables and translation anyway. Almost all clock
drivers did it, so such exception is not justified.

> There might be holes in the IDs if not all bits have reset maps.
> I don't think that would be a bug either.

Bug was of course highly exaggerated example. :)

Best regards,
Krzysztof

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 11:48, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 11:09, Jerome Brunet wrote:
>> 
>> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> 
>>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>>
>>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>> [...]
>>>>>> +/*
>>>>>> + * CLKID index values
>>>>>> + */
>>>>>> +
>>>>>> +#define CLKID_FIXED_PLL			1
>>>>>> +#define CLKID_FCLK_DIV2			3
>>>>>> +#define CLKID_FCLK_DIV3			5
>>>>>> +#define CLKID_FCLK_DIV4			7
>>>>>> +#define CLKID_FCLK_DIV5			9
>>>>>> +#define CLKID_FCLK_DIV7			11
>>>>>
>>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>>
>>>>
>>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>>> only the leaf.
>>>
>>> I understand you do not expose them all, but that is not the reason to
>>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>>> expected to put register offsets into the bindings (you do not bindings
>>> in such case).
>> 
>> Why is it not an IDs if it not continuous in the bindings ?
>> 
>> If there is technical reason, we'll probably end up exposing everything. It
>> would not be a dramatic change. I asked for this over v1 because we have
>> done that is the past and I think it makes sense.
>> 
>> I'm happy to be convinced to do things differently. Just looking for the
>> technical reason that require contiuous exposed IDs.
>> 
>> The other IDs exists, but we do not expose them as bindings.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125
>
> https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/
>
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>
> https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/
>
> The IDs are abstract numbers, where the number does not matter because
> it is not tied to driver implementation or device programming model. The
> driver maps ID to respective clock.
>
> Using some meaningful numbers as these IDs, means you tied bindings to
> your implementation and any change in implementation requires change in
> the bindings. This contradicts the idea of bindings.
>

I totally agree. Bindings ID are abstract numbers.
We do follow that. We even document it:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n118

It is just a choice to not expose some IDs.
It is not tied to the implementation at all.
I think we actually follow the rules and the idea behind it.

We can expose then all If you still think what we are doing is not appropriate.

I'd like things to be consistent though. So if the decision is to
expose everything, I'll probably end up doing the same for the old SoCs.

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 11:48, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 11:09, Jerome Brunet wrote:
>> 
>> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> 
>>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>>
>>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>> [...]
>>>>>> +/*
>>>>>> + * CLKID index values
>>>>>> + */
>>>>>> +
>>>>>> +#define CLKID_FIXED_PLL			1
>>>>>> +#define CLKID_FCLK_DIV2			3
>>>>>> +#define CLKID_FCLK_DIV3			5
>>>>>> +#define CLKID_FCLK_DIV4			7
>>>>>> +#define CLKID_FCLK_DIV5			9
>>>>>> +#define CLKID_FCLK_DIV7			11
>>>>>
>>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>>
>>>>
>>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>>> only the leaf.
>>>
>>> I understand you do not expose them all, but that is not the reason to
>>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>>> expected to put register offsets into the bindings (you do not bindings
>>> in such case).
>> 
>> Why is it not an IDs if it not continuous in the bindings ?
>> 
>> If there is technical reason, we'll probably end up exposing everything. It
>> would not be a dramatic change. I asked for this over v1 because we have
>> done that is the past and I think it makes sense.
>> 
>> I'm happy to be convinced to do things differently. Just looking for the
>> technical reason that require contiuous exposed IDs.
>> 
>> The other IDs exists, but we do not expose them as bindings.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125
>
> https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/
>
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>
> https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/
>
> The IDs are abstract numbers, where the number does not matter because
> it is not tied to driver implementation or device programming model. The
> driver maps ID to respective clock.
>
> Using some meaningful numbers as these IDs, means you tied bindings to
> your implementation and any change in implementation requires change in
> the bindings. This contradicts the idea of bindings.
>

I totally agree. Bindings ID are abstract numbers.
We do follow that. We even document it:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n118

It is just a choice to not expose some IDs.
It is not tied to the implementation at all.
I think we actually follow the rules and the idea behind it.

We can expose then all If you still think what we are doing is not appropriate.

I'd like things to be consistent though. So if the decision is to
expose everything, I'll probably end up doing the same for the old SoCs.

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 11:48, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:

> On 28/07/2022 11:09, Jerome Brunet wrote:
>> 
>> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> 
>>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>>
>>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>> [...]
>>>>>> +/*
>>>>>> + * CLKID index values
>>>>>> + */
>>>>>> +
>>>>>> +#define CLKID_FIXED_PLL			1
>>>>>> +#define CLKID_FCLK_DIV2			3
>>>>>> +#define CLKID_FCLK_DIV3			5
>>>>>> +#define CLKID_FCLK_DIV4			7
>>>>>> +#define CLKID_FCLK_DIV5			9
>>>>>> +#define CLKID_FCLK_DIV7			11
>>>>>
>>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>>
>>>>
>>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>>> only the leaf.
>>>
>>> I understand you do not expose them all, but that is not the reason to
>>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>>> expected to put register offsets into the bindings (you do not bindings
>>> in such case).
>> 
>> Why is it not an IDs if it not continuous in the bindings ?
>> 
>> If there is technical reason, we'll probably end up exposing everything. It
>> would not be a dramatic change. I asked for this over v1 because we have
>> done that is the past and I think it makes sense.
>> 
>> I'm happy to be convinced to do things differently. Just looking for the
>> technical reason that require contiuous exposed IDs.
>> 
>> The other IDs exists, but we do not expose them as bindings.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125
>
> https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/
>
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>
> https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/
>
> The IDs are abstract numbers, where the number does not matter because
> it is not tied to driver implementation or device programming model. The
> driver maps ID to respective clock.
>
> Using some meaningful numbers as these IDs, means you tied bindings to
> your implementation and any change in implementation requires change in
> the bindings. This contradicts the idea of bindings.
>

I totally agree. Bindings ID are abstract numbers.
We do follow that. We even document it:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n118

It is just a choice to not expose some IDs.
It is not tied to the implementation at all.
I think we actually follow the rules and the idea behind it.

We can expose then all If you still think what we are doing is not appropriate.

I'd like things to be consistent though. So if the decision is to
expose everything, I'll probably end up doing the same for the old SoCs.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 11:54, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 11:48, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 11:09, Jerome Brunet wrote:
>>>
>>> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>
>>>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>>>
>>>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>>
>>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>> [...]
>>>>>>> +/*
>>>>>>> + * CLKID index values
>>>>>>> + */
>>>>>>> +
>>>>>>> +#define CLKID_FIXED_PLL			1
>>>>>>> +#define CLKID_FCLK_DIV2			3
>>>>>>> +#define CLKID_FCLK_DIV3			5
>>>>>>> +#define CLKID_FCLK_DIV4			7
>>>>>>> +#define CLKID_FCLK_DIV5			9
>>>>>>> +#define CLKID_FCLK_DIV7			11
>>>>>>
>>>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>>>
>>>>>
>>>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>>>> only the leaf.
>>>>
>>>> I understand you do not expose them all, but that is not the reason to
>>>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>>>> expected to put register offsets into the bindings (you do not bindings
>>>> in such case).
>>>
>>> Why is it not an IDs if it not continuous in the bindings ?
>>>
>>> If there is technical reason, we'll probably end up exposing everything. It
>>> would not be a dramatic change. I asked for this over v1 because we have
>>> done that is the past and I think it makes sense.
>>>
>>> I'm happy to be convinced to do things differently. Just looking for the
>>> technical reason that require contiuous exposed IDs.
>>>
>>> The other IDs exists, but we do not expose them as bindings.
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125
>>
>> https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/
>>
>> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>>
>> https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/
>>
>> The IDs are abstract numbers, where the number does not matter because
>> it is not tied to driver implementation or device programming model. The
>> driver maps ID to respective clock.
>>
>> Using some meaningful numbers as these IDs, means you tied bindings to
>> your implementation and any change in implementation requires change in
>> the bindings. This contradicts the idea of bindings.
>>
> 
> I totally agree. Bindings ID are abstract numbers.
> We do follow that. We even document it:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n118
> 
> It is just a choice to not expose some IDs.
> It is not tied to the implementation at all.
> I think we actually follow the rules and the idea behind it.
> 
> We can expose then all If you still think what we are doing is not appropriate.

No, no need. You are right and I took your not-by-one-increment-ID by
other approaches I saw.

The IDs do not have to be incremental, they should not be tied to
programming model.

You have it done and documented, so thanks for explanation:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 11:54, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 11:48, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 11:09, Jerome Brunet wrote:
>>>
>>> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>
>>>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>>>
>>>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>>
>>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>> [...]
>>>>>>> +/*
>>>>>>> + * CLKID index values
>>>>>>> + */
>>>>>>> +
>>>>>>> +#define CLKID_FIXED_PLL			1
>>>>>>> +#define CLKID_FCLK_DIV2			3
>>>>>>> +#define CLKID_FCLK_DIV3			5
>>>>>>> +#define CLKID_FCLK_DIV4			7
>>>>>>> +#define CLKID_FCLK_DIV5			9
>>>>>>> +#define CLKID_FCLK_DIV7			11
>>>>>>
>>>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>>>
>>>>>
>>>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>>>> only the leaf.
>>>>
>>>> I understand you do not expose them all, but that is not the reason to
>>>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>>>> expected to put register offsets into the bindings (you do not bindings
>>>> in such case).
>>>
>>> Why is it not an IDs if it not continuous in the bindings ?
>>>
>>> If there is technical reason, we'll probably end up exposing everything. It
>>> would not be a dramatic change. I asked for this over v1 because we have
>>> done that is the past and I think it makes sense.
>>>
>>> I'm happy to be convinced to do things differently. Just looking for the
>>> technical reason that require contiuous exposed IDs.
>>>
>>> The other IDs exists, but we do not expose them as bindings.
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125
>>
>> https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/
>>
>> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>>
>> https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/
>>
>> The IDs are abstract numbers, where the number does not matter because
>> it is not tied to driver implementation or device programming model. The
>> driver maps ID to respective clock.
>>
>> Using some meaningful numbers as these IDs, means you tied bindings to
>> your implementation and any change in implementation requires change in
>> the bindings. This contradicts the idea of bindings.
>>
> 
> I totally agree. Bindings ID are abstract numbers.
> We do follow that. We even document it:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n118
> 
> It is just a choice to not expose some IDs.
> It is not tied to the implementation at all.
> I think we actually follow the rules and the idea behind it.
> 
> We can expose then all If you still think what we are doing is not appropriate.

No, no need. You are right and I took your not-by-one-increment-ID by
other approaches I saw.

The IDs do not have to be incremental, they should not be tied to
programming model.

You have it done and documented, so thanks for explanation:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 11:54, Jerome Brunet wrote:
> 
> On Thu 28 Jul 2022 at 11:48, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> 
>> On 28/07/2022 11:09, Jerome Brunet wrote:
>>>
>>> On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>
>>>> On 28/07/2022 10:50, Jerome Brunet wrote:
>>>>>
>>>>> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>>
>>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>> [...]
>>>>>>> +/*
>>>>>>> + * CLKID index values
>>>>>>> + */
>>>>>>> +
>>>>>>> +#define CLKID_FIXED_PLL			1
>>>>>>> +#define CLKID_FCLK_DIV2			3
>>>>>>> +#define CLKID_FCLK_DIV3			5
>>>>>>> +#define CLKID_FCLK_DIV4			7
>>>>>>> +#define CLKID_FCLK_DIV5			9
>>>>>>> +#define CLKID_FCLK_DIV7			11
>>>>>>
>>>>>> Why these aren't continuous? IDs are expected to be incremented by 1.
>>>>>>
>>>>>
>>>>> All clocks have IDs, it is one big table in the driver, but we are not exposing them all.
>>>>> For example, with composite 'mux / div / gate' assembly, we usually need
>>>>> only the leaf.
>>>>
>>>> I understand you do not expose them all, but that is not the reason to
>>>> increment ID by 2 or 3... Otherwise these are not IDs and you are not
>>>> expected to put register offsets into the bindings (you do not bindings
>>>> in such case).
>>>
>>> Why is it not an IDs if it not continuous in the bindings ?
>>>
>>> If there is technical reason, we'll probably end up exposing everything. It
>>> would not be a dramatic change. I asked for this over v1 because we have
>>> done that is the past and I think it makes sense.
>>>
>>> I'm happy to be convinced to do things differently. Just looking for the
>>> technical reason that require contiuous exposed IDs.
>>>
>>> The other IDs exists, but we do not expose them as bindings.
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125
>>
>> https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/
>>
>> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>>
>> https://lore.kernel.org/linux-devicetree/b60f5fd2-dc48-9375-da1c-ffcfe8292683@linaro.org/
>>
>> The IDs are abstract numbers, where the number does not matter because
>> it is not tied to driver implementation or device programming model. The
>> driver maps ID to respective clock.
>>
>> Using some meaningful numbers as these IDs, means you tied bindings to
>> your implementation and any change in implementation requires change in
>> the bindings. This contradicts the idea of bindings.
>>
> 
> I totally agree. Bindings ID are abstract numbers.
> We do follow that. We even document it:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n118
> 
> It is just a choice to not expose some IDs.
> It is not tied to the implementation at all.
> I think we actually follow the rules and the idea behind it.
> 
> We can expose then all If you still think what we are doing is not appropriate.

No, no need. You are right and I took your not-by-one-increment-ID by
other approaches I saw.

The IDs do not have to be incremental, they should not be tied to
programming model.

You have it done and documented, so thanks for explanation:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

Hi Krzysztof,
	Thanks for your reply.

On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 28/07/2022 07:42, Yu Tu wrote:
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> 
> 
> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..f872d0c0c253 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>   F:	drivers/clk/meson/
>>   F:	include/dt-bindings/clock/gxbb*
>>   F:	include/dt-bindings/clock/meson*
>> +F:	include/dt-bindings/clock/s4-clkc.h
>>   
>>   ARM/Amlogic Meson SoC Crypto Drivers
>>   M:	Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..b686c8877419
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
> 
> Filename with vendor prefix, so:
> amlogic,s4-clkc.h
It's fine with me. It's mainly Jerome's opinion.

> 
>> @@ -0,0 +1,146 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_FIXED_PLL			1
>> +#define CLKID_FCLK_DIV2			3
>> +#define CLKID_FCLK_DIV3			5
>> +#define CLKID_FCLK_DIV4			7
>> +#define CLKID_FCLK_DIV5			9
>> +#define CLKID_FCLK_DIV7			11
> 
> Why these aren't continuous? IDs are expected to be incremented by 1.
> 
>> +
>> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
> 
> 
> Best regards,
> Krzysztof
> 
> .

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

Hi Krzysztof,
	Thanks for your reply.

On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 28/07/2022 07:42, Yu Tu wrote:
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> 
> 
> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..f872d0c0c253 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>   F:	drivers/clk/meson/
>>   F:	include/dt-bindings/clock/gxbb*
>>   F:	include/dt-bindings/clock/meson*
>> +F:	include/dt-bindings/clock/s4-clkc.h
>>   
>>   ARM/Amlogic Meson SoC Crypto Drivers
>>   M:	Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..b686c8877419
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
> 
> Filename with vendor prefix, so:
> amlogic,s4-clkc.h
It's fine with me. It's mainly Jerome's opinion.

> 
>> @@ -0,0 +1,146 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_FIXED_PLL			1
>> +#define CLKID_FCLK_DIV2			3
>> +#define CLKID_FCLK_DIV3			5
>> +#define CLKID_FCLK_DIV4			7
>> +#define CLKID_FCLK_DIV5			9
>> +#define CLKID_FCLK_DIV7			11
> 
> Why these aren't continuous? IDs are expected to be incremented by 1.
> 
>> +
>> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
> 
> 
> Best regards,
> Krzysztof
> 
> .

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

Hi Krzysztof,
	Thanks for your reply.

On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 28/07/2022 07:42, Yu Tu wrote:
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> 
> 
> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..f872d0c0c253 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>   F:	drivers/clk/meson/
>>   F:	include/dt-bindings/clock/gxbb*
>>   F:	include/dt-bindings/clock/meson*
>> +F:	include/dt-bindings/clock/s4-clkc.h
>>   
>>   ARM/Amlogic Meson SoC Crypto Drivers
>>   M:	Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..b686c8877419
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
> 
> Filename with vendor prefix, so:
> amlogic,s4-clkc.h
It's fine with me. It's mainly Jerome's opinion.

> 
>> @@ -0,0 +1,146 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_FIXED_PLL			1
>> +#define CLKID_FCLK_DIV2			3
>> +#define CLKID_FCLK_DIV3			5
>> +#define CLKID_FCLK_DIV4			7
>> +#define CLKID_FCLK_DIV5			9
>> +#define CLKID_FCLK_DIV7			11
> 
> Why these aren't continuous? IDs are expected to be incremented by 1.
> 
>> +
>> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
> 
> 
> Best regards,
> Krzysztof
> 
> .

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 12:05, Yu Tu wrote:
> Hi Krzysztof,
> 	Thanks for your reply.
> 
> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 28/07/2022 07:42, Yu Tu wrote:
>>> Add new clock controller compatible and dt-bindings header for the
>>> Everything-Else domain of the S4 SoC.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>
>>
>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index c1abc53f9e91..f872d0c0c253 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>   F:	drivers/clk/meson/
>>>   F:	include/dt-bindings/clock/gxbb*
>>>   F:	include/dt-bindings/clock/meson*
>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>   
>>>   ARM/Amlogic Meson SoC Crypto Drivers
>>>   M:	Corentin Labbe <clabbe@baylibre.com>
>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>> new file mode 100644
>>> index 000000000000..b686c8877419
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>
>> Filename with vendor prefix, so:
>> amlogic,s4-clkc.h
> It's fine with me. It's mainly Jerome's opinion.

To clarify: I understand such naming might bring inconsistency, but we
want to bring some order in the bindings directories. They keep growing
and at some point the model names might start conflicting.


Best regards,
Krzysztof

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 12:05, Yu Tu wrote:
> Hi Krzysztof,
> 	Thanks for your reply.
> 
> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 28/07/2022 07:42, Yu Tu wrote:
>>> Add new clock controller compatible and dt-bindings header for the
>>> Everything-Else domain of the S4 SoC.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>
>>
>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index c1abc53f9e91..f872d0c0c253 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>   F:	drivers/clk/meson/
>>>   F:	include/dt-bindings/clock/gxbb*
>>>   F:	include/dt-bindings/clock/meson*
>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>   
>>>   ARM/Amlogic Meson SoC Crypto Drivers
>>>   M:	Corentin Labbe <clabbe@baylibre.com>
>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>> new file mode 100644
>>> index 000000000000..b686c8877419
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>
>> Filename with vendor prefix, so:
>> amlogic,s4-clkc.h
> It's fine with me. It's mainly Jerome's opinion.

To clarify: I understand such naming might bring inconsistency, but we
want to bring some order in the bindings directories. They keep growing
and at some point the model names might start conflicting.


Best regards,
Krzysztof

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Krzysztof Kozlowski]

On 28/07/2022 12:05, Yu Tu wrote:
> Hi Krzysztof,
> 	Thanks for your reply.
> 
> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 28/07/2022 07:42, Yu Tu wrote:
>>> Add new clock controller compatible and dt-bindings header for the
>>> Everything-Else domain of the S4 SoC.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>
>>
>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index c1abc53f9e91..f872d0c0c253 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>   F:	drivers/clk/meson/
>>>   F:	include/dt-bindings/clock/gxbb*
>>>   F:	include/dt-bindings/clock/meson*
>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>   
>>>   ARM/Amlogic Meson SoC Crypto Drivers
>>>   M:	Corentin Labbe <clabbe@baylibre.com>
>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>> new file mode 100644
>>> index 000000000000..b686c8877419
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>
>> Filename with vendor prefix, so:
>> amlogic,s4-clkc.h
> It's fine with me. It's mainly Jerome's opinion.

To clarify: I understand such naming might bring inconsistency, but we
want to bring some order in the bindings directories. They keep growing
and at some point the model names might start conflicting.


Best regards,
Krzysztof

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 28/07/2022 12:05, Yu Tu wrote:
>> Hi Krzysztof,
>> 	Thanks for your reply.
>>
>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>> Add new clock controller compatible and dt-bindings header for the
>>>> Everything-Else domain of the S4 SoC.
>>>>
>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>
>>>
>>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>    F:	drivers/clk/meson/
>>>>    F:	include/dt-bindings/clock/gxbb*
>>>>    F:	include/dt-bindings/clock/meson*
>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>    
>>>>    ARM/Amlogic Meson SoC Crypto Drivers
>>>>    M:	Corentin Labbe <clabbe@baylibre.com>
>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>> new file mode 100644
>>>> index 000000000000..b686c8877419
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>
>>> Filename with vendor prefix, so:
>>> amlogic,s4-clkc.h
>> It's fine with me. It's mainly Jerome's opinion.
> 
> To clarify: I understand such naming might bring inconsistency, but we
> want to bring some order in the bindings directories. They keep growing
> and at some point the model names might start conflicting.
If Jerome agrees, I will change it according to your opinion and make 
another edition.

> 
> 
> Best regards,
> Krzysztof
> 
> .

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 28/07/2022 12:05, Yu Tu wrote:
>> Hi Krzysztof,
>> 	Thanks for your reply.
>>
>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>> Add new clock controller compatible and dt-bindings header for the
>>>> Everything-Else domain of the S4 SoC.
>>>>
>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>
>>>
>>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>    F:	drivers/clk/meson/
>>>>    F:	include/dt-bindings/clock/gxbb*
>>>>    F:	include/dt-bindings/clock/meson*
>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>    
>>>>    ARM/Amlogic Meson SoC Crypto Drivers
>>>>    M:	Corentin Labbe <clabbe@baylibre.com>
>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>> new file mode 100644
>>>> index 000000000000..b686c8877419
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>
>>> Filename with vendor prefix, so:
>>> amlogic,s4-clkc.h
>> It's fine with me. It's mainly Jerome's opinion.
> 
> To clarify: I understand such naming might bring inconsistency, but we
> want to bring some order in the bindings directories. They keep growing
> and at some point the model names might start conflicting.
If Jerome agrees, I will change it according to your opinion and make 
another edition.

> 
> 
> Best regards,
> Krzysztof
> 
> .

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 28/07/2022 12:05, Yu Tu wrote:
>> Hi Krzysztof,
>> 	Thanks for your reply.
>>
>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>> Add new clock controller compatible and dt-bindings header for the
>>>> Everything-Else domain of the S4 SoC.
>>>>
>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>
>>>
>>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>    F:	drivers/clk/meson/
>>>>    F:	include/dt-bindings/clock/gxbb*
>>>>    F:	include/dt-bindings/clock/meson*
>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>    
>>>>    ARM/Amlogic Meson SoC Crypto Drivers
>>>>    M:	Corentin Labbe <clabbe@baylibre.com>
>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>> new file mode 100644
>>>> index 000000000000..b686c8877419
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>
>>> Filename with vendor prefix, so:
>>> amlogic,s4-clkc.h
>> It's fine with me. It's mainly Jerome's opinion.
> 
> To clarify: I understand such naming might bring inconsistency, but we
> want to bring some order in the bindings directories. They keep growing
> and at some point the model names might start conflicting.
If Jerome agrees, I will change it according to your opinion and make 
another edition.

> 
> 
> Best regards,
> Krzysztof
> 
> .

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 18:19, Yu Tu <yu.tu@amlogic.com> wrote:

> On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>> On 28/07/2022 12:05, Yu Tu wrote:
>>> Hi Krzysztof,
>>> 	Thanks for your reply.
>>>
>>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>>> Add new clock controller compatible and dt-bindings header for the
>>>>> Everything-Else domain of the S4 SoC.
>>>>>
>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>>
>>>>
>>>>
>>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>>> --- a/MAINTAINERS
>>>>> +++ b/MAINTAINERS
>>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>>    F:	drivers/clk/meson/
>>>>>    F:	include/dt-bindings/clock/gxbb*
>>>>>    F:	include/dt-bindings/clock/meson*
>>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>>       ARM/Amlogic Meson SoC Crypto Drivers
>>>>>    M:	Corentin Labbe <clabbe@baylibre.com>
>>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>>> new file mode 100644
>>>>> index 000000000000..b686c8877419
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>>
>>>> Filename with vendor prefix, so:
>>>> amlogic,s4-clkc.h
>>> It's fine with me. It's mainly Jerome's opinion.
>> To clarify: I understand such naming might bring inconsistency, but we
>> want to bring some order in the bindings directories. They keep growing
>> and at some point the model names might start conflicting.
> If Jerome agrees, I will change it according to your opinion and make
> another edition.

I'm aligned with Krzysztof on this. Please add the vendor prefix.

It was mistake to omit the vendor prefix. Unfortunately, I don't think
we can fix the old bindings now.

>
>> 
>> Best regards,
>> Krzysztof
>> .

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 18:19, Yu Tu <yu.tu@amlogic.com> wrote:

> On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>> On 28/07/2022 12:05, Yu Tu wrote:
>>> Hi Krzysztof,
>>> 	Thanks for your reply.
>>>
>>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>>> Add new clock controller compatible and dt-bindings header for the
>>>>> Everything-Else domain of the S4 SoC.
>>>>>
>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>>
>>>>
>>>>
>>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>>> --- a/MAINTAINERS
>>>>> +++ b/MAINTAINERS
>>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>>    F:	drivers/clk/meson/
>>>>>    F:	include/dt-bindings/clock/gxbb*
>>>>>    F:	include/dt-bindings/clock/meson*
>>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>>       ARM/Amlogic Meson SoC Crypto Drivers
>>>>>    M:	Corentin Labbe <clabbe@baylibre.com>
>>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>>> new file mode 100644
>>>>> index 000000000000..b686c8877419
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>>
>>>> Filename with vendor prefix, so:
>>>> amlogic,s4-clkc.h
>>> It's fine with me. It's mainly Jerome's opinion.
>> To clarify: I understand such naming might bring inconsistency, but we
>> want to bring some order in the bindings directories. They keep growing
>> and at some point the model names might start conflicting.
> If Jerome agrees, I will change it according to your opinion and make
> another edition.

I'm aligned with Krzysztof on this. Please add the vendor prefix.

It was mistake to omit the vendor prefix. Unfortunately, I don't think
we can fix the old bindings now.

>
>> 
>> Best regards,
>> Krzysztof
>> .


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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Jerome Brunet]

On Thu 28 Jul 2022 at 18:19, Yu Tu <yu.tu@amlogic.com> wrote:

> On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>> On 28/07/2022 12:05, Yu Tu wrote:
>>> Hi Krzysztof,
>>> 	Thanks for your reply.
>>>
>>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>>> Add new clock controller compatible and dt-bindings header for the
>>>>> Everything-Else domain of the S4 SoC.
>>>>>
>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>>
>>>>
>>>>
>>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>>> --- a/MAINTAINERS
>>>>> +++ b/MAINTAINERS
>>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>>    F:	drivers/clk/meson/
>>>>>    F:	include/dt-bindings/clock/gxbb*
>>>>>    F:	include/dt-bindings/clock/meson*
>>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>>       ARM/Amlogic Meson SoC Crypto Drivers
>>>>>    M:	Corentin Labbe <clabbe@baylibre.com>
>>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>>> new file mode 100644
>>>>> index 000000000000..b686c8877419
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>>
>>>> Filename with vendor prefix, so:
>>>> amlogic,s4-clkc.h
>>> It's fine with me. It's mainly Jerome's opinion.
>> To clarify: I understand such naming might bring inconsistency, but we
>> want to bring some order in the bindings directories. They keep growing
>> and at some point the model names might start conflicting.
> If Jerome agrees, I will change it according to your opinion and make
> another edition.

I'm aligned with Krzysztof on this. Please add the vendor prefix.

It was mistake to omit the vendor prefix. Unfortunately, I don't think
we can fix the old bindings now.

>
>> 
>> Best regards,
>> Krzysztof
>> .


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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

On 2022/7/28 19:48, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 18:19, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>> On 28/07/2022 12:05, Yu Tu wrote:
>>>> Hi Krzysztof,
>>>> 	Thanks for your reply.
>>>>
>>>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>>>> Add new clock controller compatible and dt-bindings header for the
>>>>>> Everything-Else domain of the S4 SoC.
>>>>>>
>>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>>>
>>>>>
>>>>>
>>>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>>>> --- a/MAINTAINERS
>>>>>> +++ b/MAINTAINERS
>>>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>>>     F:	drivers/clk/meson/
>>>>>>     F:	include/dt-bindings/clock/gxbb*
>>>>>>     F:	include/dt-bindings/clock/meson*
>>>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>>>        ARM/Amlogic Meson SoC Crypto Drivers
>>>>>>     M:	Corentin Labbe <clabbe@baylibre.com>
>>>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>>>> new file mode 100644
>>>>>> index 000000000000..b686c8877419
>>>>>> --- /dev/null
>>>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>>>
>>>>> Filename with vendor prefix, so:
>>>>> amlogic,s4-clkc.h
>>>> It's fine with me. It's mainly Jerome's opinion.
>>> To clarify: I understand such naming might bring inconsistency, but we
>>> want to bring some order in the bindings directories. They keep growing
>>> and at some point the model names might start conflicting.
>> If Jerome agrees, I will change it according to your opinion and make
>> another edition.
> 
> I'm aligned with Krzysztof on this. Please add the vendor prefix.
I will add it in next version.

> 
> It was mistake to omit the vendor prefix. Unfortunately, I don't think
> we can fix the old bindings now.
> 
>>
>>>
>>> Best regards,
>>> Krzysztof
>>> .
> 
> .

Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

On 2022/7/28 19:48, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 18:19, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>> On 28/07/2022 12:05, Yu Tu wrote:
>>>> Hi Krzysztof,
>>>> 	Thanks for your reply.
>>>>
>>>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>>>> Add new clock controller compatible and dt-bindings header for the
>>>>>> Everything-Else domain of the S4 SoC.
>>>>>>
>>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>>>
>>>>>
>>>>>
>>>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>>>> --- a/MAINTAINERS
>>>>>> +++ b/MAINTAINERS
>>>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>>>     F:	drivers/clk/meson/
>>>>>>     F:	include/dt-bindings/clock/gxbb*
>>>>>>     F:	include/dt-bindings/clock/meson*
>>>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>>>        ARM/Amlogic Meson SoC Crypto Drivers
>>>>>>     M:	Corentin Labbe <clabbe@baylibre.com>
>>>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>>>> new file mode 100644
>>>>>> index 000000000000..b686c8877419
>>>>>> --- /dev/null
>>>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>>>
>>>>> Filename with vendor prefix, so:
>>>>> amlogic,s4-clkc.h
>>>> It's fine with me. It's mainly Jerome's opinion.
>>> To clarify: I understand such naming might bring inconsistency, but we
>>> want to bring some order in the bindings directories. They keep growing
>>> and at some point the model names might start conflicting.
>> If Jerome agrees, I will change it according to your opinion and make
>> another edition.
> 
> I'm aligned with Krzysztof on this. Please add the vendor prefix.
I will add it in next version.

> 
> It was mistake to omit the vendor prefix. Unfortunately, I don't think
> we can fix the old bindings now.
> 
>>
>>>
>>> Best regards,
>>> Krzysztof
>>> .
> 
> .

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Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings

[Yu Tu]

On 2022/7/28 19:48, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 18:19, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> On 2022/7/28 18:09, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>> On 28/07/2022 12:05, Yu Tu wrote:
>>>> Hi Krzysztof,
>>>> 	Thanks for your reply.
>>>>
>>>> On 2022/7/28 16:41, Krzysztof Kozlowski wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On 28/07/2022 07:42, Yu Tu wrote:
>>>>>> Add new clock controller compatible and dt-bindings header for the
>>>>>> Everything-Else domain of the S4 SoC.
>>>>>>
>>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>>>
>>>>>
>>>>>
>>>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>>>> index c1abc53f9e91..f872d0c0c253 100644
>>>>>> --- a/MAINTAINERS
>>>>>> +++ b/MAINTAINERS
>>>>>> @@ -1775,6 +1775,7 @@ F:	Documentation/devicetree/bindings/clock/amlogic*
>>>>>>     F:	drivers/clk/meson/
>>>>>>     F:	include/dt-bindings/clock/gxbb*
>>>>>>     F:	include/dt-bindings/clock/meson*
>>>>>> +F:	include/dt-bindings/clock/s4-clkc.h
>>>>>>        ARM/Amlogic Meson SoC Crypto Drivers
>>>>>>     M:	Corentin Labbe <clabbe@baylibre.com>
>>>>>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>>>>>> new file mode 100644
>>>>>> index 000000000000..b686c8877419
>>>>>> --- /dev/null
>>>>>> +++ b/include/dt-bindings/clock/s4-clkc.h
>>>>>
>>>>> Filename with vendor prefix, so:
>>>>> amlogic,s4-clkc.h
>>>> It's fine with me. It's mainly Jerome's opinion.
>>> To clarify: I understand such naming might bring inconsistency, but we
>>> want to bring some order in the bindings directories. They keep growing
>>> and at some point the model names might start conflicting.
>> If Jerome agrees, I will change it according to your opinion and make
>> another edition.
> 
> I'm aligned with Krzysztof on this. Please add the vendor prefix.
I will add it in next version.

> 
> It was mistake to omit the vendor prefix. Unfortunately, I don't think
> we can fix the old bindings now.
> 
>>
>>>
>>> Best regards,
>>> Krzysztof
>>> .
> 
> .

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[PATCH V2 2/3] arm64: dts: meson: add S4 Soc clock controller in DT

[Yu Tu]

Added information about the S4 SOC Clock controller in DT.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ff213618a598..3add7fcaffa9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/s4-clkc.h>
 
 / {
 	cpus {
@@ -118,6 +119,16 @@ gpio_intc: interrupt-controller@4080 {
 					<10 11 12 13 14 15 16 17 18 19 20 21>;
 			};
 
+			clkc: clock-controller {
+				compatible = "amlogic,s4-clkc";
+				reg = <0x0 0x0 0x0 0x49c>,
+				      <0x0 0x8000 0x0 0x348>;
+				reg-names = "basic", "pll";
+				#clock-cells = <1>;
+				clocks = <&xtal>;
+				clock-names = "xtal";
+			};
+
 			uart_B: serial@7a000 {
 				compatible = "amlogic,meson-s4-uart",
 					     "amlogic,meson-ao-uart";
-- 
2.33.1

[PATCH V2 2/3] arm64: dts: meson: add S4 Soc clock controller in DT

[Yu Tu]

Added information about the S4 SOC Clock controller in DT.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ff213618a598..3add7fcaffa9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/s4-clkc.h>
 
 / {
 	cpus {
@@ -118,6 +119,16 @@ gpio_intc: interrupt-controller@4080 {
 					<10 11 12 13 14 15 16 17 18 19 20 21>;
 			};
 
+			clkc: clock-controller {
+				compatible = "amlogic,s4-clkc";
+				reg = <0x0 0x0 0x0 0x49c>,
+				      <0x0 0x8000 0x0 0x348>;
+				reg-names = "basic", "pll";
+				#clock-cells = <1>;
+				clocks = <&xtal>;
+				clock-names = "xtal";
+			};
+
 			uart_B: serial@7a000 {
 				compatible = "amlogic,meson-s4-uart",
 					     "amlogic,meson-ao-uart";
-- 
2.33.1


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[PATCH V2 2/3] arm64: dts: meson: add S4 Soc clock controller in DT

[Yu Tu]

Added information about the S4 SOC Clock controller in DT.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ff213618a598..3add7fcaffa9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/s4-clkc.h>
 
 / {
 	cpus {
@@ -118,6 +119,16 @@ gpio_intc: interrupt-controller@4080 {
 					<10 11 12 13 14 15 16 17 18 19 20 21>;
 			};
 
+			clkc: clock-controller {
+				compatible = "amlogic,s4-clkc";
+				reg = <0x0 0x0 0x0 0x49c>,
+				      <0x0 0x8000 0x0 0x348>;
+				reg-names = "basic", "pll";
+				#clock-cells = <1>;
+				clocks = <&xtal>;
+				clock-names = "xtal";
+			};
+
 			uart_B: serial@7a000 {
 				compatible = "amlogic,meson-s4-uart",
 					     "amlogic,meson-ao-uart";
-- 
2.33.1


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[PATCH V2 3/3] clk: meson: s4: add s4 SoC clock controller driver

[Yu Tu]

Add the peripheral clock controller found in the s4 SoC family.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 drivers/clk/meson/Kconfig  |   15 +
 drivers/clk/meson/Makefile |    1 +
 drivers/clk/meson/s4.c     | 4732 ++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/s4.h     |  296 +++
 4 files changed, 5044 insertions(+)
 create mode 100644 drivers/clk/meson/s4.c
 create mode 100644 drivers/clk/meson/s4.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index fc002c155bc3..a3b630db991c 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -115,4 +115,19 @@ config COMMON_CLK_G12A
 	help
 	  Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
 	  devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_S4
+	tristate "S4 SoC clock controllers support"
+	depends on ARM64
+	default y
+	select COMMON_CLK_MESON_REGMAP
+	select COMMON_CLK_MESON_DUALDIV
+	select COMMON_CLK_MESON_MPLL
+	select COMMON_CLK_MESON_PLL
+	select COMMON_CLK_MESON_VID_PLL_DIV
+	select MFD_SYSCON
+	help
+	  Support for the clock controller on Amlogic S805X2 and S905Y4 devices,
+	  aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
+	  Say Y if you want peripherals and CPU frequency scaling to work.
 endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 6eca2a406ee3..b3ef5f67820f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
 obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
 obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
+obj-$(CONFIG_COMMON_CLK_S4) += s4.o
diff --git a/drivers/clk/meson/s4.c b/drivers/clk/meson/s4.c
new file mode 100644
index 000000000000..03dc603ab023
--- /dev/null
+++ b/drivers/clk/meson/s4.c
@@ -0,0 +1,4732 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-S4 Clock Controller Driver
+ *
+ * Copyright (c) 2021 Amlogic, inc.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "s4.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap s4_fixed_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_FIXPLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fixed_pll_dco",
+		.ops = &meson_clk_pll_ro_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fixed_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_FIXPLL_CTRL0,
+		.shift = 16,
+		.width = 2,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fixed_pll",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll_dco.hw
+		},
+		.num_parents = 1,
+		/*
+		 * This clock won't ever change at runtime so
+		 * CLK_SET_RATE_PARENT is not required
+		 */
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div2_div = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div2 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div2_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div3_div = {
+	.mult = 1,
+	.div = 3,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div3_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div3 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 20,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div3",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div3_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div4_div = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div4_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div4 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 21,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div4",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div4_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div5_div = {
+	.mult = 1,
+	.div = 5,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div5_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div5 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 22,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div5",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div5_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div7_div = {
+	.mult = 1,
+	.div = 7,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div7_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div7 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 23,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div7",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div7_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div2p5_div = {
+	.mult = 2,
+	.div = 5,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2p5_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div2p5 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2p5",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div2p5_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static const struct pll_mult_range s4_gp0_pll_mult_range = {
+	.min = 125,
+	.max = 250,
+};
+
+/*
+ * Internal gp0 pll emulation configuration parameters
+ */
+static const struct reg_sequence s4_gp0_init_regs[] = {
+	{ .reg = ANACTRL_GP0PLL_CTRL1,	.def = 0x00000000 },
+	{ .reg = ANACTRL_GP0PLL_CTRL2,	.def = 0x00000000 },
+	{ .reg = ANACTRL_GP0PLL_CTRL3,	.def = 0x48681c00 },
+	{ .reg = ANACTRL_GP0PLL_CTRL4,	.def = 0x88770290 },
+	{ .reg = ANACTRL_GP0PLL_CTRL5,	.def = 0x39272000 },
+	{ .reg = ANACTRL_GP0PLL_CTRL6,	.def = 0x56540000 }
+};
+
+static struct clk_regmap s4_gp0_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_GP0PLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+		.range = &s4_gp0_pll_mult_range,
+		.init_regs = s4_gp0_init_regs,
+		.init_count = ARRAY_SIZE(s4_gp0_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gp0_pll_dco",
+		.ops = &meson_clk_pll_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_gp0_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_GP0PLL_CTRL0,
+		.shift = 16,
+		.width = 3,
+		.flags = (CLK_DIVIDER_POWER_OF_TWO |
+			  CLK_DIVIDER_ROUND_CLOSEST),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gp0_pll",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_gp0_pll_dco.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * Internal hifi pll emulation configuration parameters
+ */
+static const struct reg_sequence s4_hifi_init_regs[] = {
+	{ .reg = ANACTRL_HIFIPLL_CTRL1,	.def = 0x00010e56 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00000000 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL3,	.def = 0x6a285c00 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL4,	.def = 0x65771290 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL5,	.def = 0x39272000 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL6,	.def = 0x56540000 }
+};
+
+static struct clk_regmap s4_hifi_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+		.range = &s4_gp0_pll_mult_range,
+		.init_regs = s4_hifi_init_regs,
+		.init_count = ARRAY_SIZE(s4_hifi_init_regs),
+		.flags = CLK_MESON_PLL_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hifi_pll_dco",
+		.ops = &meson_clk_pll_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_hifi_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_HIFIPLL_CTRL0,
+		.shift = 16,
+		.width = 2,
+		.flags = (CLK_DIVIDER_POWER_OF_TWO |
+			  CLK_DIVIDER_ROUND_CLOSEST),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hifi_pll",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hifi_pll_dco.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_pll_dco",
+		.ops = &meson_clk_pll_ro_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+		/*
+		 * Display directly handle hdmi pll registers ATM, we need
+		 * NOCACHE to keep our view of the clock as accurate as
+		 * possible
+		 */
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk_regmap s4_hdmi_pll_od = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_HDMIPLL_CTRL0,
+		.shift = 16,
+		.width = 4,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_pll_od",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdmi_pll_dco.hw
+		},
+		.num_parents = 1,
+		/*
+		 * Display directly handle hdmi pll registers ATM, we need
+		 * NOCACHE to keep our view of the clock as accurate as
+		 * possible
+		 */
+		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_HDMIPLL_CTRL0,
+		.shift = 20,
+		.width = 2,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_pll",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdmi_pll_od.hw
+		},
+		.num_parents = 1,
+		/*
+		 * Display directly handle hdmi pll registers ATM, we need
+		 * NOCACHE to keep our view of the clock as accurate as
+		 * possible
+		 */
+		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_fixed_factor s4_mpll_50m_div = {
+	.mult = 1,
+	.div = 80,
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll_50m_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll_dco.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll_50m = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = ANACTRL_FIXPLL_CTRL3,
+		.mask = 0x1,
+		.shift = 5,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll_50m",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", },
+			{ .hw = &s4_mpll_50m_div.hw },
+		},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_fixed_factor s4_mpll_prediv = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll_prediv",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll_dco.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static const struct reg_sequence s4_mpll0_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll0_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll0_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll0_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll0_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL1,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll0_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct reg_sequence s4_mpll1_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL4,	.def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll1_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll1_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll1_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll1_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL3,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll1_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct reg_sequence s4_mpll2_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll2_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll2_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll2_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll2_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll2 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL5,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll2",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll2_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct reg_sequence s4_mpll3_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll3_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll3_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll3_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll3_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll3 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL7,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll3",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll3_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * rtc 32k clock in gate
+ */
+static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "rtc_32k_by_oscin_clkin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static const struct meson_clk_dualdiv_param s4_32k_div_table[] = {
+	{
+		.dual	= 1,
+		.n1	= 733,
+		.m1	= 8,
+		.n2	= 732,
+		.m2	= 11,
+	},
+	{}
+};
+
+static struct clk_regmap s4_rtc_32k_by_oscin_div = {
+	.data = &(struct meson_clk_dualdiv_data){
+		.n1 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.n2 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.m1 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.m2 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.dual = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.table = s4_32k_div_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "rtc_32k_by_oscin_div",
+		.ops = &meson_clk_dualdiv_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_rtc_32k_by_oscin_clkin.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_rtc_32k_by_oscin_sel = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+		.mask = 0x1,
+		.shift = 24,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "rtc_32k_by_oscin_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_rtc_32k_by_oscin_div.hw,
+			&s4_rtc_32k_by_oscin_clkin.hw,
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_rtc_32k_by_oscin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "rtc_32k_by_oscin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_rtc_32k_by_oscin_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * This RTC clock can be supplied by an external 32KHz crystal oscillator.
+ * If it is used, it should be documented in using fW_name and documented in the
+ * Bindings. Not currently in use on this board, so skip it.
+ */
+static u32 rtc_clk_sel[] = { 0, 1 };
+static const struct clk_parent_data rtc_clk_sel_parent_data[] = {
+	{ .hw = &s4_rtc_32k_by_oscin.hw },
+	{ .hw = &s4_rtc_32k_by_oscin_div.hw },
+	{ .fw_name = "ext-32k-0",  }
+};
+
+static struct clk_regmap s4_rtc_clk = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_RTC_CTRL,
+		.mask = 0x3,
+		.shift = 0,
+		.table = rtc_clk_sel,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "rtc_clk_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = rtc_clk_sel_parent_data,
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * sys clk
+ * The clock corresponding to these 5 is AXi_CLK, which is dedicated to AXI. So skip it.
+ */
+static u32 mux_table_sys_ab_clk_sel[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data sys_ab_clk_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_rtc_clk.hw }
+};
+
+static struct clk_regmap s4_sysclk_b_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.mask = 0x7,
+		.shift = 26,
+		.table = mux_table_sys_ab_clk_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_b_sel",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_data = sys_ab_clk_parent_data,
+		.num_parents = ARRAY_SIZE(sys_ab_clk_parent_data),
+	},
+};
+
+static struct clk_regmap s4_sysclk_b_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.shift = 16,
+		.width = 10,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_b_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_b_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sysclk_b = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.bit_idx = 29,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sysclk_b",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_b_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sysclk_a_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.mask = 0x7,
+		.shift = 10,
+		.table = mux_table_sys_ab_clk_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_a_sel",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_data = sys_ab_clk_parent_data,
+		.num_parents = ARRAY_SIZE(sys_ab_clk_parent_data),
+	},
+};
+
+static struct clk_regmap s4_sysclk_a_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.shift = 0,
+		.width = 10,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_a_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_a_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sysclk_a = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.bit_idx = 13,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sysclk_a",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_a_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sys_clk = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.mask = 0x1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sys_clk",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_a.hw,
+			&s4_sysclk_b.hw
+		},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_clkin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECA_CTRL0,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "ceca_32k_clkin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_div = {
+	.data = &(struct meson_clk_dualdiv_data){
+		.n1 = {
+			.reg_off = CLKCTRL_CECA_CTRL0,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.n2 = {
+			.reg_off = CLKCTRL_CECA_CTRL0,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.m1 = {
+			.reg_off = CLKCTRL_CECA_CTRL1,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.m2 = {
+			.reg_off = CLKCTRL_CECA_CTRL1,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.dual = {
+			.reg_off = CLKCTRL_CECA_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.table = s4_32k_div_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_div",
+		.ops = &meson_clk_dualdiv_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_clkin.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_sel_pre = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECA_CTRL1,
+		.mask = 0x1,
+		.shift = 24,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_sel_pre",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_div.hw,
+			&s4_ceca_32k_clkin.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_sel = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECA_CTRL1,
+		.mask = 0x1,
+		.shift = 31,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_sel_pre.hw,
+			&s4_rtc_clk.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_clkout = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECA_CTRL0,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_clkout",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_clkin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECB_CTRL0,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cecb_32k_clkin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_div = {
+	.data = &(struct meson_clk_dualdiv_data){
+		.n1 = {
+			.reg_off = CLKCTRL_CECB_CTRL0,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.n2 = {
+			.reg_off = CLKCTRL_CECB_CTRL0,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.m1 = {
+			.reg_off = CLKCTRL_CECB_CTRL1,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.m2 = {
+			.reg_off = CLKCTRL_CECB_CTRL1,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.dual = {
+			.reg_off = CLKCTRL_CECB_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.table = s4_32k_div_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_div",
+		.ops = &meson_clk_dualdiv_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_clkin.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_sel_pre = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECB_CTRL1,
+		.mask = 0x1,
+		.shift = 24,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_sel_pre",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_div.hw,
+			&s4_cecb_32k_clkin.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_sel = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECB_CTRL1,
+		.mask = 0x1,
+		.shift = 31,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_sel_pre.hw,
+			&s4_rtc_clk.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_clkout = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECB_CTRL0,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_clkout",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_sc_parent_data[] = {
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .fw_name = "xtal", }
+};
+
+static struct clk_regmap s4_sc_clk_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SC_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sc_clk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sc_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sc_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sc_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SC_CLK_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sc_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sc_clk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sc_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SC_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sc_clk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sc_clk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_12_24M_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CLK12_24_CTRL,
+		.bit_idx = 11,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "12_24m_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_12M_clk_div = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "12M",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_12_24M_clk_gate.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_12_24M_clk = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_CLK12_24_CTRL,
+		.mask = 0x1,
+		.shift = 10,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "12_24m",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_12_24M_clk_gate.hw,
+			&s4_12M_clk_div.hw,
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* Video Clocks */
+static struct clk_regmap s4_vid_pll_div = {
+	.data = &(struct meson_vid_pll_div_data){
+		.val = {
+			.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
+			.shift   = 0,
+			.width   = 15,
+		},
+		.sel = {
+			.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
+			.shift   = 16,
+			.width   = 2,
+		},
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vid_pll_div",
+		.ops = &meson_vid_pll_div_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_pll.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vid_pll_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_PLL_CLK_DIV,
+		.mask = 0x1,
+		.shift = 18,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vid_pll_sel",
+		.ops = &clk_regmap_mux_ops,
+		/*
+		 * bit 18 selects from 2 possible parents:
+		 * vid_pll_div or hdmi_pll
+		 */
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vid_pll_div.hw,
+			&s4_hdmi_pll.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vid_pll = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_PLL_CLK_DIV,
+		.bit_idx = 19,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vid_pll",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vid_pll_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_vclk_parent_hws[] = {
+	&s4_vid_pll.hw,
+	&s4_gp0_pll.hw,
+	&s4_hifi_pll.hw,
+	&s4_mpll1.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div4.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw
+};
+
+static struct clk_regmap s4_vclk_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 16,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vclk_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vclk_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 16,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vclk_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vclk_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_input = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.bit_idx = 16,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_input",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_input = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_DIV,
+		.bit_idx = 16,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_input",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_input.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VIID_CLK_DIV,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_input.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_vclk = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 19,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 19,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 0,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div2_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 1,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div2_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div4_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 2,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div4_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div6_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 3,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div6_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div12_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div12_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 0,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div2_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 1,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div2_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div4_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 2,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div4_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div6_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 3,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div6_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div12_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div12_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div2 = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div2",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div2_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div4 = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div4",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div4_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div6 = {
+	.mult = 1,
+	.div = 6,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div6",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div6_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div12 = {
+	.mult = 1,
+	.div = 12,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div12",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div12_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div2 = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div2",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div2_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div4 = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div4",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div4_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div6 = {
+	.mult = 1,
+	.div = 6,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div6",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div6_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div12 = {
+	.mult = 1,
+	.div = 12,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div12",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div12_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+/*
+ * bits 31:28 selects from 12 possible parents:
+ * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
+ * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12r.
+ * The 5,6,7 corresponds to no real clock, so threre are not used.
+ */
+static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_hw *s4_cts_parent_hws[] = {
+	&s4_vclk_div1.hw,
+	&s4_vclk_div2.hw,
+	&s4_vclk_div4.hw,
+	&s4_vclk_div6.hw,
+	&s4_vclk_div12.hw,
+	&s4_vclk2_div1.hw,
+	&s4_vclk2_div2.hw,
+	&s4_vclk2_div4.hw,
+	&s4_vclk2_div6.hw,
+	&s4_vclk2_div12.hw
+};
+
+static struct clk_regmap s4_cts_enci_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.mask = 0xf,
+		.shift = 28,
+		.table = mux_table_cts_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_enci_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_encp_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.mask = 0xf,
+		.shift = 20,
+		.table = mux_table_cts_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_encp_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_vdac_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VIID_CLK_DIV,
+		.mask = 0xf,
+		.shift = 28,
+		.table = mux_table_cts_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_vdac_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+/*
+ * TOFIX: add support for cts_tcon
+ * bits 31:28 selects from 12 possible parents:
+ * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
+ * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
+ * cts_tcon
+ */
+static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_hw *s4_cts_hdmi_tx_parent_hws[] = {
+	&s4_vclk_div1.hw,
+	&s4_vclk_div2.hw,
+	&s4_vclk_div4.hw,
+	&s4_vclk_div6.hw,
+	&s4_vclk_div12.hw,
+	&s4_vclk2_div1.hw,
+	&s4_vclk2_div2.hw,
+	&s4_vclk2_div4.hw,
+	&s4_vclk2_div6.hw,
+	&s4_vclk2_div12.hw
+};
+
+static struct clk_regmap s4_hdmi_tx_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.mask = 0xf,
+		.shift = 16,
+		.table = mux_table_hdmi_tx_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_tx_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_hdmi_tx_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_hdmi_tx_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_enci = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 0,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_enci",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cts_enci_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_encp = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 2,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_encp",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cts_encp_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_vdac = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_vdac",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cts_vdac_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_tx = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 5,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdmi_tx",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdmi_tx_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* HDMI Clocks */
+static const struct clk_parent_data s4_hdmi_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw }
+};
+
+static struct clk_regmap s4_hdmi_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_hdmi_parent_data,
+		.num_parents = ARRAY_SIZE(s4_hdmi_parent_data),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_sel.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_hdmi = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdmi",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_ts_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_TS_CLK_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ts_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "xtal",
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_ts_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_TS_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ts_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ts_clk_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+/*
+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
+ * muxed by a glitch-free switch. The CCF can manage this glitch-free
+ * mux because it does top-to-bottom updates the each clock tree and
+ * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
+ */
+static const struct clk_parent_data s4_mali_0_1_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_fclk_div2p5.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw }
+};
+
+static struct clk_regmap s4_mali_0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_mali_0_1_parent_data,
+		.num_parents = ARRAY_SIZE(s4_mali_0_1_parent_data),
+		/*
+		 * Don't request the parent to change the rate because
+		 * all GPU frequencies can be derived from the fclk_*
+		 * clocks and one special GP0_PLL setting. This is
+		 * important because we need the MPLL clocks for audio.
+		 */
+		.flags = 0,
+	},
+};
+
+static struct clk_regmap s4_mali_0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_mali_0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_mali_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_mali_0_1_parent_data,
+		.num_parents = ARRAY_SIZE(s4_mali_0_1_parent_data),
+		/*
+		 * Don't request the parent to change the rate because
+		 * all GPU frequencies can be derived from the fclk_*
+		 * clocks and one special GP0_PLL setting. This is
+		 * important because we need the MPLL clocks for audio.
+		 */
+		.flags = 0,
+	},
+};
+
+static struct clk_regmap s4_mali_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_1_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_mali_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_mali_parent_hws[] = {
+	&s4_mali_0.hw,
+	&s4_mali_1.hw
+};
+
+static struct clk_regmap s4_mali_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.mask = 1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_mali_parent_hws,
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* VDEC clocks */
+static const struct clk_parent_data s4_dec_parent_data[] = {
+	{ .hw = &s4_fclk_div2p5.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .fw_name = "xtal", }
+};
+
+static struct clk_regmap s4_vdec_p0_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_p0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p1_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p1_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p1_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_p1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_vdec_mux_parent_hws[] = {
+	&s4_vdec_p0.hw,
+	&s4_vdec_p1.hw
+};
+
+static struct clk_regmap s4_vdec_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.mask = 0x1,
+		.shift = 15,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vdec_mux_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vdec_mux_parent_hws),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p0_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC2_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC2_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC2_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hevcf_p0_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p1_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p1_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p1_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hevcf_p1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_hevcf_mux_parent_hws[] = {
+	&s4_hevcf_p0.hw,
+	&s4_hevcf_p1.hw
+};
+
+static struct clk_regmap s4_hevcf_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.mask = 0x1,
+		.shift = 15,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_hevcf_mux_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_hevcf_mux_parent_hws),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* VPU Clock */
+
+static const struct clk_hw *s4_vpu_parent_hws[] = {
+	&s4_fclk_div3.hw,
+	&s4_fclk_div4.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw,
+	&s4_mpll1.hw,
+	&s4_vid_pll.hw,
+	&s4_hifi_pll.hw,
+	&s4_gp0_pll.hw
+};
+
+static struct clk_regmap s4_vpu_0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vpu_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vpu_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vpu_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vpu_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.mask = 1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu",
+		.ops = &clk_regmap_mux_ops,
+		/*
+		 * bit 31 selects from 2 possible parents:
+		 * vpu_0 or vpu_1
+		 */
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_0.hw,
+			&s4_vpu_1.hw,
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static const struct clk_parent_data vpu_clkb_tmp_parent_data[] = {
+	{ .hw = &s4_vpu.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw }
+};
+
+static struct clk_regmap s4_vpu_clkb_tmp_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.mask = 0x3,
+		.shift = 20,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkb_tmp_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = vpu_clkb_tmp_parent_data,
+		.num_parents = ARRAY_SIZE(vpu_clkb_tmp_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb_tmp_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.shift = 16,
+		.width = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkb_tmp_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_tmp_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb_tmp = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkb_tmp",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_tmp_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkb_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_tmp.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkb",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *vpu_clkc_parent_hws[] = {
+	&s4_fclk_div4.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw,
+	&s4_mpll1.hw,
+	&s4_vid_pll.hw,
+	&s4_mpll2.hw,
+	&s4_gp0_pll.hw
+};
+
+static struct clk_regmap s4_vpu_clkc_p0_mux  = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = vpu_clkc_parent_hws,
+		.num_parents = ARRAY_SIZE(vpu_clkc_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkc_p0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p1_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p1_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = vpu_clkc_parent_hws,
+		.num_parents = ARRAY_SIZE(vpu_clkc_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p1_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkc_p1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_vpu_mux_parent_hws[] = {
+	&s4_vpu_clkc_p0.hw,
+	&s4_vpu_clkc_p1.hw
+};
+
+static struct clk_regmap s4_vpu_clkc_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.mask = 0x1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vpu_mux_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vpu_mux_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+/* VAPB Clock */
+
+static const struct clk_hw *s4_vapb_parent_hws[] = {
+	&s4_fclk_div4.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw,
+	&s4_mpll1.hw,
+	&s4_vid_pll.hw,
+	&s4_mpll2.hw,
+	&s4_fclk_div2p5.hw
+};
+
+static struct clk_regmap s4_vapb_0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vapb_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vapb_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vapb_0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vapb_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vapb_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_1_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vapb_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.mask = 1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_sel",
+		.ops = &clk_regmap_mux_ops,
+		/*
+		 * bit 31 selects from 2 possible parents:
+		 * vapb_0 or vapb_1
+		 */
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_0.hw,
+			&s4_vapb_1.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_ge2d_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "ge2d_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vapb.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_esmclk_parent_hws[] = {
+	&s4_fclk_div7.hw,
+	&s4_fclk_div4.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div5.hw
+};
+
+static struct clk_regmap s4_hdcp22_esmclk_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_esmclk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_esmclk_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_esmclk_parent_hws),
+	},
+};
+
+static struct clk_regmap s4_hdcp22_esmclk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_esmclk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_esmclk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdcp22_esmclk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdcp22_esmclk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_esmclk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_skpclk_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw }
+};
+
+static struct clk_regmap s4_hdcp22_skpclk_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_skpclk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_skpclk_parent_data,
+		.num_parents = ARRAY_SIZE(s4_skpclk_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdcp22_skpclk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_skpclk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_skpclk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdcp22_skpclk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdcp22_skpclk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_skpclk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_vdin_parent_data[]  = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_vid_pll.hw }
+};
+
+static struct clk_regmap s4_vdin_meas_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdin_meas_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_vdin_parent_data,
+		.num_parents = ARRAY_SIZE(s4_vdin_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdin_meas_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdin_meas_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdin_meas_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdin_meas_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdin_meas_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdin_meas_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* EMMC/NAND clock */
+
+static const struct clk_parent_data s4_sd_emmc_clk0_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_fclk_div2p5.hw },
+	/*
+	 * Following these parent clocks, we should also have had mpll2, mpll3
+	 * and gp0_pll but these clocks are too precious to be used here. All
+	 * the necessary rates for MMC and NAND operation can be acheived using
+	 * hifi_pll or fclk_div clocks
+	 */
+};
+
+static struct clk_regmap s4_sd_emmc_c_clk0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_NAND_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_c_clk0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sd_emmc_clk0_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_c_clk0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_NAND_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_c_clk0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_c_clk0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_c_clk0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_NAND_CLK_CTRL,
+		.bit_idx = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sd_emmc_c_clk0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_c_clk0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_a_clk0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_a_clk0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sd_emmc_clk0_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_a_clk0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_a_clk0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_a_clk0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_a_clk0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.bit_idx = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sd_emmc_a_clk0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_a_clk0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_b_clk0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_b_clk0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sd_emmc_clk0_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_b_clk0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_b_clk0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_b_clk0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_b_clk0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.bit_idx = 23,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sd_emmc_b_clk0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_b_clk0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* SPICC SCLK source clock */
+
+static const struct clk_parent_data s4_spicc_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_sys_clk.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+};
+
+static struct clk_regmap s4_spicc0_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SPICC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "spicc0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_spicc_parent_data,
+		.num_parents = ARRAY_SIZE(s4_spicc_parent_data),
+	},
+};
+
+static struct clk_regmap s4_spicc0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SPICC_CLK_CTRL,
+		.shift = 0,
+		.width = 6,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "spicc0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_spicc0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_spicc0_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SPICC_CLK_CTRL,
+		.bit_idx = 6,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "spicc0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_spicc0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* PWM CLOCK */
+
+static const struct clk_parent_data s4_pwm_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_vid_pll.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw }
+};
+
+static struct clk_regmap s4_pwm_a_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_a_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_a_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_a_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_a_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_a_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_a_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_a_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_b_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_b_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_b_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_b_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_b_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_b_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_b_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_b_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_c_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_c_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_c_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_c_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_c_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_c_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_c_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_c_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_d_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_d_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_d_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_d_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_d_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_d_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_d_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_d_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_e_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_e_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_e_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_e_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_e_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_e_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_e_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_e_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_f_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_f_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_f_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_f_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_f_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_f_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_f_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_f_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_g_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_g_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_g_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_g_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_g_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_g_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_g_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_g_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_h_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_h_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_h_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_h_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_h_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_h_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_h_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_h_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_i_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_i_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_i_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_i_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_i_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_i_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_i_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_i_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_j_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_j_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_j_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_j_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_h_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_j_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_j_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_j_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_saradc_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_SAR_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "saradc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", },
+			{ .hw = &s4_sys_clk.hw },
+		},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap s4_saradc_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_SAR_CLK_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "saradc_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_saradc_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_saradc_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_SAR_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "saradc_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_saradc_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * gen clk is designed for debug/monitor some internal clock quality. Some of the
+ * corresponding clock sources are not described in the clock tree, so they are skipped.
+ */
+static u32 s4_gen_clk_mux_table[] = { 0, 5, 7, 19, 21, 22,
+				      23, 24, 25, 26, 27, 28 };
+static const struct clk_parent_data s4_gen_clk_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_mpll0.hw },
+	{ .hw = &s4_mpll1.hw },
+	{ .hw = &s4_mpll2.hw },
+	{ .hw = &s4_mpll3.hw }
+};
+
+static struct clk_regmap s4_gen_clk_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_GEN_CLK_CTRL,
+		.mask = 0x1f,
+		.shift = 12,
+		.table = s4_gen_clk_mux_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gen_clk_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_gen_clk_parent_data,
+		.num_parents = ARRAY_SIZE(s4_gen_clk_parent_data),
+	},
+};
+
+static struct clk_regmap s4_gen_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_GEN_CLK_CTRL,
+		.shift = 0,
+		.width = 11,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gen_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_gen_clk_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_gen_clk = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_GEN_CLK_CTRL,
+		.bit_idx = 11,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "gen_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_gen_clk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_adc_extclk_in_parent_data[]  = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_mpll2.hw },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .hw = &s4_hifi_pll.hw }
+};
+
+static struct clk_regmap s4_adc_extclk_in_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "adc_extclk_in_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_adc_extclk_in_parent_data,
+		.num_parents = ARRAY_SIZE(s4_adc_extclk_in_parent_data),
+	},
+};
+
+static struct clk_regmap s4_adc_extclk_in_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "adc_extclk_in_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_adc_extclk_in_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_adc_extclk_in_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "adc_extclk_in",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_adc_extclk_in_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_demod_core_clk_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "demod_core_clk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", },
+			{ .hw = &s4_fclk_div7.hw },
+			{ .hw = &s4_fclk_div4.hw },
+			{ .hw = &s4_adc_extclk_in_gate.hw }
+		},
+		.num_parents = 4,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_demod_core_clk_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "demod_core_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_demod_core_clk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_demod_core_clk_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "demod_core_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_demod_core_clk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+#define MESON_GATE(_name, _reg, _bit) \
+	MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)
+
+static MESON_GATE(s4_ddr,		CLKCTRL_SYS_CLK_EN0_REG0, 0);
+static MESON_GATE(s4_dos,		CLKCTRL_SYS_CLK_EN0_REG0, 1);
+static MESON_GATE(s4_ethphy,		CLKCTRL_SYS_CLK_EN0_REG0, 4);
+static MESON_GATE(s4_mali,		CLKCTRL_SYS_CLK_EN0_REG0, 6);
+static MESON_GATE(s4_aocpu,		CLKCTRL_SYS_CLK_EN0_REG0, 13);
+static MESON_GATE(s4_aucpu,		CLKCTRL_SYS_CLK_EN0_REG0, 14);
+static MESON_GATE(s4_cec,		CLKCTRL_SYS_CLK_EN0_REG0, 16);
+static MESON_GATE(s4_sdemmca,		CLKCTRL_SYS_CLK_EN0_REG0, 24);
+static MESON_GATE(s4_sdemmcb,		CLKCTRL_SYS_CLK_EN0_REG0, 25);
+static MESON_GATE(s4_nand,		CLKCTRL_SYS_CLK_EN0_REG0, 26);
+static MESON_GATE(s4_smartcard,		CLKCTRL_SYS_CLK_EN0_REG0, 27);
+static MESON_GATE(s4_acodec,		CLKCTRL_SYS_CLK_EN0_REG0, 28);
+static MESON_GATE(s4_spifc,		CLKCTRL_SYS_CLK_EN0_REG0, 29);
+static MESON_GATE(s4_msr_clk,		CLKCTRL_SYS_CLK_EN0_REG0, 30);
+static MESON_GATE(s4_ir_ctrl,		CLKCTRL_SYS_CLK_EN0_REG0, 31);
+
+static MESON_GATE(s4_audio,		CLKCTRL_SYS_CLK_EN0_REG1, 0);
+static MESON_GATE(s4_eth,		CLKCTRL_SYS_CLK_EN0_REG1, 3);
+static MESON_GATE(s4_uart_a,		CLKCTRL_SYS_CLK_EN0_REG1, 5);
+static MESON_GATE(s4_uart_b,		CLKCTRL_SYS_CLK_EN0_REG1, 6);
+static MESON_GATE(s4_uart_c,		CLKCTRL_SYS_CLK_EN0_REG1, 7);
+static MESON_GATE(s4_uart_d,		CLKCTRL_SYS_CLK_EN0_REG1, 8);
+static MESON_GATE(s4_uart_e,		CLKCTRL_SYS_CLK_EN0_REG1, 9);
+static MESON_GATE(s4_aififo,		CLKCTRL_SYS_CLK_EN0_REG1, 11);
+static MESON_GATE(s4_ts_ddr,		CLKCTRL_SYS_CLK_EN0_REG1, 15);
+static MESON_GATE(s4_ts_pll,		CLKCTRL_SYS_CLK_EN0_REG1, 16);
+static MESON_GATE(s4_g2d,		CLKCTRL_SYS_CLK_EN0_REG1, 20);
+static MESON_GATE(s4_spicc0,		CLKCTRL_SYS_CLK_EN0_REG1, 21);
+static MESON_GATE(s4_usb,		CLKCTRL_SYS_CLK_EN0_REG1, 26);
+static MESON_GATE(s4_i2c_m_a,		CLKCTRL_SYS_CLK_EN0_REG1, 30);
+static MESON_GATE(s4_i2c_m_b,		CLKCTRL_SYS_CLK_EN0_REG1, 31);
+
+static MESON_GATE(s4_i2c_m_c,		CLKCTRL_SYS_CLK_EN0_REG2, 0);
+static MESON_GATE(s4_i2c_m_d,		CLKCTRL_SYS_CLK_EN0_REG2, 1);
+static MESON_GATE(s4_i2c_m_e,		CLKCTRL_SYS_CLK_EN0_REG2, 2);
+static MESON_GATE(s4_hdmitx_apb,	CLKCTRL_SYS_CLK_EN0_REG2, 4);
+static MESON_GATE(s4_i2c_s_a,		CLKCTRL_SYS_CLK_EN0_REG2, 5);
+static MESON_GATE(s4_usb1_to_ddr,	CLKCTRL_SYS_CLK_EN0_REG2, 8);
+static MESON_GATE(s4_hdcp22,		CLKCTRL_SYS_CLK_EN0_REG2, 10);
+static MESON_GATE(s4_mmc_apb,		CLKCTRL_SYS_CLK_EN0_REG2, 11);
+static MESON_GATE(s4_rsa,		CLKCTRL_SYS_CLK_EN0_REG2, 18);
+static MESON_GATE(s4_cpu_debug,		CLKCTRL_SYS_CLK_EN0_REG2, 19);
+static MESON_GATE(s4_vpu_intr,		CLKCTRL_SYS_CLK_EN0_REG2, 25);
+static MESON_GATE(s4_demod,		CLKCTRL_SYS_CLK_EN0_REG2, 27);
+static MESON_GATE(s4_sar_adc,		CLKCTRL_SYS_CLK_EN0_REG2, 28);
+static MESON_GATE(s4_gic,		CLKCTRL_SYS_CLK_EN0_REG2, 30);
+
+static MESON_GATE(s4_pwm_ab,		CLKCTRL_SYS_CLK_EN0_REG3, 7);
+static MESON_GATE(s4_pwm_cd,		CLKCTRL_SYS_CLK_EN0_REG3, 8);
+static MESON_GATE(s4_pwm_ef,		CLKCTRL_SYS_CLK_EN0_REG3, 9);
+static MESON_GATE(s4_pwm_gh,		CLKCTRL_SYS_CLK_EN0_REG3, 10);
+static MESON_GATE(s4_pwm_ij,		CLKCTRL_SYS_CLK_EN0_REG3, 11);
+
+/* Array of all clocks provided by this provider */
+static struct clk_hw_onecell_data s4_hw_onecell_data = {
+	.hws = {
+		[CLKID_FIXED_PLL_DCO]		= &s4_fixed_pll_dco.hw,
+		[CLKID_FIXED_PLL]		= &s4_fixed_pll.hw,
+		[CLKID_FCLK_DIV2_DIV]		= &s4_fclk_div2_div.hw,
+		[CLKID_FCLK_DIV2]		= &s4_fclk_div2.hw,
+		[CLKID_FCLK_DIV3_DIV]		= &s4_fclk_div3_div.hw,
+		[CLKID_FCLK_DIV3]		= &s4_fclk_div3.hw,
+		[CLKID_FCLK_DIV4_DIV]		= &s4_fclk_div4_div.hw,
+		[CLKID_FCLK_DIV4]		= &s4_fclk_div4.hw,
+		[CLKID_FCLK_DIV5_DIV]		= &s4_fclk_div5_div.hw,
+		[CLKID_FCLK_DIV5]		= &s4_fclk_div5.hw,
+		[CLKID_FCLK_DIV7_DIV]		= &s4_fclk_div7_div.hw,
+		[CLKID_FCLK_DIV7]		= &s4_fclk_div7.hw,
+		[CLKID_FCLK_DIV2P5_DIV]		= &s4_fclk_div2p5_div.hw,
+		[CLKID_FCLK_DIV2P5]		= &s4_fclk_div2p5.hw,
+
+		[CLKID_GP0_PLL_DCO]		= &s4_gp0_pll_dco.hw,
+		[CLKID_GP0_PLL]			= &s4_gp0_pll.hw,
+
+		[CLKID_HIFI_PLL_DCO]		= &s4_hifi_pll_dco.hw,
+		[CLKID_HIFI_PLL]		= &s4_hifi_pll.hw,
+		[CLKID_HDMI_PLL_DCO]		= &s4_hdmi_pll_dco.hw,
+		[CLKID_HDMI_PLL_OD]		= &s4_hdmi_pll_od.hw,
+		[CLKID_HDMI_PLL]		= &s4_hdmi_pll.hw,
+		[CLKID_MPLL_50M_DIV]		= &s4_mpll_50m_div.hw,
+		[CLKID_MPLL_50M]		= &s4_mpll_50m.hw,
+		[CLKID_MPLL_PREDIV]		= &s4_mpll_prediv.hw,
+		[CLKID_MPLL0_DIV]		= &s4_mpll0_div.hw,
+		[CLKID_MPLL0]			= &s4_mpll0.hw,
+		[CLKID_MPLL1_DIV]		= &s4_mpll1_div.hw,
+		[CLKID_MPLL1]			= &s4_mpll1.hw,
+		[CLKID_MPLL2_DIV]		= &s4_mpll2_div.hw,
+		[CLKID_MPLL2]			= &s4_mpll2.hw,
+		[CLKID_MPLL3_DIV]		= &s4_mpll3_div.hw,
+		[CLKID_MPLL3]			= &s4_mpll3.hw,
+
+		[CLKID_RTC_32K_CLKIN]		= &s4_rtc_32k_by_oscin_clkin.hw,
+		[CLKID_RTC_32K_DIV]		= &s4_rtc_32k_by_oscin_div.hw,
+		[CLKID_RTC_32K_SEL]		= &s4_rtc_32k_by_oscin_sel.hw,
+		[CLKID_RTC_32K_XATL]		= &s4_rtc_32k_by_oscin.hw,
+		[CLKID_RTC_CLK]			= &s4_rtc_clk.hw,
+
+		[CLKID_SYS_CLK_B_SEL]		= &s4_sysclk_b_sel.hw,
+		[CLKID_SYS_CLK_B_DIV]		= &s4_sysclk_b_div.hw,
+		[CLKID_SYS_CLK_B_GATE]		= &s4_sysclk_b.hw,
+		[CLKID_SYS_CLK_A_SEL]		= &s4_sysclk_a_sel.hw,
+		[CLKID_SYS_CLK_A_DIV]		= &s4_sysclk_a_div.hw,
+		[CLKID_SYS_CLK_A_GATE]		= &s4_sysclk_a.hw,
+		[CLKID_SYS_CLK]			= &s4_sys_clk.hw,
+
+		[CLKID_CECA_32K_CLKIN]		= &s4_ceca_32k_clkin.hw,
+		[CLKID_CECA_32K_DIV]		= &s4_ceca_32k_div.hw,
+		[CLKID_CECA_32K_SEL_PRE]	= &s4_ceca_32k_sel_pre.hw,
+		[CLKID_CECA_32K_SEL]		= &s4_ceca_32k_sel.hw,
+		[CLKID_CECA_32K_CLKOUT]		= &s4_ceca_32k_clkout.hw,
+
+		[CLKID_CECB_32K_CLKIN]		= &s4_cecb_32k_clkin.hw,
+		[CLKID_CECB_32K_DIV]		= &s4_cecb_32k_div.hw,
+		[CLKID_CECB_32K_SEL_PRE]	= &s4_cecb_32k_sel_pre.hw,
+		[CLKID_CECB_32K_SEL]		= &s4_cecb_32k_sel.hw,
+		[CLKID_CECB_32K_CLKOUT]		= &s4_cecb_32k_clkout.hw,
+
+		[CLKID_SC_CLK_SEL]		= &s4_sc_clk_mux.hw,
+		[CLKID_SC_CLK_DIV]		= &s4_sc_clk_div.hw,
+		[CLKID_SC_CLK_GATE]		= &s4_sc_clk_gate.hw,
+
+		[CLKID_12_24M_CLK_GATE]		= &s4_12_24M_clk_gate.hw,
+		[CLKID_12M_CLK_DIV]		= &s4_12M_clk_div.hw,
+		[CLKID_12_24M_CLK_SEL]		= &s4_12_24M_clk.hw,
+
+		[CLKID_VID_PLL_DIV]		= &s4_vid_pll_div.hw,
+		[CLKID_VID_PLL_SEL]		= &s4_vid_pll_sel.hw,
+		[CLKID_VID_PLL]			= &s4_vid_pll.hw,
+		[CLKID_VCLK_SEL]		= &s4_vclk_sel.hw,
+		[CLKID_VCLK2_SEL]		= &s4_vclk2_sel.hw,
+		[CLKID_VCLK_INPUT]		= &s4_vclk_input.hw,
+		[CLKID_VCLK2_INPUT]		= &s4_vclk2_input.hw,
+		[CLKID_VCLK_DIV]		= &s4_vclk_div.hw,
+		[CLKID_VCLK2_DIV]		= &s4_vclk2_div.hw,
+		[CLKID_VCLK]			= &s4_vclk.hw,
+		[CLKID_VCLK2]			= &s4_vclk2.hw,
+		[CLKID_VCLK_DIV1]		= &s4_vclk_div1.hw,
+		[CLKID_VCLK_DIV2_EN]		= &s4_vclk_div2_en.hw,
+		[CLKID_VCLK_DIV4_EN]		= &s4_vclk_div4_en.hw,
+		[CLKID_VCLK_DIV6_EN]		= &s4_vclk_div6_en.hw,
+		[CLKID_VCLK_DIV12_EN]		= &s4_vclk_div12_en.hw,
+		[CLKID_VCLK2_DIV1]		= &s4_vclk2_div1.hw,
+		[CLKID_VCLK2_DIV2_EN]		= &s4_vclk2_div2_en.hw,
+		[CLKID_VCLK2_DIV4_EN]		= &s4_vclk2_div4_en.hw,
+		[CLKID_VCLK2_DIV6_EN]		= &s4_vclk2_div6_en.hw,
+		[CLKID_VCLK2_DIV12_EN]		= &s4_vclk2_div12_en.hw,
+		[CLKID_VCLK_DIV2]		= &s4_vclk_div2.hw,
+		[CLKID_VCLK_DIV4]		= &s4_vclk_div4.hw,
+		[CLKID_VCLK_DIV6]		= &s4_vclk_div6.hw,
+		[CLKID_VCLK_DIV12]		= &s4_vclk_div12.hw,
+		[CLKID_VCLK2_DIV2]		= &s4_vclk2_div2.hw,
+		[CLKID_VCLK2_DIV4]		= &s4_vclk2_div4.hw,
+		[CLKID_VCLK2_DIV6]		= &s4_vclk2_div6.hw,
+		[CLKID_VCLK2_DIV12]		= &s4_vclk2_div12.hw,
+		[CLKID_CTS_ENCI_SEL]		= &s4_cts_enci_sel.hw,
+		[CLKID_CTS_ENCP_SEL]		= &s4_cts_encp_sel.hw,
+		[CLKID_CTS_VDAC_SEL]		= &s4_cts_vdac_sel.hw,
+		[CLKID_HDMI_TX_SEL]		= &s4_hdmi_tx_sel.hw,
+		[CLKID_CTS_ENCI]		= &s4_cts_enci.hw,
+		[CLKID_CTS_ENCP]		= &s4_cts_encp.hw,
+		[CLKID_CTS_VDAC]		= &s4_cts_vdac.hw,
+		[CLKID_HDMI_TX]			= &s4_hdmi_tx.hw,
+		[CLKID_HDMI_SEL]		= &s4_hdmi_sel.hw,
+		[CLKID_HDMI_DIV]		= &s4_hdmi_div.hw,
+		[CLKID_HDMI]			= &s4_hdmi.hw,
+
+		[CLKID_TS_CLK_DIV]		= &s4_ts_clk_div.hw,
+		[CLKID_TS_CLK_GATE]		= &s4_ts_clk_gate.hw,
+
+		[CLKID_MALI_0_SEL]		= &s4_mali_0_sel.hw,
+		[CLKID_MALI_0_DIV]		= &s4_mali_0_div.hw,
+		[CLKID_MALI_0]			= &s4_mali_0.hw,
+		[CLKID_MALI_1_SEL]		= &s4_mali_1_sel.hw,
+		[CLKID_MALI_1_DIV]		= &s4_mali_1_div.hw,
+		[CLKID_MALI_1]			= &s4_mali_1.hw,
+		[CLKID_MALI]			= &s4_mali_mux.hw,
+
+		[CLKID_VDEC_P0_SEL]		= &s4_vdec_p0_mux.hw,
+		[CLKID_VDEC_P0_DIV]		= &s4_vdec_p0_div.hw,
+		[CLKID_VDEC_P0]			= &s4_vdec_p0.hw,
+		[CLKID_VDEC_P1_SEL]		= &s4_vdec_p1_mux.hw,
+		[CLKID_VDEC_P1_DIV]		= &s4_vdec_p1_div.hw,
+		[CLKID_VDEC_P1]			= &s4_vdec_p1.hw,
+		[CLKID_VDEC_SEL]		= &s4_vdec_mux.hw,
+
+		[CLKID_HEVCF_P0_SEL]		= &s4_hevcf_p0_mux.hw,
+		[CLKID_HEVCF_P0_DIV]		= &s4_hevcf_p0_div.hw,
+		[CLKID_HEVCF_P0]		= &s4_hevcf_p0.hw,
+		[CLKID_HEVCF_P1_SEL]		= &s4_hevcf_p1_mux.hw,
+		[CLKID_HEVCF_P1_DIV]		= &s4_hevcf_p1_div.hw,
+		[CLKID_HEVCF_P1]		= &s4_hevcf_p1.hw,
+		[CLKID_HEVCF_SEL]		= &s4_hevcf_mux.hw,
+
+		[CLKID_VPU_0_SEL]		= &s4_vpu_0_sel.hw,
+		[CLKID_VPU_0_DIV]		= &s4_vpu_0_div.hw,
+		[CLKID_VPU_0]			= &s4_vpu_0.hw,
+		[CLKID_VPU_1_SEL]		= &s4_vpu_1_sel.hw,
+		[CLKID_VPU_1_DIV]		= &s4_vpu_1_div.hw,
+		[CLKID_VPU_1]			= &s4_vpu_1.hw,
+		[CLKID_VPU]			= &s4_vpu.hw,
+
+		[CLKID_VPU_CLKB_TMP_SEL]	= &s4_vpu_clkb_tmp_mux.hw,
+		[CLKID_VPU_CLKB_TMP_DIV]	= &s4_vpu_clkb_tmp_div.hw,
+		[CLKID_VPU_CLKB_TMP]		= &s4_vpu_clkb_tmp.hw,
+		[CLKID_VPU_CLKB_DIV]		= &s4_vpu_clkb_div.hw,
+		[CLKID_VPU_CLKB]		= &s4_vpu_clkb.hw,
+		[CLKID_VPU_CLKC_P0_SEL]		= &s4_vpu_clkc_p0_mux.hw,
+		[CLKID_VPU_CLKC_P0_DIV]		= &s4_vpu_clkc_p0_div.hw,
+		[CLKID_VPU_CLKC_P0]		= &s4_vpu_clkc_p0.hw,
+		[CLKID_VPU_CLKC_P1_SEL]		= &s4_vpu_clkc_p1_mux.hw,
+		[CLKID_VPU_CLKC_P1_DIV]		= &s4_vpu_clkc_p1_div.hw,
+		[CLKID_VPU_CLKC_P1]		= &s4_vpu_clkc_p1.hw,
+		[CLKID_VPU_CLKC_SEL]		= &s4_vpu_clkc_mux.hw,
+
+		[CLKID_VAPB_0_SEL]		= &s4_vapb_0_sel.hw,
+		[CLKID_VAPB_0_DIV]		= &s4_vapb_0_div.hw,
+		[CLKID_VAPB_0]			= &s4_vapb_0.hw,
+		[CLKID_VAPB_1_SEL]		= &s4_vapb_1_sel.hw,
+		[CLKID_VAPB_1_DIV]		= &s4_vapb_1_div.hw,
+		[CLKID_VAPB_1]			= &s4_vapb_1.hw,
+		[CLKID_VAPB]			= &s4_vapb.hw,
+
+		[CLKID_GE2D]			= &s4_ge2d_gate.hw,
+
+		[CLKID_VDIN_MEAS_SEL]		= &s4_vdin_meas_mux.hw,
+		[CLKID_VDIN_MEAS_DIV]		= &s4_vdin_meas_div.hw,
+		[CLKID_VDIN_MEAS_GATE]		= &s4_vdin_meas_gate.hw,
+
+		[CLKID_SD_EMMC_C_CLK_SEL]	= &s4_sd_emmc_c_clk0_sel.hw,
+		[CLKID_SD_EMMC_C_CLK_DIV]	= &s4_sd_emmc_c_clk0_div.hw,
+		[CLKID_SD_EMMC_C_CLK]		= &s4_sd_emmc_c_clk0.hw,
+
+		[CLKID_SD_EMMC_A_CLK_SEL]	= &s4_sd_emmc_a_clk0_sel.hw,
+		[CLKID_SD_EMMC_A_CLK_DIV]	= &s4_sd_emmc_a_clk0_div.hw,
+		[CLKID_SD_EMMC_A_CLK]		= &s4_sd_emmc_a_clk0.hw,
+		[CLKID_SD_EMMC_B_CLK_SEL]	= &s4_sd_emmc_b_clk0_sel.hw,
+		[CLKID_SD_EMMC_B_CLK_DIV]	= &s4_sd_emmc_b_clk0_div.hw,
+		[CLKID_SD_EMMC_B_CLK]		= &s4_sd_emmc_b_clk0.hw,
+
+		[CLKID_SPICC0_SEL]		= &s4_spicc0_mux.hw,
+		[CLKID_SPICC0_DIV]		= &s4_spicc0_div.hw,
+		[CLKID_SPICC0_GATE]		= &s4_spicc0_gate.hw,
+
+		[CLKID_PWM_A_SEL]		= &s4_pwm_a_mux.hw,
+		[CLKID_PWM_A_DIV]		= &s4_pwm_a_div.hw,
+		[CLKID_PWM_A_GATE]		= &s4_pwm_a_gate.hw,
+		[CLKID_PWM_B_SEL]		= &s4_pwm_b_mux.hw,
+		[CLKID_PWM_B_DIV]		= &s4_pwm_b_div.hw,
+		[CLKID_PWM_B_GATE]		= &s4_pwm_b_gate.hw,
+		[CLKID_PWM_C_SEL]		= &s4_pwm_c_mux.hw,
+		[CLKID_PWM_C_DIV]		= &s4_pwm_c_div.hw,
+		[CLKID_PWM_C_GATE]		= &s4_pwm_c_gate.hw,
+		[CLKID_PWM_D_SEL]		= &s4_pwm_d_mux.hw,
+		[CLKID_PWM_D_DIV]		= &s4_pwm_d_div.hw,
+		[CLKID_PWM_D_GATE]		= &s4_pwm_d_gate.hw,
+		[CLKID_PWM_E_SEL]		= &s4_pwm_e_mux.hw,
+		[CLKID_PWM_E_DIV]		= &s4_pwm_e_div.hw,
+		[CLKID_PWM_E_GATE]		= &s4_pwm_e_gate.hw,
+		[CLKID_PWM_F_SEL]		= &s4_pwm_f_mux.hw,
+		[CLKID_PWM_F_DIV]		= &s4_pwm_f_div.hw,
+		[CLKID_PWM_F_GATE]		= &s4_pwm_f_gate.hw,
+		[CLKID_PWM_G_SEL]		= &s4_pwm_g_mux.hw,
+		[CLKID_PWM_G_DIV]		= &s4_pwm_g_div.hw,
+		[CLKID_PWM_G_GATE]		= &s4_pwm_g_gate.hw,
+		[CLKID_PWM_H_SEL]		= &s4_pwm_h_mux.hw,
+		[CLKID_PWM_H_DIV]		= &s4_pwm_h_div.hw,
+		[CLKID_PWM_H_GATE]		= &s4_pwm_h_gate.hw,
+		[CLKID_PWM_I_SEL]		= &s4_pwm_i_mux.hw,
+		[CLKID_PWM_I_DIV]		= &s4_pwm_i_div.hw,
+		[CLKID_PWM_I_GATE]		= &s4_pwm_i_gate.hw,
+		[CLKID_PWM_J_SEL]		= &s4_pwm_j_mux.hw,
+		[CLKID_PWM_J_DIV]		= &s4_pwm_j_div.hw,
+		[CLKID_PWM_J_GATE]		= &s4_pwm_j_gate.hw,
+
+		[CLKID_SARADC_SEL]		= &s4_saradc_mux.hw,
+		[CLKID_SARADC_DIV]		= &s4_saradc_div.hw,
+		[CLKID_SARADC_GATE]		= &s4_saradc_gate.hw,
+
+		[CLKID_GEN_SEL]			= &s4_gen_clk_sel.hw,
+		[CLKID_GEN_DIV]			= &s4_gen_clk_div.hw,
+		[CLKID_GEN_GATE]		= &s4_gen_clk.hw,
+
+		[CLKID_DDR]			= &s4_ddr.hw,
+		[CLKID_DOS]			= &s4_dos.hw,
+		[CLKID_ETHPHY]			= &s4_ethphy.hw,
+		[CLKID_MALI_GATE]		= &s4_mali.hw,
+		[CLKID_AOCPU]			= &s4_aocpu.hw,
+		[CLKID_AUCPU]			= &s4_aucpu.hw,
+		[CLKID_CEC]			= &s4_cec.hw,
+		[CLKID_SD_EMMC_A]		= &s4_sdemmca.hw,
+		[CLKID_SD_EMMC_B]		= &s4_sdemmcb.hw,
+		[CLKID_NAND]			= &s4_nand.hw,
+		[CLKID_SMARTCARD]		= &s4_smartcard.hw,
+		[CLKID_ACODEC]			= &s4_acodec.hw,
+		[CLKID_SPIFC]			= &s4_spifc.hw,
+		[CLKID_MSR_CLK]			= &s4_msr_clk.hw,
+		[CLKID_IR_CTRL]			= &s4_ir_ctrl.hw,
+
+		[CLKID_AUDIO]			= &s4_audio.hw,
+		[CLKID_ETH]			= &s4_eth.hw,
+		[CLKID_UART_A]			= &s4_uart_a.hw,
+		[CLKID_UART_B]			= &s4_uart_b.hw,
+		[CLKID_UART_C]			= &s4_uart_c.hw,
+		[CLKID_UART_D]			= &s4_uart_d.hw,
+		[CLKID_UART_E]			= &s4_uart_e.hw,
+		[CLKID_AIFIFO]			= &s4_aififo.hw,
+		[CLKID_TS_DDR]			= &s4_ts_ddr.hw,
+		[CLKID_TS_PLL]			= &s4_ts_pll.hw,
+		[CLKID_G2D]			= &s4_g2d.hw,
+		[CLKID_SPICC0]			= &s4_spicc0.hw,
+		[CLKID_USB]			= &s4_usb.hw,
+		[CLKID_I2C_M_A]			= &s4_i2c_m_a.hw,
+		[CLKID_I2C_M_B]			= &s4_i2c_m_b.hw,
+		[CLKID_I2C_M_C]			= &s4_i2c_m_c.hw,
+		[CLKID_I2C_M_D]			= &s4_i2c_m_d.hw,
+		[CLKID_I2C_M_E]			= &s4_i2c_m_e.hw,
+		[CLKID_HDMITX_APB]		= &s4_hdmitx_apb.hw,
+		[CLKID_I2C_S_A]			= &s4_i2c_s_a.hw,
+		[CLKID_USB1_TO_DDR]		= &s4_usb1_to_ddr.hw,
+		[CLKID_HDCP22]			= &s4_hdcp22.hw,
+		[CLKID_MMC_APB]			= &s4_mmc_apb.hw,
+		[CLKID_RSA]			= &s4_rsa.hw,
+		[CLKID_CPU_DEBUG]		= &s4_cpu_debug.hw,
+		[CLKID_VPU_INTR]		= &s4_vpu_intr.hw,
+		[CLKID_DEMOD]			= &s4_demod.hw,
+		[CLKID_SAR_ADC]			= &s4_sar_adc.hw,
+		[CLKID_GIC]			= &s4_gic.hw,
+		[CLKID_PWM_AB]			= &s4_pwm_ab.hw,
+		[CLKID_PWM_CD]			= &s4_pwm_cd.hw,
+		[CLKID_PWM_EF]			= &s4_pwm_ef.hw,
+		[CLKID_PWM_GH]			= &s4_pwm_gh.hw,
+		[CLKID_PWM_IJ]			= &s4_pwm_ij.hw,
+
+		[CLKID_HDCP22_ESMCLK_SEL]	= &s4_hdcp22_esmclk_mux.hw,
+		[CLKID_HDCP22_ESMCLK_DIV]	= &s4_hdcp22_esmclk_div.hw,
+		[CLKID_HDCP22_ESMCLK_GATE]	= &s4_hdcp22_esmclk_gate.hw,
+		[CLKID_HDCP22_SKPCLK_SEL]	= &s4_hdcp22_skpclk_mux.hw,
+		[CLKID_HDCP22_SKPCLK_DIV]	= &s4_hdcp22_skpclk_div.hw,
+		[CLKID_HDCP22_SKPCLK_GATE]	= &s4_hdcp22_skpclk_gate.hw,
+
+		[NR_CLKS]			= NULL
+	},
+	.num = NR_CLKS,
+};
+
+/* Convenience table to populate regmap in .probe */
+static struct clk_regmap *const s4_clk_regmaps[] = {
+	&s4_rtc_32k_by_oscin_clkin,
+	&s4_rtc_32k_by_oscin_div,
+	&s4_rtc_32k_by_oscin_sel,
+	&s4_rtc_32k_by_oscin,
+	&s4_rtc_clk,
+
+	&s4_sysclk_b_sel,
+	&s4_sysclk_b_div,
+	&s4_sysclk_b,
+	&s4_sysclk_a_sel,
+	&s4_sysclk_a_div,
+	&s4_sysclk_a,
+	&s4_sys_clk,
+
+	&s4_ceca_32k_clkin,
+	&s4_ceca_32k_div,
+	&s4_ceca_32k_sel_pre,
+	&s4_ceca_32k_sel,
+	&s4_ceca_32k_clkout,
+	&s4_cecb_32k_clkin,
+	&s4_cecb_32k_div,
+	&s4_cecb_32k_sel_pre,
+	&s4_cecb_32k_sel,
+	&s4_cecb_32k_clkout,
+
+	&s4_sc_clk_mux,
+	&s4_sc_clk_div,
+	&s4_sc_clk_gate,
+
+	&s4_12_24M_clk_gate,
+	&s4_12_24M_clk,
+	&s4_vid_pll_div,
+	&s4_vid_pll_sel,
+	&s4_vid_pll,
+	&s4_vclk_sel,
+	&s4_vclk2_sel,
+	&s4_vclk_input,
+	&s4_vclk2_input,
+	&s4_vclk_div,
+	&s4_vclk2_div,
+	&s4_vclk,
+	&s4_vclk2,
+	&s4_vclk_div1,
+	&s4_vclk_div2_en,
+	&s4_vclk_div4_en,
+	&s4_vclk_div6_en,
+	&s4_vclk_div12_en,
+	&s4_vclk2_div1,
+	&s4_vclk2_div2_en,
+	&s4_vclk2_div4_en,
+	&s4_vclk2_div6_en,
+	&s4_vclk2_div12_en,
+	&s4_cts_enci_sel,
+	&s4_cts_encp_sel,
+	&s4_cts_vdac_sel,
+	&s4_hdmi_tx_sel,
+	&s4_cts_enci,
+	&s4_cts_encp,
+	&s4_cts_vdac,
+	&s4_hdmi_tx,
+
+	&s4_hdmi_sel,
+	&s4_hdmi_div,
+	&s4_hdmi,
+	&s4_ts_clk_div,
+	&s4_ts_clk_gate,
+
+	&s4_mali_0_sel,
+	&s4_mali_0_div,
+	&s4_mali_0,
+	&s4_mali_1_sel,
+	&s4_mali_1_div,
+	&s4_mali_1,
+	&s4_mali_mux,
+
+	&s4_vdec_p0_mux,
+	&s4_vdec_p0_div,
+	&s4_vdec_p0,
+	&s4_vdec_p1_mux,
+	&s4_vdec_p1_div,
+	&s4_vdec_p1,
+	&s4_vdec_mux,
+
+	&s4_hevcf_p0_mux,
+	&s4_hevcf_p0_div,
+	&s4_hevcf_p0,
+	&s4_hevcf_p1_mux,
+	&s4_hevcf_p1_div,
+	&s4_hevcf_p1,
+	&s4_hevcf_mux,
+
+	&s4_vpu_0_sel,
+	&s4_vpu_0_div,
+	&s4_vpu_0,
+	&s4_vpu_1_sel,
+	&s4_vpu_1_div,
+	&s4_vpu_1,
+	&s4_vpu,
+	&s4_vpu_clkb_tmp_mux,
+	&s4_vpu_clkb_tmp_div,
+	&s4_vpu_clkb_tmp,
+	&s4_vpu_clkb_div,
+	&s4_vpu_clkb,
+	&s4_vpu_clkc_p0_mux,
+	&s4_vpu_clkc_p0_div,
+	&s4_vpu_clkc_p0,
+	&s4_vpu_clkc_p1_mux,
+	&s4_vpu_clkc_p1_div,
+	&s4_vpu_clkc_p1,
+	&s4_vpu_clkc_mux,
+
+	&s4_vapb_0_sel,
+	&s4_vapb_0_div,
+	&s4_vapb_0,
+	&s4_vapb_1_sel,
+	&s4_vapb_1_div,
+	&s4_vapb_1,
+	&s4_vapb,
+	&s4_ge2d_gate,
+
+	&s4_hdcp22_esmclk_mux,
+	&s4_hdcp22_esmclk_div,
+	&s4_hdcp22_esmclk_gate,
+	&s4_hdcp22_skpclk_mux,
+	&s4_hdcp22_skpclk_div,
+	&s4_hdcp22_skpclk_gate,
+
+	&s4_vdin_meas_mux,
+	&s4_vdin_meas_div,
+	&s4_vdin_meas_gate,
+
+	&s4_sd_emmc_c_clk0_sel,
+	&s4_sd_emmc_c_clk0_div,
+	&s4_sd_emmc_c_clk0,
+	&s4_sd_emmc_a_clk0_sel,
+	&s4_sd_emmc_a_clk0_div,
+	&s4_sd_emmc_a_clk0,
+	&s4_sd_emmc_b_clk0_sel,
+	&s4_sd_emmc_b_clk0_div,
+	&s4_sd_emmc_b_clk0,
+
+	&s4_spicc0_mux,
+	&s4_spicc0_div,
+	&s4_spicc0_gate,
+
+	&s4_pwm_a_mux,
+	&s4_pwm_a_div,
+	&s4_pwm_a_gate,
+	&s4_pwm_b_mux,
+	&s4_pwm_b_div,
+	&s4_pwm_b_gate,
+	&s4_pwm_c_mux,
+	&s4_pwm_c_div,
+	&s4_pwm_c_gate,
+	&s4_pwm_d_mux,
+	&s4_pwm_d_div,
+	&s4_pwm_d_gate,
+	&s4_pwm_e_mux,
+	&s4_pwm_e_div,
+	&s4_pwm_e_gate,
+	&s4_pwm_f_mux,
+	&s4_pwm_f_div,
+	&s4_pwm_f_gate,
+	&s4_pwm_g_mux,
+	&s4_pwm_g_div,
+	&s4_pwm_g_gate,
+	&s4_pwm_h_mux,
+	&s4_pwm_h_div,
+	&s4_pwm_h_gate,
+	&s4_pwm_i_mux,
+	&s4_pwm_i_div,
+	&s4_pwm_i_gate,
+	&s4_pwm_j_mux,
+	&s4_pwm_j_div,
+	&s4_pwm_j_gate,
+
+	&s4_saradc_mux,
+	&s4_saradc_div,
+	&s4_saradc_gate,
+
+	&s4_gen_clk_sel,
+	&s4_gen_clk_div,
+	&s4_gen_clk,
+
+	&s4_ddr,
+	&s4_dos,
+	&s4_ethphy,
+	&s4_mali,
+	&s4_aocpu,
+	&s4_aucpu,
+	&s4_cec,
+	&s4_sdemmca,
+	&s4_sdemmcb,
+	&s4_nand,
+	&s4_smartcard,
+	&s4_acodec,
+	&s4_spifc,
+	&s4_msr_clk,
+	&s4_ir_ctrl,
+	&s4_audio,
+	&s4_eth,
+	&s4_uart_a,
+	&s4_uart_b,
+	&s4_uart_c,
+	&s4_uart_d,
+	&s4_uart_e,
+	&s4_aififo,
+	&s4_ts_ddr,
+	&s4_ts_pll,
+	&s4_g2d,
+	&s4_spicc0,
+	&s4_usb,
+	&s4_i2c_m_a,
+	&s4_i2c_m_b,
+	&s4_i2c_m_c,
+	&s4_i2c_m_d,
+	&s4_i2c_m_e,
+	&s4_hdmitx_apb,
+	&s4_i2c_s_a,
+	&s4_usb1_to_ddr,
+	&s4_hdcp22,
+	&s4_mmc_apb,
+	&s4_rsa,
+	&s4_cpu_debug,
+	&s4_vpu_intr,
+	&s4_demod,
+	&s4_sar_adc,
+	&s4_gic,
+	&s4_pwm_ab,
+	&s4_pwm_cd,
+	&s4_pwm_ef,
+	&s4_pwm_gh,
+	&s4_pwm_ij,
+	&s4_demod_core_clk_mux,
+	&s4_demod_core_clk_div,
+	&s4_demod_core_clk_gate,
+	&s4_adc_extclk_in_mux,
+	&s4_adc_extclk_in_div,
+	&s4_adc_extclk_in_gate,
+};
+
+static struct clk_regmap *const s4_pll_clk_regmaps[] = {
+	&s4_fixed_pll_dco,
+	&s4_fixed_pll,
+	&s4_fclk_div2,
+	&s4_fclk_div3,
+	&s4_fclk_div4,
+	&s4_fclk_div5,
+	&s4_fclk_div7,
+	&s4_fclk_div2p5,
+	&s4_gp0_pll_dco,
+	&s4_gp0_pll,
+	&s4_hifi_pll_dco,
+	&s4_hifi_pll,
+	&s4_hdmi_pll_dco,
+	&s4_hdmi_pll_od,
+	&s4_hdmi_pll,
+	&s4_mpll_50m,
+	&s4_mpll0_div,
+	&s4_mpll0,
+	&s4_mpll1_div,
+	&s4_mpll1,
+	&s4_mpll2_div,
+	&s4_mpll2,
+	&s4_mpll3_div,
+	&s4_mpll3,
+};
+
+static const struct reg_sequence s4_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL0,	.def = 0x00000543 },
+};
+
+static struct regmap_config clkc_regmap_config = {
+	.reg_bits       = 32,
+	.val_bits       = 32,
+	.reg_stride     = 4,
+};
+
+static struct regmap *s4_regmap_resource(struct device *dev, char *name)
+{
+	struct resource res;
+	void __iomem *base;
+	int i;
+	struct device_node *node = dev->of_node;
+
+	i = of_property_match_string(node, "reg-names", name);
+	if (of_address_to_resource(node, i, &res))
+		return ERR_PTR(-ENOENT);
+
+	base = devm_ioremap_resource(dev, &res);
+	if (IS_ERR(base))
+		return ERR_CAST(base);
+
+	clkc_regmap_config.max_register = resource_size(&res) - 4;
+	clkc_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL,
+						 "%s-%s", node->name,
+						 name);
+	if (!clkc_regmap_config.name)
+		return ERR_PTR(-ENOMEM);
+
+	return devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
+}
+
+static int meson_s4_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct regmap *basic_map;
+	struct regmap *pll_map;
+	const struct clk_hw_onecell_data *hw_onecell_data;
+	int ret, i;
+
+	hw_onecell_data = of_device_get_match_data(&pdev->dev);
+	if (!hw_onecell_data)
+		return -EINVAL;
+
+	/* Get regmap for different clock area */
+	basic_map = s4_regmap_resource(dev, "basic");
+	if (IS_ERR(basic_map)) {
+		dev_err(dev, "basic clk registers not found\n");
+		return PTR_ERR(basic_map);
+	}
+
+	pll_map = s4_regmap_resource(dev, "pll");
+	if (IS_ERR(pll_map)) {
+		dev_err(dev, "pll clk registers not found\n");
+		return PTR_ERR(pll_map);
+	}
+
+	ret = regmap_multi_reg_write(pll_map, s4_init_regs, ARRAY_SIZE(s4_init_regs));
+	if (ret) {
+		dev_err(dev, "Failed to init registers\n");
+		return ret;
+	}
+
+	/* Populate regmap for the regmap backed clocks */
+	for (i = 0; i < ARRAY_SIZE(s4_clk_regmaps); i++)
+		s4_clk_regmaps[i]->map = basic_map;
+
+	for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
+		s4_pll_clk_regmaps[i]->map = pll_map;
+
+	for (i = 0; i < hw_onecell_data->num; i++) {
+		/* array might be sparse */
+		if (!hw_onecell_data->hws[i])
+			continue;
+		ret = devm_clk_hw_register(dev, hw_onecell_data->hws[i]);
+		if (ret) {
+			dev_err(dev, "Clock registration failed\n");
+			return ret;
+		}
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+					   (void *)hw_onecell_data);
+}
+
+static const struct of_device_id clkc_match_table[] = {
+	{
+		.compatible = "amlogic,s4-clkc",
+		.data = &s4_hw_onecell_data
+	},
+	{}
+};
+
+static struct platform_driver s4_driver = {
+	.probe		= meson_s4_probe,
+	.driver		= {
+		.name	= "s4-clkc",
+		.of_match_table = clkc_match_table,
+	},
+};
+
+module_platform_driver(s4_driver);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/meson/s4.h b/drivers/clk/meson/s4.h
new file mode 100644
index 000000000000..be11316ba244
--- /dev/null
+++ b/drivers/clk/meson/s4.h
@@ -0,0 +1,296 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, inc.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef __MESON_S4_H__
+#define __MESON_S4_H__
+
+/*
+ * Clock controller register offsets
+ * REG_BASE:  REGISTER_BASE_ADDR = 0xfe000000
+ */
+#define CLKCTRL_OSCIN_CTRL                         (0x0001 << 2)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL0                 (0x0002 << 2)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL1                 (0x0003 << 2)
+#define CLKCTRL_RTC_CTRL                           (0x0004 << 2)
+#define CLKCTRL_CHECK_CLK_RESULT                   (0x0005 << 2)
+#define CLKCTRL_MBIST_ATSPEED_CTRL                 (0x0006 << 2)
+#define CLKCTRL_LOCK_BIT_REG0                      (0x0008 << 2)
+#define CLKCTRL_LOCK_BIT_REG1                      (0x0009 << 2)
+#define CLKCTRL_LOCK_BIT_REG2                      (0x000a << 2)
+#define CLKCTRL_LOCK_BIT_REG3                      (0x000b << 2)
+#define CLKCTRL_PROT_BIT_REG0                      (0x000c << 2)
+#define CLKCTRL_PROT_BIT_REG1                      (0x000d << 2)
+#define CLKCTRL_PROT_BIT_REG2                      (0x000e << 2)
+#define CLKCTRL_PROT_BIT_REG3                      (0x000f << 2)
+#define CLKCTRL_SYS_CLK_CTRL0                      (0x0010 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG0                   (0x0011 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG1                   (0x0012 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG2                   (0x0013 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG3                   (0x0014 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG0                   (0x0015 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG1                   (0x0016 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG2                   (0x0017 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG3                   (0x0018 << 2)
+#define CLKCTRL_SYS_CLK_VPU_EN0                    (0x0019 << 2)
+#define CLKCTRL_SYS_CLK_VPU_EN1                    (0x001a << 2)
+#define CLKCTRL_AXI_CLK_CTRL0                      (0x001b << 2)
+#define CLKCTRL_TST_CTRL0                          (0x0020 << 2)
+#define CLKCTRL_TST_CTRL1                          (0x0021 << 2)
+#define CLKCTRL_CECA_CTRL0                         (0x0022 << 2)
+#define CLKCTRL_CECA_CTRL1                         (0x0023 << 2)
+#define CLKCTRL_CECB_CTRL0                         (0x0024 << 2)
+#define CLKCTRL_CECB_CTRL1                         (0x0025 << 2)
+#define CLKCTRL_SC_CLK_CTRL                        (0x0026 << 2)
+#define CLKCTRL_DSPA_CLK_CTRL0                     (0x0027 << 2)
+#define CLKCTRL_DSPB_CLK_CTRL0                     (0x0028 << 2)
+#define CLKCTRL_RAMA_CLK_CTRL0                     (0x0029 << 2)
+#define CLKCTRL_CLK12_24_CTRL                      (0x002a << 2)
+#define CLKCTRL_VID_CLK_CTRL                       (0x0030 << 2)
+#define CLKCTRL_VID_CLK_CTRL2                      (0x0031 << 2)
+#define CLKCTRL_VID_CLK_DIV                        (0x0032 << 2)
+#define CLKCTRL_VIID_CLK_DIV                       (0x0033 << 2)
+#define CLKCTRL_VIID_CLK_CTRL                      (0x0034 << 2)
+#define CLKCTRL_HDMI_CLK_CTRL                      (0x0038 << 2)
+#define CLKCTRL_VID_PLL_CLK_DIV                    (0x0039 << 2)
+#define CLKCTRL_VPU_CLK_CTRL                       (0x003a << 2)
+#define CLKCTRL_VPU_CLKB_CTRL                      (0x003b << 2)
+#define CLKCTRL_VPU_CLKC_CTRL                      (0x003c << 2)
+#define CLKCTRL_VID_LOCK_CLK_CTRL                  (0x003d << 2)
+#define CLKCTRL_VDIN_MEAS_CLK_CTRL                 (0x003e << 2)
+#define CLKCTRL_VAPBCLK_CTRL                       (0x003f << 2)
+#define CLKCTRL_HDCP22_CTRL                        (0x0040 << 2)
+#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL               (0x0041 << 2)
+#define CLKCTRL_CDAC_CLK_CTRL                      (0x0042 << 2)
+#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL              (0x0043 << 2)
+#define CLKCTRL_CSI2_ADAPT_CLK_CTRL                (0x0044 << 2)
+#define CLKCTRL_VDEC_CLK_CTRL                      (0x0050 << 2)
+#define CLKCTRL_VDEC2_CLK_CTRL                     (0x0051 << 2)
+#define CLKCTRL_VDEC3_CLK_CTRL                     (0x0052 << 2)
+#define CLKCTRL_VDEC4_CLK_CTRL                     (0x0053 << 2)
+#define CLKCTRL_WAVE420L_CLK_CTRL                  (0x0054 << 2)
+#define CLKCTRL_WAVE420L_CLK_CTRL2                 (0x0055 << 2)
+#define CLKCTRL_TS_CLK_CTRL                        (0x0056 << 2)
+#define CLKCTRL_MALI_CLK_CTRL                      (0x0057 << 2)
+#define CLKCTRL_VIPNANOQ_CLK_CTRL                  (0x0058 << 2)
+#define CLKCTRL_ETH_CLK_CTRL                       (0x0059 << 2)
+#define CLKCTRL_NAND_CLK_CTRL                      (0x005a << 2)
+#define CLKCTRL_SD_EMMC_CLK_CTRL                   (0x005b << 2)
+#define CLKCTRL_BT656_CLK_CTRL                     (0x005c << 2)
+#define CLKCTRL_SPICC_CLK_CTRL                     (0x005d << 2)
+#define CLKCTRL_GEN_CLK_CTRL                       (0x005e << 2)
+#define CLKCTRL_SAR_CLK_CTRL                       (0x005f << 2)
+#define CLKCTRL_PWM_CLK_AB_CTRL                    (0x0060 << 2)
+#define CLKCTRL_PWM_CLK_CD_CTRL                    (0x0061 << 2)
+#define CLKCTRL_PWM_CLK_EF_CTRL                    (0x0062 << 2)
+#define CLKCTRL_PWM_CLK_GH_CTRL                    (0x0063 << 2)
+#define CLKCTRL_PWM_CLK_IJ_CTRL                    (0x0064 << 2)
+#define CLKCTRL_DEMOD_CLK_CTRL                     (0x0080 << 2)
+#define CLKCTRL_DEMOD_CLK_CTRL1                    (0x0081 << 2)
+#define CLKCTRL_DEMOD_32K_CTRL0                    (0x0082 << 2)
+#define CLKCTRL_DEMOD_32K_CTRL1                    (0x0083 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL                     (0x0100 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL1                    (0x0101 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL2                    (0x0103 << 2)
+#define CLKCTRL_TIMESTAMP_RD0                      (0x0104 << 2)
+#define CLKCTRL_TIMESTAMP_RD1                      (0x0105 << 2)
+#define CLKCTRL_TIMEBASE_CTRL0                     (0x0106 << 2)
+#define CLKCTRL_TIMEBASE_CTRL1                     (0x0107 << 2)
+#define CLKCTRL_EFUSE_CPU_CFG01                    (0x0120 << 2)
+#define CLKCTRL_EFUSE_CPU_CFG2                     (0x0121 << 2)
+#define CLKCTRL_EFUSE_ENCP_CFG0                    (0x0122 << 2)
+#define CLKCTRL_EFUSE_MALI_CFG01                   (0x0123 << 2)
+#define CLKCTRL_EFUSE_HEVCB_CFG01                  (0x0124 << 2)
+#define CLKCTRL_EFUSE_HEVCB_CFG2                   (0x0125 << 2)
+#define CLKCTRL_EFUSE_LOCK                         (0x0126 << 2)
+
+/* ANA_CTRL - Registers
+ * REG_BASE:  REGISTER_BASE_ADDR = 0xfe008000
+ */
+#define ANACTRL_FIXPLL_CTRL0                       (0x0010 << 2)
+#define ANACTRL_FIXPLL_CTRL1                       (0x0011 << 2)
+#define ANACTRL_FIXPLL_CTRL2                       (0x0012 << 2)
+#define ANACTRL_FIXPLL_CTRL3                       (0x0013 << 2)
+#define ANACTRL_FIXPLL_CTRL4                       (0x0014 << 2)
+#define ANACTRL_FIXPLL_CTRL5                       (0x0015 << 2)
+#define ANACTRL_FIXPLL_CTRL6                       (0x0016 << 2)
+#define ANACTRL_FIXPLL_STS                         (0x0017 << 2)
+#define ANACTRL_GP0PLL_CTRL0                       (0x0020 << 2)
+#define ANACTRL_GP0PLL_CTRL1                       (0x0021 << 2)
+#define ANACTRL_GP0PLL_CTRL2                       (0x0022 << 2)
+#define ANACTRL_GP0PLL_CTRL3                       (0x0023 << 2)
+#define ANACTRL_GP0PLL_CTRL4                       (0x0024 << 2)
+#define ANACTRL_GP0PLL_CTRL5                       (0x0025 << 2)
+#define ANACTRL_GP0PLL_CTRL6                       (0x0026 << 2)
+#define ANACTRL_GP0PLL_STS                         (0x0027 << 2)
+#define ANACTRL_HIFIPLL_CTRL0                      (0x0040 << 2)
+#define ANACTRL_HIFIPLL_CTRL1                      (0x0041 << 2)
+#define ANACTRL_HIFIPLL_CTRL2                      (0x0042 << 2)
+#define ANACTRL_HIFIPLL_CTRL3                      (0x0043 << 2)
+#define ANACTRL_HIFIPLL_CTRL4                      (0x0044 << 2)
+#define ANACTRL_HIFIPLL_CTRL5                      (0x0045 << 2)
+#define ANACTRL_HIFIPLL_CTRL6                      (0x0046 << 2)
+#define ANACTRL_HIFIPLL_STS                        (0x0047 << 2)
+#define ANACTRL_MPLL_CTRL0                         (0x0060 << 2)
+#define ANACTRL_MPLL_CTRL1                         (0x0061 << 2)
+#define ANACTRL_MPLL_CTRL2                         (0x0062 << 2)
+#define ANACTRL_MPLL_CTRL3                         (0x0063 << 2)
+#define ANACTRL_MPLL_CTRL4                         (0x0064 << 2)
+#define ANACTRL_MPLL_CTRL5                         (0x0065 << 2)
+#define ANACTRL_MPLL_CTRL6                         (0x0066 << 2)
+#define ANACTRL_MPLL_CTRL7                         (0x0067 << 2)
+#define ANACTRL_MPLL_CTRL8                         (0x0068 << 2)
+#define ANACTRL_MPLL_STS                           (0x0069 << 2)
+#define ANACTRL_HDMIPLL_CTRL0                      (0x0070 << 2)
+#define ANACTRL_HDMIPLL_CTRL1                      (0x0071 << 2)
+#define ANACTRL_HDMIPLL_CTRL2                      (0x0072 << 2)
+#define ANACTRL_HDMIPLL_CTRL3                      (0x0073 << 2)
+#define ANACTRL_HDMIPLL_CTRL4                      (0x0074 << 2)
+#define ANACTRL_HDMIPLL_CTRL5                      (0x0075 << 2)
+#define ANACTRL_HDMIPLL_CTRL6                      (0x0076 << 2)
+#define ANACTRL_HDMIPLL_STS                        (0x0077 << 2)
+#define ANACTRL_HDMIPLL_VLOCK                      (0x0079 << 2)
+
+/*
+ * CLKID index values
+ *
+ * These indices are entirely contrived and do not map onto the hardware.
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
+ * to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
+ */
+#define CLKID_FIXED_PLL_DCO		0
+#define CLKID_FCLK_DIV2_DIV		2
+#define CLKID_FCLK_DIV3_DIV		4
+#define CLKID_FCLK_DIV4_DIV		6
+#define CLKID_FCLK_DIV5_DIV		8
+#define CLKID_FCLK_DIV7_DIV		10
+#define CLKID_FCLK_DIV2P5_DIV		12
+#define CLKID_GP0_PLL_DCO		14
+#define CLKID_HIFI_PLL_DCO		16
+#define CLKID_HDMI_PLL_DCO		18
+#define CLKID_HDMI_PLL_OD		19
+#define CLKID_MPLL_50M_DIV		21
+#define CLKID_MPLL_PREDIV		23
+#define CLKID_MPLL0_DIV			24
+#define CLKID_MPLL1_DIV			26
+#define CLKID_MPLL2_DIV			28
+#define CLKID_MPLL3_DIV			30
+#define CLKID_RTC_32K_CLKIN		32
+#define CLKID_RTC_32K_DIV		33
+#define CLKID_RTC_32K_SEL		34
+#define CLKID_RTC_32K_XATL		35
+#define CLKID_SYS_CLK_B_SEL		37
+#define CLKID_SYS_CLK_B_DIV		38
+#define CLKID_SYS_CLK_A_SEL		40
+#define CLKID_SYS_CLK_A_DIV		41
+#define CLKID_CECA_32K_CLKIN		44
+#define CLKID_CECA_32K_DIV		45
+#define CLKID_CECA_32K_SEL_PRE		46
+#define CLKID_CECA_32K_SEL		47
+#define CLKID_CECB_32K_CLKIN		49
+#define CLKID_CECB_32K_DIV		50
+#define CLKID_CECB_32K_SEL_PRE		51
+#define CLKID_CECB_32K_SEL		52
+#define CLKID_SC_CLK_SEL		54
+#define CLKID_SC_CLK_DIV		55
+#define CLKID_12_24M_CLK_GATE		57
+#define CLKID_12M_CLK_DIV		58
+#define CLKID_VID_PLL_DIV		60
+#define CLKID_VID_PLL_SEL		61
+#define CLKID_VCLK_SEL			63
+#define CLKID_VCLK2_SEL			64
+#define CLKID_VCLK_INPUT		65
+#define CLKID_VCLK2_INPUT		66
+#define CLKID_VCLK_DIV			67
+#define CLKID_VCLK2_DIV			68
+#define CLKID_VCLK_DIV2_EN		72
+#define CLKID_VCLK_DIV4_EN		73
+#define CLKID_VCLK_DIV6_EN		74
+#define CLKID_VCLK_DIV12_EN		75
+#define CLKID_VCLK2_DIV2_EN		77
+#define CLKID_VCLK2_DIV4_EN		78
+#define CLKID_VCLK2_DIV6_EN		79
+#define CLKID_VCLK2_DIV12_EN		80
+#define CLKID_CTS_ENCI_SEL		89
+#define CLKID_CTS_ENCP_SEL		90
+#define CLKID_CTS_VDAC_SEL		91
+#define CLKID_HDMI_TX_SEL		92
+#define CLKID_HDMI_TX			96
+#define CLKID_HDMI_SEL			97
+#define CLKID_HDMI_DIV			98
+#define CLKID_TS_CLK_DIV		100
+#define CLKID_MALI_0_SEL		102
+#define CLKID_MALI_0_DIV		103
+#define CLKID_MALI_1_SEL		105
+#define CLKID_MALI_1_DIV		106
+#define CLKID_VDEC_P0_SEL		109
+#define CLKID_VDEC_P0_DIV		110
+#define CLKID_VDEC_P1_SEL		112
+#define CLKID_VDEC_P1_DIV		113
+#define CLKID_HEVCF_P0_SEL		116
+#define CLKID_HEVCF_P0_DIV		117
+#define CLKID_HEVCF_P1_SEL		119
+#define CLKID_HEVCF_P1_DIV		120
+#define CLKID_VPU_0_SEL			123
+#define CLKID_VPU_0_DIV			124
+#define CLKID_VPU_1_SEL			126
+#define CLKID_VPU_1_DIV			127
+#define CLKID_VPU_CLKB_TMP_SEL		130
+#define CLKID_VPU_CLKB_TMP_DIV		131
+#define CLKID_VPU_CLKB_DIV		133
+#define CLKID_VPU_CLKC_P0_SEL		135
+#define CLKID_VPU_CLKC_P0_DIV		136
+#define CLKID_VPU_CLKC_P1_SEL		138
+#define CLKID_VPU_CLKC_P1_DIV		139
+#define CLKID_VAPB_0_SEL		142
+#define CLKID_VAPB_0_DIV		143
+#define CLKID_VAPB_1_SEL		145
+#define CLKID_VAPB_1_DIV		146
+#define CLKID_VDIN_MEAS_SEL		150
+#define CLKID_VDIN_MEAS_DIV		151
+#define CLKID_SD_EMMC_C_CLK_SEL		153
+#define CLKID_SD_EMMC_C_CLK_DIV		154
+#define CLKID_SD_EMMC_A_CLK_SEL		156
+#define CLKID_SD_EMMC_A_CLK_DIV		157
+#define CLKID_SD_EMMC_B_CLK_SEL		159
+#define CLKID_SD_EMMC_B_CLK_DIV		160
+#define CLKID_SPICC0_SEL		162
+#define CLKID_SPICC0_DIV		163
+#define CLKID_PWM_A_SEL			165
+#define CLKID_PWM_A_DIV			166
+#define CLKID_PWM_B_SEL			168
+#define CLKID_PWM_B_DIV			169
+#define CLKID_PWM_C_SEL			171
+#define CLKID_PWM_C_DIV			172
+#define CLKID_PWM_D_SEL			174
+#define CLKID_PWM_D_DIV			175
+#define CLKID_PWM_E_SEL			177
+#define CLKID_PWM_E_DIV			178
+#define CLKID_PWM_F_SEL			180
+#define CLKID_PWM_F_DIV			181
+#define CLKID_PWM_G_SEL			183
+#define CLKID_PWM_G_DIV			184
+#define CLKID_PWM_H_SEL			186
+#define CLKID_PWM_H_DIV			187
+#define CLKID_PWM_I_SEL			189
+#define CLKID_PWM_I_DIV			190
+#define CLKID_PWM_J_SEL			192
+#define CLKID_PWM_J_DIV			193
+#define CLKID_SARADC_SEL		195
+#define CLKID_SARADC_DIV		196
+#define CLKID_GEN_SEL			198
+#define CLKID_GEN_DIV			199
+#define CLKID_HDCP22_ESMCLK_SEL		251
+#define CLKID_HDCP22_ESMCLK_DIV		252
+#define CLKID_HDCP22_SKPCLK_SEL		254
+#define CLKID_HDCP22_SKPCLK_DIV		255
+
+#define NR_CLKS				257
+/* include the CLKIDs that have been made part of the DT binding */
+#include <dt-bindings/clock/s4-clkc.h>
+
+#endif /* __MESON_S4_H__ */
-- 
2.33.1

[PATCH V2 3/3] clk: meson: s4: add s4 SoC clock controller driver

[Yu Tu]

Add the peripheral clock controller found in the s4 SoC family.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 drivers/clk/meson/Kconfig  |   15 +
 drivers/clk/meson/Makefile |    1 +
 drivers/clk/meson/s4.c     | 4732 ++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/s4.h     |  296 +++
 4 files changed, 5044 insertions(+)
 create mode 100644 drivers/clk/meson/s4.c
 create mode 100644 drivers/clk/meson/s4.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index fc002c155bc3..a3b630db991c 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -115,4 +115,19 @@ config COMMON_CLK_G12A
 	help
 	  Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
 	  devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_S4
+	tristate "S4 SoC clock controllers support"
+	depends on ARM64
+	default y
+	select COMMON_CLK_MESON_REGMAP
+	select COMMON_CLK_MESON_DUALDIV
+	select COMMON_CLK_MESON_MPLL
+	select COMMON_CLK_MESON_PLL
+	select COMMON_CLK_MESON_VID_PLL_DIV
+	select MFD_SYSCON
+	help
+	  Support for the clock controller on Amlogic S805X2 and S905Y4 devices,
+	  aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
+	  Say Y if you want peripherals and CPU frequency scaling to work.
 endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 6eca2a406ee3..b3ef5f67820f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
 obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
 obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
+obj-$(CONFIG_COMMON_CLK_S4) += s4.o
diff --git a/drivers/clk/meson/s4.c b/drivers/clk/meson/s4.c
new file mode 100644
index 000000000000..03dc603ab023
--- /dev/null
+++ b/drivers/clk/meson/s4.c
@@ -0,0 +1,4732 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-S4 Clock Controller Driver
+ *
+ * Copyright (c) 2021 Amlogic, inc.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "s4.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap s4_fixed_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_FIXPLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_FIXPLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fixed_pll_dco",
+		.ops = &meson_clk_pll_ro_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fixed_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_FIXPLL_CTRL0,
+		.shift = 16,
+		.width = 2,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fixed_pll",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll_dco.hw
+		},
+		.num_parents = 1,
+		/*
+		 * This clock won't ever change at runtime so
+		 * CLK_SET_RATE_PARENT is not required
+		 */
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div2_div = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div2 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div2_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div3_div = {
+	.mult = 1,
+	.div = 3,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div3_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div3 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 20,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div3",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div3_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div4_div = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div4_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div4 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 21,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div4",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div4_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div5_div = {
+	.mult = 1,
+	.div = 5,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div5_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div5 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 22,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div5",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div5_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div7_div = {
+	.mult = 1,
+	.div = 7,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div7_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div7 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 23,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div7",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div7_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_fclk_div2p5_div = {
+	.mult = 2,
+	.div = 5,
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2p5_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_fclk_div2p5 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_FIXPLL_CTRL1,
+		.bit_idx = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "fclk_div2p5",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fclk_div2p5_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static const struct pll_mult_range s4_gp0_pll_mult_range = {
+	.min = 125,
+	.max = 250,
+};
+
+/*
+ * Internal gp0 pll emulation configuration parameters
+ */
+static const struct reg_sequence s4_gp0_init_regs[] = {
+	{ .reg = ANACTRL_GP0PLL_CTRL1,	.def = 0x00000000 },
+	{ .reg = ANACTRL_GP0PLL_CTRL2,	.def = 0x00000000 },
+	{ .reg = ANACTRL_GP0PLL_CTRL3,	.def = 0x48681c00 },
+	{ .reg = ANACTRL_GP0PLL_CTRL4,	.def = 0x88770290 },
+	{ .reg = ANACTRL_GP0PLL_CTRL5,	.def = 0x39272000 },
+	{ .reg = ANACTRL_GP0PLL_CTRL6,	.def = 0x56540000 }
+};
+
+static struct clk_regmap s4_gp0_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_GP0PLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_GP0PLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+		.range = &s4_gp0_pll_mult_range,
+		.init_regs = s4_gp0_init_regs,
+		.init_count = ARRAY_SIZE(s4_gp0_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gp0_pll_dco",
+		.ops = &meson_clk_pll_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_gp0_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_GP0PLL_CTRL0,
+		.shift = 16,
+		.width = 3,
+		.flags = (CLK_DIVIDER_POWER_OF_TWO |
+			  CLK_DIVIDER_ROUND_CLOSEST),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gp0_pll",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_gp0_pll_dco.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * Internal hifi pll emulation configuration parameters
+ */
+static const struct reg_sequence s4_hifi_init_regs[] = {
+	{ .reg = ANACTRL_HIFIPLL_CTRL1,	.def = 0x00010e56 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00000000 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL3,	.def = 0x6a285c00 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL4,	.def = 0x65771290 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL5,	.def = 0x39272000 },
+	{ .reg = ANACTRL_HIFIPLL_CTRL6,	.def = 0x56540000 }
+};
+
+static struct clk_regmap s4_hifi_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_HIFIPLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+		.range = &s4_gp0_pll_mult_range,
+		.init_regs = s4_hifi_init_regs,
+		.init_count = ARRAY_SIZE(s4_hifi_init_regs),
+		.flags = CLK_MESON_PLL_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hifi_pll_dco",
+		.ops = &meson_clk_pll_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_hifi_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_HIFIPLL_CTRL0,
+		.shift = 16,
+		.width = 2,
+		.flags = (CLK_DIVIDER_POWER_OF_TWO |
+			  CLK_DIVIDER_ROUND_CLOSEST),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hifi_pll",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hifi_pll_dco.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_pll_dco = {
+	.data = &(struct meson_clk_pll_data){
+		.en = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.m = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 0,
+			.width   = 8,
+		},
+		.n = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 10,
+			.width   = 5,
+		},
+		.frac = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL1,
+			.shift   = 0,
+			.width   = 17,
+		},
+		.l = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 31,
+			.width   = 1,
+		},
+		.rst = {
+			.reg_off = ANACTRL_HDMIPLL_CTRL0,
+			.shift   = 29,
+			.width   = 1,
+		},
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_pll_dco",
+		.ops = &meson_clk_pll_ro_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+		/*
+		 * Display directly handle hdmi pll registers ATM, we need
+		 * NOCACHE to keep our view of the clock as accurate as
+		 * possible
+		 */
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk_regmap s4_hdmi_pll_od = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_HDMIPLL_CTRL0,
+		.shift = 16,
+		.width = 4,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_pll_od",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdmi_pll_dco.hw
+		},
+		.num_parents = 1,
+		/*
+		 * Display directly handle hdmi pll registers ATM, we need
+		 * NOCACHE to keep our view of the clock as accurate as
+		 * possible
+		 */
+		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_pll = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = ANACTRL_HDMIPLL_CTRL0,
+		.shift = 20,
+		.width = 2,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_pll",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdmi_pll_od.hw
+		},
+		.num_parents = 1,
+		/*
+		 * Display directly handle hdmi pll registers ATM, we need
+		 * NOCACHE to keep our view of the clock as accurate as
+		 * possible
+		 */
+		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_fixed_factor s4_mpll_50m_div = {
+	.mult = 1,
+	.div = 80,
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll_50m_div",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll_dco.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll_50m = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = ANACTRL_FIXPLL_CTRL3,
+		.mask = 0x1,
+		.shift = 5,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll_50m",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", },
+			{ .hw = &s4_mpll_50m_div.hw },
+		},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_fixed_factor s4_mpll_prediv = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll_prediv",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_fixed_pll_dco.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static const struct reg_sequence s4_mpll0_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll0_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL1,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll0_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll0_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll0_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL1,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll0_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct reg_sequence s4_mpll1_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL4,	.def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll1_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL3,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll1_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll1_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll1_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL3,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll1_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct reg_sequence s4_mpll2_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll2_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL5,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll2_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll2_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll2_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll2 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL5,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll2",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll2_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct reg_sequence s4_mpll3_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll3_div = {
+	.data = &(struct meson_clk_mpll_data){
+		.sdm = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 0,
+			.width   = 14,
+		},
+		.sdm_en = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 30,
+			.width	 = 1,
+		},
+		.n2 = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 20,
+			.width   = 9,
+		},
+		.ssen = {
+			.reg_off = ANACTRL_MPLL_CTRL7,
+			.shift   = 29,
+			.width	 = 1,
+		},
+		.lock = &meson_clk_lock,
+		.init_regs = s4_mpll3_init_regs,
+		.init_count = ARRAY_SIZE(s4_mpll3_init_regs),
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll3_div",
+		.ops = &meson_clk_mpll_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mpll_prediv.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_mpll3 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = ANACTRL_MPLL_CTRL7,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mpll3",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_mpll3_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * rtc 32k clock in gate
+ */
+static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "rtc_32k_by_oscin_clkin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static const struct meson_clk_dualdiv_param s4_32k_div_table[] = {
+	{
+		.dual	= 1,
+		.n1	= 733,
+		.m1	= 8,
+		.n2	= 732,
+		.m2	= 11,
+	},
+	{}
+};
+
+static struct clk_regmap s4_rtc_32k_by_oscin_div = {
+	.data = &(struct meson_clk_dualdiv_data){
+		.n1 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.n2 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.m1 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.m2 = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.dual = {
+			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.table = s4_32k_div_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "rtc_32k_by_oscin_div",
+		.ops = &meson_clk_dualdiv_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_rtc_32k_by_oscin_clkin.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_rtc_32k_by_oscin_sel = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+		.mask = 0x1,
+		.shift = 24,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "rtc_32k_by_oscin_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_rtc_32k_by_oscin_div.hw,
+			&s4_rtc_32k_by_oscin_clkin.hw,
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_rtc_32k_by_oscin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "rtc_32k_by_oscin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_rtc_32k_by_oscin_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * This RTC clock can be supplied by an external 32KHz crystal oscillator.
+ * If it is used, it should be documented in using fW_name and documented in the
+ * Bindings. Not currently in use on this board, so skip it.
+ */
+static u32 rtc_clk_sel[] = { 0, 1 };
+static const struct clk_parent_data rtc_clk_sel_parent_data[] = {
+	{ .hw = &s4_rtc_32k_by_oscin.hw },
+	{ .hw = &s4_rtc_32k_by_oscin_div.hw },
+	{ .fw_name = "ext-32k-0",  }
+};
+
+static struct clk_regmap s4_rtc_clk = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_RTC_CTRL,
+		.mask = 0x3,
+		.shift = 0,
+		.table = rtc_clk_sel,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "rtc_clk_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = rtc_clk_sel_parent_data,
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * sys clk
+ * The clock corresponding to these 5 is AXi_CLK, which is dedicated to AXI. So skip it.
+ */
+static u32 mux_table_sys_ab_clk_sel[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data sys_ab_clk_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_rtc_clk.hw }
+};
+
+static struct clk_regmap s4_sysclk_b_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.mask = 0x7,
+		.shift = 26,
+		.table = mux_table_sys_ab_clk_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_b_sel",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_data = sys_ab_clk_parent_data,
+		.num_parents = ARRAY_SIZE(sys_ab_clk_parent_data),
+	},
+};
+
+static struct clk_regmap s4_sysclk_b_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.shift = 16,
+		.width = 10,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_b_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_b_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sysclk_b = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.bit_idx = 29,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sysclk_b",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_b_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sysclk_a_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.mask = 0x7,
+		.shift = 10,
+		.table = mux_table_sys_ab_clk_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_a_sel",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_data = sys_ab_clk_parent_data,
+		.num_parents = ARRAY_SIZE(sys_ab_clk_parent_data),
+	},
+};
+
+static struct clk_regmap s4_sysclk_a_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.shift = 0,
+		.width = 10,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sysclk_a_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_a_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sysclk_a = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.bit_idx = 13,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sysclk_a",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_a_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sys_clk = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SYS_CLK_CTRL0,
+		.mask = 0x1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sys_clk",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sysclk_a.hw,
+			&s4_sysclk_b.hw
+		},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_clkin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECA_CTRL0,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "ceca_32k_clkin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_div = {
+	.data = &(struct meson_clk_dualdiv_data){
+		.n1 = {
+			.reg_off = CLKCTRL_CECA_CTRL0,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.n2 = {
+			.reg_off = CLKCTRL_CECA_CTRL0,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.m1 = {
+			.reg_off = CLKCTRL_CECA_CTRL1,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.m2 = {
+			.reg_off = CLKCTRL_CECA_CTRL1,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.dual = {
+			.reg_off = CLKCTRL_CECA_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.table = s4_32k_div_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_div",
+		.ops = &meson_clk_dualdiv_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_clkin.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_sel_pre = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECA_CTRL1,
+		.mask = 0x1,
+		.shift = 24,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_sel_pre",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_div.hw,
+			&s4_ceca_32k_clkin.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_sel = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECA_CTRL1,
+		.mask = 0x1,
+		.shift = 31,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_sel_pre.hw,
+			&s4_rtc_clk.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_ceca_32k_clkout = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECA_CTRL0,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ceca_32k_clkout",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ceca_32k_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_clkin = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECB_CTRL0,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cecb_32k_clkin",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_div = {
+	.data = &(struct meson_clk_dualdiv_data){
+		.n1 = {
+			.reg_off = CLKCTRL_CECB_CTRL0,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.n2 = {
+			.reg_off = CLKCTRL_CECB_CTRL0,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.m1 = {
+			.reg_off = CLKCTRL_CECB_CTRL1,
+			.shift   = 0,
+			.width   = 12,
+		},
+		.m2 = {
+			.reg_off = CLKCTRL_CECB_CTRL1,
+			.shift   = 12,
+			.width   = 12,
+		},
+		.dual = {
+			.reg_off = CLKCTRL_CECB_CTRL0,
+			.shift   = 28,
+			.width   = 1,
+		},
+		.table = s4_32k_div_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_div",
+		.ops = &meson_clk_dualdiv_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_clkin.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_sel_pre = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECB_CTRL1,
+		.mask = 0x1,
+		.shift = 24,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_sel_pre",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_div.hw,
+			&s4_cecb_32k_clkin.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_sel = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_CECB_CTRL1,
+		.mask = 0x1,
+		.shift = 31,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_sel_pre.hw,
+			&s4_rtc_clk.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cecb_32k_clkout = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CECB_CTRL0,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cecb_32k_clkout",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cecb_32k_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_sc_parent_data[] = {
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .fw_name = "xtal", }
+};
+
+static struct clk_regmap s4_sc_clk_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SC_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sc_clk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sc_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sc_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sc_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SC_CLK_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sc_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sc_clk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sc_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SC_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sc_clk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sc_clk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_12_24M_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_CLK12_24_CTRL,
+		.bit_idx = 11,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "12_24m_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", }
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_12M_clk_div = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "12M",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_12_24M_clk_gate.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_12_24M_clk = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_CLK12_24_CTRL,
+		.mask = 0x1,
+		.shift = 10,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "12_24m",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_12_24M_clk_gate.hw,
+			&s4_12M_clk_div.hw,
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* Video Clocks */
+static struct clk_regmap s4_vid_pll_div = {
+	.data = &(struct meson_vid_pll_div_data){
+		.val = {
+			.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
+			.shift   = 0,
+			.width   = 15,
+		},
+		.sel = {
+			.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
+			.shift   = 16,
+			.width   = 2,
+		},
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vid_pll_div",
+		.ops = &meson_vid_pll_div_ro_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_pll.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vid_pll_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_PLL_CLK_DIV,
+		.mask = 0x1,
+		.shift = 18,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vid_pll_sel",
+		.ops = &clk_regmap_mux_ops,
+		/*
+		 * bit 18 selects from 2 possible parents:
+		 * vid_pll_div or hdmi_pll
+		 */
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vid_pll_div.hw,
+			&s4_hdmi_pll.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vid_pll = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_PLL_CLK_DIV,
+		.bit_idx = 19,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vid_pll",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vid_pll_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_vclk_parent_hws[] = {
+	&s4_vid_pll.hw,
+	&s4_gp0_pll.hw,
+	&s4_hifi_pll.hw,
+	&s4_mpll1.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div4.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw
+};
+
+static struct clk_regmap s4_vclk_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 16,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vclk_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vclk_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 16,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vclk_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vclk_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_input = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.bit_idx = 16,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_input",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_input = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_DIV,
+		.bit_idx = 16,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_input",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_input.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VIID_CLK_DIV,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_input.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_vclk = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 19,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 19,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 0,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div2_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 1,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div2_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div4_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 2,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div4_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div6_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 3,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div6_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk_div12_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL,
+		.bit_idx = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk_div12_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 0,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div2_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 1,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div2_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div4_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 2,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div4_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div6_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 3,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div6_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vclk2_div12_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VIID_CLK_CTRL,
+		.bit_idx = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vclk2_div12_en",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div2 = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div2",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div2_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div4 = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div4",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div4_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div6 = {
+	.mult = 1,
+	.div = 6,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div6",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div6_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk_div12 = {
+	.mult = 1,
+	.div = 12,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk_div12",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk_div12_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div2 = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div2",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div2_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div4 = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div4",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div4_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div6 = {
+	.mult = 1,
+	.div = 6,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div6",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div6_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_fixed_factor s4_vclk2_div12 = {
+	.mult = 1,
+	.div = 12,
+	.hw.init = &(struct clk_init_data){
+		.name = "vclk2_div12",
+		.ops = &clk_fixed_factor_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vclk2_div12_en.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+/*
+ * bits 31:28 selects from 12 possible parents:
+ * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
+ * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12r.
+ * The 5,6,7 corresponds to no real clock, so threre are not used.
+ */
+static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_hw *s4_cts_parent_hws[] = {
+	&s4_vclk_div1.hw,
+	&s4_vclk_div2.hw,
+	&s4_vclk_div4.hw,
+	&s4_vclk_div6.hw,
+	&s4_vclk_div12.hw,
+	&s4_vclk2_div1.hw,
+	&s4_vclk2_div2.hw,
+	&s4_vclk2_div4.hw,
+	&s4_vclk2_div6.hw,
+	&s4_vclk2_div12.hw
+};
+
+static struct clk_regmap s4_cts_enci_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.mask = 0xf,
+		.shift = 28,
+		.table = mux_table_cts_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_enci_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_encp_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VID_CLK_DIV,
+		.mask = 0xf,
+		.shift = 20,
+		.table = mux_table_cts_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_encp_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_vdac_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VIID_CLK_DIV,
+		.mask = 0xf,
+		.shift = 28,
+		.table = mux_table_cts_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_vdac_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+/*
+ * TOFIX: add support for cts_tcon
+ * bits 31:28 selects from 12 possible parents:
+ * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
+ * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
+ * cts_tcon
+ */
+static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_hw *s4_cts_hdmi_tx_parent_hws[] = {
+	&s4_vclk_div1.hw,
+	&s4_vclk_div2.hw,
+	&s4_vclk_div4.hw,
+	&s4_vclk_div6.hw,
+	&s4_vclk_div12.hw,
+	&s4_vclk2_div1.hw,
+	&s4_vclk2_div2.hw,
+	&s4_vclk2_div4.hw,
+	&s4_vclk2_div6.hw,
+	&s4_vclk2_div12.hw
+};
+
+static struct clk_regmap s4_hdmi_tx_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.mask = 0xf,
+		.shift = 16,
+		.table = mux_table_hdmi_tx_sel,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_tx_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_cts_hdmi_tx_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_cts_hdmi_tx_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_enci = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 0,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_enci",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cts_enci_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_encp = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 2,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_encp",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cts_encp_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_cts_vdac = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_vdac",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_cts_vdac_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_tx = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VID_CLK_CTRL2,
+		.bit_idx = 5,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdmi_tx",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdmi_tx_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* HDMI Clocks */
+static const struct clk_parent_data s4_hdmi_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw }
+};
+
+static struct clk_regmap s4_hdmi_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_hdmi_parent_data,
+		.num_parents = ARRAY_SIZE(s4_hdmi_parent_data),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_hdmi_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdmi_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_sel.hw },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_hdmi = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_HDMI_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdmi",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_ts_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_TS_CLK_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ts_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "xtal",
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap s4_ts_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_TS_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ts_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_ts_clk_div.hw
+		},
+		.num_parents = 1,
+	},
+};
+
+/*
+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
+ * muxed by a glitch-free switch. The CCF can manage this glitch-free
+ * mux because it does top-to-bottom updates the each clock tree and
+ * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
+ */
+static const struct clk_parent_data s4_mali_0_1_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_fclk_div2p5.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw }
+};
+
+static struct clk_regmap s4_mali_0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_mali_0_1_parent_data,
+		.num_parents = ARRAY_SIZE(s4_mali_0_1_parent_data),
+		/*
+		 * Don't request the parent to change the rate because
+		 * all GPU frequencies can be derived from the fclk_*
+		 * clocks and one special GP0_PLL setting. This is
+		 * important because we need the MPLL clocks for audio.
+		 */
+		.flags = 0,
+	},
+};
+
+static struct clk_regmap s4_mali_0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_mali_0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_mali_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_mali_0_1_parent_data,
+		.num_parents = ARRAY_SIZE(s4_mali_0_1_parent_data),
+		/*
+		 * Don't request the parent to change the rate because
+		 * all GPU frequencies can be derived from the fclk_*
+		 * clocks and one special GP0_PLL setting. This is
+		 * important because we need the MPLL clocks for audio.
+		 */
+		.flags = 0,
+	},
+};
+
+static struct clk_regmap s4_mali_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_1_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_mali_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_mali_1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_mali_parent_hws[] = {
+	&s4_mali_0.hw,
+	&s4_mali_1.hw
+};
+
+static struct clk_regmap s4_mali_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_MALI_CLK_CTRL,
+		.mask = 1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_mali_parent_hws,
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* VDEC clocks */
+static const struct clk_parent_data s4_dec_parent_data[] = {
+	{ .hw = &s4_fclk_div2p5.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .fw_name = "xtal", }
+};
+
+static struct clk_regmap s4_vdec_p0_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_p0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p1_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p1_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_p1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p1_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdec_p1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_p1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdec_p1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_vdec_mux_parent_hws[] = {
+	&s4_vdec_p0.hw,
+	&s4_vdec_p1.hw
+};
+
+static struct clk_regmap s4_vdec_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC3_CLK_CTRL,
+		.mask = 0x1,
+		.shift = 15,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vdec_mux_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vdec_mux_parent_hws),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p0_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC2_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC2_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC2_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hevcf_p0_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p1_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p1_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_dec_parent_data,
+		.num_parents = ARRAY_SIZE(s4_dec_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf_p1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p1_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hevcf_p1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hevcf_p1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hevcf_p1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_hevcf_mux_parent_hws[] = {
+	&s4_hevcf_p0.hw,
+	&s4_hevcf_p1.hw
+};
+
+static struct clk_regmap s4_hevcf_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDEC4_CLK_CTRL,
+		.mask = 0x1,
+		.shift = 15,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hevcf",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_hevcf_mux_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_hevcf_mux_parent_hws),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* VPU Clock */
+
+static const struct clk_hw *s4_vpu_parent_hws[] = {
+	&s4_fclk_div3.hw,
+	&s4_fclk_div4.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw,
+	&s4_mpll1.hw,
+	&s4_vid_pll.hw,
+	&s4_hifi_pll.hw,
+	&s4_gp0_pll.hw
+};
+
+static struct clk_regmap s4_vpu_0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vpu_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vpu_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vpu_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vpu_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_sel.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_div.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLK_CTRL,
+		.mask = 1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu",
+		.ops = &clk_regmap_mux_ops,
+		/*
+		 * bit 31 selects from 2 possible parents:
+		 * vpu_0 or vpu_1
+		 */
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_0.hw,
+			&s4_vpu_1.hw,
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static const struct clk_parent_data vpu_clkb_tmp_parent_data[] = {
+	{ .hw = &s4_vpu.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw }
+};
+
+static struct clk_regmap s4_vpu_clkb_tmp_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.mask = 0x3,
+		.shift = 20,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkb_tmp_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = vpu_clkb_tmp_parent_data,
+		.num_parents = ARRAY_SIZE(vpu_clkb_tmp_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb_tmp_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.shift = 16,
+		.width = 4,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkb_tmp_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_tmp_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb_tmp = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkb_tmp",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_tmp_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkb_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_tmp.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkb = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKB_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkb",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkb_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *vpu_clkc_parent_hws[] = {
+	&s4_fclk_div4.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw,
+	&s4_mpll1.hw,
+	&s4_vid_pll.hw,
+	&s4_mpll2.hw,
+	&s4_gp0_pll.hw
+};
+
+static struct clk_regmap s4_vpu_clkc_p0_mux  = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = vpu_clkc_parent_hws,
+		.num_parents = ARRAY_SIZE(vpu_clkc_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkc_p0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p1_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p1_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = vpu_clkc_parent_hws,
+		.num_parents = ARRAY_SIZE(vpu_clkc_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_p1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p1_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vpu_clkc_p1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vpu_clkc_p1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vpu_clkc_p1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_vpu_mux_parent_hws[] = {
+	&s4_vpu_clkc_p0.hw,
+	&s4_vpu_clkc_p1.hw
+};
+
+static struct clk_regmap s4_vpu_clkc_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VPU_CLKC_CTRL,
+		.mask = 0x1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vpu_clkc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vpu_mux_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vpu_mux_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+/* VAPB Clock */
+
+static const struct clk_hw *s4_vapb_parent_hws[] = {
+	&s4_fclk_div4.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div5.hw,
+	&s4_fclk_div7.hw,
+	&s4_mpll1.hw,
+	&s4_vid_pll.hw,
+	&s4_mpll2.hw,
+	&s4_fclk_div2p5.hw
+};
+
+static struct clk_regmap s4_vapb_0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vapb_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vapb_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vapb_0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_vapb_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_vapb_parent_hws),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_1_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vapb_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_1_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vapb = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.mask = 1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vapb_sel",
+		.ops = &clk_regmap_mux_ops,
+		/*
+		 * bit 31 selects from 2 possible parents:
+		 * vapb_0 or vapb_1
+		 */
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vapb_0.hw,
+			&s4_vapb_1.hw
+		},
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap s4_ge2d_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VAPBCLK_CTRL,
+		.bit_idx = 30,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "ge2d_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) { &s4_vapb.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *s4_esmclk_parent_hws[] = {
+	&s4_fclk_div7.hw,
+	&s4_fclk_div4.hw,
+	&s4_fclk_div3.hw,
+	&s4_fclk_div5.hw
+};
+
+static struct clk_regmap s4_hdcp22_esmclk_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_esmclk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = s4_esmclk_parent_hws,
+		.num_parents = ARRAY_SIZE(s4_esmclk_parent_hws),
+	},
+};
+
+static struct clk_regmap s4_hdcp22_esmclk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_esmclk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_esmclk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdcp22_esmclk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdcp22_esmclk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_esmclk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_skpclk_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw }
+};
+
+static struct clk_regmap s4_hdcp22_skpclk_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_skpclk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_skpclk_parent_data,
+		.num_parents = ARRAY_SIZE(s4_skpclk_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdcp22_skpclk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "hdcp22_skpclk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_skpclk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_hdcp22_skpclk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_HDCP22_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "hdcp22_skpclk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_hdcp22_skpclk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_vdin_parent_data[]  = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_vid_pll.hw }
+};
+
+static struct clk_regmap s4_vdin_meas_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdin_meas_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_vdin_parent_data,
+		.num_parents = ARRAY_SIZE(s4_vdin_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdin_meas_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdin_meas_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdin_meas_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_vdin_meas_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdin_meas_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_vdin_meas_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* EMMC/NAND clock */
+
+static const struct clk_parent_data s4_sd_emmc_clk0_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_fclk_div2p5.hw },
+	/*
+	 * Following these parent clocks, we should also have had mpll2, mpll3
+	 * and gp0_pll but these clocks are too precious to be used here. All
+	 * the necessary rates for MMC and NAND operation can be acheived using
+	 * hifi_pll or fclk_div clocks
+	 */
+};
+
+static struct clk_regmap s4_sd_emmc_c_clk0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_NAND_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_c_clk0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sd_emmc_clk0_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_c_clk0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_NAND_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_c_clk0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_c_clk0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_c_clk0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_NAND_CLK_CTRL,
+		.bit_idx = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sd_emmc_c_clk0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_c_clk0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_a_clk0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_a_clk0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sd_emmc_clk0_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_a_clk0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_a_clk0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_a_clk0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_a_clk0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.bit_idx = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sd_emmc_a_clk0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_a_clk0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_b_clk0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_b_clk0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_sd_emmc_clk0_parent_data,
+		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_b_clk0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sd_emmc_b_clk0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_b_clk0_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_sd_emmc_b_clk0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+		.bit_idx = 23,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "sd_emmc_b_clk0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_sd_emmc_b_clk0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* SPICC SCLK source clock */
+
+static const struct clk_parent_data s4_spicc_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_sys_clk.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+};
+
+static struct clk_regmap s4_spicc0_mux = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_SPICC_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 7,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "spicc0_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_spicc_parent_data,
+		.num_parents = ARRAY_SIZE(s4_spicc_parent_data),
+	},
+};
+
+static struct clk_regmap s4_spicc0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_SPICC_CLK_CTRL,
+		.shift = 0,
+		.width = 6,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "spicc0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_spicc0_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_spicc0_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_SPICC_CLK_CTRL,
+		.bit_idx = 6,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "spicc0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_spicc0_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/* PWM CLOCK */
+
+static const struct clk_parent_data s4_pwm_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_vid_pll.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw }
+};
+
+static struct clk_regmap s4_pwm_a_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_a_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_a_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_a_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_a_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_a_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_a_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_a_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_b_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_b_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_b_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_b_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_b_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_b_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_AB_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_b_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_b_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_c_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_c_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_c_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_c_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_c_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_c_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_c_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_c_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_d_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_d_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_d_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_d_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_d_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_d_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_CD_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_d_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_d_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_e_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_e_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_e_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_e_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_e_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_e_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_e_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_e_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_f_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_f_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_f_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_f_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_f_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_f_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_EF_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_f_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_f_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_g_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_g_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_g_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_g_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_g_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_g_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_g_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_g_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_h_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_h_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_h_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_h_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_h_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_h_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_GH_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_h_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_h_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_i_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_i_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_i_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_i_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_i_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_i_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_i_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_i_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_j_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.mask = 0x3,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_j_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_pwm_parent_data,
+		.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_j_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_j_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_h_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_pwm_j_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "pwm_j_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_pwm_j_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_saradc_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_SAR_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "saradc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", },
+			{ .hw = &s4_sys_clk.hw },
+		},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap s4_saradc_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_SAR_CLK_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "saradc_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_saradc_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_saradc_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_SAR_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "saradc_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_saradc_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+/*
+ * gen clk is designed for debug/monitor some internal clock quality. Some of the
+ * corresponding clock sources are not described in the clock tree, so they are skipped.
+ */
+static u32 s4_gen_clk_mux_table[] = { 0, 5, 7, 19, 21, 22,
+				      23, 24, 25, 26, 27, 28 };
+static const struct clk_parent_data s4_gen_clk_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .hw = &s4_hifi_pll.hw },
+	{ .hw = &s4_fclk_div2.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_mpll0.hw },
+	{ .hw = &s4_mpll1.hw },
+	{ .hw = &s4_mpll2.hw },
+	{ .hw = &s4_mpll3.hw }
+};
+
+static struct clk_regmap s4_gen_clk_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = CLKCTRL_GEN_CLK_CTRL,
+		.mask = 0x1f,
+		.shift = 12,
+		.table = s4_gen_clk_mux_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gen_clk_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_gen_clk_parent_data,
+		.num_parents = ARRAY_SIZE(s4_gen_clk_parent_data),
+	},
+};
+
+static struct clk_regmap s4_gen_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = CLKCTRL_GEN_CLK_CTRL,
+		.shift = 0,
+		.width = 11,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "gen_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_gen_clk_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_gen_clk = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = CLKCTRL_GEN_CLK_CTRL,
+		.bit_idx = 11,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "gen_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_gen_clk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_parent_data s4_adc_extclk_in_parent_data[]  = {
+	{ .fw_name = "xtal", },
+	{ .hw = &s4_fclk_div4.hw },
+	{ .hw = &s4_fclk_div3.hw },
+	{ .hw = &s4_fclk_div5.hw },
+	{ .hw = &s4_fclk_div7.hw },
+	{ .hw = &s4_mpll2.hw },
+	{ .hw = &s4_gp0_pll.hw },
+	{ .hw = &s4_hifi_pll.hw }
+};
+
+static struct clk_regmap s4_adc_extclk_in_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.mask = 0x7,
+		.shift = 25,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "adc_extclk_in_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = s4_adc_extclk_in_parent_data,
+		.num_parents = ARRAY_SIZE(s4_adc_extclk_in_parent_data),
+	},
+};
+
+static struct clk_regmap s4_adc_extclk_in_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "adc_extclk_in_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_adc_extclk_in_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_adc_extclk_in_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "adc_extclk_in",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_adc_extclk_in_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_demod_core_clk_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "demod_core_clk_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = (const struct clk_parent_data []) {
+			{ .fw_name = "xtal", },
+			{ .hw = &s4_fclk_div7.hw },
+			{ .hw = &s4_fclk_div4.hw },
+			{ .hw = &s4_adc_extclk_in_gate.hw }
+		},
+		.num_parents = 4,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_demod_core_clk_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "demod_core_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_demod_core_clk_mux.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap s4_demod_core_clk_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = CLKCTRL_DEMOD_CLK_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "demod_core_clk",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&s4_demod_core_clk_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+#define MESON_GATE(_name, _reg, _bit) \
+	MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)
+
+static MESON_GATE(s4_ddr,		CLKCTRL_SYS_CLK_EN0_REG0, 0);
+static MESON_GATE(s4_dos,		CLKCTRL_SYS_CLK_EN0_REG0, 1);
+static MESON_GATE(s4_ethphy,		CLKCTRL_SYS_CLK_EN0_REG0, 4);
+static MESON_GATE(s4_mali,		CLKCTRL_SYS_CLK_EN0_REG0, 6);
+static MESON_GATE(s4_aocpu,		CLKCTRL_SYS_CLK_EN0_REG0, 13);
+static MESON_GATE(s4_aucpu,		CLKCTRL_SYS_CLK_EN0_REG0, 14);
+static MESON_GATE(s4_cec,		CLKCTRL_SYS_CLK_EN0_REG0, 16);
+static MESON_GATE(s4_sdemmca,		CLKCTRL_SYS_CLK_EN0_REG0, 24);
+static MESON_GATE(s4_sdemmcb,		CLKCTRL_SYS_CLK_EN0_REG0, 25);
+static MESON_GATE(s4_nand,		CLKCTRL_SYS_CLK_EN0_REG0, 26);
+static MESON_GATE(s4_smartcard,		CLKCTRL_SYS_CLK_EN0_REG0, 27);
+static MESON_GATE(s4_acodec,		CLKCTRL_SYS_CLK_EN0_REG0, 28);
+static MESON_GATE(s4_spifc,		CLKCTRL_SYS_CLK_EN0_REG0, 29);
+static MESON_GATE(s4_msr_clk,		CLKCTRL_SYS_CLK_EN0_REG0, 30);
+static MESON_GATE(s4_ir_ctrl,		CLKCTRL_SYS_CLK_EN0_REG0, 31);
+
+static MESON_GATE(s4_audio,		CLKCTRL_SYS_CLK_EN0_REG1, 0);
+static MESON_GATE(s4_eth,		CLKCTRL_SYS_CLK_EN0_REG1, 3);
+static MESON_GATE(s4_uart_a,		CLKCTRL_SYS_CLK_EN0_REG1, 5);
+static MESON_GATE(s4_uart_b,		CLKCTRL_SYS_CLK_EN0_REG1, 6);
+static MESON_GATE(s4_uart_c,		CLKCTRL_SYS_CLK_EN0_REG1, 7);
+static MESON_GATE(s4_uart_d,		CLKCTRL_SYS_CLK_EN0_REG1, 8);
+static MESON_GATE(s4_uart_e,		CLKCTRL_SYS_CLK_EN0_REG1, 9);
+static MESON_GATE(s4_aififo,		CLKCTRL_SYS_CLK_EN0_REG1, 11);
+static MESON_GATE(s4_ts_ddr,		CLKCTRL_SYS_CLK_EN0_REG1, 15);
+static MESON_GATE(s4_ts_pll,		CLKCTRL_SYS_CLK_EN0_REG1, 16);
+static MESON_GATE(s4_g2d,		CLKCTRL_SYS_CLK_EN0_REG1, 20);
+static MESON_GATE(s4_spicc0,		CLKCTRL_SYS_CLK_EN0_REG1, 21);
+static MESON_GATE(s4_usb,		CLKCTRL_SYS_CLK_EN0_REG1, 26);
+static MESON_GATE(s4_i2c_m_a,		CLKCTRL_SYS_CLK_EN0_REG1, 30);
+static MESON_GATE(s4_i2c_m_b,		CLKCTRL_SYS_CLK_EN0_REG1, 31);
+
+static MESON_GATE(s4_i2c_m_c,		CLKCTRL_SYS_CLK_EN0_REG2, 0);
+static MESON_GATE(s4_i2c_m_d,		CLKCTRL_SYS_CLK_EN0_REG2, 1);
+static MESON_GATE(s4_i2c_m_e,		CLKCTRL_SYS_CLK_EN0_REG2, 2);
+static MESON_GATE(s4_hdmitx_apb,	CLKCTRL_SYS_CLK_EN0_REG2, 4);
+static MESON_GATE(s4_i2c_s_a,		CLKCTRL_SYS_CLK_EN0_REG2, 5);
+static MESON_GATE(s4_usb1_to_ddr,	CLKCTRL_SYS_CLK_EN0_REG2, 8);
+static MESON_GATE(s4_hdcp22,		CLKCTRL_SYS_CLK_EN0_REG2, 10);
+static MESON_GATE(s4_mmc_apb,		CLKCTRL_SYS_CLK_EN0_REG2, 11);
+static MESON_GATE(s4_rsa,		CLKCTRL_SYS_CLK_EN0_REG2, 18);
+static MESON_GATE(s4_cpu_debug,		CLKCTRL_SYS_CLK_EN0_REG2, 19);
+static MESON_GATE(s4_vpu_intr,		CLKCTRL_SYS_CLK_EN0_REG2, 25);
+static MESON_GATE(s4_demod,		CLKCTRL_SYS_CLK_EN0_REG2, 27);
+static MESON_GATE(s4_sar_adc,		CLKCTRL_SYS_CLK_EN0_REG2, 28);
+static MESON_GATE(s4_gic,		CLKCTRL_SYS_CLK_EN0_REG2, 30);
+
+static MESON_GATE(s4_pwm_ab,		CLKCTRL_SYS_CLK_EN0_REG3, 7);
+static MESON_GATE(s4_pwm_cd,		CLKCTRL_SYS_CLK_EN0_REG3, 8);
+static MESON_GATE(s4_pwm_ef,		CLKCTRL_SYS_CLK_EN0_REG3, 9);
+static MESON_GATE(s4_pwm_gh,		CLKCTRL_SYS_CLK_EN0_REG3, 10);
+static MESON_GATE(s4_pwm_ij,		CLKCTRL_SYS_CLK_EN0_REG3, 11);
+
+/* Array of all clocks provided by this provider */
+static struct clk_hw_onecell_data s4_hw_onecell_data = {
+	.hws = {
+		[CLKID_FIXED_PLL_DCO]		= &s4_fixed_pll_dco.hw,
+		[CLKID_FIXED_PLL]		= &s4_fixed_pll.hw,
+		[CLKID_FCLK_DIV2_DIV]		= &s4_fclk_div2_div.hw,
+		[CLKID_FCLK_DIV2]		= &s4_fclk_div2.hw,
+		[CLKID_FCLK_DIV3_DIV]		= &s4_fclk_div3_div.hw,
+		[CLKID_FCLK_DIV3]		= &s4_fclk_div3.hw,
+		[CLKID_FCLK_DIV4_DIV]		= &s4_fclk_div4_div.hw,
+		[CLKID_FCLK_DIV4]		= &s4_fclk_div4.hw,
+		[CLKID_FCLK_DIV5_DIV]		= &s4_fclk_div5_div.hw,
+		[CLKID_FCLK_DIV5]		= &s4_fclk_div5.hw,
+		[CLKID_FCLK_DIV7_DIV]		= &s4_fclk_div7_div.hw,
+		[CLKID_FCLK_DIV7]		= &s4_fclk_div7.hw,
+		[CLKID_FCLK_DIV2P5_DIV]		= &s4_fclk_div2p5_div.hw,
+		[CLKID_FCLK_DIV2P5]		= &s4_fclk_div2p5.hw,
+
+		[CLKID_GP0_PLL_DCO]		= &s4_gp0_pll_dco.hw,
+		[CLKID_GP0_PLL]			= &s4_gp0_pll.hw,
+
+		[CLKID_HIFI_PLL_DCO]		= &s4_hifi_pll_dco.hw,
+		[CLKID_HIFI_PLL]		= &s4_hifi_pll.hw,
+		[CLKID_HDMI_PLL_DCO]		= &s4_hdmi_pll_dco.hw,
+		[CLKID_HDMI_PLL_OD]		= &s4_hdmi_pll_od.hw,
+		[CLKID_HDMI_PLL]		= &s4_hdmi_pll.hw,
+		[CLKID_MPLL_50M_DIV]		= &s4_mpll_50m_div.hw,
+		[CLKID_MPLL_50M]		= &s4_mpll_50m.hw,
+		[CLKID_MPLL_PREDIV]		= &s4_mpll_prediv.hw,
+		[CLKID_MPLL0_DIV]		= &s4_mpll0_div.hw,
+		[CLKID_MPLL0]			= &s4_mpll0.hw,
+		[CLKID_MPLL1_DIV]		= &s4_mpll1_div.hw,
+		[CLKID_MPLL1]			= &s4_mpll1.hw,
+		[CLKID_MPLL2_DIV]		= &s4_mpll2_div.hw,
+		[CLKID_MPLL2]			= &s4_mpll2.hw,
+		[CLKID_MPLL3_DIV]		= &s4_mpll3_div.hw,
+		[CLKID_MPLL3]			= &s4_mpll3.hw,
+
+		[CLKID_RTC_32K_CLKIN]		= &s4_rtc_32k_by_oscin_clkin.hw,
+		[CLKID_RTC_32K_DIV]		= &s4_rtc_32k_by_oscin_div.hw,
+		[CLKID_RTC_32K_SEL]		= &s4_rtc_32k_by_oscin_sel.hw,
+		[CLKID_RTC_32K_XATL]		= &s4_rtc_32k_by_oscin.hw,
+		[CLKID_RTC_CLK]			= &s4_rtc_clk.hw,
+
+		[CLKID_SYS_CLK_B_SEL]		= &s4_sysclk_b_sel.hw,
+		[CLKID_SYS_CLK_B_DIV]		= &s4_sysclk_b_div.hw,
+		[CLKID_SYS_CLK_B_GATE]		= &s4_sysclk_b.hw,
+		[CLKID_SYS_CLK_A_SEL]		= &s4_sysclk_a_sel.hw,
+		[CLKID_SYS_CLK_A_DIV]		= &s4_sysclk_a_div.hw,
+		[CLKID_SYS_CLK_A_GATE]		= &s4_sysclk_a.hw,
+		[CLKID_SYS_CLK]			= &s4_sys_clk.hw,
+
+		[CLKID_CECA_32K_CLKIN]		= &s4_ceca_32k_clkin.hw,
+		[CLKID_CECA_32K_DIV]		= &s4_ceca_32k_div.hw,
+		[CLKID_CECA_32K_SEL_PRE]	= &s4_ceca_32k_sel_pre.hw,
+		[CLKID_CECA_32K_SEL]		= &s4_ceca_32k_sel.hw,
+		[CLKID_CECA_32K_CLKOUT]		= &s4_ceca_32k_clkout.hw,
+
+		[CLKID_CECB_32K_CLKIN]		= &s4_cecb_32k_clkin.hw,
+		[CLKID_CECB_32K_DIV]		= &s4_cecb_32k_div.hw,
+		[CLKID_CECB_32K_SEL_PRE]	= &s4_cecb_32k_sel_pre.hw,
+		[CLKID_CECB_32K_SEL]		= &s4_cecb_32k_sel.hw,
+		[CLKID_CECB_32K_CLKOUT]		= &s4_cecb_32k_clkout.hw,
+
+		[CLKID_SC_CLK_SEL]		= &s4_sc_clk_mux.hw,
+		[CLKID_SC_CLK_DIV]		= &s4_sc_clk_div.hw,
+		[CLKID_SC_CLK_GATE]		= &s4_sc_clk_gate.hw,
+
+		[CLKID_12_24M_CLK_GATE]		= &s4_12_24M_clk_gate.hw,
+		[CLKID_12M_CLK_DIV]		= &s4_12M_clk_div.hw,
+		[CLKID_12_24M_CLK_SEL]		= &s4_12_24M_clk.hw,
+
+		[CLKID_VID_PLL_DIV]		= &s4_vid_pll_div.hw,
+		[CLKID_VID_PLL_SEL]		= &s4_vid_pll_sel.hw,
+		[CLKID_VID_PLL]			= &s4_vid_pll.hw,
+		[CLKID_VCLK_SEL]		= &s4_vclk_sel.hw,
+		[CLKID_VCLK2_SEL]		= &s4_vclk2_sel.hw,
+		[CLKID_VCLK_INPUT]		= &s4_vclk_input.hw,
+		[CLKID_VCLK2_INPUT]		= &s4_vclk2_input.hw,
+		[CLKID_VCLK_DIV]		= &s4_vclk_div.hw,
+		[CLKID_VCLK2_DIV]		= &s4_vclk2_div.hw,
+		[CLKID_VCLK]			= &s4_vclk.hw,
+		[CLKID_VCLK2]			= &s4_vclk2.hw,
+		[CLKID_VCLK_DIV1]		= &s4_vclk_div1.hw,
+		[CLKID_VCLK_DIV2_EN]		= &s4_vclk_div2_en.hw,
+		[CLKID_VCLK_DIV4_EN]		= &s4_vclk_div4_en.hw,
+		[CLKID_VCLK_DIV6_EN]		= &s4_vclk_div6_en.hw,
+		[CLKID_VCLK_DIV12_EN]		= &s4_vclk_div12_en.hw,
+		[CLKID_VCLK2_DIV1]		= &s4_vclk2_div1.hw,
+		[CLKID_VCLK2_DIV2_EN]		= &s4_vclk2_div2_en.hw,
+		[CLKID_VCLK2_DIV4_EN]		= &s4_vclk2_div4_en.hw,
+		[CLKID_VCLK2_DIV6_EN]		= &s4_vclk2_div6_en.hw,
+		[CLKID_VCLK2_DIV12_EN]		= &s4_vclk2_div12_en.hw,
+		[CLKID_VCLK_DIV2]		= &s4_vclk_div2.hw,
+		[CLKID_VCLK_DIV4]		= &s4_vclk_div4.hw,
+		[CLKID_VCLK_DIV6]		= &s4_vclk_div6.hw,
+		[CLKID_VCLK_DIV12]		= &s4_vclk_div12.hw,
+		[CLKID_VCLK2_DIV2]		= &s4_vclk2_div2.hw,
+		[CLKID_VCLK2_DIV4]		= &s4_vclk2_div4.hw,
+		[CLKID_VCLK2_DIV6]		= &s4_vclk2_div6.hw,
+		[CLKID_VCLK2_DIV12]		= &s4_vclk2_div12.hw,
+		[CLKID_CTS_ENCI_SEL]		= &s4_cts_enci_sel.hw,
+		[CLKID_CTS_ENCP_SEL]		= &s4_cts_encp_sel.hw,
+		[CLKID_CTS_VDAC_SEL]		= &s4_cts_vdac_sel.hw,
+		[CLKID_HDMI_TX_SEL]		= &s4_hdmi_tx_sel.hw,
+		[CLKID_CTS_ENCI]		= &s4_cts_enci.hw,
+		[CLKID_CTS_ENCP]		= &s4_cts_encp.hw,
+		[CLKID_CTS_VDAC]		= &s4_cts_vdac.hw,
+		[CLKID_HDMI_TX]			= &s4_hdmi_tx.hw,
+		[CLKID_HDMI_SEL]		= &s4_hdmi_sel.hw,
+		[CLKID_HDMI_DIV]		= &s4_hdmi_div.hw,
+		[CLKID_HDMI]			= &s4_hdmi.hw,
+
+		[CLKID_TS_CLK_DIV]		= &s4_ts_clk_div.hw,
+		[CLKID_TS_CLK_GATE]		= &s4_ts_clk_gate.hw,
+
+		[CLKID_MALI_0_SEL]		= &s4_mali_0_sel.hw,
+		[CLKID_MALI_0_DIV]		= &s4_mali_0_div.hw,
+		[CLKID_MALI_0]			= &s4_mali_0.hw,
+		[CLKID_MALI_1_SEL]		= &s4_mali_1_sel.hw,
+		[CLKID_MALI_1_DIV]		= &s4_mali_1_div.hw,
+		[CLKID_MALI_1]			= &s4_mali_1.hw,
+		[CLKID_MALI]			= &s4_mali_mux.hw,
+
+		[CLKID_VDEC_P0_SEL]		= &s4_vdec_p0_mux.hw,
+		[CLKID_VDEC_P0_DIV]		= &s4_vdec_p0_div.hw,
+		[CLKID_VDEC_P0]			= &s4_vdec_p0.hw,
+		[CLKID_VDEC_P1_SEL]		= &s4_vdec_p1_mux.hw,
+		[CLKID_VDEC_P1_DIV]		= &s4_vdec_p1_div.hw,
+		[CLKID_VDEC_P1]			= &s4_vdec_p1.hw,
+		[CLKID_VDEC_SEL]		= &s4_vdec_mux.hw,
+
+		[CLKID_HEVCF_P0_SEL]		= &s4_hevcf_p0_mux.hw,
+		[CLKID_HEVCF_P0_DIV]		= &s4_hevcf_p0_div.hw,
+		[CLKID_HEVCF_P0]		= &s4_hevcf_p0.hw,
+		[CLKID_HEVCF_P1_SEL]		= &s4_hevcf_p1_mux.hw,
+		[CLKID_HEVCF_P1_DIV]		= &s4_hevcf_p1_div.hw,
+		[CLKID_HEVCF_P1]		= &s4_hevcf_p1.hw,
+		[CLKID_HEVCF_SEL]		= &s4_hevcf_mux.hw,
+
+		[CLKID_VPU_0_SEL]		= &s4_vpu_0_sel.hw,
+		[CLKID_VPU_0_DIV]		= &s4_vpu_0_div.hw,
+		[CLKID_VPU_0]			= &s4_vpu_0.hw,
+		[CLKID_VPU_1_SEL]		= &s4_vpu_1_sel.hw,
+		[CLKID_VPU_1_DIV]		= &s4_vpu_1_div.hw,
+		[CLKID_VPU_1]			= &s4_vpu_1.hw,
+		[CLKID_VPU]			= &s4_vpu.hw,
+
+		[CLKID_VPU_CLKB_TMP_SEL]	= &s4_vpu_clkb_tmp_mux.hw,
+		[CLKID_VPU_CLKB_TMP_DIV]	= &s4_vpu_clkb_tmp_div.hw,
+		[CLKID_VPU_CLKB_TMP]		= &s4_vpu_clkb_tmp.hw,
+		[CLKID_VPU_CLKB_DIV]		= &s4_vpu_clkb_div.hw,
+		[CLKID_VPU_CLKB]		= &s4_vpu_clkb.hw,
+		[CLKID_VPU_CLKC_P0_SEL]		= &s4_vpu_clkc_p0_mux.hw,
+		[CLKID_VPU_CLKC_P0_DIV]		= &s4_vpu_clkc_p0_div.hw,
+		[CLKID_VPU_CLKC_P0]		= &s4_vpu_clkc_p0.hw,
+		[CLKID_VPU_CLKC_P1_SEL]		= &s4_vpu_clkc_p1_mux.hw,
+		[CLKID_VPU_CLKC_P1_DIV]		= &s4_vpu_clkc_p1_div.hw,
+		[CLKID_VPU_CLKC_P1]		= &s4_vpu_clkc_p1.hw,
+		[CLKID_VPU_CLKC_SEL]		= &s4_vpu_clkc_mux.hw,
+
+		[CLKID_VAPB_0_SEL]		= &s4_vapb_0_sel.hw,
+		[CLKID_VAPB_0_DIV]		= &s4_vapb_0_div.hw,
+		[CLKID_VAPB_0]			= &s4_vapb_0.hw,
+		[CLKID_VAPB_1_SEL]		= &s4_vapb_1_sel.hw,
+		[CLKID_VAPB_1_DIV]		= &s4_vapb_1_div.hw,
+		[CLKID_VAPB_1]			= &s4_vapb_1.hw,
+		[CLKID_VAPB]			= &s4_vapb.hw,
+
+		[CLKID_GE2D]			= &s4_ge2d_gate.hw,
+
+		[CLKID_VDIN_MEAS_SEL]		= &s4_vdin_meas_mux.hw,
+		[CLKID_VDIN_MEAS_DIV]		= &s4_vdin_meas_div.hw,
+		[CLKID_VDIN_MEAS_GATE]		= &s4_vdin_meas_gate.hw,
+
+		[CLKID_SD_EMMC_C_CLK_SEL]	= &s4_sd_emmc_c_clk0_sel.hw,
+		[CLKID_SD_EMMC_C_CLK_DIV]	= &s4_sd_emmc_c_clk0_div.hw,
+		[CLKID_SD_EMMC_C_CLK]		= &s4_sd_emmc_c_clk0.hw,
+
+		[CLKID_SD_EMMC_A_CLK_SEL]	= &s4_sd_emmc_a_clk0_sel.hw,
+		[CLKID_SD_EMMC_A_CLK_DIV]	= &s4_sd_emmc_a_clk0_div.hw,
+		[CLKID_SD_EMMC_A_CLK]		= &s4_sd_emmc_a_clk0.hw,
+		[CLKID_SD_EMMC_B_CLK_SEL]	= &s4_sd_emmc_b_clk0_sel.hw,
+		[CLKID_SD_EMMC_B_CLK_DIV]	= &s4_sd_emmc_b_clk0_div.hw,
+		[CLKID_SD_EMMC_B_CLK]		= &s4_sd_emmc_b_clk0.hw,
+
+		[CLKID_SPICC0_SEL]		= &s4_spicc0_mux.hw,
+		[CLKID_SPICC0_DIV]		= &s4_spicc0_div.hw,
+		[CLKID_SPICC0_GATE]		= &s4_spicc0_gate.hw,
+
+		[CLKID_PWM_A_SEL]		= &s4_pwm_a_mux.hw,
+		[CLKID_PWM_A_DIV]		= &s4_pwm_a_div.hw,
+		[CLKID_PWM_A_GATE]		= &s4_pwm_a_gate.hw,
+		[CLKID_PWM_B_SEL]		= &s4_pwm_b_mux.hw,
+		[CLKID_PWM_B_DIV]		= &s4_pwm_b_div.hw,
+		[CLKID_PWM_B_GATE]		= &s4_pwm_b_gate.hw,
+		[CLKID_PWM_C_SEL]		= &s4_pwm_c_mux.hw,
+		[CLKID_PWM_C_DIV]		= &s4_pwm_c_div.hw,
+		[CLKID_PWM_C_GATE]		= &s4_pwm_c_gate.hw,
+		[CLKID_PWM_D_SEL]		= &s4_pwm_d_mux.hw,
+		[CLKID_PWM_D_DIV]		= &s4_pwm_d_div.hw,
+		[CLKID_PWM_D_GATE]		= &s4_pwm_d_gate.hw,
+		[CLKID_PWM_E_SEL]		= &s4_pwm_e_mux.hw,
+		[CLKID_PWM_E_DIV]		= &s4_pwm_e_div.hw,
+		[CLKID_PWM_E_GATE]		= &s4_pwm_e_gate.hw,
+		[CLKID_PWM_F_SEL]		= &s4_pwm_f_mux.hw,
+		[CLKID_PWM_F_DIV]		= &s4_pwm_f_div.hw,
+		[CLKID_PWM_F_GATE]		= &s4_pwm_f_gate.hw,
+		[CLKID_PWM_G_SEL]		= &s4_pwm_g_mux.hw,
+		[CLKID_PWM_G_DIV]		= &s4_pwm_g_div.hw,
+		[CLKID_PWM_G_GATE]		= &s4_pwm_g_gate.hw,
+		[CLKID_PWM_H_SEL]		= &s4_pwm_h_mux.hw,
+		[CLKID_PWM_H_DIV]		= &s4_pwm_h_div.hw,
+		[CLKID_PWM_H_GATE]		= &s4_pwm_h_gate.hw,
+		[CLKID_PWM_I_SEL]		= &s4_pwm_i_mux.hw,
+		[CLKID_PWM_I_DIV]		= &s4_pwm_i_div.hw,
+		[CLKID_PWM_I_GATE]		= &s4_pwm_i_gate.hw,
+		[CLKID_PWM_J_SEL]		= &s4_pwm_j_mux.hw,
+		[CLKID_PWM_J_DIV]		= &s4_pwm_j_div.hw,
+		[CLKID_PWM_J_GATE]		= &s4_pwm_j_gate.hw,
+
+		[CLKID_SARADC_SEL]		= &s4_saradc_mux.hw,
+		[CLKID_SARADC_DIV]		= &s4_saradc_div.hw,
+		[CLKID_SARADC_GATE]		= &s4_saradc_gate.hw,
+
+		[CLKID_GEN_SEL]			= &s4_gen_clk_sel.hw,
+		[CLKID_GEN_DIV]			= &s4_gen_clk_div.hw,
+		[CLKID_GEN_GATE]		= &s4_gen_clk.hw,
+
+		[CLKID_DDR]			= &s4_ddr.hw,
+		[CLKID_DOS]			= &s4_dos.hw,
+		[CLKID_ETHPHY]			= &s4_ethphy.hw,
+		[CLKID_MALI_GATE]		= &s4_mali.hw,
+		[CLKID_AOCPU]			= &s4_aocpu.hw,
+		[CLKID_AUCPU]			= &s4_aucpu.hw,
+		[CLKID_CEC]			= &s4_cec.hw,
+		[CLKID_SD_EMMC_A]		= &s4_sdemmca.hw,
+		[CLKID_SD_EMMC_B]		= &s4_sdemmcb.hw,
+		[CLKID_NAND]			= &s4_nand.hw,
+		[CLKID_SMARTCARD]		= &s4_smartcard.hw,
+		[CLKID_ACODEC]			= &s4_acodec.hw,
+		[CLKID_SPIFC]			= &s4_spifc.hw,
+		[CLKID_MSR_CLK]			= &s4_msr_clk.hw,
+		[CLKID_IR_CTRL]			= &s4_ir_ctrl.hw,
+
+		[CLKID_AUDIO]			= &s4_audio.hw,
+		[CLKID_ETH]			= &s4_eth.hw,
+		[CLKID_UART_A]			= &s4_uart_a.hw,
+		[CLKID_UART_B]			= &s4_uart_b.hw,
+		[CLKID_UART_C]			= &s4_uart_c.hw,
+		[CLKID_UART_D]			= &s4_uart_d.hw,
+		[CLKID_UART_E]			= &s4_uart_e.hw,
+		[CLKID_AIFIFO]			= &s4_aififo.hw,
+		[CLKID_TS_DDR]			= &s4_ts_ddr.hw,
+		[CLKID_TS_PLL]			= &s4_ts_pll.hw,
+		[CLKID_G2D]			= &s4_g2d.hw,
+		[CLKID_SPICC0]			= &s4_spicc0.hw,
+		[CLKID_USB]			= &s4_usb.hw,
+		[CLKID_I2C_M_A]			= &s4_i2c_m_a.hw,
+		[CLKID_I2C_M_B]			= &s4_i2c_m_b.hw,
+		[CLKID_I2C_M_C]			= &s4_i2c_m_c.hw,
+		[CLKID_I2C_M_D]			= &s4_i2c_m_d.hw,
+		[CLKID_I2C_M_E]			= &s4_i2c_m_e.hw,
+		[CLKID_HDMITX_APB]		= &s4_hdmitx_apb.hw,
+		[CLKID_I2C_S_A]			= &s4_i2c_s_a.hw,
+		[CLKID_USB1_TO_DDR]		= &s4_usb1_to_ddr.hw,
+		[CLKID_HDCP22]			= &s4_hdcp22.hw,
+		[CLKID_MMC_APB]			= &s4_mmc_apb.hw,
+		[CLKID_RSA]			= &s4_rsa.hw,
+		[CLKID_CPU_DEBUG]		= &s4_cpu_debug.hw,
+		[CLKID_VPU_INTR]		= &s4_vpu_intr.hw,
+		[CLKID_DEMOD]			= &s4_demod.hw,
+		[CLKID_SAR_ADC]			= &s4_sar_adc.hw,
+		[CLKID_GIC]			= &s4_gic.hw,
+		[CLKID_PWM_AB]			= &s4_pwm_ab.hw,
+		[CLKID_PWM_CD]			= &s4_pwm_cd.hw,
+		[CLKID_PWM_EF]			= &s4_pwm_ef.hw,
+		[CLKID_PWM_GH]			= &s4_pwm_gh.hw,
+		[CLKID_PWM_IJ]			= &s4_pwm_ij.hw,
+
+		[CLKID_HDCP22_ESMCLK_SEL]	= &s4_hdcp22_esmclk_mux.hw,
+		[CLKID_HDCP22_ESMCLK_DIV]	= &s4_hdcp22_esmclk_div.hw,
+		[CLKID_HDCP22_ESMCLK_GATE]	= &s4_hdcp22_esmclk_gate.hw,
+		[CLKID_HDCP22_SKPCLK_SEL]	= &s4_hdcp22_skpclk_mux.hw,
+		[CLKID_HDCP22_SKPCLK_DIV]	= &s4_hdcp22_skpclk_div.hw,
+		[CLKID_HDCP22_SKPCLK_GATE]	= &s4_hdcp22_skpclk_gate.hw,
+
+		[NR_CLKS]			= NULL
+	},
+	.num = NR_CLKS,
+};
+
+/* Convenience table to populate regmap in .probe */
+static struct clk_regmap *const s4_clk_regmaps[] = {
+	&s4_rtc_32k_by_oscin_clkin,
+	&s4_rtc_32k_by_oscin_div,
+	&s4_rtc_32k_by_oscin_sel,
+	&s4_rtc_32k_by_oscin,
+	&s4_rtc_clk,
+
+	&s4_sysclk_b_sel,
+	&s4_sysclk_b_div,
+	&s4_sysclk_b,
+	&s4_sysclk_a_sel,
+	&s4_sysclk_a_div,
+	&s4_sysclk_a,
+	&s4_sys_clk,
+
+	&s4_ceca_32k_clkin,
+	&s4_ceca_32k_div,
+	&s4_ceca_32k_sel_pre,
+	&s4_ceca_32k_sel,
+	&s4_ceca_32k_clkout,
+	&s4_cecb_32k_clkin,
+	&s4_cecb_32k_div,
+	&s4_cecb_32k_sel_pre,
+	&s4_cecb_32k_sel,
+	&s4_cecb_32k_clkout,
+
+	&s4_sc_clk_mux,
+	&s4_sc_clk_div,
+	&s4_sc_clk_gate,
+
+	&s4_12_24M_clk_gate,
+	&s4_12_24M_clk,
+	&s4_vid_pll_div,
+	&s4_vid_pll_sel,
+	&s4_vid_pll,
+	&s4_vclk_sel,
+	&s4_vclk2_sel,
+	&s4_vclk_input,
+	&s4_vclk2_input,
+	&s4_vclk_div,
+	&s4_vclk2_div,
+	&s4_vclk,
+	&s4_vclk2,
+	&s4_vclk_div1,
+	&s4_vclk_div2_en,
+	&s4_vclk_div4_en,
+	&s4_vclk_div6_en,
+	&s4_vclk_div12_en,
+	&s4_vclk2_div1,
+	&s4_vclk2_div2_en,
+	&s4_vclk2_div4_en,
+	&s4_vclk2_div6_en,
+	&s4_vclk2_div12_en,
+	&s4_cts_enci_sel,
+	&s4_cts_encp_sel,
+	&s4_cts_vdac_sel,
+	&s4_hdmi_tx_sel,
+	&s4_cts_enci,
+	&s4_cts_encp,
+	&s4_cts_vdac,
+	&s4_hdmi_tx,
+
+	&s4_hdmi_sel,
+	&s4_hdmi_div,
+	&s4_hdmi,
+	&s4_ts_clk_div,
+	&s4_ts_clk_gate,
+
+	&s4_mali_0_sel,
+	&s4_mali_0_div,
+	&s4_mali_0,
+	&s4_mali_1_sel,
+	&s4_mali_1_div,
+	&s4_mali_1,
+	&s4_mali_mux,
+
+	&s4_vdec_p0_mux,
+	&s4_vdec_p0_div,
+	&s4_vdec_p0,
+	&s4_vdec_p1_mux,
+	&s4_vdec_p1_div,
+	&s4_vdec_p1,
+	&s4_vdec_mux,
+
+	&s4_hevcf_p0_mux,
+	&s4_hevcf_p0_div,
+	&s4_hevcf_p0,
+	&s4_hevcf_p1_mux,
+	&s4_hevcf_p1_div,
+	&s4_hevcf_p1,
+	&s4_hevcf_mux,
+
+	&s4_vpu_0_sel,
+	&s4_vpu_0_div,
+	&s4_vpu_0,
+	&s4_vpu_1_sel,
+	&s4_vpu_1_div,
+	&s4_vpu_1,
+	&s4_vpu,
+	&s4_vpu_clkb_tmp_mux,
+	&s4_vpu_clkb_tmp_div,
+	&s4_vpu_clkb_tmp,
+	&s4_vpu_clkb_div,
+	&s4_vpu_clkb,
+	&s4_vpu_clkc_p0_mux,
+	&s4_vpu_clkc_p0_div,
+	&s4_vpu_clkc_p0,
+	&s4_vpu_clkc_p1_mux,
+	&s4_vpu_clkc_p1_div,
+	&s4_vpu_clkc_p1,
+	&s4_vpu_clkc_mux,
+
+	&s4_vapb_0_sel,
+	&s4_vapb_0_div,
+	&s4_vapb_0,
+	&s4_vapb_1_sel,
+	&s4_vapb_1_div,
+	&s4_vapb_1,
+	&s4_vapb,
+	&s4_ge2d_gate,
+
+	&s4_hdcp22_esmclk_mux,
+	&s4_hdcp22_esmclk_div,
+	&s4_hdcp22_esmclk_gate,
+	&s4_hdcp22_skpclk_mux,
+	&s4_hdcp22_skpclk_div,
+	&s4_hdcp22_skpclk_gate,
+
+	&s4_vdin_meas_mux,
+	&s4_vdin_meas_div,
+	&s4_vdin_meas_gate,
+
+	&s4_sd_emmc_c_clk0_sel,
+	&s4_sd_emmc_c_clk0_div,
+	&s4_sd_emmc_c_clk0,
+	&s4_sd_emmc_a_clk0_sel,
+	&s4_sd_emmc_a_clk0_div,
+	&s4_sd_emmc_a_clk0,
+	&s4_sd_emmc_b_clk0_sel,
+	&s4_sd_emmc_b_clk0_div,
+	&s4_sd_emmc_b_clk0,
+
+	&s4_spicc0_mux,
+	&s4_spicc0_div,
+	&s4_spicc0_gate,
+
+	&s4_pwm_a_mux,
+	&s4_pwm_a_div,
+	&s4_pwm_a_gate,
+	&s4_pwm_b_mux,
+	&s4_pwm_b_div,
+	&s4_pwm_b_gate,
+	&s4_pwm_c_mux,
+	&s4_pwm_c_div,
+	&s4_pwm_c_gate,
+	&s4_pwm_d_mux,
+	&s4_pwm_d_div,
+	&s4_pwm_d_gate,
+	&s4_pwm_e_mux,
+	&s4_pwm_e_div,
+	&s4_pwm_e_gate,
+	&s4_pwm_f_mux,
+	&s4_pwm_f_div,
+	&s4_pwm_f_gate,
+	&s4_pwm_g_mux,
+	&s4_pwm_g_div,
+	&s4_pwm_g_gate,
+	&s4_pwm_h_mux,
+	&s4_pwm_h_div,
+	&s4_pwm_h_gate,
+	&s4_pwm_i_mux,
+	&s4_pwm_i_div,
+	&s4_pwm_i_gate,
+	&s4_pwm_j_mux,
+	&s4_pwm_j_div,
+	&s4_pwm_j_gate,
+
+	&s4_saradc_mux,
+	&s4_saradc_div,
+	&s4_saradc_gate,
+
+	&s4_gen_clk_sel,
+	&s4_gen_clk_div,
+	&s4_gen_clk,
+
+	&s4_ddr,
+	&s4_dos,
+	&s4_ethphy,
+	&s4_mali,
+	&s4_aocpu,
+	&s4_aucpu,
+	&s4_cec,
+	&s4_sdemmca,
+	&s4_sdemmcb,
+	&s4_nand,
+	&s4_smartcard,
+	&s4_acodec,
+	&s4_spifc,
+	&s4_msr_clk,
+	&s4_ir_ctrl,
+	&s4_audio,
+	&s4_eth,
+	&s4_uart_a,
+	&s4_uart_b,
+	&s4_uart_c,
+	&s4_uart_d,
+	&s4_uart_e,
+	&s4_aififo,
+	&s4_ts_ddr,
+	&s4_ts_pll,
+	&s4_g2d,
+	&s4_spicc0,
+	&s4_usb,
+	&s4_i2c_m_a,
+	&s4_i2c_m_b,
+	&s4_i2c_m_c,
+	&s4_i2c_m_d,
+	&s4_i2c_m_e,
+	&s4_hdmitx_apb,
+	&s4_i2c_s_a,
+	&s4_usb1_to_ddr,
+	&s4_hdcp22,
+	&s4_mmc_apb,
+	&s4_rsa,
+	&s4_cpu_debug,
+	&s4_vpu_intr,
+	&s4_demod,
+	&s4_sar_adc,
+	&s4_gic,
+	&s4_pwm_ab,
+	&s4_pwm_cd,
+	&s4_pwm_ef,
+	&s4_pwm_gh,
+	&s4_pwm_ij,
+	&s4_demod_core_clk_mux,
+	&s4_demod_core_clk_div,
+	&s4_demod_core_clk_gate,
+	&s4_adc_extclk_in_mux,
+	&s4_adc_extclk_in_div,
+	&s4_adc_extclk_in_gate,
+};
+
+static struct clk_regmap *const s4_pll_clk_regmaps[] = {
+	&s4_fixed_pll_dco,
+	&s4_fixed_pll,
+	&s4_fclk_div2,
+	&s4_fclk_div3,
+	&s4_fclk_div4,
+	&s4_fclk_div5,
+	&s4_fclk_div7,
+	&s4_fclk_div2p5,
+	&s4_gp0_pll_dco,
+	&s4_gp0_pll,
+	&s4_hifi_pll_dco,
+	&s4_hifi_pll,
+	&s4_hdmi_pll_dco,
+	&s4_hdmi_pll_od,
+	&s4_hdmi_pll,
+	&s4_mpll_50m,
+	&s4_mpll0_div,
+	&s4_mpll0,
+	&s4_mpll1_div,
+	&s4_mpll1,
+	&s4_mpll2_div,
+	&s4_mpll2,
+	&s4_mpll3_div,
+	&s4_mpll3,
+};
+
+static const struct reg_sequence s4_init_regs[] = {
+	{ .reg = ANACTRL_MPLL_CTRL0,	.def = 0x00000543 },
+};
+
+static struct regmap_config clkc_regmap_config = {
+	.reg_bits       = 32,
+	.val_bits       = 32,
+	.reg_stride     = 4,
+};
+
+static struct regmap *s4_regmap_resource(struct device *dev, char *name)
+{
+	struct resource res;
+	void __iomem *base;
+	int i;
+	struct device_node *node = dev->of_node;
+
+	i = of_property_match_string(node, "reg-names", name);
+	if (of_address_to_resource(node, i, &res))
+		return ERR_PTR(-ENOENT);
+
+	base = devm_ioremap_resource(dev, &res);
+	if (IS_ERR(base))
+		return ERR_CAST(base);
+
+	clkc_regmap_config.max_register = resource_size(&res) - 4;
+	clkc_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL,
+						 "%s-%s", node->name,
+						 name);
+	if (!clkc_regmap_config.name)
+		return ERR_PTR(-ENOMEM);
+
+	return devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
+}
+
+static int meson_s4_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct regmap *basic_map;
+	struct regmap *pll_map;
+	const struct clk_hw_onecell_data *hw_onecell_data;
+	int ret, i;
+
+	hw_onecell_data = of_device_get_match_data(&pdev->dev);
+	if (!hw_onecell_data)
+		return -EINVAL;
+
+	/* Get regmap for different clock area */
+	basic_map = s4_regmap_resource(dev, "basic");
+	if (IS_ERR(basic_map)) {
+		dev_err(dev, "basic clk registers not found\n");
+		return PTR_ERR(basic_map);
+	}
+
+	pll_map = s4_regmap_resource(dev, "pll");
+	if (IS_ERR(pll_map)) {
+		dev_err(dev, "pll clk registers not found\n");
+		return PTR_ERR(pll_map);
+	}
+
+	ret = regmap_multi_reg_write(pll_map, s4_init_regs, ARRAY_SIZE(s4_init_regs));
+	if (ret) {
+		dev_err(dev, "Failed to init registers\n");
+		return ret;
+	}
+
+	/* Populate regmap for the regmap backed clocks */
+	for (i = 0; i < ARRAY_SIZE(s4_clk_regmaps); i++)
+		s4_clk_regmaps[i]->map = basic_map;
+
+	for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
+		s4_pll_clk_regmaps[i]->map = pll_map;
+
+	for (i = 0; i < hw_onecell_data->num; i++) {
+		/* array might be sparse */
+		if (!hw_onecell_data->hws[i])
+			continue;
+		ret = devm_clk_hw_register(dev, hw_onecell_data->hws[i]);
+		if (ret) {
+			dev_err(dev, "Clock registration failed\n");
+			return ret;
+		}
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+					   (void *)hw_onecell_data);
+}
+
+static const struct of_device_id clkc_match_table[] = {
+	{
+		.compatible = "amlogic,s4-clkc",
+		.data = &s4_hw_onecell_data
+	},
+	{}
+};
+
+static struct platform_driver s4_driver = {
+	.probe		= meson_s4_probe,
+	.driver		= {
+		.name	= "s4-clkc",
+		.of_match_table = clkc_match_table,
+	},
+};
+
+module_platform_driver(s4_driver);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/meson/s4.h b/drivers/clk/meson/s4.h
new file mode 100644
index 000000000000..be11316ba244
--- /dev/null
+++ b/drivers/clk/meson/s4.h
@@ -0,0 +1,296 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, inc.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef __MESON_S4_H__
+#define __MESON_S4_H__
+
+/*
+ * Clock controller register offsets
+ * REG_BASE:  REGISTER_BASE_ADDR = 0xfe000000
+ */
+#define CLKCTRL_OSCIN_CTRL                         (0x0001 << 2)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL0                 (0x0002 << 2)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL1                 (0x0003 << 2)
+#define CLKCTRL_RTC_CTRL                           (0x0004 << 2)
+#define CLKCTRL_CHECK_CLK_RESULT                   (0x0005 << 2)
+#define CLKCTRL_MBIST_ATSPEED_CTRL                 (0x0006 << 2)
+#define CLKCTRL_LOCK_BIT_REG0                      (0x0008 << 2)
+#define CLKCTRL_LOCK_BIT_REG1                      (0x0009 << 2)
+#define CLKCTRL_LOCK_BIT_REG2                      (0x000a << 2)
+#define CLKCTRL_LOCK_BIT_REG3                      (0x000b << 2)
+#define CLKCTRL_PROT_BIT_REG0                      (0x000c << 2)
+#define CLKCTRL_PROT_BIT_REG1                      (0x000d << 2)
+#define CLKCTRL_PROT_BIT_REG2                      (0x000e << 2)
+#define CLKCTRL_PROT_BIT_REG3                      (0x000f << 2)
+#define CLKCTRL_SYS_CLK_CTRL0                      (0x0010 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG0                   (0x0011 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG1                   (0x0012 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG2                   (0x0013 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG3                   (0x0014 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG0                   (0x0015 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG1                   (0x0016 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG2                   (0x0017 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG3                   (0x0018 << 2)
+#define CLKCTRL_SYS_CLK_VPU_EN0                    (0x0019 << 2)
+#define CLKCTRL_SYS_CLK_VPU_EN1                    (0x001a << 2)
+#define CLKCTRL_AXI_CLK_CTRL0                      (0x001b << 2)
+#define CLKCTRL_TST_CTRL0                          (0x0020 << 2)
+#define CLKCTRL_TST_CTRL1                          (0x0021 << 2)
+#define CLKCTRL_CECA_CTRL0                         (0x0022 << 2)
+#define CLKCTRL_CECA_CTRL1                         (0x0023 << 2)
+#define CLKCTRL_CECB_CTRL0                         (0x0024 << 2)
+#define CLKCTRL_CECB_CTRL1                         (0x0025 << 2)
+#define CLKCTRL_SC_CLK_CTRL                        (0x0026 << 2)
+#define CLKCTRL_DSPA_CLK_CTRL0                     (0x0027 << 2)
+#define CLKCTRL_DSPB_CLK_CTRL0                     (0x0028 << 2)
+#define CLKCTRL_RAMA_CLK_CTRL0                     (0x0029 << 2)
+#define CLKCTRL_CLK12_24_CTRL                      (0x002a << 2)
+#define CLKCTRL_VID_CLK_CTRL                       (0x0030 << 2)
+#define CLKCTRL_VID_CLK_CTRL2                      (0x0031 << 2)
+#define CLKCTRL_VID_CLK_DIV                        (0x0032 << 2)
+#define CLKCTRL_VIID_CLK_DIV                       (0x0033 << 2)
+#define CLKCTRL_VIID_CLK_CTRL                      (0x0034 << 2)
+#define CLKCTRL_HDMI_CLK_CTRL                      (0x0038 << 2)
+#define CLKCTRL_VID_PLL_CLK_DIV                    (0x0039 << 2)
+#define CLKCTRL_VPU_CLK_CTRL                       (0x003a << 2)
+#define CLKCTRL_VPU_CLKB_CTRL                      (0x003b << 2)
+#define CLKCTRL_VPU_CLKC_CTRL                      (0x003c << 2)
+#define CLKCTRL_VID_LOCK_CLK_CTRL                  (0x003d << 2)
+#define CLKCTRL_VDIN_MEAS_CLK_CTRL                 (0x003e << 2)
+#define CLKCTRL_VAPBCLK_CTRL                       (0x003f << 2)
+#define CLKCTRL_HDCP22_CTRL                        (0x0040 << 2)
+#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL               (0x0041 << 2)
+#define CLKCTRL_CDAC_CLK_CTRL                      (0x0042 << 2)
+#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL              (0x0043 << 2)
+#define CLKCTRL_CSI2_ADAPT_CLK_CTRL                (0x0044 << 2)
+#define CLKCTRL_VDEC_CLK_CTRL                      (0x0050 << 2)
+#define CLKCTRL_VDEC2_CLK_CTRL                     (0x0051 << 2)
+#define CLKCTRL_VDEC3_CLK_CTRL                     (0x0052 << 2)
+#define CLKCTRL_VDEC4_CLK_CTRL                     (0x0053 << 2)
+#define CLKCTRL_WAVE420L_CLK_CTRL                  (0x0054 << 2)
+#define CLKCTRL_WAVE420L_CLK_CTRL2                 (0x0055 << 2)
+#define CLKCTRL_TS_CLK_CTRL                        (0x0056 << 2)
+#define CLKCTRL_MALI_CLK_CTRL                      (0x0057 << 2)
+#define CLKCTRL_VIPNANOQ_CLK_CTRL                  (0x0058 << 2)
+#define CLKCTRL_ETH_CLK_CTRL                       (0x0059 << 2)
+#define CLKCTRL_NAND_CLK_CTRL                      (0x005a << 2)
+#define CLKCTRL_SD_EMMC_CLK_CTRL                   (0x005b << 2)
+#define CLKCTRL_BT656_CLK_CTRL                     (0x005c << 2)
+#define CLKCTRL_SPICC_CLK_CTRL                     (0x005d << 2)
+#define CLKCTRL_GEN_CLK_CTRL                       (0x005e << 2)
+#define CLKCTRL_SAR_CLK_CTRL                       (0x005f << 2)
+#define CLKCTRL_PWM_CLK_AB_CTRL                    (0x0060 << 2)
+#define CLKCTRL_PWM_CLK_CD_CTRL                    (0x0061 << 2)
+#define CLKCTRL_PWM_CLK_EF_CTRL                    (0x0062 << 2)
+#define CLKCTRL_PWM_CLK_GH_CTRL                    (0x0063 << 2)
+#define CLKCTRL_PWM_CLK_IJ_CTRL                    (0x0064 << 2)
+#define CLKCTRL_DEMOD_CLK_CTRL                     (0x0080 << 2)
+#define CLKCTRL_DEMOD_CLK_CTRL1                    (0x0081 << 2)
+#define CLKCTRL_DEMOD_32K_CTRL0                    (0x0082 << 2)
+#define CLKCTRL_DEMOD_32K_CTRL1                    (0x0083 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL                     (0x0100 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL1                    (0x0101 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL2                    (0x0103 << 2)
+#define CLKCTRL_TIMESTAMP_RD0                      (0x0104 << 2)
+#define CLKCTRL_TIMESTAMP_RD1                      (0x0105 << 2)
+#define CLKCTRL_TIMEBASE_CTRL0                     (0x0106 << 2)
+#define CLKCTRL_TIMEBASE_CTRL1                     (0x0107 << 2)
+#define CLKCTRL_EFUSE_CPU_CFG01                    (0x0120 << 2)
+#define CLKCTRL_EFUSE_CPU_CFG2                     (0x0121 << 2)
+#define CLKCTRL_EFUSE_ENCP_CFG0                    (0x0122 << 2)
+#define CLKCTRL_EFUSE_MALI_CFG01                   (0x0123 << 2)
+#define CLKCTRL_EFUSE_HEVCB_CFG01                  (0x0124 << 2)
+#define CLKCTRL_EFUSE_HEVCB_CFG2                   (0x0125 << 2)
+#define CLKCTRL_EFUSE_LOCK                         (0x0126 << 2)
+
+/* ANA_CTRL - Registers
+ * REG_BASE:  REGISTER_BASE_ADDR = 0xfe008000
+ */
+#define ANACTRL_FIXPLL_CTRL0                       (0x0010 << 2)
+#define ANACTRL_FIXPLL_CTRL1                       (0x0011 << 2)
+#define ANACTRL_FIXPLL_CTRL2                       (0x0012 << 2)
+#define ANACTRL_FIXPLL_CTRL3                       (0x0013 << 2)
+#define ANACTRL_FIXPLL_CTRL4                       (0x0014 << 2)
+#define ANACTRL_FIXPLL_CTRL5                       (0x0015 << 2)
+#define ANACTRL_FIXPLL_CTRL6                       (0x0016 << 2)
+#define ANACTRL_FIXPLL_STS                         (0x0017 << 2)
+#define ANACTRL_GP0PLL_CTRL0                       (0x0020 << 2)
+#define ANACTRL_GP0PLL_CTRL1                       (0x0021 << 2)
+#define ANACTRL_GP0PLL_CTRL2                       (0x0022 << 2)
+#define ANACTRL_GP0PLL_CTRL3                       (0x0023 << 2)
+#define ANACTRL_GP0PLL_CTRL4                       (0x0024 << 2)
+#define ANACTRL_GP0PLL_CTRL5                       (0x0025 << 2)
+#define ANACTRL_GP0PLL_CTRL6                       (0x0026 << 2)
+#define ANACTRL_GP0PLL_STS                         (0x0027 << 2)
+#define ANACTRL_HIFIPLL_CTRL0                      (0x0040 << 2)
+#define ANACTRL_HIFIPLL_CTRL1                      (0x0041 << 2)
+#define ANACTRL_HIFIPLL_CTRL2                      (0x0042 << 2)
+#define ANACTRL_HIFIPLL_CTRL3                      (0x0043 << 2)
+#define ANACTRL_HIFIPLL_CTRL4                      (0x0044 << 2)
+#define ANACTRL_HIFIPLL_CTRL5                      (0x0045 << 2)
+#define ANACTRL_HIFIPLL_CTRL6                      (0x0046 << 2)
+#define ANACTRL_HIFIPLL_STS                        (0x0047 << 2)
+#define ANACTRL_MPLL_CTRL0                         (0x0060 << 2)
+#define ANACTRL_MPLL_CTRL1                         (0x0061 << 2)
+#define ANACTRL_MPLL_CTRL2                         (0x0062 << 2)
+#define ANACTRL_MPLL_CTRL3                         (0x0063 << 2)
+#define ANACTRL_MPLL_CTRL4                         (0x0064 << 2)
+#define ANACTRL_MPLL_CTRL5                         (0x0065 << 2)
+#define ANACTRL_MPLL_CTRL6                         (0x0066 << 2)
+#define ANACTRL_MPLL_CTRL7                         (0x0067 << 2)
+#define ANACTRL_MPLL_CTRL8                         (0x0068 << 2)
+#define ANACTRL_MPLL_STS                           (0x0069 << 2)
+#define ANACTRL_HDMIPLL_CTRL0                      (0x0070 << 2)
+#define ANACTRL_HDMIPLL_CTRL1                      (0x0071 << 2)
+#define ANACTRL_HDMIPLL_CTRL2                      (0x0072 << 2)
+#define ANACTRL_HDMIPLL_CTRL3                      (0x0073 << 2)
+#define ANACTRL_HDMIPLL_CTRL4                      (0x0074 << 2)
+#define ANACTRL_HDMIPLL_CTRL5                      (0x0075 << 2)
+#define ANACTRL_HDMIPLL_CTRL6                      (0x0076 << 2)
+#define ANACTRL_HDMIPLL_STS                        (0x0077 << 2)
+#define ANACTRL_HDMIPLL_VLOCK                      (0x0079 << 2)
+
+/*
+ * CLKID index values
+ *
+ * These indices are entirely contrived and do not map onto the hardware.
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
+ * to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
+ */
+#define CLKID_FIXED_PLL_DCO		0
+#define CLKID_FCLK_DIV2_DIV		2
+#define CLKID_FCLK_DIV3_DIV		4
+#define CLKID_FCLK_DIV4_DIV		6
+#define CLKID_FCLK_DIV5_DIV		8
+#define CLKID_FCLK_DIV7_DIV		10
+#define CLKID_FCLK_DIV2P5_DIV		12
+#define CLKID_GP0_PLL_DCO		14
+#define CLKID_HIFI_PLL_DCO		16
+#define CLKID_HDMI_PLL_DCO		18
+#define CLKID_HDMI_PLL_OD		19
+#define CLKID_MPLL_50M_DIV		21
+#define CLKID_MPLL_PREDIV		23
+#define CLKID_MPLL0_DIV			24
+#define CLKID_MPLL1_DIV			26
+#define CLKID_MPLL2_DIV			28
+#define CLKID_MPLL3_DIV			30
+#define CLKID_RTC_32K_CLKIN		32
+#define CLKID_RTC_32K_DIV		33
+#define CLKID_RTC_32K_SEL		34
+#define CLKID_RTC_32K_XATL		35
+#define CLKID_SYS_CLK_B_SEL		37
+#define CLKID_SYS_CLK_B_DIV		38
+#define CLKID_SYS_CLK_A_SEL		40
+#define CLKID_SYS_CLK_A_DIV		41
+#define CLKID_CECA_32K_CLKIN		44
+#define CLKID_CECA_32K_DIV		45
+#define CLKID_CECA_32K_SEL_PRE		46
+#define CLKID_CECA_32K_SEL		47
+#define CLKID_CECB_32K_CLKIN		49
+#define CLKID_CECB_32K_DIV		50
+#define CLKID_CECB_32K_SEL_PRE		51
+#define CLKID_CECB_32K_SEL		52
+#define CLKID_SC_CLK_SEL		54
+#define CLKID_SC_CLK_DIV		55
+#define CLKID_12_24M_CLK_GATE		57
+#define CLKID_12M_CLK_DIV		58
+#define CLKID_VID_PLL_DIV		60
+#define CLKID_VID_PLL_SEL		61
+#define CLKID_VCLK_SEL			63
+#define CLKID_VCLK2_SEL			64
+#define CLKID_VCLK_INPUT		65
+#define CLKID_VCLK2_INPUT		66
+#define CLKID_VCLK_DIV			67
+#define CLKID_VCLK2_DIV			68
+#define CLKID_VCLK_DIV2_EN		72
+#define CLKID_VCLK_DIV4_EN		73
+#define CLKID_VCLK_DIV6_EN		74
+#define CLKID_VCLK_DIV12_EN		75
+#define CLKID_VCLK2_DIV2_EN		77
+#define CLKID_VCLK2_DIV4_EN		78
+#define CLKID_VCLK2_DIV6_EN		79
+#define CLKID_VCLK2_DIV12_EN		80
+#define CLKID_CTS_ENCI_SEL		89
+#define CLKID_CTS_ENCP_SEL		90
+#define CLKID_CTS_VDAC_SEL		91
+#define CLKID_HDMI_TX_SEL		92
+#define CLKID_HDMI_TX			96
+#define CLKID_HDMI_SEL			97
+#define CLKID_HDMI_DIV			98
+#define CLKID_TS_CLK_DIV		100
+#define CLKID_MALI_0_SEL		102
+#define CLKID_MALI_0_DIV		103
+#define CLKID_MALI_1_SEL		105
+#define CLKID_MALI_1_DIV		106
+#define CLKID_VDEC_P0_SEL		109
+#define CLKID_VDEC_P0_DIV		110
+#define CLKID_VDEC_P1_SEL		112
+#define CLKID_VDEC_P1_DIV		113
+#define CLKID_HEVCF_P0_SEL		116
+#define CLKID_HEVCF_P0_DIV		117
+#define CLKID_HEVCF_P1_SEL		119
+#define CLKID_HEVCF_P1_DIV		120
+#define CLKID_VPU_0_SEL			123
+#define CLKID_VPU_0_DIV			124
+#define CLKID_VPU_1_SEL			126
+#define CLKID_VPU_1_DIV			127
+#define CLKID_VPU_CLKB_TMP_SEL		130
+#define CLKID_VPU_CLKB_TMP_DIV		131
+#define CLKID_VPU_CLKB_DIV		133
+#define CLKID_VPU_CLKC_P0_SEL		135
+#define CLKID_VPU_CLKC_P0_DIV		136
+#define CLKID_VPU_CLKC_P1_SEL		138
+#define CLKID_VPU_CLKC_P1_DIV		139
+#define CLKID_VAPB_0_SEL		142
+#define CLKID_VAPB_0_DIV		143
+#define CLKID_VAPB_1_SEL		145
+#define CLKID_VAPB_1_DIV		146
+#define CLKID_VDIN_MEAS_SEL		150
+#define CLKID_VDIN_MEAS_DIV		151
+#define CLKID_SD_EMMC_C_CLK_SEL		153
+#define CLKID_SD_EMMC_C_CLK_DIV		154
+#define CLKID_SD_EMMC_A_CLK_SEL		156
+#define CLKID_SD_EMMC_A_CLK_DIV		157
+#define CLKID_SD_EMMC_B_CLK_SEL		159
+#define CLKID_SD_EMMC_B_CLK_DIV		160
+#define CLKID_SPICC0_SEL		162
+#define CLKID_SPICC0_DIV		163
+#define CLKID_PWM_A_SEL			165
+#define CLKID_PWM_A_DIV			166
+#define CLKID_PWM_B_SEL			168
+#define CLKID_PWM_B_DIV			169
+#define CLKID_PWM_C_SEL			171
+#define CLKID_PWM_C_DIV			172
+#define CLKID_PWM_D_SEL			174
+#define CLKID_PWM_D_DIV			175
+#define CLKID_PWM_E_SEL			177
+#define CLKID_PWM_E_DIV			178
+#define CLKID_PWM_F_SEL			180
+#define CLKID_PWM_F_DIV			181
+#define CLKID_PWM_G_SEL			183
+#define CLKID_PWM_G_DIV			184
+#define CLKID_PWM_H_SEL			186
+#define CLKID_PWM_H_DIV			187
+#define CLKID_PWM_I_SEL			189
+#define CLKID_PWM_I_DIV			190
+#define CLKID_PWM_J_SEL			192
+#define CLKID_PWM_J_DIV			193
+#define CLKID_SARADC_SEL		195
+#define CLKID_SARADC_DIV		196
+#define CLKID_GEN_SEL			198
+#define CLKID_GEN_DIV			199
+#define CLKID_HDCP22_ESMCLK_SEL		251
+#define CLKID_HDCP22_ESMCLK_DIV		252
+#define CLKID_HDCP22_SKPCLK_SEL		254
+#define CLKID_HDCP22_SKPCLK_DIV		255
+
+#define NR_CLKS				257
+/* include the CLKIDs that have been made part of the DT binding */
+#include <dt-bindings/clock/s4-clkc.h>
+
+#endif /* __MESON_S4_H__ */
-- 
2.33.1


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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:

> 1. Add clock controller driver for S4 SOC.
>
> Yu Tu (3):
>   dt-bindings: clk: meson: add S4 SoC clock controller bindings
>   arm64: dts: meson: add S4 Soc clock controller in DT
>   clk: meson: s4: add s4 SoC clock controller driver
>
> V1 -> V2: Change format as discussed in the email.
>
> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>
>  .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>  MAINTAINERS                                   |    1 +
>  arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>  drivers/clk/meson/Kconfig                     |   15 +
>  drivers/clk/meson/Makefile                    |    1 +
>  drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>  drivers/clk/meson/s4.h                        |  296 ++
>  include/dt-bindings/clock/s4-clkc.h           |  146 +
>  8 files changed, 5203 insertions(+)
>  create mode 100644 drivers/clk/meson/s4.c
>  create mode 100644 drivers/clk/meson/s4.h
>  create mode 100644 include/dt-bindings/clock/s4-clkc.h
>
>
> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6

Please don't post until you have addressed *ALL* the comments from the
previous version.

At first glance, I can see that this is still a single driver for
what is obviously 2 controllers with 2 register spaces. Simple comments
like the "<< 2" in the register declaration have not been addressed either.

Seeing that, I have not reviewed this version further.
I won't until all the comments from v1 are either addressed or answered.

Regards
Jerome

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:

> 1. Add clock controller driver for S4 SOC.
>
> Yu Tu (3):
>   dt-bindings: clk: meson: add S4 SoC clock controller bindings
>   arm64: dts: meson: add S4 Soc clock controller in DT
>   clk: meson: s4: add s4 SoC clock controller driver
>
> V1 -> V2: Change format as discussed in the email.
>
> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>
>  .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>  MAINTAINERS                                   |    1 +
>  arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>  drivers/clk/meson/Kconfig                     |   15 +
>  drivers/clk/meson/Makefile                    |    1 +
>  drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>  drivers/clk/meson/s4.h                        |  296 ++
>  include/dt-bindings/clock/s4-clkc.h           |  146 +
>  8 files changed, 5203 insertions(+)
>  create mode 100644 drivers/clk/meson/s4.c
>  create mode 100644 drivers/clk/meson/s4.h
>  create mode 100644 include/dt-bindings/clock/s4-clkc.h
>
>
> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6

Please don't post until you have addressed *ALL* the comments from the
previous version.

At first glance, I can see that this is still a single driver for
what is obviously 2 controllers with 2 register spaces. Simple comments
like the "<< 2" in the register declaration have not been addressed either.

Seeing that, I have not reviewed this version further.
I won't until all the comments from v1 are either addressed or answered.

Regards
Jerome

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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:

> 1. Add clock controller driver for S4 SOC.
>
> Yu Tu (3):
>   dt-bindings: clk: meson: add S4 SoC clock controller bindings
>   arm64: dts: meson: add S4 Soc clock controller in DT
>   clk: meson: s4: add s4 SoC clock controller driver
>
> V1 -> V2: Change format as discussed in the email.
>
> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>
>  .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>  MAINTAINERS                                   |    1 +
>  arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>  drivers/clk/meson/Kconfig                     |   15 +
>  drivers/clk/meson/Makefile                    |    1 +
>  drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>  drivers/clk/meson/s4.h                        |  296 ++
>  include/dt-bindings/clock/s4-clkc.h           |  146 +
>  8 files changed, 5203 insertions(+)
>  create mode 100644 drivers/clk/meson/s4.c
>  create mode 100644 drivers/clk/meson/s4.h
>  create mode 100644 include/dt-bindings/clock/s4-clkc.h
>
>
> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6

Please don't post until you have addressed *ALL* the comments from the
previous version.

At first glance, I can see that this is still a single driver for
what is obviously 2 controllers with 2 register spaces. Simple comments
like the "<< 2" in the register declaration have not been addressed either.

Seeing that, I have not reviewed this version further.
I won't until all the comments from v1 are either addressed or answered.

Regards
Jerome

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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi JB，

On 2022/7/28 15:08, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> 1. Add clock controller driver for S4 SOC.
>>
>> Yu Tu (3):
>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>    clk: meson: s4: add s4 SoC clock controller driver
>>
>> V1 -> V2: Change format as discussed in the email.
>>
>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>
>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>   MAINTAINERS                                   |    1 +
>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>   drivers/clk/meson/Kconfig                     |   15 +
>>   drivers/clk/meson/Makefile                    |    1 +
>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>   drivers/clk/meson/s4.h                        |  296 ++
>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>   8 files changed, 5203 insertions(+)
>>   create mode 100644 drivers/clk/meson/s4.c
>>   create mode 100644 drivers/clk/meson/s4.h
>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>
>>
>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
> 
> Please don't post until you have addressed *ALL* the comments from the
> previous version.
The last email asked you to adopt A1 method, but you did not reply?

> 
> At first glance, I can see that this is still a single driver for
> what is obviously 2 controllers with 2 register spaces. Simple comments
> like the "<< 2" in the register declaration have not been addressed either.
I understand that this should be a controller, just two address 
descriptions. One is the various PLL registers and one is the clock for 
the peripherals. And PLL is to provide a clock source for various 
peripheral clocks. So a clock controller is reasonable. I think you got 
it wrong.

Ok, if you insist on using two clock controllers,, please provide your 
the reason and example code?

> 
> Seeing that, I have not reviewed this version further.
> I won't until all the comments from v1 are either addressed or answer
> 
> Regards
> Jerome
> 
> .

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi JB，

On 2022/7/28 15:08, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> 1. Add clock controller driver for S4 SOC.
>>
>> Yu Tu (3):
>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>    clk: meson: s4: add s4 SoC clock controller driver
>>
>> V1 -> V2: Change format as discussed in the email.
>>
>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>
>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>   MAINTAINERS                                   |    1 +
>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>   drivers/clk/meson/Kconfig                     |   15 +
>>   drivers/clk/meson/Makefile                    |    1 +
>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>   drivers/clk/meson/s4.h                        |  296 ++
>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>   8 files changed, 5203 insertions(+)
>>   create mode 100644 drivers/clk/meson/s4.c
>>   create mode 100644 drivers/clk/meson/s4.h
>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>
>>
>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
> 
> Please don't post until you have addressed *ALL* the comments from the
> previous version.
The last email asked you to adopt A1 method, but you did not reply?

> 
> At first glance, I can see that this is still a single driver for
> what is obviously 2 controllers with 2 register spaces. Simple comments
> like the "<< 2" in the register declaration have not been addressed either.
I understand that this should be a controller, just two address 
descriptions. One is the various PLL registers and one is the clock for 
the peripherals. And PLL is to provide a clock source for various 
peripheral clocks. So a clock controller is reasonable. I think you got 
it wrong.

Ok, if you insist on using two clock controllers,, please provide your 
the reason and example code?

> 
> Seeing that, I have not reviewed this version further.
> I won't until all the comments from v1 are either addressed or answer
> 
> Regards
> Jerome
> 
> .

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi JB，

On 2022/7/28 15:08, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> 1. Add clock controller driver for S4 SOC.
>>
>> Yu Tu (3):
>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>    clk: meson: s4: add s4 SoC clock controller driver
>>
>> V1 -> V2: Change format as discussed in the email.
>>
>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>
>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>   MAINTAINERS                                   |    1 +
>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>   drivers/clk/meson/Kconfig                     |   15 +
>>   drivers/clk/meson/Makefile                    |    1 +
>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>   drivers/clk/meson/s4.h                        |  296 ++
>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>   8 files changed, 5203 insertions(+)
>>   create mode 100644 drivers/clk/meson/s4.c
>>   create mode 100644 drivers/clk/meson/s4.h
>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>
>>
>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
> 
> Please don't post until you have addressed *ALL* the comments from the
> previous version.
The last email asked you to adopt A1 method, but you did not reply?

> 
> At first glance, I can see that this is still a single driver for
> what is obviously 2 controllers with 2 register spaces. Simple comments
> like the "<< 2" in the register declaration have not been addressed either.
I understand that this should be a controller, just two address 
descriptions. One is the various PLL registers and one is the clock for 
the peripherals. And PLL is to provide a clock source for various 
peripheral clocks. So a clock controller is reasonable. I think you got 
it wrong.

Ok, if you insist on using two clock controllers,, please provide your 
the reason and example code?

> 
> Seeing that, I have not reviewed this version further.
> I won't until all the comments from v1 are either addressed or answer
> 
> Regards
> Jerome
> 
> .

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi JB,
	We suspect that you are not looking carefully. You only see two base 
addresses for controllers, so you think you should use two clock 
controllers. But you're missing their direct connection.

On 2022/7/28 16:06, Yu Tu wrote:
> Hi JB，
> 
> On 2022/7/28 15:08, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>>
>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>
>>> 1. Add clock controller driver for S4 SOC.
>>>
>>> Yu Tu (3):
>>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>>    clk: meson: s4: add s4 SoC clock controller driver
>>>
>>> V1 -> V2: Change format as discussed in the email.
>>>
>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/ 
>>>
>>>
>>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>   MAINTAINERS                                   |    1 +
>>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>   drivers/clk/meson/Kconfig                     |   15 +
>>>   drivers/clk/meson/Makefile                    |    1 +
>>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>   drivers/clk/meson/s4.h                        |  296 ++
>>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>   8 files changed, 5203 insertions(+)
>>>   create mode 100644 drivers/clk/meson/s4.c
>>>   create mode 100644 drivers/clk/meson/s4.h
>>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>
>>>
>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>
>> Please don't post until you have addressed *ALL* the comments from the
>> previous version.
> The last email asked you to adopt A1 method, but you did not reply?
> 
>>
>> At first glance, I can see that this is still a single driver for
>> what is obviously 2 controllers with 2 register spaces. Simple comments
>> like the "<< 2" in the register declaration have not been addressed 
>> either.
> I understand that this should be a controller, just two address 
> descriptions. One is the various PLL registers and one is the clock for 
> the peripherals. And PLL is to provide a clock source for various 
> peripheral clocks. So a clock controller is reasonable. I think you got 
> it wrong.
> 
> Ok, if you insist on using two clock controllers,, please provide your 
> the reason and example code?
> 
>>
>> Seeing that, I have not reviewed this version further.
>> I won't until all the comments from v1 are either addressed or answer
>>
>> Regards
>> Jerome
>>
>> .

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi JB,
	We suspect that you are not looking carefully. You only see two base 
addresses for controllers, so you think you should use two clock 
controllers. But you're missing their direct connection.

On 2022/7/28 16:06, Yu Tu wrote:
> Hi JB，
> 
> On 2022/7/28 15:08, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>>
>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>
>>> 1. Add clock controller driver for S4 SOC.
>>>
>>> Yu Tu (3):
>>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>>    clk: meson: s4: add s4 SoC clock controller driver
>>>
>>> V1 -> V2: Change format as discussed in the email.
>>>
>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/ 
>>>
>>>
>>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>   MAINTAINERS                                   |    1 +
>>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>   drivers/clk/meson/Kconfig                     |   15 +
>>>   drivers/clk/meson/Makefile                    |    1 +
>>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>   drivers/clk/meson/s4.h                        |  296 ++
>>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>   8 files changed, 5203 insertions(+)
>>>   create mode 100644 drivers/clk/meson/s4.c
>>>   create mode 100644 drivers/clk/meson/s4.h
>>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>
>>>
>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>
>> Please don't post until you have addressed *ALL* the comments from the
>> previous version.
> The last email asked you to adopt A1 method, but you did not reply?
> 
>>
>> At first glance, I can see that this is still a single driver for
>> what is obviously 2 controllers with 2 register spaces. Simple comments
>> like the "<< 2" in the register declaration have not been addressed 
>> either.
> I understand that this should be a controller, just two address 
> descriptions. One is the various PLL registers and one is the clock for 
> the peripherals. And PLL is to provide a clock source for various 
> peripheral clocks. So a clock controller is reasonable. I think you got 
> it wrong.
> 
> Ok, if you insist on using two clock controllers,, please provide your 
> the reason and example code?
> 
>>
>> Seeing that, I have not reviewed this version further.
>> I won't until all the comments from v1 are either addressed or answer
>>
>> Regards
>> Jerome
>>
>> .

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi JB,
	We suspect that you are not looking carefully. You only see two base 
addresses for controllers, so you think you should use two clock 
controllers. But you're missing their direct connection.

On 2022/7/28 16:06, Yu Tu wrote:
> Hi JB，
> 
> On 2022/7/28 15:08, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>>
>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>
>>> 1. Add clock controller driver for S4 SOC.
>>>
>>> Yu Tu (3):
>>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>>    clk: meson: s4: add s4 SoC clock controller driver
>>>
>>> V1 -> V2: Change format as discussed in the email.
>>>
>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/ 
>>>
>>>
>>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>   MAINTAINERS                                   |    1 +
>>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>   drivers/clk/meson/Kconfig                     |   15 +
>>>   drivers/clk/meson/Makefile                    |    1 +
>>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>   drivers/clk/meson/s4.h                        |  296 ++
>>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>   8 files changed, 5203 insertions(+)
>>>   create mode 100644 drivers/clk/meson/s4.c
>>>   create mode 100644 drivers/clk/meson/s4.h
>>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>
>>>
>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>
>> Please don't post until you have addressed *ALL* the comments from the
>> previous version.
> The last email asked you to adopt A1 method, but you did not reply?
> 
>>
>> At first glance, I can see that this is still a single driver for
>> what is obviously 2 controllers with 2 register spaces. Simple comments
>> like the "<< 2" in the register declaration have not been addressed 
>> either.
> I understand that this should be a controller, just two address 
> descriptions. One is the various PLL registers and one is the clock for 
> the peripherals. And PLL is to provide a clock source for various 
> peripheral clocks. So a clock controller is reasonable. I think you got 
> it wrong.
> 
> Ok, if you insist on using two clock controllers,, please provide your 
> the reason and example code?
> 
>>
>> Seeing that, I have not reviewed this version further.
>> I won't until all the comments from v1 are either addressed or answer
>>
>> Regards
>> Jerome
>>
>> .

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:

> Hi JB，
>
> On 2022/7/28 15:08, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>> 
>>> 1. Add clock controller driver for S4 SOC.
>>>
>>> Yu Tu (3):
>>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>>    clk: meson: s4: add s4 SoC clock controller driver
>>>
>>> V1 -> V2: Change format as discussed in the email.
>>>
>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>
>>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>   MAINTAINERS                                   |    1 +
>>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>   drivers/clk/meson/Kconfig                     |   15 +
>>>   drivers/clk/meson/Makefile                    |    1 +
>>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>   drivers/clk/meson/s4.h                        |  296 ++
>>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>   8 files changed, 5203 insertions(+)
>>>   create mode 100644 drivers/clk/meson/s4.c
>>>   create mode 100644 drivers/clk/meson/s4.h
>>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>
>>>
>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>> Please don't post until you have addressed *ALL* the comments from the
>> previous version.
> The last email asked you to adopt A1 method, but you did not reply?
>
>> At first glance, I can see that this is still a single driver for
>> what is obviously 2 controllers with 2 register spaces. Simple comments
>> like the "<< 2" in the register declaration have not been addressed either.
> I understand that this should be a controller, just two address
> descriptions. One is the various PLL registers and one is the clock for 
> the peripherals. And PLL is to provide a clock source for various
> peripheral clocks. So a clock controller is reasonable. I think you got 
> it wrong.

I don't think I do. This looks exactly like the A1.
The post of that controller are still in the  archive and I am sure your
colleagues can give you the history.

You clearly have register regions providing clock, separated by
0x8000. Claiming that as one big region is bad design.

There has been several remarks about using a big syscon on V1,
unaddressed too.

CCF has everything necessary in place to handle each register region
separately, properly and pass clock around.

You can handle it as a single controller, claiming the two regions
individually but:
# 1 - handling 2 different regmaps in the controller is going to be
      bigger mess than you think
# 2 - I am far from convinced there is any reason to do so


>
> Ok, if you insist on using two clock controllers,, please provide your the
> reason and example code?
>
>> Seeing that, I have not reviewed this version further.
>> I won't until all the comments from v1 are either addressed or answer
>> Regards
>> Jerome
>> .

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:

> Hi JB，
>
> On 2022/7/28 15:08, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>> 
>>> 1. Add clock controller driver for S4 SOC.
>>>
>>> Yu Tu (3):
>>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>>    clk: meson: s4: add s4 SoC clock controller driver
>>>
>>> V1 -> V2: Change format as discussed in the email.
>>>
>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>
>>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>   MAINTAINERS                                   |    1 +
>>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>   drivers/clk/meson/Kconfig                     |   15 +
>>>   drivers/clk/meson/Makefile                    |    1 +
>>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>   drivers/clk/meson/s4.h                        |  296 ++
>>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>   8 files changed, 5203 insertions(+)
>>>   create mode 100644 drivers/clk/meson/s4.c
>>>   create mode 100644 drivers/clk/meson/s4.h
>>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>
>>>
>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>> Please don't post until you have addressed *ALL* the comments from the
>> previous version.
> The last email asked you to adopt A1 method, but you did not reply?
>
>> At first glance, I can see that this is still a single driver for
>> what is obviously 2 controllers with 2 register spaces. Simple comments
>> like the "<< 2" in the register declaration have not been addressed either.
> I understand that this should be a controller, just two address
> descriptions. One is the various PLL registers and one is the clock for 
> the peripherals. And PLL is to provide a clock source for various
> peripheral clocks. So a clock controller is reasonable. I think you got 
> it wrong.

I don't think I do. This looks exactly like the A1.
The post of that controller are still in the  archive and I am sure your
colleagues can give you the history.

You clearly have register regions providing clock, separated by
0x8000. Claiming that as one big region is bad design.

There has been several remarks about using a big syscon on V1,
unaddressed too.

CCF has everything necessary in place to handle each register region
separately, properly and pass clock around.

You can handle it as a single controller, claiming the two regions
individually but:
# 1 - handling 2 different regmaps in the controller is going to be
      bigger mess than you think
# 2 - I am far from convinced there is any reason to do so


>
> Ok, if you insist on using two clock controllers,, please provide your the
> reason and example code?
>
>> Seeing that, I have not reviewed this version further.
>> I won't until all the comments from v1 are either addressed or answer
>> Regards
>> Jerome
>> .


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:

> Hi JB，
>
> On 2022/7/28 15:08, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>> 
>>> 1. Add clock controller driver for S4 SOC.
>>>
>>> Yu Tu (3):
>>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>>    clk: meson: s4: add s4 SoC clock controller driver
>>>
>>> V1 -> V2: Change format as discussed in the email.
>>>
>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>
>>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>   MAINTAINERS                                   |    1 +
>>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>   drivers/clk/meson/Kconfig                     |   15 +
>>>   drivers/clk/meson/Makefile                    |    1 +
>>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>   drivers/clk/meson/s4.h                        |  296 ++
>>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>   8 files changed, 5203 insertions(+)
>>>   create mode 100644 drivers/clk/meson/s4.c
>>>   create mode 100644 drivers/clk/meson/s4.h
>>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>
>>>
>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>> Please don't post until you have addressed *ALL* the comments from the
>> previous version.
> The last email asked you to adopt A1 method, but you did not reply?
>
>> At first glance, I can see that this is still a single driver for
>> what is obviously 2 controllers with 2 register spaces. Simple comments
>> like the "<< 2" in the register declaration have not been addressed either.
> I understand that this should be a controller, just two address
> descriptions. One is the various PLL registers and one is the clock for 
> the peripherals. And PLL is to provide a clock source for various
> peripheral clocks. So a clock controller is reasonable. I think you got 
> it wrong.

I don't think I do. This looks exactly like the A1.
The post of that controller are still in the  archive and I am sure your
colleagues can give you the history.

You clearly have register regions providing clock, separated by
0x8000. Claiming that as one big region is bad design.

There has been several remarks about using a big syscon on V1,
unaddressed too.

CCF has everything necessary in place to handle each register region
separately, properly and pass clock around.

You can handle it as a single controller, claiming the two regions
individually but:
# 1 - handling 2 different regmaps in the controller is going to be
      bigger mess than you think
# 2 - I am far from convinced there is any reason to do so


>
> Ok, if you insist on using two clock controllers,, please provide your the
> reason and example code?
>
>> Seeing that, I have not reviewed this version further.
>> I won't until all the comments from v1 are either addressed or answer
>> Regards
>> Jerome
>> .


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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi Jerome,
	Thanks for your reply and explanation.

On 2022/7/28 16:27, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> Hi JB，
>>
>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>
>>>> 1. Add clock controller driver for S4 SOC.
>>>>
>>>> Yu Tu (3):
>>>>     dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>     arm64: dts: meson: add S4 Soc clock controller in DT
>>>>     clk: meson: s4: add s4 SoC clock controller driver
>>>>
>>>> V1 -> V2: Change format as discussed in the email.
>>>>
>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>
>>>>    .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>    MAINTAINERS                                   |    1 +
>>>>    arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>    drivers/clk/meson/Kconfig                     |   15 +
>>>>    drivers/clk/meson/Makefile                    |    1 +
>>>>    drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>    drivers/clk/meson/s4.h                        |  296 ++
>>>>    include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>    8 files changed, 5203 insertions(+)
>>>>    create mode 100644 drivers/clk/meson/s4.c
>>>>    create mode 100644 drivers/clk/meson/s4.h
>>>>    create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>
>>>>
>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>> Please don't post until you have addressed *ALL* the comments from the
>>> previous version.
>> The last email asked you to adopt A1 method, but you did not reply?
>>
>>> At first glance, I can see that this is still a single driver for
>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>> like the "<< 2" in the register declaration have not been addressed either.
>> I understand that this should be a controller, just two address
>> descriptions. One is the various PLL registers and one is the clock for
>> the peripherals. And PLL is to provide a clock source for various
>> peripheral clocks. So a clock controller is reasonable. I think you got
>> it wrong.
> 
> I don't think I do. This looks exactly like the A1.
> The post of that controller are still in the  archive and I am sure your
> colleagues can give you the history.
> 
> You clearly have register regions providing clock, separated by
> 0x8000. Claiming that as one big region is bad design.
> 
> There has been several remarks about using a big syscon on V1,
> unaddressed too.
> 
> CCF has everything necessary in place to handle each register region
> separately, properly and pass clock around.
> 
> You can handle it as a single controller, claiming the two regions
> individually but:
> # 1 - handling 2 different regmaps in the controller is going to be
>        bigger mess than you think
> # 2 - I am far from convinced there is any reason to do so
> 
It makes sense, as you say, to separate the two controllers. But I think 
the only thing that was forced apart was that the digital designers 
didn't put these registers together when they were designing the chips.

I'm going to separate the two controllers like you said.

> 
>>
>> Ok, if you insist on using two clock controllers,, please provide your the
>> reason and example code?
>>
>>> Seeing that, I have not reviewed this version further.
>>> I won't until all the comments from v1 are either addressed or answer
>>> Regards
>>> Jerome
>>> .
> 
> .

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi Jerome,
	Thanks for your reply and explanation.

On 2022/7/28 16:27, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> Hi JB，
>>
>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>
>>>> 1. Add clock controller driver for S4 SOC.
>>>>
>>>> Yu Tu (3):
>>>>     dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>     arm64: dts: meson: add S4 Soc clock controller in DT
>>>>     clk: meson: s4: add s4 SoC clock controller driver
>>>>
>>>> V1 -> V2: Change format as discussed in the email.
>>>>
>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>
>>>>    .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>    MAINTAINERS                                   |    1 +
>>>>    arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>    drivers/clk/meson/Kconfig                     |   15 +
>>>>    drivers/clk/meson/Makefile                    |    1 +
>>>>    drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>    drivers/clk/meson/s4.h                        |  296 ++
>>>>    include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>    8 files changed, 5203 insertions(+)
>>>>    create mode 100644 drivers/clk/meson/s4.c
>>>>    create mode 100644 drivers/clk/meson/s4.h
>>>>    create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>
>>>>
>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>> Please don't post until you have addressed *ALL* the comments from the
>>> previous version.
>> The last email asked you to adopt A1 method, but you did not reply?
>>
>>> At first glance, I can see that this is still a single driver for
>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>> like the "<< 2" in the register declaration have not been addressed either.
>> I understand that this should be a controller, just two address
>> descriptions. One is the various PLL registers and one is the clock for
>> the peripherals. And PLL is to provide a clock source for various
>> peripheral clocks. So a clock controller is reasonable. I think you got
>> it wrong.
> 
> I don't think I do. This looks exactly like the A1.
> The post of that controller are still in the  archive and I am sure your
> colleagues can give you the history.
> 
> You clearly have register regions providing clock, separated by
> 0x8000. Claiming that as one big region is bad design.
> 
> There has been several remarks about using a big syscon on V1,
> unaddressed too.
> 
> CCF has everything necessary in place to handle each register region
> separately, properly and pass clock around.
> 
> You can handle it as a single controller, claiming the two regions
> individually but:
> # 1 - handling 2 different regmaps in the controller is going to be
>        bigger mess than you think
> # 2 - I am far from convinced there is any reason to do so
> 
It makes sense, as you say, to separate the two controllers. But I think 
the only thing that was forced apart was that the digital designers 
didn't put these registers together when they were designing the chips.

I'm going to separate the two controllers like you said.

> 
>>
>> Ok, if you insist on using two clock controllers,, please provide your the
>> reason and example code?
>>
>>> Seeing that, I have not reviewed this version further.
>>> I won't until all the comments from v1 are either addressed or answer
>>> Regards
>>> Jerome
>>> .
> 
> .

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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

Hi Jerome,
	Thanks for your reply and explanation.

On 2022/7/28 16:27, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> Hi JB，
>>
>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>
>>>> 1. Add clock controller driver for S4 SOC.
>>>>
>>>> Yu Tu (3):
>>>>     dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>     arm64: dts: meson: add S4 Soc clock controller in DT
>>>>     clk: meson: s4: add s4 SoC clock controller driver
>>>>
>>>> V1 -> V2: Change format as discussed in the email.
>>>>
>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>
>>>>    .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>    MAINTAINERS                                   |    1 +
>>>>    arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>    drivers/clk/meson/Kconfig                     |   15 +
>>>>    drivers/clk/meson/Makefile                    |    1 +
>>>>    drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>    drivers/clk/meson/s4.h                        |  296 ++
>>>>    include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>    8 files changed, 5203 insertions(+)
>>>>    create mode 100644 drivers/clk/meson/s4.c
>>>>    create mode 100644 drivers/clk/meson/s4.h
>>>>    create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>
>>>>
>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>> Please don't post until you have addressed *ALL* the comments from the
>>> previous version.
>> The last email asked you to adopt A1 method, but you did not reply?
>>
>>> At first glance, I can see that this is still a single driver for
>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>> like the "<< 2" in the register declaration have not been addressed either.
>> I understand that this should be a controller, just two address
>> descriptions. One is the various PLL registers and one is the clock for
>> the peripherals. And PLL is to provide a clock source for various
>> peripheral clocks. So a clock controller is reasonable. I think you got
>> it wrong.
> 
> I don't think I do. This looks exactly like the A1.
> The post of that controller are still in the  archive and I am sure your
> colleagues can give you the history.
> 
> You clearly have register regions providing clock, separated by
> 0x8000. Claiming that as one big region is bad design.
> 
> There has been several remarks about using a big syscon on V1,
> unaddressed too.
> 
> CCF has everything necessary in place to handle each register region
> separately, properly and pass clock around.
> 
> You can handle it as a single controller, claiming the two regions
> individually but:
> # 1 - handling 2 different regmaps in the controller is going to be
>        bigger mess than you think
> # 2 - I am far from convinced there is any reason to do so
> 
It makes sense, as you say, to separate the two controllers. But I think 
the only thing that was forced apart was that the digital designers 
didn't put these registers together when they were designing the chips.

I'm going to separate the two controllers like you said.

> 
>>
>> Ok, if you insist on using two clock controllers,, please provide your the
>> reason and example code?
>>
>>> Seeing that, I have not reviewed this version further.
>>> I won't until all the comments from v1 are either addressed or answer
>>> Regards
>>> Jerome
>>> .
> 
> .

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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 16:55, Yu Tu <yu.tu@amlogic.com> wrote:

> Hi Jerome,
> 	Thanks for your reply and explanation.
>
> On 2022/7/28 16:27, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
>> 
>>> Hi JB，
>>>
>>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>>
>>>>> 1. Add clock controller driver for S4 SOC.
>>>>>
>>>>> Yu Tu (3):
>>>>>     dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>>     arm64: dts: meson: add S4 Soc clock controller in DT
>>>>>     clk: meson: s4: add s4 SoC clock controller driver
>>>>>
>>>>> V1 -> V2: Change format as discussed in the email.
>>>>>
>>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>>
>>>>>    .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>>    MAINTAINERS                                   |    1 +
>>>>>    arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>>    drivers/clk/meson/Kconfig                     |   15 +
>>>>>    drivers/clk/meson/Makefile                    |    1 +
>>>>>    drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>>    drivers/clk/meson/s4.h                        |  296 ++
>>>>>    include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>>    8 files changed, 5203 insertions(+)
>>>>>    create mode 100644 drivers/clk/meson/s4.c
>>>>>    create mode 100644 drivers/clk/meson/s4.h
>>>>>    create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>>
>>>>>
>>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>>> Please don't post until you have addressed *ALL* the comments from the
>>>> previous version.
>>> The last email asked you to adopt A1 method, but you did not reply?
>>>
>>>> At first glance, I can see that this is still a single driver for
>>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>>> like the "<< 2" in the register declaration have not been addressed either.
>>> I understand that this should be a controller, just two address
>>> descriptions. One is the various PLL registers and one is the clock for
>>> the peripherals. And PLL is to provide a clock source for various
>>> peripheral clocks. So a clock controller is reasonable. I think you got
>>> it wrong.
>> I don't think I do. This looks exactly like the A1.
>> The post of that controller are still in the  archive and I am sure your
>> colleagues can give you the history.
>> You clearly have register regions providing clock, separated by
>> 0x8000. Claiming that as one big region is bad design.
>> There has been several remarks about using a big syscon on V1,
>> unaddressed too.
>> CCF has everything necessary in place to handle each register region
>> separately, properly and pass clock around.
>> You can handle it as a single controller, claiming the two regions
>> individually but:
>> # 1 - handling 2 different regmaps in the controller is going to be
>>        bigger mess than you think
>> # 2 - I am far from convinced there is any reason to do so
>> 
> It makes sense, as you say, to separate the two controllers. But I think
> the only thing that was forced apart was that the digital designers 
> didn't put these registers together when they were designing the chips.
>

One controller is providing all the base PLLs
The other is providing most (if not all) the devices clocks.
This does not look like coincidence or mistake to me.

> I'm going to separate the two controllers like you said.
>
>> 
>>>
>>> Ok, if you insist on using two clock controllers,, please provide your the
>>> reason and example code?
>>>
>>>> Seeing that, I have not reviewed this version further.
>>>> I won't until all the comments from v1 are either addressed or answer
>>>> Regards
>>>> Jerome
>>>> .
>> .

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 16:55, Yu Tu <yu.tu@amlogic.com> wrote:

> Hi Jerome,
> 	Thanks for your reply and explanation.
>
> On 2022/7/28 16:27, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
>> 
>>> Hi JB，
>>>
>>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>>
>>>>> 1. Add clock controller driver for S4 SOC.
>>>>>
>>>>> Yu Tu (3):
>>>>>     dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>>     arm64: dts: meson: add S4 Soc clock controller in DT
>>>>>     clk: meson: s4: add s4 SoC clock controller driver
>>>>>
>>>>> V1 -> V2: Change format as discussed in the email.
>>>>>
>>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>>
>>>>>    .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>>    MAINTAINERS                                   |    1 +
>>>>>    arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>>    drivers/clk/meson/Kconfig                     |   15 +
>>>>>    drivers/clk/meson/Makefile                    |    1 +
>>>>>    drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>>    drivers/clk/meson/s4.h                        |  296 ++
>>>>>    include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>>    8 files changed, 5203 insertions(+)
>>>>>    create mode 100644 drivers/clk/meson/s4.c
>>>>>    create mode 100644 drivers/clk/meson/s4.h
>>>>>    create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>>
>>>>>
>>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>>> Please don't post until you have addressed *ALL* the comments from the
>>>> previous version.
>>> The last email asked you to adopt A1 method, but you did not reply?
>>>
>>>> At first glance, I can see that this is still a single driver for
>>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>>> like the "<< 2" in the register declaration have not been addressed either.
>>> I understand that this should be a controller, just two address
>>> descriptions. One is the various PLL registers and one is the clock for
>>> the peripherals. And PLL is to provide a clock source for various
>>> peripheral clocks. So a clock controller is reasonable. I think you got
>>> it wrong.
>> I don't think I do. This looks exactly like the A1.
>> The post of that controller are still in the  archive and I am sure your
>> colleagues can give you the history.
>> You clearly have register regions providing clock, separated by
>> 0x8000. Claiming that as one big region is bad design.
>> There has been several remarks about using a big syscon on V1,
>> unaddressed too.
>> CCF has everything necessary in place to handle each register region
>> separately, properly and pass clock around.
>> You can handle it as a single controller, claiming the two regions
>> individually but:
>> # 1 - handling 2 different regmaps in the controller is going to be
>>        bigger mess than you think
>> # 2 - I am far from convinced there is any reason to do so
>> 
> It makes sense, as you say, to separate the two controllers. But I think
> the only thing that was forced apart was that the digital designers 
> didn't put these registers together when they were designing the chips.
>

One controller is providing all the base PLLs
The other is providing most (if not all) the devices clocks.
This does not look like coincidence or mistake to me.

> I'm going to separate the two controllers like you said.
>
>> 
>>>
>>> Ok, if you insist on using two clock controllers,, please provide your the
>>> reason and example code?
>>>
>>>> Seeing that, I have not reviewed this version further.
>>>> I won't until all the comments from v1 are either addressed or answer
>>>> Regards
>>>> Jerome
>>>> .
>> .


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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Jerome Brunet]

On Thu 28 Jul 2022 at 16:55, Yu Tu <yu.tu@amlogic.com> wrote:

> Hi Jerome,
> 	Thanks for your reply and explanation.
>
> On 2022/7/28 16:27, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
>> 
>>> Hi JB，
>>>
>>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>>
>>>>> 1. Add clock controller driver for S4 SOC.
>>>>>
>>>>> Yu Tu (3):
>>>>>     dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>>     arm64: dts: meson: add S4 Soc clock controller in DT
>>>>>     clk: meson: s4: add s4 SoC clock controller driver
>>>>>
>>>>> V1 -> V2: Change format as discussed in the email.
>>>>>
>>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>>
>>>>>    .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>>    MAINTAINERS                                   |    1 +
>>>>>    arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>>    drivers/clk/meson/Kconfig                     |   15 +
>>>>>    drivers/clk/meson/Makefile                    |    1 +
>>>>>    drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>>    drivers/clk/meson/s4.h                        |  296 ++
>>>>>    include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>>    8 files changed, 5203 insertions(+)
>>>>>    create mode 100644 drivers/clk/meson/s4.c
>>>>>    create mode 100644 drivers/clk/meson/s4.h
>>>>>    create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>>
>>>>>
>>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>>> Please don't post until you have addressed *ALL* the comments from the
>>>> previous version.
>>> The last email asked you to adopt A1 method, but you did not reply?
>>>
>>>> At first glance, I can see that this is still a single driver for
>>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>>> like the "<< 2" in the register declaration have not been addressed either.
>>> I understand that this should be a controller, just two address
>>> descriptions. One is the various PLL registers and one is the clock for
>>> the peripherals. And PLL is to provide a clock source for various
>>> peripheral clocks. So a clock controller is reasonable. I think you got
>>> it wrong.
>> I don't think I do. This looks exactly like the A1.
>> The post of that controller are still in the  archive and I am sure your
>> colleagues can give you the history.
>> You clearly have register regions providing clock, separated by
>> 0x8000. Claiming that as one big region is bad design.
>> There has been several remarks about using a big syscon on V1,
>> unaddressed too.
>> CCF has everything necessary in place to handle each register region
>> separately, properly and pass clock around.
>> You can handle it as a single controller, claiming the two regions
>> individually but:
>> # 1 - handling 2 different regmaps in the controller is going to be
>>        bigger mess than you think
>> # 2 - I am far from convinced there is any reason to do so
>> 
> It makes sense, as you say, to separate the two controllers. But I think
> the only thing that was forced apart was that the digital designers 
> didn't put these registers together when they were designing the chips.
>

One controller is providing all the base PLLs
The other is providing most (if not all) the devices clocks.
This does not look like coincidence or mistake to me.

> I'm going to separate the two controllers like you said.
>
>> 
>>>
>>> Ok, if you insist on using two clock controllers,, please provide your the
>>> reason and example code?
>>>
>>>> Seeing that, I have not reviewed this version further.
>>>> I won't until all the comments from v1 are either addressed or answer
>>>> Regards
>>>> Jerome
>>>> .
>> .


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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

On 2022/7/28 17:03, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 16:55, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> Hi Jerome,
>> 	Thanks for your reply and explanation.
>>
>> On 2022/7/28 16:27, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
>>>
>>>> Hi JB，
>>>>
>>>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>>>
>>>>>> 1. Add clock controller driver for S4 SOC.
>>>>>>
>>>>>> Yu Tu (3):
>>>>>>      dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>>>      arm64: dts: meson: add S4 Soc clock controller in DT
>>>>>>      clk: meson: s4: add s4 SoC clock controller driver
>>>>>>
>>>>>> V1 -> V2: Change format as discussed in the email.
>>>>>>
>>>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>>>
>>>>>>     .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>>>     MAINTAINERS                                   |    1 +
>>>>>>     arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>>>     drivers/clk/meson/Kconfig                     |   15 +
>>>>>>     drivers/clk/meson/Makefile                    |    1 +
>>>>>>     drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>>>     drivers/clk/meson/s4.h                        |  296 ++
>>>>>>     include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>>>     8 files changed, 5203 insertions(+)
>>>>>>     create mode 100644 drivers/clk/meson/s4.c
>>>>>>     create mode 100644 drivers/clk/meson/s4.h
>>>>>>     create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>>>
>>>>>>
>>>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>>>> Please don't post until you have addressed *ALL* the comments from the
>>>>> previous version.
>>>> The last email asked you to adopt A1 method, but you did not reply?
>>>>
>>>>> At first glance, I can see that this is still a single driver for
>>>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>>>> like the "<< 2" in the register declaration have not been addressed either.
>>>> I understand that this should be a controller, just two address
>>>> descriptions. One is the various PLL registers and one is the clock for
>>>> the peripherals. And PLL is to provide a clock source for various
>>>> peripheral clocks. So a clock controller is reasonable. I think you got
>>>> it wrong.
>>> I don't think I do. This looks exactly like the A1.
>>> The post of that controller are still in the  archive and I am sure your
>>> colleagues can give you the history.
>>> You clearly have register regions providing clock, separated by
>>> 0x8000. Claiming that as one big region is bad design.
>>> There has been several remarks about using a big syscon on V1,
>>> unaddressed too.
>>> CCF has everything necessary in place to handle each register region
>>> separately, properly and pass clock around.
>>> You can handle it as a single controller, claiming the two regions
>>> individually but:
>>> # 1 - handling 2 different regmaps in the controller is going to be
>>>         bigger mess than you think
>>> # 2 - I am far from convinced there is any reason to do so
>>>
>> It makes sense, as you say, to separate the two controllers. But I think
>> the only thing that was forced apart was that the digital designers
>> didn't put these registers together when they were designing the chips.
>>
> 
> One controller is providing all the base PLLs
> The other is providing most (if not all) the devices clocks.
> This does not look like coincidence or mistake to me.
Thanks for your reply. Looks like I got it wrong. However, I will talk 
to the chip designer about whether it is possible to put these registers 
in the later chip so that it may be easier for our software to process.

> 
>> I'm going to separate the two controllers like you said.
>>
>>>
>>>>
>>>> Ok, if you insist on using two clock controllers,, please provide your the
>>>> reason and example code?
>>>>
>>>>> Seeing that, I have not reviewed this version further.
>>>>> I won't until all the comments from v1 are either addressed or answer
>>>>> Regards
>>>>> Jerome
>>>>> .
>>> .
> 
> .

Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

On 2022/7/28 17:03, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 16:55, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> Hi Jerome,
>> 	Thanks for your reply and explanation.
>>
>> On 2022/7/28 16:27, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
>>>
>>>> Hi JB，
>>>>
>>>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>>>
>>>>>> 1. Add clock controller driver for S4 SOC.
>>>>>>
>>>>>> Yu Tu (3):
>>>>>>      dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>>>      arm64: dts: meson: add S4 Soc clock controller in DT
>>>>>>      clk: meson: s4: add s4 SoC clock controller driver
>>>>>>
>>>>>> V1 -> V2: Change format as discussed in the email.
>>>>>>
>>>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>>>
>>>>>>     .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>>>     MAINTAINERS                                   |    1 +
>>>>>>     arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>>>     drivers/clk/meson/Kconfig                     |   15 +
>>>>>>     drivers/clk/meson/Makefile                    |    1 +
>>>>>>     drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>>>     drivers/clk/meson/s4.h                        |  296 ++
>>>>>>     include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>>>     8 files changed, 5203 insertions(+)
>>>>>>     create mode 100644 drivers/clk/meson/s4.c
>>>>>>     create mode 100644 drivers/clk/meson/s4.h
>>>>>>     create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>>>
>>>>>>
>>>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>>>> Please don't post until you have addressed *ALL* the comments from the
>>>>> previous version.
>>>> The last email asked you to adopt A1 method, but you did not reply?
>>>>
>>>>> At first glance, I can see that this is still a single driver for
>>>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>>>> like the "<< 2" in the register declaration have not been addressed either.
>>>> I understand that this should be a controller, just two address
>>>> descriptions. One is the various PLL registers and one is the clock for
>>>> the peripherals. And PLL is to provide a clock source for various
>>>> peripheral clocks. So a clock controller is reasonable. I think you got
>>>> it wrong.
>>> I don't think I do. This looks exactly like the A1.
>>> The post of that controller are still in the  archive and I am sure your
>>> colleagues can give you the history.
>>> You clearly have register regions providing clock, separated by
>>> 0x8000. Claiming that as one big region is bad design.
>>> There has been several remarks about using a big syscon on V1,
>>> unaddressed too.
>>> CCF has everything necessary in place to handle each register region
>>> separately, properly and pass clock around.
>>> You can handle it as a single controller, claiming the two regions
>>> individually but:
>>> # 1 - handling 2 different regmaps in the controller is going to be
>>>         bigger mess than you think
>>> # 2 - I am far from convinced there is any reason to do so
>>>
>> It makes sense, as you say, to separate the two controllers. But I think
>> the only thing that was forced apart was that the digital designers
>> didn't put these registers together when they were designing the chips.
>>
> 
> One controller is providing all the base PLLs
> The other is providing most (if not all) the devices clocks.
> This does not look like coincidence or mistake to me.
Thanks for your reply. Looks like I got it wrong. However, I will talk 
to the chip designer about whether it is possible to put these registers 
in the later chip so that it may be easier for our software to process.

> 
>> I'm going to separate the two controllers like you said.
>>
>>>
>>>>
>>>> Ok, if you insist on using two clock controllers,, please provide your the
>>>> reason and example code?
>>>>
>>>>> Seeing that, I have not reviewed this version further.
>>>>> I won't until all the comments from v1 are either addressed or answer
>>>>> Regards
>>>>> Jerome
>>>>> .
>>> .
> 
> .

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linux-arm-kernel@lists.infradead.org
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Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

[Yu Tu]

On 2022/7/28 17:03, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 16:55, Yu Tu <yu.tu@amlogic.com> wrote:
> 
>> Hi Jerome,
>> 	Thanks for your reply and explanation.
>>
>> On 2022/7/28 16:27, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu 28 Jul 2022 at 16:06, Yu Tu <yu.tu@amlogic.com> wrote:
>>>
>>>> Hi JB，
>>>>
>>>> On 2022/7/28 15:08, Jerome Brunet wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>>>>>
>>>>>> 1. Add clock controller driver for S4 SOC.
>>>>>>
>>>>>> Yu Tu (3):
>>>>>>      dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>>>>>      arm64: dts: meson: add S4 Soc clock controller in DT
>>>>>>      clk: meson: s4: add s4 SoC clock controller driver
>>>>>>
>>>>>> V1 -> V2: Change format as discussed in the email.
>>>>>>
>>>>>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>>>>>
>>>>>>     .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>>>>>     MAINTAINERS                                   |    1 +
>>>>>>     arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>>>>>     drivers/clk/meson/Kconfig                     |   15 +
>>>>>>     drivers/clk/meson/Makefile                    |    1 +
>>>>>>     drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>>>>>     drivers/clk/meson/s4.h                        |  296 ++
>>>>>>     include/dt-bindings/clock/s4-clkc.h           |  146 +
>>>>>>     8 files changed, 5203 insertions(+)
>>>>>>     create mode 100644 drivers/clk/meson/s4.c
>>>>>>     create mode 100644 drivers/clk/meson/s4.h
>>>>>>     create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>>>>>
>>>>>>
>>>>>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>>>>> Please don't post until you have addressed *ALL* the comments from the
>>>>> previous version.
>>>> The last email asked you to adopt A1 method, but you did not reply?
>>>>
>>>>> At first glance, I can see that this is still a single driver for
>>>>> what is obviously 2 controllers with 2 register spaces. Simple comments
>>>>> like the "<< 2" in the register declaration have not been addressed either.
>>>> I understand that this should be a controller, just two address
>>>> descriptions. One is the various PLL registers and one is the clock for
>>>> the peripherals. And PLL is to provide a clock source for various
>>>> peripheral clocks. So a clock controller is reasonable. I think you got
>>>> it wrong.
>>> I don't think I do. This looks exactly like the A1.
>>> The post of that controller are still in the  archive and I am sure your
>>> colleagues can give you the history.
>>> You clearly have register regions providing clock, separated by
>>> 0x8000. Claiming that as one big region is bad design.
>>> There has been several remarks about using a big syscon on V1,
>>> unaddressed too.
>>> CCF has everything necessary in place to handle each register region
>>> separately, properly and pass clock around.
>>> You can handle it as a single controller, claiming the two regions
>>> individually but:
>>> # 1 - handling 2 different regmaps in the controller is going to be
>>>         bigger mess than you think
>>> # 2 - I am far from convinced there is any reason to do so
>>>
>> It makes sense, as you say, to separate the two controllers. But I think
>> the only thing that was forced apart was that the digital designers
>> didn't put these registers together when they were designing the chips.
>>
> 
> One controller is providing all the base PLLs
> The other is providing most (if not all) the devices clocks.
> This does not look like coincidence or mistake to me.
Thanks for your reply. Looks like I got it wrong. However, I will talk 
to the chip designer about whether it is possible to put these registers 
in the later chip so that it may be easier for our software to process.

> 
>> I'm going to separate the two controllers like you said.
>>
>>>
>>>>
>>>> Ok, if you insist on using two clock controllers,, please provide your the
>>>> reason and example code?
>>>>
>>>>> Seeing that, I have not reviewed this version further.
>>>>> I won't until all the comments from v1 are either addressed or answer
>>>>> Regards
>>>>> Jerome
>>>>> .
>>> .
> 
> .

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