From: Suzuki K Poulose <Suzuki.Poulose@arm.com> To: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will.deacon@arm.com, robin.murphy@arm.com Subject: Re: [PATCH v2 5/5] arm64: perf: Add support for chaining event counters Date: Mon, 11 Jun 2018 14:54:16 +0100 [thread overview] Message-ID: <847dfe5c-665c-6398-f87f-3ca56e73f5aa@arm.com> (raw) In-Reply-To: <4a5b5e7f-fc0b-84e3-fc65-b9f860029207@arm.com> On 08/06/18 15:46, Suzuki K Poulose wrote: > Hi Mark, > > On 06/06/2018 07:01 PM, Mark Rutland wrote: >> On Tue, May 29, 2018 at 11:55:56AM +0100, Suzuki K Poulose wrote: > >>> - value |= 0xffffffff00000000ULL; >>> + if (!armv8pmu_event_is_64bit(event)) >>> + value |= 0xffffffff00000000ULL; >>> write_sysreg(value, pmccntr_el0); >>> - } else if (armv8pmu_select_counter(idx) == idx) >>> - write_sysreg(value, pmxevcntr_el0); >>> + } else >>> + armv8pmu_write_hw_counter(event, value); >>> } >> >>> +static inline void armv8pmu_write_event_type(struct perf_event *event) >>> +{ >>> + struct hw_perf_event *hwc = &event->hw; >>> + int idx = hwc->idx; >>> + >>> + /* >>> + * For chained events, write the the low counter event type >>> + * followed by the high counter. The high counter is programmed >>> + * with CHAIN event code with filters set to count at all ELs. >>> + */ >>> + if (armv8pmu_event_is_chained(event)) { >>> + u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN | >>> + ARMV8_PMU_INCLUDE_EL2; >>> + >>> + armv8pmu_write_evtype(idx - 1, hwc->config_base); >>> + isb(); >>> + armv8pmu_write_evtype(idx, chain_evt); >> >> The ISB isn't necessary here, AFAICT. We only do this while the PMU is >> disabled; no? > > You're right. I was just following the ARM ARM. Taking another look, it is not clear about the semantics of "pmu->enable()" and pmu->disable() callbacks. I don't see any reference to them in the perf core driver anymore. The perf core uses add() / del () instead, with the PMU turned off. Do you have any idea about the enable()/disable() callbacks ? Am I missing something ? Suzuki
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From: Suzuki.Poulose@arm.com (Suzuki K Poulose) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/5] arm64: perf: Add support for chaining event counters Date: Mon, 11 Jun 2018 14:54:16 +0100 [thread overview] Message-ID: <847dfe5c-665c-6398-f87f-3ca56e73f5aa@arm.com> (raw) In-Reply-To: <4a5b5e7f-fc0b-84e3-fc65-b9f860029207@arm.com> On 08/06/18 15:46, Suzuki K Poulose wrote: > Hi Mark, > > On 06/06/2018 07:01 PM, Mark Rutland wrote: >> On Tue, May 29, 2018 at 11:55:56AM +0100, Suzuki K Poulose wrote: > >>> -??????? value |= 0xffffffff00000000ULL; >>> +??????? if (!armv8pmu_event_is_64bit(event)) >>> +??????????? value |= 0xffffffff00000000ULL; >>> ????????? write_sysreg(value, pmccntr_el0); >>> -??? } else if (armv8pmu_select_counter(idx) == idx) >>> -??????? write_sysreg(value, pmxevcntr_el0); >>> +??? } else >>> +??????? armv8pmu_write_hw_counter(event, value); >>> ? } >> >>> +static inline void armv8pmu_write_event_type(struct perf_event *event) >>> +{ >>> +??? struct hw_perf_event *hwc = &event->hw; >>> +??? int idx = hwc->idx; >>> + >>> +??? /* >>> +???? * For chained events, write the the low counter event type >>> +???? * followed by the high counter. The high counter is programmed >>> +???? * with CHAIN event code with filters set to count at all ELs. >>> +???? */ >>> +??? if (armv8pmu_event_is_chained(event)) { >>> +??????? u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN | >>> +??????????????? ARMV8_PMU_INCLUDE_EL2; >>> + >>> +??????? armv8pmu_write_evtype(idx - 1, hwc->config_base); >>> +??????? isb(); >>> +??????? armv8pmu_write_evtype(idx, chain_evt); >> >> The ISB isn't necessary here, AFAICT. We only do this while the PMU is >> disabled; no? > > You're right. I was just following the ARM ARM. Taking another look, it is not clear about the semantics of "pmu->enable()" and pmu->disable() callbacks. I don't see any reference to them in the perf core driver anymore. The perf core uses add() / del () instead, with the PMU turned off. Do you have any idea about the enable()/disable() callbacks ? Am I missing something ? Suzuki
next prev parent reply other threads:[~2018-06-11 13:54 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-29 10:55 [PATCH v2 0/5] arm64: perf: Support for chained counters Suzuki K Poulose 2018-05-29 10:55 ` Suzuki K Poulose 2018-05-29 10:55 ` [PATCH v2 1/5] arm_pmu: Clean up maximum period handling Suzuki K Poulose 2018-05-29 10:55 ` Suzuki K Poulose 2018-05-29 10:55 ` [PATCH v2 2/5] arm_pmu: Change API to support 64bit counter values Suzuki K Poulose 2018-05-29 10:55 ` Suzuki K Poulose 2018-05-29 10:55 ` [PATCH v2 3/5] arm_pmu: Add support for 64bit event counters Suzuki K Poulose 2018-05-29 10:55 ` Suzuki K Poulose 2018-06-06 16:48 ` Mark Rutland 2018-06-06 16:48 ` Mark Rutland 2018-06-07 7:34 ` Suzuki K Poulose 2018-06-07 7:34 ` Suzuki K Poulose 2018-05-29 10:55 ` [PATCH v2 4/5] arm_pmu: Tidy up clear_event_idx call backs Suzuki K Poulose 2018-05-29 10:55 ` Suzuki K Poulose 2018-05-29 10:55 ` [PATCH v2 5/5] arm64: perf: Add support for chaining event counters Suzuki K Poulose 2018-05-29 10:55 ` Suzuki K Poulose 2018-06-06 18:01 ` Mark Rutland 2018-06-06 18:01 ` Mark Rutland 2018-06-08 14:46 ` Suzuki K Poulose 2018-06-08 14:46 ` Suzuki K Poulose 2018-06-08 15:24 ` Mark Rutland 2018-06-08 15:24 ` Mark Rutland 2018-06-08 16:05 ` Suzuki K Poulose 2018-06-08 16:05 ` Suzuki K Poulose 2018-06-11 13:54 ` Suzuki K Poulose [this message] 2018-06-11 13:54 ` Suzuki K Poulose 2018-06-11 14:24 ` Mark Rutland 2018-06-11 14:24 ` Mark Rutland 2018-06-11 16:18 ` Suzuki K Poulose 2018-06-11 16:18 ` Suzuki K Poulose 2018-06-05 15:00 ` [PATCH v2 0/5] arm64: perf: Support for chained counters Julien Thierry 2018-06-05 15:00 ` Julien Thierry
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