[LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[Jerome Glisse]

CAPI (on IBM Power8 and 9) and CCIX are two new standard that
build on top of existing interconnect (like PCIE) and add the
possibility for cache coherent access both way (from CPU to
device memory and from device to main memory). This extend
what we are use to with PCIE (where only device to main memory
can be cache coherent but not CPU to device memory).

How is this memory gonna be expose to the kernel and how the
kernel gonna expose this to user space is the topic i want to
discuss. I believe this is highly device specific for instance
for GPU you want the device memory allocation and usage to be
under the control of the GPU device driver. Maybe other type
of device want different strategy.

The HMAT patchset is partialy related to all this as it is about
exposing different type of memory available in a system for CPU
(HBM, main memory, ...) and some of their properties (bandwidth,
latency, ...).


We can start by looking at how CAPI and CCIX plan to expose this
to the kernel and try to list some of the type of devices we
expect to see. Discussion can then happen on how to represent this
internaly to the kernel and how to expose this to userspace.

Note this might also trigger discussion on a NUMA like model or
on extending/replacing it by something more generic.


Peoples (alphabetical order on first name) sorry if i missed
anyone:
    "Anshuman Khandual" <khandual@linux.vnet.ibm.com>
    "Balbir Singh" <bsingharora@gmail.com>
    "Dan Williams" <dan.j.williams@intel.com>
    "John Hubbard" <jhubbard@nvidia.com>
    "Jonathan Masters" <jcm@redhat.com>
    "Ross Zwisler" <ross.zwisler@linux.intel.com>

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Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[Liubo(OS Lab)]

On 2018/1/17 5:03, Jerome Glisse wrote:
> CAPI (on IBM Power8 and 9) and CCIX are two new standard that
> build on top of existing interconnect (like PCIE) and add the
> possibility for cache coherent access both way (from CPU to
> device memory and from device to main memory). This extend
> what we are use to with PCIE (where only device to main memory
> can be cache coherent but not CPU to device memory).
> 

Yes, and more than CAPI/CCIX.
E.g A SoC may connected with different types of memory through internal system-bus.

> How is this memory gonna be expose to the kernel and how the
> kernel gonna expose this to user space is the topic i want to
> discuss. I believe this is highly device specific for instance
> for GPU you want the device memory allocation and usage to be
> under the control of the GPU device driver. Maybe other type
> of device want different strategy.
> 
> The HMAT patchset is partialy related to all this as it is about
> exposing different type of memory available in a system for CPU
> (HBM, main memory, ...) and some of their properties (bandwidth,
> latency, ...).
> 

Yes, and different type of memory doesn't mean device-memory or Nvdimm only(which are always think not as reliable as DDR).

> 
> We can start by looking at how CAPI and CCIX plan to expose this
> to the kernel and try to list some of the type of devices we
> expect to see. Discussion can then happen on how to represent this
> internaly to the kernel and how to expose this to userspace.
> 
> Note this might also trigger discussion on a NUMA like model or
> on extending/replacing it by something more generic.
> 

Agree, for NUMA model the node distance is not enough when a system has different type of memory.
Like the HMAT patches mentioned, different bandwidth ,latency, ...

> 
> Peoples (alphabetical order on first name) sorry if i missed
> anyone:
>     "Anshuman Khandual" <khandual@linux.vnet.ibm.com>
>     "Balbir Singh" <bsingharora@gmail.com>
>     "Dan Williams" <dan.j.williams@intel.com>
>     "John Hubbard" <jhubbard@nvidia.com>
>     "Jonathan Masters" <jcm@redhat.com>
>     "Ross Zwisler" <ross.zwisler@linux.intel.com>
> 


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Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[Balbir Singh]

On Wed, Jan 17, 2018 at 7:02 AM, Liubo(OS Lab) <liubo95@huawei.com> wrote:
> On 2018/1/17 5:03, Jerome Glisse wrote:
>> CAPI (on IBM Power8 and 9) and CCIX are two new standard that
>> build on top of existing interconnect (like PCIE) and add the
>> possibility for cache coherent access both way (from CPU to
>> device memory and from device to main memory). This extend
>> what we are use to with PCIE (where only device to main memory
>> can be cache coherent but not CPU to device memory).
>>
>
> Yes, and more than CAPI/CCIX.
> E.g A SoC may connected with different types of memory through internal system-bus.

cool! any references, docs?

>
>> How is this memory gonna be expose to the kernel and how the
>> kernel gonna expose this to user space is the topic i want to
>> discuss. I believe this is highly device specific for instance
>> for GPU you want the device memory allocation and usage to be
>> under the control of the GPU device driver. Maybe other type
>> of device want different strategy.
>>
>> The HMAT patchset is partialy related to all this as it is about
>> exposing different type of memory available in a system for CPU
>> (HBM, main memory, ...) and some of their properties (bandwidth,
>> latency, ...).
>>
>
> Yes, and different type of memory doesn't mean device-memory or Nvdimm only(which are always think not as reliable as DDR).
>

OK, so something probably as reliable system memory, but with
different characteristics

>>
>> We can start by looking at how CAPI and CCIX plan to expose this
>> to the kernel and try to list some of the type of devices we
>> expect to see. Discussion can then happen on how to represent this
>> internaly to the kernel and how to expose this to userspace.
>>
>> Note this might also trigger discussion on a NUMA like model or
>> on extending/replacing it by something more generic.
>>
>
> Agree, for NUMA model the node distance is not enough when a system has different type of memory.
> Like the HMAT patches mentioned, different bandwidth ,latency, ...
>

Yes, definitely worth discussing. The last time I posted
N_COHERENT_MEMORY as a patchset to isolate memory, but that met with a
lot of opposition due to lack of a full use case and end to end
demonstration. I think we can work on a proposal that provides the
benefits of NUMA, but that might require us to revisit what algorithms
should be run on what nodes, relationship between nodes.

Balbir Singh.

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Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[Figo.zhang]

[-- Attachment #1: Type: text/plain, Size: 2376 bytes --]

2018-01-17 5:03 GMT+08:00 Jerome Glisse <jglisse@redhat.com>:

> CAPI (on IBM Power8 and 9) and CCIX are two new standard that
> build on top of existing interconnect (like PCIE) and add the
> possibility for cache coherent access both way (from CPU to
> device memory and from device to main memory). This extend
> what we are use to with PCIE (where only device to main memory
> can be cache coherent but not CPU to device memory).
>

the UPI bus also support cache coherency for Intel platform, right?
it seem the specification of CCIX/CAPI protocol is not public, we cannot
know the details
about them, your topic will cover the details?


>
> How is this memory gonna be expose to the kernel and how the
> kernel gonna expose this to user space is the topic i want to
> discuss. I believe this is highly device specific for instance
> for GPU you want the device memory allocation and usage to be
> under the control of the GPU device driver. Maybe other type
> of device want different strategy.
>
i see it lack of some simple example for how to use the
HMM, because GPU driver is more
complicate for linux driver developer  except the ATI/NVIDIA developers.

>
> The HMAT patchset is partialy related to all this as it is about
> exposing different type of memory available in a system for CPU
> (HBM, main memory, ...) and some of their properties (bandwidth,
> latency, ...).
>
>
> We can start by looking at how CAPI and CCIX plan to expose this
> to the kernel and try to list some of the type of devices we
> expect to see. Discussion can then happen on how to represent this
> internaly to the kernel and how to expose this to userspace.
>
> Note this might also trigger discussion on a NUMA like model or
> on extending/replacing it by something more generic.
>
>
> Peoples (alphabetical order on first name) sorry if i missed
> anyone:
>     "Anshuman Khandual" <khandual@linux.vnet.ibm.com>
>     "Balbir Singh" <bsingharora@gmail.com>
>     "Dan Williams" <dan.j.williams@intel.com>
>     "John Hubbard" <jhubbard@nvidia.com>
>     "Jonathan Masters" <jcm@redhat.com>
>     "Ross Zwisler" <ross.zwisler@linux.intel.com>
>
> --
> To unsubscribe, send a message with 'unsubscribe linux-mm' in
> the body to majordomo@kvack.org.  For more info on Linux MM,
> see: http://www.linux-mm.org/ .
> Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a>
>

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Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[Jerome Glisse]

On Wed, Jan 17, 2018 at 09:55:14AM +0800, Figo.zhang wrote:
> 2018-01-17 5:03 GMT+08:00 Jerome Glisse <jglisse@redhat.com>:
> 
> > CAPI (on IBM Power8 and 9) and CCIX are two new standard that
> > build on top of existing interconnect (like PCIE) and add the
> > possibility for cache coherent access both way (from CPU to
> > device memory and from device to main memory). This extend
> > what we are use to with PCIE (where only device to main memory
> > can be cache coherent but not CPU to device memory).
> >
> 
> the UPI bus also support cache coherency for Intel platform, right?

AFAIK the UPI only apply between processors and is not expose to devices
except integrated Intel devices (like Intel GPU or FPGA) thus it is less
generic/open than CAPI/CCIX.

> it seem the specification of CCIX/CAPI protocol is not public, we cannot
> know the details about them, your topic will cover the details?

I can only cover what will be public at the time of summit but for
the sake of discussion the important characteristic is the cache
coherency aspect. Discussing how it is implemented, cache line
protocol and all the gory details of protocol is of little interest
from kernel point of view.


> > How is this memory gonna be expose to the kernel and how the
> > kernel gonna expose this to user space is the topic i want to
> > discuss. I believe this is highly device specific for instance
> > for GPU you want the device memory allocation and usage to be
> > under the control of the GPU device driver. Maybe other type
> > of device want different strategy.
> >
> i see it lack of some simple example for how to use the HMM, because
> GPU driver is more complicate for linux driver developer  except the
> ATI/NVIDIA developers.

HMM require a device with an MMU and capable of pausing workload that
do pagefault. Only devices complex enough i know of are GPU, Infiniband
and FPGA. HMM from feedback i had so far is that most people working on
any such device driver understand HMM. I am always happy to answer any
specific questions on the API and how it is intended to be use by device
driver (and improve kernel documentation in the process).

How HMM functionality is then expose to userspace by the device driver
is under the control of each individual device driver.

Cheers,
Jerome

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Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[Balbir Singh]

On Wed, Jan 17, 2018 at 2:33 AM, Jerome Glisse <jglisse@redhat.com> wrote:
> CAPI (on IBM Power8 and 9) and CCIX are two new standard that
> build on top of existing interconnect (like PCIE) and add the
> possibility for cache coherent access both way (from CPU to
> device memory and from device to main memory). This extend
> what we are use to with PCIE (where only device to main memory
> can be cache coherent but not CPU to device memory).
>
> How is this memory gonna be expose to the kernel and how the
> kernel gonna expose this to user space is the topic i want to
> discuss. I believe this is highly device specific for instance
> for GPU you want the device memory allocation and usage to be
> under the control of the GPU device driver. Maybe other type
> of device want different strategy.
>
> The HMAT patchset is partialy related to all this as it is about
> exposing different type of memory available in a system for CPU
> (HBM, main memory, ...) and some of their properties (bandwidth,
> latency, ...).
>
>
> We can start by looking at how CAPI and CCIX plan to expose this
> to the kernel and try to list some of the type of devices we
> expect to see. Discussion can then happen on how to represent this
> internaly to the kernel and how to expose this to userspace.
>
> Note this might also trigger discussion on a NUMA like model or
> on extending/replacing it by something more generic.
>

Yes, I agree. I've had some experience with both NUMA and HMM/CDM
models. I think we should compare and contrast the trade-offs
and also discuss how we want to expose some of the ZONE_DEVICE
information back to user space.

>
> Peoples (alphabetical order on first name) sorry if i missed
> anyone:
>     "Anshuman Khandual" <khandual@linux.vnet.ibm.com>
>     "Balbir Singh" <bsingharora@gmail.com>
>     "Dan Williams" <dan.j.williams@intel.com>
>     "John Hubbard" <jhubbard@nvidia.com>
>     "Jonathan Masters" <jcm@redhat.com>
>     "Ross Zwisler" <ross.zwisler@linux.intel.com>

I'd love to be there if invited.

Thanks,
Balbir Singh.

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Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[John Hubbard]

On 01/17/2018 08:29 AM, Balbir Singh wrote:
> On Wed, Jan 17, 2018 at 2:33 AM, Jerome Glisse <jglisse@redhat.com> wrote:
>> CAPI (on IBM Power8 and 9) and CCIX are two new standard that
>> build on top of existing interconnect (like PCIE) and add the
>> possibility for cache coherent access both way (from CPU to
>> device memory and from device to main memory). This extend
>> what we are use to with PCIE (where only device to main memory
>> can be cache coherent but not CPU to device memory).
>>
>> How is this memory gonna be expose to the kernel and how the
>> kernel gonna expose this to user space is the topic i want to
>> discuss. I believe this is highly device specific for instance
>> for GPU you want the device memory allocation and usage to be
>> under the control of the GPU device driver. Maybe other type
>> of device want different strategy.
>>
>> The HMAT patchset is partialy related to all this as it is about
>> exposing different type of memory available in a system for CPU
>> (HBM, main memory, ...) and some of their properties (bandwidth,
>> latency, ...).
>>
>>
>> We can start by looking at how CAPI and CCIX plan to expose this
>> to the kernel and try to list some of the type of devices we
>> expect to see. Discussion can then happen on how to represent this
>> internaly to the kernel and how to expose this to userspace.
>>
>> Note this might also trigger discussion on a NUMA like model or
>> on extending/replacing it by something more generic.
>>
> 
> Yes, I agree. I've had some experience with both NUMA and HMM/CDM
> models. I think we should compare and contrast the trade-offs
> and also discuss how we want to expose some of the ZONE_DEVICE
> information back to user space.

Hi Jerome and all,

Thanks for adding me here. This area is something I'm interested in,
and would love to get a chance to discuss some more. 

There are a lot of new types of computers popping up, with a remarkable
variety of memory-like components (and some unusual direct connections 
between components), even within the same box. It really is getting
interesting. 

I recall some key points from last year's discussions very clearly, 
about doing careful experiments (for example, add HMM, and see how it's 
used, rather than making large NUMA changes right away).  So now that
we are (just barely) getting some experience with NUMA and HMM systems, 
maybe we can look a bit further ahead. Admittedly, not much further; as  
noted on the other thread ("HMM status upstream"), there is still ongoing
effort to finish up various device drivers, and get together an open source 
compute stack.


thanks,
-- 
John Hubbard
NVIDIA

> 
>>
>> Peoples (alphabetical order on first name) sorry if i missed
>> anyone:
>>     "Anshuman Khandual" <khandual@linux.vnet.ibm.com>
>>     "Balbir Singh" <bsingharora@gmail.com>
>>     "Dan Williams" <dan.j.williams@intel.com>
>>     "John Hubbard" <jhubbard@nvidia.com>
>>     "Jonathan Masters" <jcm@redhat.com>
>>     "Ross Zwisler" <ross.zwisler@linux.intel.com>
> 
> I'd love to be there if invited.
> 
> Thanks,
> Balbir Singh.
> 

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Re: [LSF/MM TOPIC] CAPI/CCIX cache coherent device memory (NUMA too ?)

[Ross Zwisler]

On Tue, Jan 16, 2018 at 04:03:21PM -0500, Jerome Glisse wrote:
> CAPI (on IBM Power8 and 9) and CCIX are two new standard that
> build on top of existing interconnect (like PCIE) and add the
> possibility for cache coherent access both way (from CPU to
> device memory and from device to main memory). This extend
> what we are use to with PCIE (where only device to main memory
> can be cache coherent but not CPU to device memory).
> 
> How is this memory gonna be expose to the kernel and how the
> kernel gonna expose this to user space is the topic i want to
> discuss. I believe this is highly device specific for instance
> for GPU you want the device memory allocation and usage to be
> under the control of the GPU device driver. Maybe other type
> of device want different strategy.
> 
> The HMAT patchset is partialy related to all this as it is about
> exposing different type of memory available in a system for CPU
> (HBM, main memory, ...) and some of their properties (bandwidth,
> latency, ...).
> 
> 
> We can start by looking at how CAPI and CCIX plan to expose this
> to the kernel and try to list some of the type of devices we
> expect to see. Discussion can then happen on how to represent this
> internaly to the kernel and how to expose this to userspace.
> 
> Note this might also trigger discussion on a NUMA like model or
> on extending/replacing it by something more generic.
> 
> 
> Peoples (alphabetical order on first name) sorry if i missed
> anyone:
>     "Anshuman Khandual" <khandual@linux.vnet.ibm.com>
>     "Balbir Singh" <bsingharora@gmail.com>
>     "Dan Williams" <dan.j.williams@intel.com>
>     "John Hubbard" <jhubbard@nvidia.com>
>     "Jonathan Masters" <jcm@redhat.com>
>     "Ross Zwisler" <ross.zwisler@linux.intel.com>

I'd love to be part of this discussion, thanks.

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