[PATCH] drm/i915: Ignore DRM_MODE_FLAG_DBLCLK flag with DP

[PATCH] drm/i915: Ignore DRM_MODE_FLAG_DBLCLK flag with DP

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DP spec has nothing at all to say about double clocked modes. One
might assume they don't exist, and if you think about the concept
doesn't make much sense since the link already runs at higher fixed
frequency. So let's drop the DRM_MODE_FLAG_DBLCLK checks and simply
use the mode as if it was not double clocked.

I've tested this on a Dell UP2414Q which claims to support 720x576i
and 720x480i double clocked CEA modes, and it seems perfectly happy
with both modes using the 1x clock.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eea9e36..4b0dadb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -222,9 +222,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
 
-	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-		return MODE_H_ILLEGAL;
-
 	return MODE_OK;
 }
 
@@ -1189,9 +1186,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 						intel_connector->panel.fitting_mode);
 	}
 
-	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
-		return false;
-
 	DRM_DEBUG_KMS("DP link computation with max lane count %i "
 		      "max bw %02x pixel clock %iKHz\n",
 		      max_lane_count, bws[max_clock],
-- 
2.0.5

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Re: [PATCH] drm/i915: Ignore DRM_MODE_FLAG_DBLCLK flag with DP

[Daniel Vetter]

On Mon, Feb 02, 2015 at 07:16:33PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The DP spec has nothing at all to say about double clocked modes. One
> might assume they don't exist, and if you think about the concept
> doesn't make much sense since the link already runs at higher fixed
> frequency. So let's drop the DRM_MODE_FLAG_DBLCLK checks and simply
> use the mode as if it was not double clocked.
> 
> I've tested this on a Dell UP2414Q which claims to support 720x576i
> and 720x480i double clocked CEA modes, and it seems perfectly happy
> with both modes using the 1x clock.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

What happens when this is for a dp->vga sst dongle? Or an active dvi/hdmi
dongle (not sure those exist ...), are we sure this wont upset an existing
screen somewhere?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index eea9e36..4b0dadb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -222,9 +222,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	if (mode->clock < 10000)
>  		return MODE_CLOCK_LOW;
>  
> -	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> -		return MODE_H_ILLEGAL;
> -
>  	return MODE_OK;
>  }
>  
> @@ -1189,9 +1186,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  						intel_connector->panel.fitting_mode);
>  	}
>  
> -	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> -		return false;
> -
>  	DRM_DEBUG_KMS("DP link computation with max lane count %i "
>  		      "max bw %02x pixel clock %iKHz\n",
>  		      max_lane_count, bws[max_clock],
> -- 
> 2.0.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH] drm/i915: Ignore DRM_MODE_FLAG_DBLCLK flag with DP

[Ville Syrjälä]

On Mon, Feb 02, 2015 at 06:21:31PM +0100, Daniel Vetter wrote:
> On Mon, Feb 02, 2015 at 07:16:33PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The DP spec has nothing at all to say about double clocked modes. One
> > might assume they don't exist, and if you think about the concept
> > doesn't make much sense since the link already runs at higher fixed
> > frequency. So let's drop the DRM_MODE_FLAG_DBLCLK checks and simply
> > use the mode as if it was not double clocked.
> > 
> > I've tested this on a Dell UP2414Q which claims to support 720x576i
> > and 720x480i double clocked CEA modes, and it seems perfectly happy
> > with both modes using the 1x clock.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> What happens when this is for a dp->vga sst dongle? Or an active dvi/hdmi
> dongle (not sure those exist ...), are we sure this wont upset an existing
> screen somewhere?

If it's a native DP sink, I'd expect it to not advertize the mode if it
can't do it. Unless of course we're actually supposed to double clock
with DP. As stated I can't find anything in the spec about such things.
Also the specs are rather vague on what kind of infoframes you're
supposed to send DP sinks. If we're supposed to send the AVI infoframe
then we could send the VIC and the sink could know it needs to deal
with the doubled pixels, but othewise there's no way to tell the sink
about this using any native DP mechanism. I wish the DP spec would 
be more clear on how it interacts with CEA-861, rather than just have
some vague references to it. I suppose I could try to enable the AVI
infoframe and see what happens...

As for dongles, VGA doesn't have a clock so I expect that should just
work (tm). For active DP->HDMI I suppose the dongle should realize it
needs to double up (assuming we're not supposed to double clock DP),
but I've not tried it. We do have one active dongle here so I should
be able to try it.


> -Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 6 ------
> >  1 file changed, 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index eea9e36..4b0dadb 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -222,9 +222,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
> >  	if (mode->clock < 10000)
> >  		return MODE_CLOCK_LOW;
> >  
> > -	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > -		return MODE_H_ILLEGAL;
> > -
> >  	return MODE_OK;
> >  }
> >  
> > @@ -1189,9 +1186,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >  						intel_connector->panel.fitting_mode);
> >  	}
> >  
> > -	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> > -		return false;
> > -
> >  	DRM_DEBUG_KMS("DP link computation with max lane count %i "
> >  		      "max bw %02x pixel clock %iKHz\n",
> >  		      max_lane_count, bws[max_clock],
> > -- 
> > 2.0.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915: Ignore DRM_MODE_FLAG_DBLCLK flag with DP

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5698
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              353/353              352/353
ILK                                  200/200              200/200
SNB                                  400/422              400/422
IVB              +1                 485/487              486/487
BYT                                  296/296              296/296
HSW                                  507/508              507/508
BDW                 -1              401/402              400/402
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gen3_render_linear_blits      PASS(6, M25M23M7)      CRASH(1, M23)
 IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(7, M34M4M21)PASS(18, M34M4M21)      PASS(1, M21)
 BDW  igt_gem_pwrite_pread_uncached-pwrite-blt-gtt_mmap-performance      DMESG_WARN(2, M28)PASS(7, M30M28)      DMESG_WARN(1, M28)
Note: You need to pay more attention to line start with '*'
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