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* Re: [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288
@ 2017-09-13 11:01 ` David.Wu
  0 siblings, 0 replies; 5+ messages in thread
From: David.Wu @ 2017-09-13 11:01 UTC (permalink / raw)
  To: Dr. Philipp Tomsich
  Cc: huangtao, u-boot, zhangqing, linux-rockchip, p.marczak, andy.yan, chenjh

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Content preview:  Hi Dr.Philipp 在 2017/9/13 18:24, Dr. Philipp Tomsich 写道:
   > >> On 13 Sep 2017, at 12:09, David Wu <david.wu@rock-chips.com> wrote:
  >> > > Please add a commit message. > >> Signed-off-by: David Wu <david.wu@rock-chips.com>
   > > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
  > > See above and below for requested changes. > >> --- >> drivers/clk/rockchip/clk_rk3288.c
   | 45 +++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 45 insertions(+)
   >> >> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
   >> index 478195b..29652b0 100644 >> --- a/drivers/clk/rockchip/clk_rk3288.c
   >> +++ b/drivers/clk/rockchip/clk_rk3288.c >> @@ -111,6 +111,15 @@ enum {
   >> PERI_ACLK_DIV_SHIFT = 0, >> PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
   >> >> + /* >> + * CLKSEL24 >> + * saradc_div_con: >> + * clk_saradc=24MHz/(saradc_div_con+1)
   >> + */ >> + CLK_SARADC_DIV_CON_SHIFT = 8, >> + CLK_SARADC_DIV_CON_MASK =
   0xff << CLK_SARADC_DIV_CON_SHIFT, >> + CLK_SARADC_DIV_CON_WIDTH = 8, >> +
   >> SOCSTS_DPLL_LOCK = 1 << 5, >> SOCSTS_APLL_LOCK = 1 << 6, >> SOCSTS_CPLL_LOCK
   = 1 << 7, >> @@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg
   = PLL_DIVISORS(APLL_HZ, 1, 1); >> static const struct pll_div gpll_init_cfg
   = PLL_DIVISORS(GPLL_HZ, 2, 2); >> static const struct pll_div cpll_init_cfg
   = PLL_DIVISORS(CPLL_HZ, 1, 2); >> >> +static inline u32 extract_bits(u32
  val, unsigned width, unsigned shift) >> +{ >> + return (val >> shift) & ((1
   << width) - 1); >> +} > > Please reuse what’s already available in include/bitfield.h.
   > This also applies to all call-sites for extract_bits below: they should
   directly use the already existing function. [...] 

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From: "David.Wu" <david.wu@rock-chips.com>
To: "Dr. Philipp Tomsich" <philipp.tomsich@theobroma-systems.com>
Cc: sjg@chromium.org, p.marczak@samsung.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, andy.yan@rock-chips.com, chenjh@rock-chips.com, heiko@sntech.de, zhangqing@rock-chips.com, linux-rockchip@lists.infradead.org, u-boot@lists.denx.de
Subject: Re: [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288
Date: Wed, 13 Sep 2017 19:01:29 +0800
Message-ID: <84dd68d6-40f8-50dd-1f4e-b916d0c569d5@rock-chips.com>

Hi Dr.Philipp

在 2017/9/13 18:24, Dr. Philipp Tomsich 写道:
> 
>> On 13 Sep 2017, at 12:09, David Wu <david.wu@rock-chips.com> wrote:
>>
> 
> Please add a commit message.
> 
>> Signed-off-by: David Wu <david.wu@rock-chips.com>
> 
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> 
> See above and below for requested changes.
> 
>> ---
>> drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 45 insertions(+)
>>
>> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
>> index 478195b..29652b0 100644
>> --- a/drivers/clk/rockchip/clk_rk3288.c
>> +++ b/drivers/clk/rockchip/clk_rk3288.c
>> @@ -111,6 +111,15 @@ enum {
>> 	PERI_ACLK_DIV_SHIFT	= 0,
>> 	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
>>
>> +	/*
>> +	 * CLKSEL24
>> +	 * saradc_div_con:
>> +	 * clk_saradc=24MHz/(saradc_div_con+1)
>> +	 */
>> +	CLK_SARADC_DIV_CON_SHIFT	= 8,
>> +	CLK_SARADC_DIV_CON_MASK		= 0xff << CLK_SARADC_DIV_CON_SHIFT,
>> +	CLK_SARADC_DIV_CON_WIDTH	= 8,
>> +
>> 	SOCSTS_DPLL_LOCK	= 1 << 5,
>> 	SOCSTS_APLL_LOCK	= 1 << 6,
>> 	SOCSTS_CPLL_LOCK	= 1 << 7,
>> @@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
>> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
>> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
>>
>> +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
>> +{
>> +	return (val >> shift) & ((1 << width) - 1);
>> +}
> 
> Please reuse what’s already available in include/bitfield.h.
> This also applies to all call-sites for extract_bits below: they should directly use the already existing function.

Okay, i will use the bitfield_extract（) instead of it.

> 
>> +
>> static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
>> 			 const struct pll_div *div)
>> {
>> @@ -634,6 +648,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
>> 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
>> }
>>
>> +static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
>> +{
>> +	u32 div, val;
>> +
>> +	val = readl(&cru->cru_clksel_con[24]);
>> +	div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,
>> +			   CLK_SARADC_DIV_CON_SHIFT);
>> +
>> +	return DIV_TO_RATE(OSC_HZ, div);
>> +}
>> +
>> +static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
>> +{
>> +	int src_clk_div;
>> +
>> +	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
>> +	assert(src_clk_div < 128);
>> +
>> +	rk_clrsetreg(&cru->cru_clksel_con[24],
>> +		     CLK_SARADC_DIV_CON_MASK,
>> +		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
>> +
>> +	return rockchip_saradc_get_clk(cru);
>> +}
>> +
>> static ulong rk3288_clk_get_rate(struct clk *clk)
>> {
>> 	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
>> @@ -666,6 +705,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
>> 		return gclk_rate;
>> 	case PCLK_PWM:
>> 		return PD_BUS_PCLK_HZ;
>> +	case SCLK_SARADC:
>> +		new_rate = rockchip_saradc_get_clk(priv->cru);
>> +		break;
>> 	default:
>> 		return -ENOENT;
>> 	}
>> @@ -756,6 +798,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
>> 		new_rate = rate;
>> 		break;
>> #endif
>> +	case SCLK_SARADC:
>> +		new_rate = rockchip_saradc_set_clk(priv->cru, rate);
>> +		break;
>> 	default:
>> 		return -ENOENT;
>> 	}
>> -- 
>> 2.7.4
>>
>>
> 
> 
> 
> 


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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288
@ 2017-09-13 11:01 ` David.Wu
  0 siblings, 0 replies; 5+ messages in thread
From: David.Wu @ 2017-09-13 11:01 UTC (permalink / raw)
  To: u-boot

Spam detection software, running on the system "lists.denx.de",
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Content preview:  Hi Dr.Philipp 在 2017/9/13 18:24, Dr. Philipp Tomsich 写道:
   > >> On 13 Sep 2017, at 12:09, David Wu <david.wu@rock-chips.com> wrote:
  >> > > Please add a commit message. > >> Signed-off-by: David Wu <david.wu@rock-chips.com>
   > > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
  > > See above and below for requested changes. > >> --- >> drivers/clk/rockchip/clk_rk3288.c
   | 45 +++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 45 insertions(+)
   >> >> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
   >> index 478195b..29652b0 100644 >> --- a/drivers/clk/rockchip/clk_rk3288.c
   >> +++ b/drivers/clk/rockchip/clk_rk3288.c >> @@ -111,6 +111,15 @@ enum {
   >> PERI_ACLK_DIV_SHIFT = 0, >> PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
   >> >> + /* >> + * CLKSEL24 >> + * saradc_div_con: >> + * clk_saradc=24MHz/(saradc_div_con+1)
   >> + */ >> + CLK_SARADC_DIV_CON_SHIFT = 8, >> + CLK_SARADC_DIV_CON_MASK =
   0xff << CLK_SARADC_DIV_CON_SHIFT, >> + CLK_SARADC_DIV_CON_WIDTH = 8, >> +
   >> SOCSTS_DPLL_LOCK = 1 << 5, >> SOCSTS_APLL_LOCK = 1 << 6, >> SOCSTS_CPLL_LOCK
   = 1 << 7, >> @@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg
   = PLL_DIVISORS(APLL_HZ, 1, 1); >> static const struct pll_div gpll_init_cfg
   = PLL_DIVISORS(GPLL_HZ, 2, 2); >> static const struct pll_div cpll_init_cfg
   = PLL_DIVISORS(CPLL_HZ, 1, 2); >> >> +static inline u32 extract_bits(u32
  val, unsigned width, unsigned shift) >> +{ >> + return (val >> shift) & ((1
   << width) - 1); >> +} > > Please reuse what’s already available in include/bitfield.h.
   > This also applies to all call-sites for extract_bits below: they should
   directly use the already existing function. [...] 

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From: "David.Wu" <david.wu@rock-chips.com>
Subject: Re: [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288
Date: Wed, 13 Sep 2017 19:01:29 +0800
Size: 5453
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170913/73f084b1/attachment.mht>

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288
  2017-09-13 10:09   ` [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288 David Wu
  2017-09-13 10:24     ` Dr. Philipp Tomsich
@ 2017-09-13 10:26     ` Dr. Philipp Tomsich
  1 sibling, 0 replies; 5+ messages in thread
From: Dr. Philipp Tomsich @ 2017-09-13 10:26 UTC (permalink / raw)
  To: David Wu
  Cc: huangtao, u-boot, zhangqing, linux-rockchip, p.marczak, andy.yan, chenjh


> On 13 Sep 2017, at 12:09, David Wu <david.wu@rock-chips.com> wrote:
> 

Commit message?

> Signed-off-by: David Wu <david.wu@rock-chips.com>

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

See above and below for requested changes.

> ---
> drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
> index 478195b..29652b0 100644
> --- a/drivers/clk/rockchip/clk_rk3288.c
> +++ b/drivers/clk/rockchip/clk_rk3288.c
> @@ -111,6 +111,15 @@ enum {
> 	PERI_ACLK_DIV_SHIFT	= 0,
> 	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
> 
> +	/*
> +	 * CLKSEL24
> +	 * saradc_div_con:
> +	 * clk_saradc=24MHz/(saradc_div_con+1)
> +	 */
> +	CLK_SARADC_DIV_CON_SHIFT	= 8,
> +	CLK_SARADC_DIV_CON_MASK		= 0xff << CLK_SARADC_DIV_CON_SHIFT,
> +	CLK_SARADC_DIV_CON_WIDTH	= 8,
> +
> 	SOCSTS_DPLL_LOCK	= 1 << 5,
> 	SOCSTS_APLL_LOCK	= 1 << 6,
> 	SOCSTS_CPLL_LOCK	= 1 << 7,
> @@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
> 
> +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
> +{
> +	return (val >> shift) & ((1 << width) - 1);
> +}

Same comments apply as for patch 3/8.

> +
> static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> 			 const struct pll_div *div)
> {
> @@ -634,6 +648,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
> }
> 
> +static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> +{
> +	u32 div, val;
> +
> +	val = readl(&cru->cru_clksel_con[24]);
> +	div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,
> +			   CLK_SARADC_DIV_CON_SHIFT);
> +
> +	return DIV_TO_RATE(OSC_HZ, div);
> +}
> +
> +static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
> +{
> +	int src_clk_div;
> +
> +	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
> +	assert(src_clk_div < 128);
> +
> +	rk_clrsetreg(&cru->cru_clksel_con[24],
> +		     CLK_SARADC_DIV_CON_MASK,
> +		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
> +
> +	return rockchip_saradc_get_clk(cru);
> +}
> +
> static ulong rk3288_clk_get_rate(struct clk *clk)
> {
> 	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -666,6 +705,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
> 		return gclk_rate;
> 	case PCLK_PWM:
> 		return PD_BUS_PCLK_HZ;
> +	case SCLK_SARADC:
> +		new_rate = rockchip_saradc_get_clk(priv->cru);
> +		break;
> 	default:
> 		return -ENOENT;
> 	}
> @@ -756,6 +798,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> 		new_rate = rate;
> 		break;
> #endif
> +	case SCLK_SARADC:
> +		new_rate = rockchip_saradc_set_clk(priv->cru, rate);
> +		break;
> 	default:
> 		return -ENOENT;
> 	}
> -- 
> 2.7.4
> 
> 

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^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288
  2017-09-13 10:09   ` [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288 David Wu
@ 2017-09-13 10:24     ` Dr. Philipp Tomsich
  2017-09-13 10:26     ` Dr. Philipp Tomsich
  1 sibling, 0 replies; 5+ messages in thread
From: Dr. Philipp Tomsich @ 2017-09-13 10:24 UTC (permalink / raw)
  To: David Wu
  Cc: huangtao, u-boot, zhangqing, linux-rockchip, p.marczak, andy.yan, chenjh


> On 13 Sep 2017, at 12:09, David Wu <david.wu@rock-chips.com> wrote:
> 

Please add a commit message.

> Signed-off-by: David Wu <david.wu@rock-chips.com>

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

See above and below for requested changes.

> ---
> drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
> index 478195b..29652b0 100644
> --- a/drivers/clk/rockchip/clk_rk3288.c
> +++ b/drivers/clk/rockchip/clk_rk3288.c
> @@ -111,6 +111,15 @@ enum {
> 	PERI_ACLK_DIV_SHIFT	= 0,
> 	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
> 
> +	/*
> +	 * CLKSEL24
> +	 * saradc_div_con:
> +	 * clk_saradc=24MHz/(saradc_div_con+1)
> +	 */
> +	CLK_SARADC_DIV_CON_SHIFT	= 8,
> +	CLK_SARADC_DIV_CON_MASK		= 0xff << CLK_SARADC_DIV_CON_SHIFT,
> +	CLK_SARADC_DIV_CON_WIDTH	= 8,
> +
> 	SOCSTS_DPLL_LOCK	= 1 << 5,
> 	SOCSTS_APLL_LOCK	= 1 << 6,
> 	SOCSTS_CPLL_LOCK	= 1 << 7,
> @@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
> 
> +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
> +{
> +	return (val >> shift) & ((1 << width) - 1);
> +}

Please reuse what’s already available in include/bitfield.h.
This also applies to all call-sites for extract_bits below: they should directly use the already existing function.

> +
> static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> 			 const struct pll_div *div)
> {
> @@ -634,6 +648,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
> }
> 
> +static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> +{
> +	u32 div, val;
> +
> +	val = readl(&cru->cru_clksel_con[24]);
> +	div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,
> +			   CLK_SARADC_DIV_CON_SHIFT);
> +
> +	return DIV_TO_RATE(OSC_HZ, div);
> +}
> +
> +static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
> +{
> +	int src_clk_div;
> +
> +	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
> +	assert(src_clk_div < 128);
> +
> +	rk_clrsetreg(&cru->cru_clksel_con[24],
> +		     CLK_SARADC_DIV_CON_MASK,
> +		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
> +
> +	return rockchip_saradc_get_clk(cru);
> +}
> +
> static ulong rk3288_clk_get_rate(struct clk *clk)
> {
> 	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -666,6 +705,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
> 		return gclk_rate;
> 	case PCLK_PWM:
> 		return PD_BUS_PCLK_HZ;
> +	case SCLK_SARADC:
> +		new_rate = rockchip_saradc_get_clk(priv->cru);
> +		break;
> 	default:
> 		return -ENOENT;
> 	}
> @@ -756,6 +798,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> 		new_rate = rate;
> 		break;
> #endif
> +	case SCLK_SARADC:
> +		new_rate = rockchip_saradc_set_clk(priv->cru, rate);
> +		break;
> 	default:
> 		return -ENOENT;
> 	}
> -- 
> 2.7.4
> 
> 

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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288
       [not found] ` <1505297379-12638-1-git-send-email-david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
@ 2017-09-13 10:09   ` David Wu
  2017-09-13 10:24     ` Dr. Philipp Tomsich
  2017-09-13 10:26     ` Dr. Philipp Tomsich
  0 siblings, 2 replies; 5+ messages in thread
From: David Wu @ 2017-09-13 10:09 UTC (permalink / raw)
  To: sjg-F7+t8E8rja9g9hUCZPvPmw,
	philipp.tomsich-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5
  Cc: huangtao-TNX95d0MmH7DzftRWevZcw, heiko-4mtYJXux2i+zQB+pC5nmwQ,
	u-boot-0aAXYlwwYIKGBzrmiIFOJg, zhangqing-TNX95d0MmH7DzftRWevZcw,
	kever.yang-TNX95d0MmH7DzftRWevZcw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	p.marczak-Sze3O3UU22JBDgjK7y7TUQ, David Wu,
	andy.yan-TNX95d0MmH7DzftRWevZcw, chenjh-TNX95d0MmH7DzftRWevZcw

Signed-off-by: David Wu <david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
 drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 478195b..29652b0 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -111,6 +111,15 @@ enum {
 	PERI_ACLK_DIV_SHIFT	= 0,
 	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
 
+	/*
+	 * CLKSEL24
+	 * saradc_div_con:
+	 * clk_saradc=24MHz/(saradc_div_con+1)
+	 */
+	CLK_SARADC_DIV_CON_SHIFT	= 8,
+	CLK_SARADC_DIV_CON_MASK		= 0xff << CLK_SARADC_DIV_CON_SHIFT,
+	CLK_SARADC_DIV_CON_WIDTH	= 8,
+
 	SOCSTS_DPLL_LOCK	= 1 << 5,
 	SOCSTS_APLL_LOCK	= 1 << 6,
 	SOCSTS_CPLL_LOCK	= 1 << 7,
@@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
+{
+	return (val >> shift) & ((1 << width) - 1);
+}
+
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 			 const struct pll_div *div)
 {
@@ -634,6 +648,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
 }
 
+static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
+{
+	u32 div, val;
+
+	val = readl(&cru->cru_clksel_con[24]);
+	div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,
+			   CLK_SARADC_DIV_CON_SHIFT);
+
+	return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
+{
+	int src_clk_div;
+
+	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+	assert(src_clk_div < 128);
+
+	rk_clrsetreg(&cru->cru_clksel_con[24],
+		     CLK_SARADC_DIV_CON_MASK,
+		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+	return rockchip_saradc_get_clk(cru);
+}
+
 static ulong rk3288_clk_get_rate(struct clk *clk)
 {
 	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
@@ -666,6 +705,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
 		return gclk_rate;
 	case PCLK_PWM:
 		return PD_BUS_PCLK_HZ;
+	case SCLK_SARADC:
+		new_rate = rockchip_saradc_get_clk(priv->cru);
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -756,6 +798,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 		new_rate = rate;
 		break;
 #endif
+	case SCLK_SARADC:
+		new_rate = rockchip_saradc_set_clk(priv->cru, rate);
+		break;
 	default:
 		return -ENOENT;
 	}
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-09-13 11:01 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-13 11:01 [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288 David.Wu
2017-09-13 11:01 ` [U-Boot] " David.Wu
  -- strict thread matches above, loose matches on Subject: below --
2017-09-13 10:09 [PATCH 0/8] Add rockchip Saradc support David Wu
     [not found] ` <1505297379-12638-1-git-send-email-david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-09-13 10:09   ` [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288 David Wu
2017-09-13 10:24     ` Dr. Philipp Tomsich
2017-09-13 10:26     ` Dr. Philipp Tomsich

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